Read my trip reports:

• DAC 2012 – Sunday Night Kick Off 
• Physical IP Not From ARM or Synopsys
• Collaboration at 28nm, 20nm and 14nm: IBM, Cadence, ARM, GLOBALFOUNDRIES, Samsung
• Fast Monte Carlo and Analog Fast SPICE from ProPlus at DAC
• Schematic, IC Layout, Clock and Timing Closure from IC Scape at DAC
• ST using Cadence IC Tools with Module Generators at DAC
• A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
• Fast SPICE from Kiev at DAC
• From SPICE Netlist back to Schematics at DAC
• 1,000,000,000,000 Transistor IC Layout Editing at DAC
• IC Layout Tools from Japan at DAC
• Soft Error Rate prediction software
• Fast Monte Carlo from Infiniscale at DAC
• What’s New with HSPICE at DAC?
• Samsung, Synopsys, GLOBALFOUNDRIES and ARM at DAC
• Analog Macromodels at DAC
• Shape-based IC Routing at DAC
• 3D Thermal and Mechanical Stress for IC Packaging at DAC
• IPL Alliance at DAC
• Custom IC Layout Automation at DAC
• Double Patterning Technology at DAC
• IC Cell Library Characterization at DAC
• Finding RTL Bugs Live at DAC using Formal Techniques
• EDA Tools to Optimize Memory Design, Size Standard Cells, Verify Low-Power Design, Center Analog Designs
• Laker IC Layout Update at DAC
• Electromagnetic Simulation Update from Nimbic at DAC
• DesignSync update from Dassault Systems at DAC
• FinFET Standard Cells at DAC
• AMS Simulation Update from Mentor Graphics at DAC
• Robustness, Reliability and Yield at DAC
• Analog FastSPICE update at DAC
• Methodics update at DAC
• Photo and Video overview of DAC 2012

EDA Perspective

My engineering career began at Intel designing DRAMs at a time when Design Rule Checking (DRC) and Layout Versus Schematic checking (LVS) where done manually by New College Graduates (NCGs). It quickly dawned on me that Computer Aided Design (CAD) was desperately needed. Intel had a strong culture of internally developed CAD tools however that team never seemed to be able to automate everything that I wanted, so I just started writing my own CAD tools to make my life easier as an engineer.

After 8 years in IC design I decided to do something about the dearth of Electronic Design Automation (EDA) tools and joined a start-up called Silicon Compilers Inc in San Jose. The vision at SCI was quite powerful: Design at a high level of abstraction, push a button and the chip is automatically created both logically and physically. Mentor Graphics saw the promise of SCI and acquired the company.

My perspective on EDA comes from experience as a full-custom IC circuit designer, Application Engineer, Technical Marketing Engineer, Product Marketing Manager, EDA consultant and EDA blogger.

EDA Consulting Services

I will accelerate your EDA business success with marketing and training services like:

My work can be conducted in stealth mode or out in the open to fit your project.

EDA at SemiWiki.com

This new site was launched in January 2011 and covers the EDA plus IP industries with: Forums, Wiki Pages and Blogs. We have several veteran bloggers: Daniel Nenni, Paul McLellan, Eric Esteve, Ed Mckernan, Daniel Payne

• Tempus: Cadence Takes On PrimeTime , May 20, 2013
• IDesignSpec Provides Complete Register Design Automation , May 20, 2013
• Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!) , May 20, 2013
• Design Data Management – Key Winning Strategy! , May 20, 2013
• Invarian CEO Interview , May 20, 2013
• BDA Introduces High-Productivity Analog Characterization Environment (ACE) , May 20, 2013
• Oasys Announces Floorplan Compiler , May 19, 2013
• Dassault DAC Assault , May 19, 2013
• Supporting the Customer Is Everyone’s Job , May 19, 2013
• Interview with Jason Xing, Ph.D., CEO & President of ICScape Inc. , May 19, 2013

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