Mehmet Cirit, Founder of Library Technologies
I first met Mehmet at Silicon Compilers in the 80’s and have kept in touch with him over the years.
New product – Chip Timer, speeds up ASIC designs by building digital library cells on the fly. Uses both Solution Ware and Cell Opt tools to do design optimization. This approach can improve timing by 50%. As an example we took the SPARC processor in 65nm technology and showed how to improve the clock speed from 1.2 GHz to 2.4 GHz.
Q: How is that different than Zenasis?
A: We’re a bit different, they were combining cells, we’re optimizing existing cells per path. We don’t create new cells.
Beta testing right now at an account, stay tuned for a press release.
Yield Opt – Determines best and worst case conditions for each cell to use just two PVT corners. Finds worst and best case timing per cell. Their tool launches your favorite SPICE circuit simulator to get results and use monte carlo values from the process models. Similar to using exhaustive monte carlo, rather it is using a smart optimization. Anyone with a digital library would benefit from Yield Opt.
Cell Opt – Does timing and power optimization per cell in your library. Tool changes your device sizes to meet your specs on digital cells.
Solution Ware – Creates libraries for logic synthesis tools, also can do libraries for memories and standard cells.
DAC 2010 – It’s a busy year for us and Chip Timer looks to be a revolutionary product.
Customers – Medtronic (biomedical company), Tabula (startup), Exar (mixed-signal).