Marketing EDA

Ethernet & IP @ Automotive Technology Day
2022-11-09 08:00 - 2022-11-10 17:00 (Asia/Tokyo) | PACIFICO Yokohama North, 1 Chome-1-2 Minatomirai, Nishi Ward, Yokohama, Japan
Onsite registration may be limited, register now to be sure to get admission.

The 2022 IEEE SA Ethernet & IP @ Automotive Technology Day (E&IP@ATD) is the premier venue for automobile manufacturers, suppliers, semiconductor vendors, tool providers, engineers, scientists, educators, and the media to share ground breaking ideas along with implementation strategies and applications related to Automotive Ethernet Systems. Attendees will receive and share information, and actively participate in the latest developments in shaping Automotive Ethernet into a globally deployed, volume car automotive network.
Presentations will provide insights into the developments, trends and solutions in the following topics:

Current automotive use-cases and future perspectives
Ethernet’s role to facilitate cloud connectivity
Ethernet network design and specification
Ethernet requirements for automated driving applications
Safety, security and reliability of Ethernet communications
Markets and strategies
Tools and tests methods
Present and future physical layer and protocol solutions

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Achieving Fast Turnaround Time of Functional ECOs with Synopsys Formality ECO
2022-11-09 10:00 - 11:00 (America/Los_Angeles)
Functional ECOs (engineering change orders) are an important part of the design cycle, enabling design teams to respond quickly to frequent, unexpected, and last-minute register-transfer logic (RTL) functional changes. ECOs are unavoidable, however, they are necessary to fix functional verification bugs or to add critical new features, which enable designers to deliver products with minimal risk for defects and on schedule.
Given the schedule pressures under which the ECO generation process operates, it is essential to:

Start the ECO generation process as soon as ECO RTL is ready
Generate a patch as fast as possible
Ensure patch accuracy and minimal disturbance to the implemented design

In this Synopsys webinar, presenters from Qualcomm and Synopsys will share how Synopsys Formality ECO’s targeted synthesis and net-based regions technologies accurately zoom in and synthesize only the regions inside modules affected by the ECO avoiding the time-consuming approach of a full re-synthesis. This approach enables Qualcomm to rapidly create compact, functionally correct, and timing-aware patches and meet its aggressive time-to-market requirements.

Speakers

Listed below are the industry leaders scheduled to speak.

Sachin Singh

Principal Engineer
Qualcomm

Sachin Singh is a principal engineer at Qualcomm where he leads the design team for cutting-edge GPU projects. He has 22 years of ASIC design experience and currently specializes in RTL-GDS flows including synthesis, equivalence checking, and functional ECOs for signoff. Sachin has a master’s degree from California State University Sacramento.

Makarand Patil

Senior Manager, R&D
Synopsys

Makarand Patil (Miki) is the R&D manager for Synopsys Formality and Formality ECO products. He has over 20 years of experience in logic equivalence checking technologies spanning various areas of equivalence checking, such as RTL-Gate verification flows, solver engines, front-end language support, functional ECO, datapath optimizations, and UPF aware verification flows. Makarand holds a master’s degree in Computer Engineering from University of Kansas and a bachelor’s degree from Mumbai University.

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