Marketing EDA

AutoSens Brussels 2023
2023-09-19 08:00 - 2023-09-21 17:00 (Europe/Brussels) | Autoworld Museum, 1000 Brussels, Brussels, Belgium
We’re bringing AutoSens to Autoworld in Brussels once again to meet and shape the future of ADAS and AV.
You can look forward to the freshest agenda of over 60 speakers across expert panels, technical case studies, and sessions covering 12 key themes. You will experience an exhibition full of demos from technology companies at the forefront of sensors and computer vision to explore.
Join us on 19-21 September 2023 at the Autoworld Museum in Brussels.

Windshield Technology

Every vehicle has one, but are they optimised for ADAS/AD? A plenary session will consider the challenges of light, heat, tilt and yaw, measurement, and other important factors when pairing cameras with windshields.

Infrastructure

A keynote session will explore infrastructure from a perception and observation perspective, as well as the communication between vehicles and the world around them (V2I and V2X).

Cyber Security & Data Privacy

With L4 and L5 drawing closer, we must consider the ‘hackability’ of vehicles more than ever before, not only for occupant safety, but to prevent (or at least minimise) the weaponisation of autonomous vehicles.

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PCB West 2023
2023-09-19 08:00 - 2023-09-22 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
The Largest Conference and Exhibition for Printed Circuit Board Design,
Fabrication and Assembly in the Silicon Valley

For more than 30 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. More than 2,000 designers, fabricators, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss.
Brought to you by PCEA: Engineering Tomorrow’s Electronics!

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QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
2023-09-21 09:00 - 10:00 (America/Los_Angeles)
Join our FREE online event to learn about the new and enhanced features and performance improvements in the latest QuantumATK V-2023.09 product release.
– Enhanced ease-of-use of training Machine-Learned FFs with new predefined Workflow Builder blocks and templates
– New interactive Interfaces Builder for building multilayer structures
– New Accelerated molecular dynamics method for crystallization
– New Thermochemistry pyrolysis tools to predict gas phase composition in surface processing – Integrated Charged point defect and defect diffusion simulation frameworks
– Major speedup in bandstructure simulations with Tight Binding models for up to million atoms
– Efficient and simplified deformation potential extraction for large nanostructures to evaluate electron-phonon coupling
– New analysis of spectral and thermal current/conductance in Transmission Analyzer
– More interactive IV Characteristics Analyzer and possibility to analyze inelastic current
– New Finite Bias Spin Transfer Torque (STT) Study Object & Analyzer to evaluate the write performance of STT-MRAM
– New Heisenberg Exchange Analyzer for exchange couplings and Curie temperature
Synopsys Webinar Speakers:
– Mattias Palsgaard, Senior Applications Engineer, Synopsys QuantumATK
– Vaida Arcisauskaite, Senior Applications Engineer, Synopsys QuantumATK
– Bo Lu, Senior R&D Engineer, Synopsys QuantumATK
Learn more about the new QuantumATK V-2023.09 release here: https://www.synopsys.com/manufacturing/quantumatk/resources/release-notes.html
You are welcome to ask questions throughout the webinar or at the end during the Q&A session. Contact us for more information at quantumatk@synopsys.com.
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Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
2023-09-21 10:00 - 11:00 (America/Los_Angeles)
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using Synopsys VCS® as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the Bluespec processor core simulated with Synopsys VCS and the results are compared with Spike instruction set simulation (ISS) results.

This presentation will showcase:

A reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV.
How designers can leverage Synopsys VCS simulation and Synopsys Verdi® for debug and relevant advanced coverage methodology, to help speed verification signoff.
The combination of RISCV-DV and Synopsys tools provides a powerful and flexible solution for RISC-V verification and highest coverage.
Demo on the RISC-V verification solution on the Synopsys Cloud platform.

Whether you are a chip verification architect or a verification engineer or a system designer, this Synopsys webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage.

Speakers

Listed below are the industry leaders scheduled to speak.

Bipul Talukdar

Senior Director, Applications Engineering
Bluespec

Bipul Talukdar is Senior Director of Applications Engineering for Bluespec Inc. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development, formal property verification, and hardware emulation. He leads Application Engineering and Support for Bluespec. Bipul has a strong background in formal verification of RISC-V based cores/subsystems, arm based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive, Cadence, Mentor Graphics (Siemens) and SmartDV Technologies give him a broad perspective on the myriad challenges faced by design and verification teams, allowing him to partner with customers for success throughout product evaluations and deployment. Bipul holds a Bachelor of Science in Engineering, Electronics, and Telecommunication from India’s National Institute of Technology, Silchar. He is based in San Jose, California.

Prabha Krishnaswami

Applications Engineer, Senior Staff
Synopsys

Prabha Krishnaswami is an Application Engineer at Synopsys, focusing on VCS and Verdi products. She also collaborates with the global RISC-V customers to showcase the Synopsys RISC-V solution. She has a background in design and verification with expertise in SoCs and subsystems. Prabha likes music, reading and enjoys long walks.

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UCIe-Based Chiplet Verification - from IP to SoC
2023-09-21 11:00 - 12:00 (America/Los_Angeles)
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence, the verification topologies of such designs have exponentially increased.
In this webinar, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally, at the system-level.
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