BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT 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BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20250309T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20251102T070000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250224T080000 DTEND;TZID=America/Los_Angeles:20250227T170000 DTSTAMP:20241213T183758Z CREATED:20241213T183758Z LAST-MODIFIED:20241213T183758Z UID:8595-1740384000-1740675600@marketingeda.com SUMMARY:DVCON US 2025 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-us-2025/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/DVCON-US-2025.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250125T080000 DTEND;TZID=America/Los_Angeles:20250130T170000 DTSTAMP:20241220T214552Z CREATED:20241220T214552Z LAST-MODIFIED:20241220T214552Z UID:8691-1737792000-1738256400@marketingeda.com SUMMARY:SPIE Photonics West DESCRIPTION:Browse the 2025 program; discover all the ways you’ll connect with colleagues \n\nJoin the world’s largest photonics technologies event. Learn the most cutting-edge research in biomedical optics\, biophotonics\, industrial lasers\, optoelectronics\, microfabrication\, displays\, quantum technologies\, and more. \nReview the lineup of outstanding plenary speakers from around the globe. Select advanced training from more than 50 courses. Discuss your product requirements with top optics and photonics suppliers at any of the four exhibitions throughout the week\, and participate in the strong industry program. The week is full of important engagements\, and we look forward to seeing you there. \nConferences and courses: 25–30 January 2025\nBiOS Expo: 25–26 January 2025\nQuantum West Expo: 28–29 January 2025\nPhotonics West Exhibition: 28–30 January 2025 \nCo-located with SPIE AR | VR | MR 2025\nand SPIE Global Business Forum 2025 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/spie-photonics-west/ LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SPIE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250121T080000 DTEND;TZID=America/Los_Angeles:20250123T170000 DTSTAMP:20240723T220633Z CREATED:20240723T220210Z LAST-MODIFIED:20240723T220633Z UID:8174-1737446400-1737651600@marketingeda.com SUMMARY:Chiplet Summit 2025 DESCRIPTION:Position Your Company as a Leader in an Emerging Technology.  Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia).  Share Thoughts with Key Experts and Analysts.  Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. \n\nOnly event totally dedicated to the skyrocketing chiplet market\nTop experts\, major keynotes\, and critical topics will draw big-time customers\nPractical orientation will attract key designers and specifiers\nVendor-neutral show offers opportunities to everyone\n\nThe third annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. \nThey’ll get the scoop on ways to make their chiplets run faster\, scale better\, use less power\, and be more flexible. \nThis unique event gives attendees a place to network with peers\, ask questions of the experts\, and talk to vendors offering a wide variety of products and services. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplet-summit-2025/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chiplet-Summit-2025-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20250120T080000 DTEND;TZID=Asia/Tokyo:20250123T170000 DTSTAMP:20241213T182220Z CREATED:20241213T182220Z LAST-MODIFIED:20241213T182220Z UID:8592-1737360000-1737651600@marketingeda.com SUMMARY:ASP-DAC 2025 DESCRIPTION:ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2025 is 30th conference. ASP-DAC 2025 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2025. \n\nDate: Jan. 20-23\, 2025\nPlace: Tokyo Odaiba Miraikan\, Japan\nGeneral Chair: Yuichi Nakamura (NEC)\nTechnical Program Chair: Yu Wang (Tsinghua University)\nDesign Contest Co-Chairs: Mahfuzul Islam (Institute of Science Tokyo)\, Shinya Takamaeda Yamazaki (The University of Tokyo)\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/asp-dac-2025/ LOCATION:Tokyo Odaiba Miraikan\, 2 Chome-3-6 Aomi\, Tokyo\, Koto CIty\, 135-0064\, Japan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ASP-DAC-2025.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250107T080000 DTEND;TZID=America/Los_Angeles:20250110T170000 DTSTAMP:20241209T181610Z CREATED:20241004T181728Z LAST-MODIFIED:20241209T181610Z UID:8380-1736236800-1736528400@marketingeda.com SUMMARY:CES 2025 DESCRIPTION:The world’s most powerful tech event is your place to experience the innovations transforming how we live. \n\n\n\n\nThis is where global brands get business done\, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Registration for CES 2025 is now open. \n\n\nCES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges. \n\n\n\n\n\nCES connects innovators\, decision makers\, media\, influencers\, visionaries\, and potential customers across the entire tech ecosystem. \nDon’t be left in the past as we shape the future.\n\nGlobally showcase your technology products\nStand side-by-side with the world’s most disruptive innovators\nPromote your brand through curated opportunities to connect with influencers and prospective partners\n\nCES is owned and produced by the Consumer Technology Association (CTA)®\, which provides the ultimate platform for technology leaders to connect\, collaborate\, and propel consumer technology forward. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ces-2025/ LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20250104T080000 DTEND;TZID=Asia/Kolkata:20250108T170000 DTSTAMP:20250104T202845Z CREATED:20241203T180905Z LAST-MODIFIED:20250104T202845Z UID:8547-1735977600-1736355600@marketingeda.com SUMMARY:38th International Conference on VLSI Design DESCRIPTION:International VLSI Design & Embedded Systems conference is a Premier Global conference with legacy of over three and half decades. This Global Annual technical conference that focusses on latest advancements in VLSI and Embedded Systems\, is attended by over 2000 engineers\, students & faculty\, industry\, academia\, researchers\, bureaucrats and government bodies. \nVLSI Design Conference started as a simple idea in 1985: to sense the level of VLSI activities in India with a focus on engineering education & research. \nWith its global footprints VLSID is recognized as a ‘Sister Conference’ of Design Automation Conference. This conference is sponsored by VLSI Society of India (VSI) \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/38th-international-conference-on-vlsi-design/ LOCATION:The Leela Palace\, Bengaluru\, India CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2025-e1733248863710.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T080000 DTEND;TZID=America/Los_Angeles:20241212T210000 DTSTAMP:20241112T204519Z CREATED:20241112T204519Z LAST-MODIFIED:20241112T204519Z UID:8498-1733990400-1734037200@marketingeda.com SUMMARY:PDF Solutions - AI Executive Conference DESCRIPTION:This one-day Executive Conference will feature presentations from PDF Solutions executives\, industry thought leaders\, solutions partners and customers on the state of art and best practices to design\, deploy\, scale\, and manage trusted AI / ML solutions across the global semiconductor industry. \nSpeakers from: ADI\, Advantest\, Cerebras\, Intel\, Microsoft\, SAP\, Siemens\, TEL\, Teradyne\, Voltai\, Yurts and PDF Solutions. \n\n\n\nEvent Overview\n\n\n\n\n\n\n\n\n\n\n\n8:00am – 9:00am PT \n\n\n  REGISTRATION\n\n\n\n\n   9:00am – 5:30am PT \n\n\nCONFERENCE\n\n\n\n\n\n\n\n\n    5:30pm – 6:30pm PT \n\n\nCOCKTAIL HOUR\n\n\n\n\n6:30pm – 9:00pm PT \n\n\nDINNER & SPEAKER\n\n\n\nAGENDA PREVIEW\n\n\n\n\n\n\n\n\n\n\n\nKEYNOTE \n\n\nHow Analytics and AI are helping to transform a leading semiconductor company\n\n\nAziz Safa – VP and GM\, Intel \n\n\n\n\nKEYNOTE \n\n\nAI\, the next evolution of PDF Solutions portfolio\n\n\nJohn Kibarian – CEO\, PDF Solutions \n\n\n\n\nKEYNOTE \n\n\nSecure and scalable AI for the semiconductor industry is foremost a data and model infrastructure challenge\n\n\nSaid Akar – VP\, PDF Solutions \n\n\n\n\nPANELS & DEMOS \n\n\nGenAI for semiconductor: use cases\, solutions\, and demonstrations\n\n\nVoltai\, Yurts\, SAP\, PDF Solutions \n\n\n\n\nPanel Discussion \n\n\nAI for test in a world of hybrid 3D devices\n\n\nAdvantest\, Teradyne\, Siemens\, Fabless\, Foundry \n\n\n\n\nPRESENTATIONS \n\n\nAI to use semiconductor design information\n\n\nSiemens and PDF Solutions \n\n\n\n\n\n\n\n\nLive Demo \n\n\nPDF Solutions ModelOps\nThe AI infrastructure for the global semiconductor supply chain\n\n\nPDF Solutions \n\n\n\n\nPanel Discussion \n\n\nRevisiting the notion of trust in an AI solutions world\n\n\nPDF Solutions\, Yurts\, Enterprise Applications ISV \n\n\n\n\nPANEL DISCUSSION \n\n\nHow can semiconductor companies accelerate their digital transformation with AI IDMs\n\n\nSAP\, ADI\, PDF Solutions \n\n\n\n\nPANEL DISCUSSION \n\n\nAI-enabled digital twin for semiconductor manufacturing equipment\n\n\nTEL\, PDF Solutions \n\n\n\n\nPresentations \n\n\nStrategies to quickly increase available Analytics and AI skills across the semiconductor industry\n\n\nMIT\, Intel\, LIVE Institute\, PDF Solutions \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pdf-solutions-ai-executive-conference/ LOCATION:St. Regist Hotel\, 125 3rd Street\, San Francisco\, CA\, United States CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PDF-Solutions-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20241211T080000 DTEND;TZID=Asia/Shanghai:20241212T170000 DTSTAMP:20241206T211410Z CREATED:20241206T210925Z LAST-MODIFIED:20241206T211410Z UID:8556-1733904000-1734022800@marketingeda.com SUMMARY:ICCAD-Expo 2024 DESCRIPTION:The China Integrated Circuit Design Industry Exhibition (ICCAD-Expo) has always played an important role in promoting industrial agglomeration\, connecting industrial resources\, and mastering industry trends. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-expo-2024/ LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-Expo-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20241210T090000 DTEND;TZID=Europe/Paris:20241211T190000 DTSTAMP:20241122T185502Z CREATED:20241122T185502Z LAST-MODIFIED:20241122T185502Z UID:8524-1733821200-1733943600@marketingeda.com SUMMARY:IP-SoC Conference 2024\, Europe DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2024 will be the 27th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, … \nAny question? Please contact us \n\n\n\n\n\n\nDay 1\n\n\n\n\n\n\n\n9.00 am\nWelcome Session\n \nChairperson: Gabrièle Saucier – Design And Reuse\n\n\n\n\nIP SoC Community: EU as a main player ? \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nThe network evolution and radio implications \nFredrik Tillman\nHead of Integrated Radio Systems\nEricsson \nAbout me\n\n\n\n\nIncreased competitiveness and sustainability in connectivity with advanced substrates solutions \nFrancois Brunier\nPartnership Program Manager\nSoitec \nAbout me\n\n\n\n\nChips Act and EU design Platform \nOlivier Thomas\nCEA \nAbout me\n\n\n\n\n10.20 am\nBreak\n\n\n\n11.00 am\nInterface IP\n \nChairperson: Olivier Thomas – CEA\n\n\n\n\nThe Critical Role of PCIe 7.0 & CXL 3.1 Solutions in Enabling AI applications \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\nIoT Solutions\n\n\n\nHow to select the best Audio codec architecture to enhance your wearables? \nEtienne Faucher\nProduct Marketing Manager\nDolphin Semiconductor \nAbout me\n\n\n\n\nWireless and Batteryless Interface for IoT \nPolina Proskurova\nProject Manager\nNTLab \nAbout me\n\n\n\n\n12.00 pm\nLunch Break\n\n\n\n1.00 pm\nAutomotive Solutions\n\n\n\nTowards a Sustainable Automobile: Reinventing the Industry for Green and Circular Mobility \nJerome Fohet\nMarketing and Communications Director\nSoitec \nAbout me\n\n\n\n\nSilicon Lifecycle Management (SLM) in context of Chiplets for Automotive \nGraham Woods\nPrincipal Product Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\nProtecting Automotive Networks with MACsec Security \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nCyber Resilience and Safety in Automotive: How Security IP Provides Essential Primitives for Compliance \nGordon Fairley\nKudelski IoT \nAbout me\n\n\n\n\n2.30 pm\nBreak\n\n\n\n2.45 pm\nSecurity IP\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nSecure-IC Differential Loop PUF : Overcoming some weaknesses of the traditional Loop PUF while enhancing its usability \nBrice GAIGNOUX\nPre-Sales Engineer EMEA\nSecure-IC \nAbout me\n\n\n\n\nThe CHERI Alliance – getting security embedded into electronic systems \nMike Eftimakis\nFounding Director\nCHERI Alliance \nAbout me\n\n\n\n\nIntegrated Security Solutions: How SRAM-based PUF Augments Embedded Hardware Secure Modules in a Post-Quantum World \nErik van der Sluis\nPrincipal R&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nSecurity Verification in SoCs \nAli Hmedat\nSenior Design vérification Engineer\nAEDVICES CONSULTING \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nWireless Solutions\n\n\n\nInCirT Pioneers High-Performance Data Converter Technologies for Next-Gen Wireless Communications \nDr.-Ing. Oner Hanay\nCEO\nInCirT GmbH \nAbout me\n\n\n\n\nBattle of the Bits: Evaluating Lossless Data Compression Algorithms and Cores \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\n5.00 pm\nBreak\n\n\n\n5.30 pm\nOpen Panel: Greener Electronics: a myth or a reality ?\n\n\n\n\n\n\n\n\n\n\n\n6R Greenness Profiling for IC and Boards \n\n\n\n\n\n\n\nGabrièle Saucier\nCEO\nDesign And Reuse\n\n\nwith \nDagmara Zielinska\nDesign And Reuse\n\n\nand \nArnaud Serra\nDesign And Reuse\n\n\n\n\n\nAbout me\n\n\n\n\n\n\n\n\nIC Life time modeling : a critical parameter for Greener Electronics \nHN Nguyen\nCTO\nMETASymbiose \nAbout me\n\n\n\n\nStrategic decision-making in the semiconductor sector: shifting from relative to absolute sustainability \nThibault Pirson\nPhD\, research assistant\nUCLouvain \nAbout me\n\n\n\n\n19.00 pm\nJoin the wine tasting party sponsored by Soitec \nDo not miss D&R banquet\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2\n\n\n\n\n\n\n\n9.00 am\nAnalog Design\n\n\n\nHow to Enhance Energy Efficiency and Reduce Costs with Advanced In-Situ Sensors? \nVincent Telandro\nProduct Marketing Manager\nDolphin Semiconductor \nAbout me\n\n\n\n\nStandardizing CDC and RDC abstract models \nJean-Christophe Brignone\nSMTS\nSTMicroelectronics \nAbout me\n\n\n\nDesign Platform and Design Flow\n \nChairperson: Erkan Isa – Fraunhofer-Gesellschaft\n\n\n\n\nMake Chip: the one and only turnkey 22FDX design environment \nPatrick Döll\nPhysical IC Design Engineer\nRacyics GmbH \nAbout me\n\n\n\n\nKeysom Studio – Design Space Exploration of processor architectures \nLuca TESTA\nCofounder & COO\nKeysom \nAbout me\n\n\n\n\nStandard EDA tools based asynchronous design flow \nGODARD Adrien\nPhD student\nSTMicroelectronics \nAbout me\n\n\n\n\nAutomated Abstractions: High-Level Model Generation from Design Specifications or RTL Descriptions \nANDRIAMISAINA Choukataly-Caaliph\nCEA \nAbout me\n\n\n\nMigration and Yield Consideration\n\n\n\nPorting ASIC IP Cores to FPGA: It’s Not a Cakewalk! \nPhilipp Jacobsohn\nPrincipal Application Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nNiche gets super niche in the SEMI conductor Equipment domain \nP SRINIVASA RAGHAVAN\nPractice Head\, Semiconductor BU\nHCL TECH \nAbout me\n\n\n\n\n12.00 pm\nLunch Break\n\n\nWhat’s new on FDSOI: the SOIL Project\n \nChairperson: Philippe Flatresse – Soitec\n\n\n\n\nSolidify the European FDSOI ecosystem and accelerating its industrial deployment; A Chips JU initiative \nMartin LABRUNE\nEuropean & France Public Affairs\nSTMicroelectronics \nAbout me\n\n\n\n\nDesigning Intelligence from our SOIL \nKrishna Pradee\nSoitec \nAbout me\n\n\n\n\nInnovating the Future with SOIL: Next-Gen IPs\, Transfer from Research to Silicon \nDamian Panter\nFraunhofer \nAbout me\n\n\n\n\nFrom silicon to the use cases\, SOIL as a test bench for automotive applications \nLeonardo Govoni\nAED Vantage GmbH \nAbout me\n\n\n\nFDSOI IP\n\n\n\nMarket Available FDSOI IP \nDagmara Zielinska\nPartnership Program Manager\nDesign And Reuse \nAbout me\n\n\n\n\nDesigning SOC with ABX® – Challenges and Solutions \nFlorian Bilstein\nDirector Design Service\nRacyics GmbH \nAbout me\n\n\n\n\nUltra-wide band digital-to-analogue converter for wireless communication \nDr.-Ing. Oner Hanay\nCEO\nInCirT GmbH \nAbout me\n\n\n\nPanel: Building a strong FDSOI Ecosystem: A Catalyst for Tomorrow’s market wide Applications \nOrganizer:  Philippe Flatresse – Soitec \nFDSOI Technology has been over for quite a long time. This panel will investigate whether or not the technology and Ecosystem supporting this technology worldwide have now reached its full maturity or are still in a growing phase. The panel groups FDSOI technology specialists\, FDSOI Business managers\, researchers and FDSOI IP providers. \nWith the participation of: \n\n\nOlivier Thomas\nCEA\n\n\nRainer Lutz\nSoitec\n\n\nAnton Klotz\nFraunhofer\n\n\n\n\nFlorian Bilstein\nRacyics GmbH\n\n\nMichel Vasmer\nCapgemini Engineering\n\n\n\n\n\n\n\n17.00 pm\nJoin the reception organized by the European SOIL FDSOI Ecosystem\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-conference-2024-europe/ LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-2024-Europe.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241207T080000 DTEND;TZID=America/Los_Angeles:20241211T170000 DTSTAMP:20241018T161813Z CREATED:20241008T155901Z LAST-MODIFIED:20241018T161813Z UID:8386-1733558400-1733936400@marketingeda.com SUMMARY:70th Annual IEEE International Electron Devices Meeting - IEDM 2024 DESCRIPTION:IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology\, design\, manufacturing\, physics\, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology\, advanced memory\, displays\, sensors\, MEMS devices\, novel quantum and nano-scale devices and phenomenology\, optoelectronics\, devices for power and energy harvesting\, high-speed devices\, as well as process technology and device modeling and simulation. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/70th-annual-ieee-international-electron-devices-meeting/ LOCATION:Hilton San Francisco Union Square\, 333 O'Farrell Street\, San Francisco\, 94102\, United States CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/70thiedmcolor.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20241120T090000 DTEND;TZID=Asia/Kolkata:20241120T170000 DTSTAMP:20241114T182631Z CREATED:20241114T182226Z LAST-MODIFIED:20241114T182631Z UID:8514-1732093200-1732122000@marketingeda.com SUMMARY:Ansys IDEAS User Conference India 2024 DESCRIPTION:Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies. \nOverview\nAt this premier conference\, you will: \n\nDiscover Key Insights: Learn from industry experts and simulation specialists about cutting-edge techniques and strategies in on-chip power integrity and reliability\nExplore Multi-Scale Multiphysics Challenges: Dive into complex topics\, including multi-scale\, multiphysics simulations essential for 3DICs and heterogeneous integration\nAccelerate Innovation: Gain valuable knowledge on how advanced simulation technologies like Sigma-DVD can streamline design processes and drive innovation\nNetwork with Experts: Connect with peers and Ansys experts\, sharing experiences and exploring new opportunities for collaboration\n\nIDEAS India is your opportunity to deepen your understanding of power-noise-reliability sign-off for Chip-Package systems\, enhance your skills\, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology. \nKey Discussion Topics\n\nSoC Power-Integrity and Reliability Sign-off\nAdvanced Power Integrity Flows: Sigma-DVD\, ROM\, IR-ECO\, etc\n3DIC / Interposer – Power\, Signal\, Thermal Integrity\nAnalog & Mixed-Signal Designs Power and Reliability\nRTL Power Analysis and Optimization\nReliability Analysis: Electromigration\, ESD\, and Thermal\nShift-left /In-design Analysis and Optimization\nChip-Package-System Co-Simulation\n\n\n\n\nAgenda\n\n\n\nTime\nSession\nSpeakers\n\n\n9:00 am – 10:00 am\nRegistration + Hi-Tea\n\n\n10:00 am – 10:15 am\nWelcome & Inauguration\nJai Pollayil\nSenior Director & Global Semiconductor AE Head\nAnsys\n\n\n10:15 am – 10:45 am\nIndustry Keynote\nBalajee Sowrirajan\nCorporate EVP & MD\nSamsung Semiconductor India Research\n\n\n10:45 am – 11:15 am\nAnsys Keynote\nJohn Lee\nGeneral Manager and Vice President\nAnsys\n\n\n11:15 am – 11:30 am\nTea/Coffee Break\n\n\n\nTrack 1: Advanced SOC Power Integrity & Reliability\n(Convention Hall)\nTrack 2: Power-Signal-Thermal-ESD Integrity across RTL / Custom IP / IC / 3DIC\n(Tactic 5)\n\n\n\nSession\nSpeakers\nSession\nSpeakers\n\n\n11:30 am – 12:00 pm\nConquering IR ECO complexity with PrimeClosure\nSynopsys\nRaghavendra Swami Sadhu\nBackside power delivery and advanced technology EM/IR analysis in Totem\nIntel\nAnil Dsouza\n\n\n12:00 pm – 12:30 pm\nMaximizing IR signoff coverage using Sigma-AV and its benefit on PPA\nGoogle\n Sandeep Gajbhare\nComprehensive Electrical & Thermal integrity of Power Management IC using a new Integrated solution\nTexas Instruments\nGirish Bijjal\n\n\n12:30 pm – 1:00 pm\nAccelerating Full Flat EMIR Sign-off of Multi-billion Instance Design using RedHawk-SC ROM (Reduced Order Model)\nSamsung Semiconductor India Research\nRaja Ramachandra Rao & Satyaki Mandal\nOptimizing Standard cell library development flow using “ParagonX” – EDA tool for IC layout parasitics analysis\nNXP Semiconductors\nRavi JN & Santhosh Kamatam\n\n\n1:00 om – 2:00 pm\nLunch Break\n\n\n2:00 pm – 2:30 pm\nAn efficient methodology for Multi-PVT EMIR analysis of Large SOCs\nNVIDIA\nRamesh Aggarwal\nSignal and Power Integrity analysis of Silicon Interposer for multi-chiplet integration\nAlphawave Semi\nGangaraju M & Yadavalli Jagadeeswari\n\n\n2:30 pm – 3:00 pm\nAccounting for IR Drop in Static Timing Analysis: A Path to Accurate Delay Estimation\nIntel\nPurushotham Reddy N & Manoj Varama S\nComprehensive Thermal Analysis of 3DIC design using Redhawk_SC-ElectroThermal (RHSC-ET\nSamsung\nRishikanth Mekala & Abhishek Chinchani\n\n\n3:00 pm – 3:30 pm\nNovel method of Vectorless IR Analysis for DFT\nMediaTek\nArun CS\nAccelerated ESD Sign-off with Pathfinder-SC: An Efficient and Scalable Approach\nGoogle\nSmaritha Kasukurthi\n\n\n3:30 pm – 4:00 pm\nOptimizing Power Integrity with RHSC in Smart PDN Framework Qualcomm\nGaurav Jain & Rajender Nune\nAn Integrated Approach to Power Analysis & Optimization: Synergizing Emulation\, RTL Design\, and Physical Design\nAMD\nNeeraj Dwivedi\n\n\n4:00 pm – 4:30 pm\nRobust techniques for IR prediction\nAMD\nSayani Das\nA Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape’s DataLake and Micro-Resiliency\nARM\nChandrakumar A\n\n\n4:30 pm – 4:35 pm\nConcluding Remarks\n\nConcluding Remarks\n\n\n\n4:35 pm – 5:00 pm\nTea & Networking\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ansys-ideas-user-conference-india-2024/ LOCATION:CA CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-20-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T080000 DTEND;TZID=America/Los_Angeles:20241114T170000 DTSTAMP:20241030T174154Z CREATED:20241030T174154Z LAST-MODIFIED:20241030T174154Z UID:8463-1731398400-1731603600@marketingeda.com SUMMARY:IEEE World Technology Summit - AI INFRASTRUCTURE DESCRIPTION:This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems\, focusing on these core areas: \n\nAI applications and their required infrastructure\nSilicon to support AI applications\nSystems to support AI applications\nSecurity and Standards\n\nAI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit\, where companies\, governments\, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions. \nThe main focus of this conference is AI Infrastructure. \nTo deliver value we need the infrastructure for AI to work!!! This infrastructure includes software\, data storage\, computing\, communications\, power and energy\, standards\, and security. \nTo form an event to address the above issues\, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns\, challenges\, solutions\, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI\, which is critical to make AI work. \nCompanies are invited to sponsor\, engage\, and have employees attend this event. \nIf interested\, contact us at: wtscontact@ieee.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-world-technology-summit-ai-infrastructure/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WTS-November-12-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241107T080000 DTEND;TZID=Asia/Taipei:20241109T170000 DTSTAMP:20240522T185455Z CREATED:20240522T185455Z LAST-MODIFIED:20240522T185455Z UID:8022-1730966400-1731171600@marketingeda.com SUMMARY:APCCAS 2024 DESCRIPTION:The APCCAS is a major international forum for researchers\, scientists\, educators\, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including\, but not limited to the following： \n\nArtificial Intelligence Circuits\, Systems\, and Applications\nDigital Integrated Circuits and Systems\nAnalog and Mixed Signal Circuits and Systems\nPower and Energy Circuits and Systems\nBiomedical Circuits and Systems\nSensory Circuits and Systems\nRF/Communications Circuits and Systems\nBeyond CMOS: Nanoelectronics and Hybrid Systems Integration\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/apccas-2024/ LOCATION:Chang Yung-Fa Foundation\, No. 11\, Zhongshan S. Rd.\, Taipei City\, Taiwan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/APCCAS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241103T080000 DTEND;TZID=America/Los_Angeles:20241108T170000 DTSTAMP:20241004T174855Z CREATED:20241004T174855Z LAST-MODIFIED:20241004T174855Z UID:8376-1730620800-1731085200@marketingeda.com SUMMARY:ITC 2024 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWe are holding the conference in beautiful San Diego\, CA.  We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! \nITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum\, where the wide range of its offerings allows ITC participants to learn\, network and conduct business. This year’s program includes a top-notch technical program\, vibrant exhibitors\, information-packed tutorials\, interactive technical panels\, three workshops\, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions\, a large number will focus on AI\, automotive\, memory\, and hardware security. In complement to the paper presentations\, there will be special sessions on hardware security certification\, chiplet integration\, silicon lifecycle management\, computing in memory\, as well as design and test of high-power compound devices and quantum electronics. \nWe are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances. \nITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology. \nThis year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening. \nLast\, but not least\, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time\, expertise\, and enthusiasm. Without their hard work and dedication\, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future. \nITC is the premier event for networking\, where professionals from all over the world converge to sharpen skills\, exchange ideas and do business. Join us\, throughout the conference\, for networking activities and to unwind. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/itc-2024/ LOCATION:Hilton San Diego Bayfront\, 1 Park Blvd\, San Diego\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241027T080000 DTEND;TZID=America/New_York:20241031T170000 DTSTAMP:20240925T172254Z CREATED:20240925T172254Z LAST-MODIFIED:20240925T172254Z UID:8353-1730016000-1730394000@marketingeda.com SUMMARY:ICCAD 2024 DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-2024/ LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20241025T093000 DTEND;TZID=Asia/Tokyo:20241025T173000 DTSTAMP:20241008T162227Z CREATED:20241008T162227Z LAST-MODIFIED:20241008T162227Z UID:8394-1729848600-1729877400@marketingeda.com SUMMARY:TSMC OIP Ecosystem Forum Japan 2024 DESCRIPTION:Learn About:\n\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-oip-ecosystem-forum-japan-2024/ LOCATION:Grand Hyatt Tokyo\, 6-10-3\, Roppongi\, Minato-ku\, Tokyo\, Japan CATEGORIES:Conference,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-OIP-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20240805T221745Z CREATED:20240805T221455Z LAST-MODIFIED:20240805T221745Z UID:8202-1729584000-1729702800@marketingeda.com SUMMARY:RISC-V Summit - North America 2024 DESCRIPTION:RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped\, powering new innovations in AI/ML\, wireless\, automotive. data center\, space\, IoT\, embedded and more. Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy a new level of design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis October\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies\, as well as to network and build relationships. Come be part of the RISC-V movement. \n\n\n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo featuring dozens of community members showcasing their the latest solutions.\n\nIt’s community-curated content\, research and innovation driving the next wave of growth for RISC-V. \nLearn about software\, systems\, development tools\, security\, the latest use cases in key markets and more. It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-north-america-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-US-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20241014T202014Z CREATED:20241014T202014Z LAST-MODIFIED:20241014T202014Z UID:8413-1728979200-1729184400@marketingeda.com SUMMARY:2024 OCP Global Summit DESCRIPTION:The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights\, foster partnerships and showcase cutting-edge advancements in open hardware and software. \nThe 2024 OCP Global Summit theme is “From Ideas to Impact”. This encapsulates the transformative journey at the heart of the Open Compute Project. This year’s theme reflects OCP’s commitment to fostering innovation that transcends theoretical discussions and manifests into real-world solutions. As the pace of technological evolution accelerates and development cycles shorten\, our industry is forced to rapidly respond to emerging trends and needs. By harnessing the collective expertise of our global community\, we turn visionary ideas into groundbreaking technologies that drive openness\, efficiency\, sustainability\, scalability and growth in the data center industry. Our focus honors the relentless pursuit of progress and the profound impact that OCP’s community-driven innovation can achieve. OCP transforms concepts into impactful advancements. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ocp-global-summit/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-OCP-Global-Summit.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20241015T080000 DTEND;TZID=Europe/Berlin:20241016T170000 DTSTAMP:20240130T165521Z CREATED:20240130T165521Z LAST-MODIFIED:20240130T165521Z UID:7564-1728979200-1729098000@marketingeda.com SUMMARY:DVCon Europe 2024 DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools\, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications\, and demonstrations for the practical use of EDA solutions for electronic design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-europe-2024/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241008T080000 DTEND;TZID=America/Los_Angeles:20241011T170000 DTSTAMP:20240926T000653Z CREATED:20240906T174011Z LAST-MODIFIED:20240926T000653Z UID:8301-1728374400-1728666000@marketingeda.com SUMMARY:PCB West 2024 DESCRIPTION:For more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pcb-west-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20241008T080000 DTEND;TZID=Europe/Madrid:20241010T170000 DTSTAMP:20240923T170650Z CREATED:20240923T170650Z LAST-MODIFIED:20240923T170650Z UID:8345-1728374400-1728579600@marketingeda.com SUMMARY:AutoSens Europe 2024 DESCRIPTION:Join us as we embark on an exciting new journey in the vibrant city of Barcelona!\n\n\n\n\nFrom 8-10 October 2024\, we will unite the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV. \nExpect over 60 expert speakers\, engaging panels\, technical case studies\, and exploration of 12 key themes. Dive into an exhibition with cutting-edge demos from sensor and computer vision leaders. \nDon’t miss AutoSens Europe 2024 in Barcelona – the future of sensing tech awaits! \n\n\nDiscover the latest technology\n\n\n\n\nFrom innovative start-ups to industry giants\, the AutoSens exhibition floor is where our community comes together to make key connections over coffee\, have critical conversations in our igloo meeting pods\, and negotiate new partnerships over drinks at our networking sessions. \nRegister now to make the most of:\n\n\n\nAccess to an expert community of over 500 experts and engineers \n\n\n\n\n\nExtensive exhibition with over 50 stands showcasing the latest technology\n\n\n\n\n\n\n\nVehicle demos from leading Tier 1 and systems companies\n\n\n\n\n\n\n\nHigh quality technical presentations from genuine experts\n\n\n\n\n\n\n\nThought-leader panel discussions that shape the industry’s future direction\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/autosens-europe-2024/ LOCATION:Palau de Congressos\, Av. de la Reina Maria Cristina\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241002T080000 DTEND;TZID=Asia/Taipei:20241002T170000 DTSTAMP:20240826T192110Z CREATED:20240826T192110Z LAST-MODIFIED:20240826T192110Z UID:8276-1727856000-1727888400@marketingeda.com SUMMARY:Memory Users Conference 2024 - China\, Taiwan DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024-china-taiwan/ LOCATION:CA CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T080000 DTEND;TZID=America/Los_Angeles:20241001T120000 DTSTAMP:20240826T192125Z CREATED:20240826T191744Z LAST-MODIFIED:20240826T192125Z UID:8273-1727769600-1727784000@marketingeda.com SUMMARY:Memory Users Conference 2024 DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024/ LOCATION:CA CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240925T080000 DTEND;TZID=America/Los_Angeles:20240927T170000 DTSTAMP:20240612T170503Z CREATED:20240612T170425Z LAST-MODIFIED:20240612T170503Z UID:8093-1727251200-1727456400@marketingeda.com SUMMARY:SISPAD 2024 DESCRIPTION:The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of leading-edge research and development in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. \nSISPAD2024 will be held in person in San José\, USA from September 25-27\, 2024. A technical workshop will be offered on September 24\, 2024. Details on the invited speakers\, technical program and workshop will be posted here as soon as they are available. There are slots still available for tutorials or workshop sessions for September 24\, please reach out to us if you are interested in organizing one. \nLooking forward to seeing you all in San José! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/sispad-2024/ LOCATION:The Westin San Jose\, 302 S Market Street\, San Jose\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SISPAD-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240918T080000 DTEND;TZID=Asia/Kolkata:20240919T170000 DTSTAMP:20240807T162934Z CREATED:20240807T162703Z LAST-MODIFIED:20240807T162934Z UID:8215-1726646400-1726765200@marketingeda.com SUMMARY:DVCon India 2024 DESCRIPTION:On behalf of the DVCon India 2024 steering committee\, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore\, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. \nWe want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an Awards Night\, which saw an amazing response last year. \nOn behalf of the DVCon India 2024 steering committee\, it gives me immense pleasure to extend a warm welcome to each and every one of you to the 9th edition of the Design and Verification Conference in India. Set to unfold from the 18th to 19th of September 2024 in the vibrant city of Bangalore\, India\, this conference promises to be a pinnacle of innovation\, collaboration and insight. \nAs we embark on this journey\, we are fuelled by the electrifying momentum\, the techno-genius excitement and the enthusiasm that characterized last year’s edition of DVCon India. Our goal for DVCon India 2024 is clear: to build upon the successes of the past and propel the conference to even greater heights. \nThis year\, our focus is laser-sharp: we aim to demystify the essence of DVCon. While some may perceive it solely as a Digital Verification Conference\, DVCon embodies much more—it encapsulates the entire spectrum of Design and Verification\, spanning from Architecture and Design to Post Silicon Validation. \nTo ensure that this message resonates loud and clear across our community\, we have formed dedicated focus groups in pivotal areas: \n\nSystem and IP level modelling\, Virtual Prototyping & ESL\nArchitecture and Design\nRISC-V and its ecosystem\nAnalog and Mixed-Signal Design and Verification and\nPost Silicon Validation.\n\nThrough these specialized groups\, we seek to foster deeper understanding\, facilitate meaningful dialogue and foster inclusive participation. \nFurthermore\, in our relentless pursuit of excellence\, we are expanding our Technical Program Committee and implementing structural enhancements to optimize the participant experience. These changes underscore our commitment to delivering value-driven content and enriching interactions. \nWe extend an open invitation to the entire technical fraternity to actively engage\, collaborate and share insights at DVCon India 2024. Your collective expertise\, passion\, and dedication are instrumental in shaping the success of this conference\, and we eagerly anticipate your invaluable contributions. \nTogether\, let us ignite the spirit of Designnovation\, celebrate the power of collaboration and chart a path towards a future defined by excellence. \nWelcome to DVCon India 2024—a platform where ideas converge\, innovations thrive\, and possibilities abound. \nHere’s to a resounding success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2024 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-india-2024/ LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240917T080000 DTEND;TZID=Asia/Tokyo:20240917T170000 DTSTAMP:20240823T182503Z CREATED:20240823T182145Z LAST-MODIFIED:20240823T182503Z UID:8269-1726560000-1726592400@marketingeda.com SUMMARY:IP-SoC Japan 24 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-japan-24/ LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20240913T080000 DTEND;TZID=Europe/Stockholm:20240915T170000 DTSTAMP:20240717T214406Z CREATED:20240717T214315Z LAST-MODIFIED:20240717T214406Z UID:8159-1726214400-1726419600@marketingeda.com SUMMARY:ORConf 2024 DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2024/ LOCATION:Gothenburg\, Gothenburg\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240912T080000 DTEND;TZID=Asia/Shanghai:20240912T170000 DTSTAMP:20240605T173645Z CREATED:20240605T173645Z LAST-MODIFIED:20240605T173645Z UID:8079-1726128000-1726160400@marketingeda.com SUMMARY:D&R IP-SoC China 2024 Day DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/ LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20240912T080000 DTEND;TZID=America/Chicago:20240912T170000 DTSTAMP:20240409T162326Z CREATED:20240409T162326Z LAST-MODIFIED:20240409T162326Z UID:7817-1726128000-1726160400@marketingeda.com SUMMARY:Verification Futures Conference 2024 Austin DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \nWe have the first speaker details on CPU User Presentations \nAccelerating RISC-V testbench development with open source RISC-V RTL and emulation\n– Varun Koyyalagunta\, Design Verification Engineer\, Tenstorrent\nToday’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also\, we should have all test collaterals ready to go\, which involves firmware\, drivers\, applications etc. \nAt Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface\, AXI\, standard instruction interface\, RISC-V Formal Interface (RVFI)\, and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready\, we could be able to replace our custom CPU RTL with open source CVA-6 processor. \nThis methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this\, we could able to innovate in the area of test collateral creation\, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL. \n3 Key Points  \n·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP \n·       Emulation is a must for software development and function verification \n·       How do we keep DV out of the critical path? \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nPresentation Title Hemendra Talesara (Company Name)\n\n\n\n\n10:15\nUser Top Verification Challenges\n\n\n\n\n10:15\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nCPU User Presentations\n\n\n\n\n11:30\nPresentation Title Mike Thompson (OpenHW Group)\n\n\n\n\n11:50\nAccelerating RISC-V testbench development development with open source RISC-V RTL and emulation \nVarun Koyyalagunta(Tenstorrent)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n14:00\nPresentation Title Speaker Name (Company Name) Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 4 – VHDL Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:30\nEvent Closes\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-austin/ LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Verification-Futures-2024-Austin.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240909T080000 DTEND;TZID=America/Los_Angeles:20240912T170000 DTSTAMP:20240718T193601Z CREATED:20240718T193601Z LAST-MODIFIED:20240718T193601Z UID:8164-1725868800-1726160400@marketingeda.com SUMMARY:AI Hardware & Edge AI Summit 2024 DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com END:VEVENT END:VCALENDAR