BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 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END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Madrid BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Stockholm BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20250309T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20251102T070000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241107T080000 DTEND;TZID=Asia/Taipei:20241109T170000 DTSTAMP:20240522T185455Z CREATED:20240522T185455Z LAST-MODIFIED:20240522T185455Z UID:8022-1730966400-1731171600@marketingeda.com SUMMARY:APCCAS 2024 DESCRIPTION:The APCCAS is a major international forum for researchers\, scientists\, educators\, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including\, but not limited to the following： \n\nArtificial Intelligence Circuits\, Systems\, and Applications\nDigital Integrated Circuits and Systems\nAnalog and Mixed Signal Circuits and Systems\nPower and Energy Circuits and Systems\nBiomedical Circuits and Systems\nSensory Circuits and Systems\nRF/Communications Circuits and Systems\nBeyond CMOS: Nanoelectronics and Hybrid Systems Integration\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/apccas-2024/ LOCATION:Chang Yung-Fa Foundation\, No. 11\, Zhongshan S. Rd.\, Taipei City\, Taiwan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/APCCAS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241103T080000 DTEND;TZID=America/Los_Angeles:20241108T170000 DTSTAMP:20241004T174855Z CREATED:20241004T174855Z LAST-MODIFIED:20241004T174855Z UID:8376-1730620800-1731085200@marketingeda.com SUMMARY:ITC 2024 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWe are holding the conference in beautiful San Diego\, CA.  We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! \nITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum\, where the wide range of its offerings allows ITC participants to learn\, network and conduct business. This year’s program includes a top-notch technical program\, vibrant exhibitors\, information-packed tutorials\, interactive technical panels\, three workshops\, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions\, a large number will focus on AI\, automotive\, memory\, and hardware security. In complement to the paper presentations\, there will be special sessions on hardware security certification\, chiplet integration\, silicon lifecycle management\, computing in memory\, as well as design and test of high-power compound devices and quantum electronics. \nWe are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances. \nITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology. \nThis year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening. \nLast\, but not least\, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time\, expertise\, and enthusiasm. Without their hard work and dedication\, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future. \nITC is the premier event for networking\, where professionals from all over the world converge to sharpen skills\, exchange ideas and do business. Join us\, throughout the conference\, for networking activities and to unwind. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/itc-2024/ LOCATION:Hilton San Diego Bayfront\, 1 Park Blvd\, San Diego\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241027T080000 DTEND;TZID=America/New_York:20241031T170000 DTSTAMP:20240925T172254Z CREATED:20240925T172254Z LAST-MODIFIED:20240925T172254Z UID:8353-1730016000-1730394000@marketingeda.com SUMMARY:ICCAD 2024 DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-2024/ LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20241025T093000 DTEND;TZID=Asia/Tokyo:20241025T173000 DTSTAMP:20241008T162227Z CREATED:20241008T162227Z LAST-MODIFIED:20241008T162227Z UID:8394-1729848600-1729877400@marketingeda.com SUMMARY:TSMC OIP Ecosystem Forum Japan 2024 DESCRIPTION:Learn About:\n\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-oip-ecosystem-forum-japan-2024/ LOCATION:Grand Hyatt Tokyo\, 6-10-3\, Roppongi\, Minato-ku\, Tokyo\, Japan CATEGORIES:Conference,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-OIP-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20240805T221745Z CREATED:20240805T221455Z LAST-MODIFIED:20240805T221745Z UID:8202-1729584000-1729702800@marketingeda.com SUMMARY:RISC-V Summit - North America 2024 DESCRIPTION:RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped\, powering new innovations in AI/ML\, wireless\, automotive. data center\, space\, IoT\, embedded and more. Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy a new level of design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis October\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies\, as well as to network and build relationships. Come be part of the RISC-V movement. \n\n\n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo featuring dozens of community members showcasing their the latest solutions.\n\nIt’s community-curated content\, research and innovation driving the next wave of growth for RISC-V. \nLearn about software\, systems\, development tools\, security\, the latest use cases in key markets and more. It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-north-america-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-US-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20241014T202014Z CREATED:20241014T202014Z LAST-MODIFIED:20241014T202014Z UID:8413-1728979200-1729184400@marketingeda.com SUMMARY:2024 OCP Global Summit DESCRIPTION:The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights\, foster partnerships and showcase cutting-edge advancements in open hardware and software. \nThe 2024 OCP Global Summit theme is “From Ideas to Impact”. This encapsulates the transformative journey at the heart of the Open Compute Project. This year’s theme reflects OCP’s commitment to fostering innovation that transcends theoretical discussions and manifests into real-world solutions. As the pace of technological evolution accelerates and development cycles shorten\, our industry is forced to rapidly respond to emerging trends and needs. By harnessing the collective expertise of our global community\, we turn visionary ideas into groundbreaking technologies that drive openness\, efficiency\, sustainability\, scalability and growth in the data center industry. Our focus honors the relentless pursuit of progress and the profound impact that OCP’s community-driven innovation can achieve. OCP transforms concepts into impactful advancements. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ocp-global-summit/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-OCP-Global-Summit.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20241015T080000 DTEND;TZID=Europe/Berlin:20241016T170000 DTSTAMP:20240130T165521Z CREATED:20240130T165521Z LAST-MODIFIED:20240130T165521Z UID:7564-1728979200-1729098000@marketingeda.com SUMMARY:DVCon Europe 2024 DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools\, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications\, and demonstrations for the practical use of EDA solutions for electronic design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-europe-2024/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241008T080000 DTEND;TZID=America/Los_Angeles:20241011T170000 DTSTAMP:20240926T000653Z CREATED:20240906T174011Z LAST-MODIFIED:20240926T000653Z UID:8301-1728374400-1728666000@marketingeda.com SUMMARY:PCB West 2024 DESCRIPTION:For more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pcb-west-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20241008T080000 DTEND;TZID=Europe/Madrid:20241010T170000 DTSTAMP:20240923T170650Z CREATED:20240923T170650Z LAST-MODIFIED:20240923T170650Z UID:8345-1728374400-1728579600@marketingeda.com SUMMARY:AutoSens Europe 2024 DESCRIPTION:Join us as we embark on an exciting new journey in the vibrant city of Barcelona!\n\n\n\n\nFrom 8-10 October 2024\, we will unite the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV. \nExpect over 60 expert speakers\, engaging panels\, technical case studies\, and exploration of 12 key themes. Dive into an exhibition with cutting-edge demos from sensor and computer vision leaders. \nDon’t miss AutoSens Europe 2024 in Barcelona – the future of sensing tech awaits! \n\n\nDiscover the latest technology\n\n\n\n\nFrom innovative start-ups to industry giants\, the AutoSens exhibition floor is where our community comes together to make key connections over coffee\, have critical conversations in our igloo meeting pods\, and negotiate new partnerships over drinks at our networking sessions. \nRegister now to make the most of:\n\n\n\nAccess to an expert community of over 500 experts and engineers \n\n\n\n\n\nExtensive exhibition with over 50 stands showcasing the latest technology\n\n\n\n\n\n\n\nVehicle demos from leading Tier 1 and systems companies\n\n\n\n\n\n\n\nHigh quality technical presentations from genuine experts\n\n\n\n\n\n\n\nThought-leader panel discussions that shape the industry’s future direction\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/autosens-europe-2024/ LOCATION:Palau de Congressos\, Av. de la Reina Maria Cristina\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241002T080000 DTEND;TZID=Asia/Taipei:20241002T170000 DTSTAMP:20240826T192110Z CREATED:20240826T192110Z LAST-MODIFIED:20240826T192110Z UID:8276-1727856000-1727888400@marketingeda.com SUMMARY:Memory Users Conference 2024 - China\, Taiwan DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024-china-taiwan/ LOCATION:NV CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T080000 DTEND;TZID=America/Los_Angeles:20241001T120000 DTSTAMP:20240826T192125Z CREATED:20240826T191744Z LAST-MODIFIED:20240826T192125Z UID:8273-1727769600-1727784000@marketingeda.com SUMMARY:Memory Users Conference 2024 DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024/ LOCATION:NV CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240925T080000 DTEND;TZID=America/Los_Angeles:20240927T170000 DTSTAMP:20240612T170503Z CREATED:20240612T170425Z LAST-MODIFIED:20240612T170503Z UID:8093-1727251200-1727456400@marketingeda.com SUMMARY:SISPAD 2024 DESCRIPTION:The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of leading-edge research and development in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. \nSISPAD2024 will be held in person in San José\, USA from September 25-27\, 2024. A technical workshop will be offered on September 24\, 2024. Details on the invited speakers\, technical program and workshop will be posted here as soon as they are available. There are slots still available for tutorials or workshop sessions for September 24\, please reach out to us if you are interested in organizing one. \nLooking forward to seeing you all in San José! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/sispad-2024/ LOCATION:The Westin San Jose\, 302 S Market Street\, San Jose\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SISPAD-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240918T080000 DTEND;TZID=Asia/Kolkata:20240919T170000 DTSTAMP:20240807T162934Z CREATED:20240807T162703Z LAST-MODIFIED:20240807T162934Z UID:8215-1726646400-1726765200@marketingeda.com SUMMARY:DVCon India 2024 DESCRIPTION:On behalf of the DVCon India 2024 steering committee\, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore\, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. \nWe want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an Awards Night\, which saw an amazing response last year. \nOn behalf of the DVCon India 2024 steering committee\, it gives me immense pleasure to extend a warm welcome to each and every one of you to the 9th edition of the Design and Verification Conference in India. Set to unfold from the 18th to 19th of September 2024 in the vibrant city of Bangalore\, India\, this conference promises to be a pinnacle of innovation\, collaboration and insight. \nAs we embark on this journey\, we are fuelled by the electrifying momentum\, the techno-genius excitement and the enthusiasm that characterized last year’s edition of DVCon India. Our goal for DVCon India 2024 is clear: to build upon the successes of the past and propel the conference to even greater heights. \nThis year\, our focus is laser-sharp: we aim to demystify the essence of DVCon. While some may perceive it solely as a Digital Verification Conference\, DVCon embodies much more—it encapsulates the entire spectrum of Design and Verification\, spanning from Architecture and Design to Post Silicon Validation. \nTo ensure that this message resonates loud and clear across our community\, we have formed dedicated focus groups in pivotal areas: \n\nSystem and IP level modelling\, Virtual Prototyping & ESL\nArchitecture and Design\nRISC-V and its ecosystem\nAnalog and Mixed-Signal Design and Verification and\nPost Silicon Validation.\n\nThrough these specialized groups\, we seek to foster deeper understanding\, facilitate meaningful dialogue and foster inclusive participation. \nFurthermore\, in our relentless pursuit of excellence\, we are expanding our Technical Program Committee and implementing structural enhancements to optimize the participant experience. These changes underscore our commitment to delivering value-driven content and enriching interactions. \nWe extend an open invitation to the entire technical fraternity to actively engage\, collaborate and share insights at DVCon India 2024. Your collective expertise\, passion\, and dedication are instrumental in shaping the success of this conference\, and we eagerly anticipate your invaluable contributions. \nTogether\, let us ignite the spirit of Designnovation\, celebrate the power of collaboration and chart a path towards a future defined by excellence. \nWelcome to DVCon India 2024—a platform where ideas converge\, innovations thrive\, and possibilities abound. \nHere’s to a resounding success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2024 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-india-2024/ LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240917T080000 DTEND;TZID=Asia/Tokyo:20240917T170000 DTSTAMP:20240823T182503Z CREATED:20240823T182145Z LAST-MODIFIED:20240823T182503Z UID:8269-1726560000-1726592400@marketingeda.com SUMMARY:IP-SoC Japan 24 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-japan-24/ LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20240913T080000 DTEND;TZID=Europe/Stockholm:20240915T170000 DTSTAMP:20240717T214406Z CREATED:20240717T214315Z LAST-MODIFIED:20240717T214406Z UID:8159-1726214400-1726419600@marketingeda.com SUMMARY:ORConf 2024 DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2024/ LOCATION:Gothenburg\, Gothenburg\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240912T080000 DTEND;TZID=Asia/Shanghai:20240912T170000 DTSTAMP:20240605T173645Z CREATED:20240605T173645Z LAST-MODIFIED:20240605T173645Z UID:8079-1726128000-1726160400@marketingeda.com SUMMARY:D&R IP-SoC China 2024 Day DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/ LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20240912T080000 DTEND;TZID=America/Chicago:20240912T170000 DTSTAMP:20240409T162326Z CREATED:20240409T162326Z LAST-MODIFIED:20240409T162326Z UID:7817-1726128000-1726160400@marketingeda.com SUMMARY:Verification Futures Conference 2024 Austin DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \nWe have the first speaker details on CPU User Presentations \nAccelerating RISC-V testbench development with open source RISC-V RTL and emulation\n– Varun Koyyalagunta\, Design Verification Engineer\, Tenstorrent\nToday’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also\, we should have all test collaterals ready to go\, which involves firmware\, drivers\, applications etc. \nAt Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface\, AXI\, standard instruction interface\, RISC-V Formal Interface (RVFI)\, and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready\, we could be able to replace our custom CPU RTL with open source CVA-6 processor. \nThis methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this\, we could able to innovate in the area of test collateral creation\, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL. \n3 Key Points  \n·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP \n·       Emulation is a must for software development and function verification \n·       How do we keep DV out of the critical path? \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nPresentation Title Hemendra Talesara (Company Name)\n\n\n\n\n10:15\nUser Top Verification Challenges\n\n\n\n\n10:15\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nCPU User Presentations\n\n\n\n\n11:30\nPresentation Title Mike Thompson (OpenHW Group)\n\n\n\n\n11:50\nAccelerating RISC-V testbench development development with open source RISC-V RTL and emulation \nVarun Koyyalagunta(Tenstorrent)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n14:00\nPresentation Title Speaker Name (Company Name) Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 4 – VHDL Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:30\nEvent Closes\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-austin/ LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Verification-Futures-2024-Austin.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240909T080000 DTEND;TZID=America/Los_Angeles:20240912T170000 DTSTAMP:20240718T193601Z CREATED:20240718T193601Z LAST-MODIFIED:20240718T193601Z UID:8164-1725868800-1726160400@marketingeda.com SUMMARY:AI Hardware & Edge AI Summit 2024 DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240829T080000 DTEND;TZID=Asia/Tokyo:20240829T170000 DTSTAMP:20240805T220150Z CREATED:20240805T220150Z LAST-MODIFIED:20240805T220150Z UID:8198-1724918400-1724950800@marketingeda.com SUMMARY:DVCon Japan 2024 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \n\n\n\nDVCon Japan 2024 will be held on August 29\, 2024 in Shinagawa\, Tokyo. \nDVCon (Design and Verification Conference) is a conference mainly sponsored by Accellera Systems Initiative. DVCon focuses on solving problems in a wide range of areas such as logic design\, architecture study\, functional verification\, HW/SW co-verification\, analog simulation\, functional safety compliance\, security verification\, and application of AI to development flow in semiconductors and systems\, DVCon is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages\, formats\, and methodologies. \nDVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022\, with online and on-demand delivery in 2022 and in-person in 2023. We were able to offer a diverse and in-depth program with a variety of paper presentations\, tutorial sessions\, and exhibits from sponsors and exhibitors. We would like to thank all the audiences\, presenters\, sponsors\, and all those involved. \nDVCon Japan 2024 will be held at a venue that is only a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning sessions will consist of general sessions and panel discussions\, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies\, SystemVerilog\, UVM\, UPF\, SystemC\, PSS\, formal verification methodologies\, HLS\, AMS\, IP-XACT\, and more\, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees\, presenters and attendees\, sponsors\, and Accellera representatives. I \nWe encourage designers\, engineers\, and managers to attend. We look forward to seeing you there. Finally\, I would like to take this opportunity to thank our Gold and Silver Sponsors and Supporters for their support of the event\, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship. \nDVCon Japan 2023 General Chair : Genichi Tanaka \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-japan-2024/ LOCATION:TKP Garde CIty Premium – Shinagawa Takanawa\, Tokyo\, TKP Garden City Premium\, Tokyo\, Japan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Japan-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240825T080000 DTEND;TZID=America/Los_Angeles:20240827T170000 DTSTAMP:20240712T004207Z CREATED:20240712T004207Z LAST-MODIFIED:20240712T004207Z UID:8141-1724572800-1724778000@marketingeda.com SUMMARY:Hot Chips 2024 DESCRIPTION:Hot Chips 2024 will be held as a hybrid conference with in-person attendance at Memorial Auditorium\, Stanford University from August 25 to 27\, 2024. \nConference Format\nHot Chips 2024 is a hybrid conference. You may register to attend Virtually or In-Person. The In-Person conference is held at Memorial Auditorium\, Stanford University. \n\nTutorials: Sunday\, August 25\nConference: Monday-Tuesday\, August 26-27\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs\, and Slack channels for BOTH tutorial and conference days. All talks are transmitted in real time and are also recorded so they may be viewed later. Details are here. \nIn-Person Conference: Includes all on-line access described above for the Virtual Conference. In addition\, In-Person registration includes breakfast\, lunch\, break snacks and receptions on Sunday and Monday evenings. \nIn-Person registrations options: \n\nConference Days only (includes Sunday evening reception)\nBoth Conference and Tutorial Days\n\nThere is no registration option for the Tutorial Day only nor for single session attendance. \nRegistration Deadlines\nEarly Registration Deadline: 11:59 PM (PDT) Friday\, August 02\, 2024. \nPlease Read: General Registration Policies. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hot-chips-2024/ LOCATION:Memorial Auditorium\, 551 Jane Stanford Way\, Stanford\, CA\, 94305\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/1681617277049-HC-Logo-Trasparent.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240806T080000 DTEND;TZID=America/Los_Angeles:20240808T170000 DTSTAMP:20240729T183004Z CREATED:20240723T173747Z LAST-MODIFIED:20240729T183004Z UID:8167-1722931200-1723136400@marketingeda.com SUMMARY:Future of Memory and Storage - 2024 DESCRIPTION:FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions. The scope of FMS will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/future-of-memory-and-storage-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240721T080000 DTEND;TZID=Asia/Kolkata:20240723T170000 DTSTAMP:20240717T213106Z CREATED:20240717T213106Z LAST-MODIFIED:20240717T213106Z UID:8156-1721548800-1721754000@marketingeda.com SUMMARY:ITC India 2024 DESCRIPTION:International Test Conference is the world’s premier venue dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, design-for-test\, design-for-manufacturing\, silicon debug\, manufacturing test\, system test\, diagnosis\, reliability and failure analysis\, and back to process and design improvement. \n\n\n\n\nAt ITC India\, design\, test\, and yield professionals can confront challenges faced by the industry\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \n\n\n\n\nThe 2024 ITC India conference is happening at The Radisson Blu Hotel\, Outer Ring Road\, Bengaluru on 21 to 23 July\, 2024. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/itc-india-2024/ LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240715T080000 DTEND;TZID=America/Los_Angeles:20240719T170000 DTSTAMP:20240710T171300Z CREATED:20240710T170314Z LAST-MODIFIED:20240710T171300Z UID:8125-1721030400-1721408400@marketingeda.com SUMMARY:IEEE SMC-IT/SCC 2024 DESCRIPTION:The International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers\, engineers\, computer architects\, scientists\, practitioners\, and space explorers with the objective of advancing information technology\, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange on all hardware and software aspects of space missions. The joint conferences will focus on current systems practice and challenges as well as emerging hardware and software technologies with applicability for future space missions. \nSystems in all aspects of the space mission will be explored\, including flight systems\, ground systems\, science data processing\, engineering and development tools\, operations\, telecommunications\, radiation-tolerant computing devices\, reliable electronics\, space-qualifiable packaging technologies. The entire information systems lifecycle of the mission development will also be covered\, such as conceptual design\, engineering tools development\, integration and test\, operations\, science analysis\, quality control. \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-smc-it-scc-2024/ LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SMC-ITSCC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240709T080000 DTEND;TZID=America/Los_Angeles:20240711T170000 DTSTAMP:20240327T191153Z CREATED:20240327T191111Z LAST-MODIFIED:20240327T191153Z UID:7778-1720512000-1720717200@marketingeda.com SUMMARY:Semicon West 2024 DESCRIPTION:SEMICON West 2024 is North America’s premier conference and exhibition that gathers the incredibly diverse global electronics supply chain together to address the semiconductor ecosystem’s greatest opportunities and changes. Join industry leaders\, experts\, and visionaries at the Moscone Center\, San Francisco\, CA from July 9–11. \nJoin us to explore groundbreaking technologies transforming the microelectronics sector and enabling smart applications. This is the perfect opportunity for top minds and manufacturers to connect\, collaborate\, innovate\, and STRONGER TOGETHER we’ll unite in our journey towards the $1T milestone! \nPrograms + Events\n\n– CEO Summit/Keynotes\n– Market Trends & Data\n– Sustainability\n– TechTALKS\n– SEMI U—Workshops\n– Test Vision Symposium\n– Smart Manufacturing\, MedTech + Mobility\n– WFD—Workforce Development\n– FLEX Conference & Exhibition\nAnd much more! \nNetworking + Activations\n\n– Lively Receptions\n– Networking Lounges\n– Beer & Wine Garden\n– Award Ceremonies\n– SEMI Booth + SEMI U\n– Private Meeting Rooms\n– Taste of San Francisco\n– Food Truck Fare\n– Media Hub\nAnd much more! \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/semicon-west-2024/ LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semicon-West-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240702T080000 DTEND;TZID=Europe/Berlin:20240704T170000 DTSTAMP:20240628T211817Z CREATED:20240628T211817Z LAST-MODIFIED:20240628T211817Z UID:8111-1719907200-1720112400@marketingeda.com SUMMARY:FPGA Conference Europe DESCRIPTION:The FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is Europe’s leading specialist conference for programmable logic devices. The conference focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. \n\n\n\n\n\n\n\n\nIn increasingly AI-driven cloud data centres\, in telecommunications and many other high-performance applications\, Field Programmable Gate Arrays (FPGA) have proven themselves as flexible and powerful accelerator solutions for a wide range of tasks. \n\n\n\n\n\n\n\n\nFPGAs – The hidden champions of microelectronics\n\n\nFrom tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed during the FPGA Conference Europe in Munich. \n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-conference-europe-2/ LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/fpga-conference-europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240623T080000 DTEND;TZID=America/Los_Angeles:20240627T170000 DTSTAMP:20240327T200918Z CREATED:20240327T194239Z LAST-MODIFIED:20240327T200918Z UID:7782-1719129600-1719507600@marketingeda.com SUMMARY:DAC 2024 DESCRIPTION:The premier event for the design and design automation of electronic chips to systems. \nAutonomous Systems\nElectronics content in modern autonomous systems (e.g.\, automotive\, robotics\, drones\, etc.) is growing at an increasingly rapid pace. Nearly every aspect of these complex systems uses smart electronics and embedded software to make our experiences safer\, more energy-efficient and enjoyable. For example\, premium vehicles can have several million lines of embedded software code running on hundreds of electronic control units. Within autonomous systems\, such as automotive\, these sub systems connect with one another by in-system networks. As the trend towards fully autonomous driving and connectivity accelerates\, the ability to deliver these innovations depends more than ever on advanced electronics and software development. \nDesign\nDAC has served as a meeting place for designers of electronic systems and providers of electronic design automation tools for over five decades. Increasingly\, the challenges faced by the industry require cross-domain interaction of researchers and practitioners working on electronic design (circuit\, architecture\, and embedded systems design) and researchers working on design methodologies and tools. DAC serves this need by covering design as a topic area in the research track\, in addition to organizing a dedicated designer track for practitioners. \nThe design topics covered in the research track include the design of cyber-physical\, SoC architectures\, accelerator-based computing\, emerging models of computation such as brain-inspired and quantum computing\, digital and analog circuits\, and emerging device technologies. \nSeparately the Designer Track allows tool users to share challenges and benefits of different tools\, flows\, and methodologies. In addition\, it provides excellent opportunities for education and networking between end users and tool developers. There is no other way to improve your “design IQ” in such a short amount of time than to attend the Designer Track. \nElectronic Design Automation\nEDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power\, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades\, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems. \nIn addition to the traditional EDA topics ranges from physical design to system architectures\, DAC features high-quality papers on design research\, design practices\, and design automation for cross-cutting topics including low-power\, reliability\, multicore/application specific/heterogeneous architectures\, 3-D integrations\, emerging device technologies\, design automation of “things”\, and their applications. DAC’s EDA technical program has been ensuring the best-in-class solutions that promise to advance EDA. \nEmbedded Systems & Software (ESS)\nEmbedded system design is the art of choosing and designing the proper combination of hardware and software components to achieve system level design goals like speed\, efficiency\, reliability\, security\, and safety. Embedded systems are an increasingly diverse\, disruptive\, and challenging field for designs ranging from mobile devices\, medical devices\, automotive\, robotics\, drones\, industrial and beyond. Embedded software is built into devices that may not necessarily be recognized as computing devices (e.g.\, thermostats\, toys\, defibrillators\, and anti-lock brakes)\, but nevertheless controls the functionality and perceived quality of these devices. \nThe ESS sessions at DAC provide a forum for discussing the challenges of embedded design and an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nAI\nArtificial intelligence (AI) program highlights the advances in the field with a focus on design and design automation at the cross section between AI algorithms and hardware. While artificial intelligence and artificial neural network research has been ongoing for more than half a century\, recent advances in accelerating the pace and scale of machine learning enabled by tensor-flow based gradient optimization in deeply layered convolutional networks (convnets) are revolutionizing the impact of artificial intelligence on every aspect of our daily lives\, ranging from smart consumer electronics and services to self-navigating cars and personalized medicine. \nThe advances in deep learning are fueled by computing architectures tailored to the distributed nature of learning and inference in neural networks\, akin to the distributed nature of neural information processing and synaptic plasticity in the biological brain. Neuromorphic brain-inspired electronics for AI aim at porting the brain’s efficacy\, efficiency\, and resilience to noise and variability to electronic equivalents in standard CMOS and emerging technologies\, offering new design challenges and opportunities to advance computing architecture beyond Moore’s law scaling limits. \nThe AI sessions at DAC focuses on the fundamentals\, accomplishments to date\, and challenges ahead in ML/AI hardware system design and design automation\, providing a forum for researchers and practitioners across all the widely varying disciplines involved to connect\, engage\, and join in shaping the future of this exciting field. \nIP\nIntellectual Property (IP) is increasingly complex\, diverse\, innovative\, and challenging. The complexity is driven by increasing requirements for higher integration levels that are reusable; the diversity to satisfy varying environmental conditions and constraints dictated by the different target markets. In addition\, the evolution of IP is being driven by innovative architectures to address the latency-power-performance needs of new disruptive applications\, such as machine learning.  The IP challenges are to cope with the complexities of advanced technology nodes. \nIP design is the art of choosing and designing the proper combination of analog\, digital\, RF hardware and software components to achieve sub-system-level design goals like speed\, power\, latency\, efficiency\, reliability\, security\, and safety. EDA tools\, automation and methods are continuously improved to help architect\, develop\, verify and manage the ever more complex IP and IP portfolios. \nThe IP Track sessions at DAC provides a forum for presenting and discussing the challenges of IP development\, verification\, integration and management.  It also provides an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nDesign on Cloud\nSystems and semiconductor companies realize the benefits of the cloud and how designing in the cloud can greatly accelerate their design cycle. Semiconductor design simulation\, verification\, lithography\, metrology\, yield analysis\, and many other workloads benefit from the scalability and performance of cloud design. \nFor all aspects of semiconductor design and manufacturing\, the new era of design in the cloud\, can optimize the process and increase yields. Industrial IoT\, data lake\, analytics\, and machine learning solutions allow you to develop smart factories and products\, provide insights to increase your operational efficiency\, and accelerate your pace of innovation. \nThe Design on Cloud sessions will focus on the aspects mentioned above plus high performance design\, verification\, and smart manufacturing\, supporting electronic design automation (EDA) in the cloud. \nSecurity\nSecurity sessions at DAC address an urgent need to create\, analyze\, evaluate\, and improve the hardware\, embedded systems and software base of the contemporary security solutions. Secure and trustworthy software and hardware components\, platforms and supply chains are vital to all domains including financial\, healthcare\, transportation\, and energy. Security of systems is becoming equally important. A revolution is underway in many industries that are “connecting the unconnected”. \nCyber physical systems\, e.g.\, automobiles\, smart grid\, medical devices\, etc.\, are taking advantage of integration of physical systems with the information systems. Not withstanding the numerous benefits\, these systems are appealing targets of attacks. Attacks on the cyber-part of such systems can have disastrous consequences in the physical world. The scope and variety of attacks on these systems present design challenges that span embedded hardware\, software\, networking\, and system design. \nSecurity topics will be featured through invited special sessions\, panels\, and lecture/poster presentations by both practitioners and researchers to share their knowledge and experience on this evolving environment. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dac-2024/ LOCATION:Moscone West\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC61.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240618T083000 DTEND;TZID=Europe/London:20240618T163000 DTSTAMP:20240404T172034Z CREATED:20240222T180733Z LAST-MODIFIED:20240404T172034Z UID:7680-1718699400-1718728200@marketingeda.com SUMMARY:Verification Futures Conference 2024 UK DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \n  \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nThe Ghosts of Challenges Past\, Present and Future \nAndy Bond (Axelera AI)\n\n\n\n\n10:05\nPresentation Title\, Speaker name ( Company name) – TBC\n\n\n\n\n10:20\nChallenges of Developing Silicon for Automotive \nDarren Galpin(UniSemi Power)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Cadence) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser presentations on Formal Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Lubis EDA) – Start – up Sponsor\n\n\n\n\n11:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 1 – TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification- TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Synopsys) – Platinum Sponsor (Keynote Speaker)\n\n\n\n\n14:00\nPresentation Title Speaker Name (Breker Verification Systems) – Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name) – Gold Sponsor\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Tom (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 2- TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification – TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 4 – UVM for MS Verification\n\n\n\n\n15:30\nPeter Grove (Renesas)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nA Semi-formal approach to coverage analysis and System-on-Chip debugging\n– Dr. Surinder Sood\, Principal Verification Engineer\, ARM \nThe most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively\, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios\, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow. \nAnother approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically\, is of the order of hundreds of minutes in many cases. Consequently\, SoC debug\, micro-architectural analysis\, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism. \nThis mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds\, consequently\, making debugging easy. Moreover\, this solution comes with a package of many allied benefits\, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios\, as well as a significant improvement in coverage analysis. \n3 Key Points  \n\nLinear Temporal logic\nFormal verification\nSystem on Chips\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-uk-2/ LOCATION:NV CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2024-UK.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240616T080000 DTEND;TZID=America/New_York:20240621T170000 DTSTAMP:20240528T171711Z CREATED:20240528T171711Z LAST-MODIFIED:20240528T171711Z UID:8056-1718524800-1718989200@marketingeda.com SUMMARY:International Microwave Symposium - IMS 2024 DESCRIPTION:We welcome you to IMS2024 in Washington D.C. The last time D.C. hosted IMS was in 1980. Our industry\, IMS and the city had a lot of changes in the last 44 years! \n\nD.C. is a kaleidoscope of tastes\, flavors\, sounds and sights. From Georgetown’s cobblestone streets and historic houses to the Wharf’s sleek new restaurants and funky music venues\, the District’s many neighborhoods have an identity all their own. Away from the political headlines of the day\, the American capital is throbbing with energy. Whether you’re sleeping blocks away from the White House or dining within the same walls that have hosted leaders from around the world\, Washington will not disappoint you. \nWashington D.C. is the nation’s capital and named after one of the USA’s founding fathers\, George Washington. George Washington later became the first president of the United States. Even today\, Washington\, the city\, is not part of border states\, Maryland\, nor Virginia. It is its own district. The district is called the District of Columbia. Columbia being the female personification of this nation\, hence Washington D.C. \nWashington\, D.C.\, was a planned city\, and many of the District’s street grids were developed in that initial plan. In 1791\, President George Washington commissioned Pierre (Peter) Charles L’Enfant\, a French-born architect and city planner\, to design the new capital\, and enlisted Scottish surveyor Alexander Ralston to help lay out the city plan. The L’Enfant Plan featured broad streets and avenues radiating out from rectangles\, providing room for open space and landscaping. L’Enfant based his design on plans of other major world cities\, including Paris\, Amsterdam\, Karlsruhe\, and Milan. \nIn June\, the weather in D.C. averages a high of 85°F (29°C) and a low of 63°F (17°C). Expect rain once every 3-4 days. We hope you take in the sights\, sounds and smells of D.C. Perhaps join us for a 5k fun run/walk around the city monuments! \nWe also want you to experience the museums in addition to the monuments. Some of our classic social events will take place in prized venues. International Spy Museum\, National Museum of the American Indian\, and National Museum of African American History and Culture all host IMS events. \nMake no mistake! We will get down to business at IMS. We expect to have participation from industry\, government and academia. We are engaged with ARL\, DARPA\, NASA-Goddard\, NRL\, NRO\, NIST\, NSWC\, and ONR to name a few. A number of aerospace and defense companies have offices or facilities in the local area\, for example BAE\, Boeing\, Chemring Sensors\, Collins Aerospace\, DRS\, General Dynamics\, Hughes Networks\, Intelsat\, iDirect\, L3Harris\, Ligado Networks\, Lockheed Martin\, Northrop Grumman\, Orbital ATK\, Raytheon\, Thales Defense and Security\, and ViaSat. \nPlease join us for an IMS you cannot afford to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-microwave-symposium-ims-2024/ LOCATION:Walter E. Washington Convention Center\, 801 Allen Y. Lew Place\, Washington\, DC\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240616T080000 DTEND;TZID=America/Los_Angeles:20240620T170000 DTSTAMP:20240226T234257Z CREATED:20240226T234257Z LAST-MODIFIED:20240226T234257Z UID:7693-1718524800-1718902800@marketingeda.com SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/ LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240612T080000 DTEND;TZID=America/Los_Angeles:20240613T170000 DTSTAMP:20240522T150924Z CREATED:20240522T150924Z LAST-MODIFIED:20240522T150924Z UID:8019-1718179200-1718298000@marketingeda.com SUMMARY:PCI-SIG 2024 DESCRIPTION:The PCI-SIG Developers Conference 2024 returned to Santa Clara on June 12-13\, 2024! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers attended this event. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nThe presentations were captured on video and are available to all members. These recordings provide a valuable opportunity to those who were unable to attend the event and for those who want to re-experience the presentations for more in-depth learning. \nAttendee Registration – Open Now!\nOnline attendee registration is open. All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting\nThe PCI-SIG Annual Meeting will be held on June 12th\, 2024. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nPCI Board Panel \nFollowing a positive response from last year’s panel\, we will be holding another Board Panel at this year’s US DevCon. We are currently accepting questions from members for the Board of Directors to address during the panel discussion. If you have a question you would like to submit\, please email them to pcidevcon@pcisig.com. \nCall for Papers – Closed\nYou will not want to miss this series of presentations as PCI-SIG members present unique tips\, tricks\, and pitfalls learned during their implementation of PCI technology. \nIf you are interested in submitting an abstract for consideration\, we encourage you to review the online Call for Papers instructions and milestones.  \n*Note that registering and submitting materials does not guarantee you will be selected as a speaker at this event. We will follow up with those selected following the associated deadlines and provide notice to those not chosen.  \nSponsorship Registration – Closed\nPCI-SIG member companies will have the opportunity to demonstrate their company’s industry leadership in advancing the PCI landscape by participating as a Sponsor of the PCI-SIG DevCon 2024. Sponsor opportunities offer a variety of benefits including onsite presence and logo promotion. \nTo review sponsor opportunities\, please visit the PCI-SIG Sponsor Opportunities web page. \nConnect with us on LinkedIn and Twitter @pci_sig #PCISIGDevCon24 \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pci-sig-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCI-SIG-2024.jpg END:VEVENT END:VCALENDAR