BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Stockholm BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET 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TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Brussels BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240918T080000 DTEND;TZID=Asia/Kolkata:20240919T170000 DTSTAMP:20240807T162934Z CREATED:20240807T162703Z LAST-MODIFIED:20240807T162934Z UID:8215-1726646400-1726765200@marketingeda.com SUMMARY:DVCon India 2024 DESCRIPTION:On behalf of the DVCon India 2024 steering committee\, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore\, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. \nWe want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an Awards Night\, which saw an amazing response last year. \nOn behalf of the DVCon India 2024 steering committee\, it gives me immense pleasure to extend a warm welcome to each and every one of you to the 9th edition of the Design and Verification Conference in India. Set to unfold from the 18th to 19th of September 2024 in the vibrant city of Bangalore\, India\, this conference promises to be a pinnacle of innovation\, collaboration and insight. \nAs we embark on this journey\, we are fuelled by the electrifying momentum\, the techno-genius excitement and the enthusiasm that characterized last year’s edition of DVCon India. Our goal for DVCon India 2024 is clear: to build upon the successes of the past and propel the conference to even greater heights. \nThis year\, our focus is laser-sharp: we aim to demystify the essence of DVCon. While some may perceive it solely as a Digital Verification Conference\, DVCon embodies much more—it encapsulates the entire spectrum of Design and Verification\, spanning from Architecture and Design to Post Silicon Validation. \nTo ensure that this message resonates loud and clear across our community\, we have formed dedicated focus groups in pivotal areas: \n\nSystem and IP level modelling\, Virtual Prototyping & ESL\nArchitecture and Design\nRISC-V and its ecosystem\nAnalog and Mixed-Signal Design and Verification and\nPost Silicon Validation.\n\nThrough these specialized groups\, we seek to foster deeper understanding\, facilitate meaningful dialogue and foster inclusive participation. \nFurthermore\, in our relentless pursuit of excellence\, we are expanding our Technical Program Committee and implementing structural enhancements to optimize the participant experience. These changes underscore our commitment to delivering value-driven content and enriching interactions. \nWe extend an open invitation to the entire technical fraternity to actively engage\, collaborate and share insights at DVCon India 2024. Your collective expertise\, passion\, and dedication are instrumental in shaping the success of this conference\, and we eagerly anticipate your invaluable contributions. \nTogether\, let us ignite the spirit of Designnovation\, celebrate the power of collaboration and chart a path towards a future defined by excellence. \nWelcome to DVCon India 2024—a platform where ideas converge\, innovations thrive\, and possibilities abound. \nHere’s to a resounding success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2024 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-india-2024/ LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240917T080000 DTEND;TZID=Asia/Tokyo:20240917T170000 DTSTAMP:20240823T182503Z CREATED:20240823T182145Z LAST-MODIFIED:20240823T182503Z UID:8269-1726560000-1726592400@marketingeda.com SUMMARY:IP-SoC Japan 24 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-japan-24/ LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20240913T080000 DTEND;TZID=Europe/Stockholm:20240915T170000 DTSTAMP:20240717T214406Z CREATED:20240717T214315Z LAST-MODIFIED:20240717T214406Z UID:8159-1726214400-1726419600@marketingeda.com SUMMARY:ORConf 2024 DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2024/ LOCATION:Gothenburg\, Gothenburg\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240912T080000 DTEND;TZID=Asia/Shanghai:20240912T170000 DTSTAMP:20240605T173645Z CREATED:20240605T173645Z LAST-MODIFIED:20240605T173645Z UID:8079-1726128000-1726160400@marketingeda.com SUMMARY:D&R IP-SoC China 2024 Day DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/ LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20240912T080000 DTEND;TZID=America/Chicago:20240912T170000 DTSTAMP:20240409T162326Z CREATED:20240409T162326Z LAST-MODIFIED:20240409T162326Z UID:7817-1726128000-1726160400@marketingeda.com SUMMARY:Verification Futures Conference 2024 Austin DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \nWe have the first speaker details on CPU User Presentations \nAccelerating RISC-V testbench development with open source RISC-V RTL and emulation\n– Varun Koyyalagunta\, Design Verification Engineer\, Tenstorrent\nToday’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also\, we should have all test collaterals ready to go\, which involves firmware\, drivers\, applications etc. \nAt Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface\, AXI\, standard instruction interface\, RISC-V Formal Interface (RVFI)\, and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready\, we could be able to replace our custom CPU RTL with open source CVA-6 processor. \nThis methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this\, we could able to innovate in the area of test collateral creation\, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL. \n3 Key Points  \n·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP \n·       Emulation is a must for software development and function verification \n·       How do we keep DV out of the critical path? \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nPresentation Title Hemendra Talesara (Company Name)\n\n\n\n\n10:15\nUser Top Verification Challenges\n\n\n\n\n10:15\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nCPU User Presentations\n\n\n\n\n11:30\nPresentation Title Mike Thompson (OpenHW Group)\n\n\n\n\n11:50\nAccelerating RISC-V testbench development development with open source RISC-V RTL and emulation \nVarun Koyyalagunta(Tenstorrent)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n14:00\nPresentation Title Speaker Name (Company Name) Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 4 – VHDL Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:30\nEvent Closes\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-austin/ LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Verification-Futures-2024-Austin.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240909T080000 DTEND;TZID=America/Los_Angeles:20240912T170000 DTSTAMP:20240718T193601Z CREATED:20240718T193601Z LAST-MODIFIED:20240718T193601Z UID:8164-1725868800-1726160400@marketingeda.com SUMMARY:AI Hardware & Edge AI Summit 2024 DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240829T080000 DTEND;TZID=Asia/Tokyo:20240829T170000 DTSTAMP:20240805T220150Z CREATED:20240805T220150Z LAST-MODIFIED:20240805T220150Z UID:8198-1724918400-1724950800@marketingeda.com SUMMARY:DVCon Japan 2024 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \n\n\n\nDVCon Japan 2024 will be held on August 29\, 2024 in Shinagawa\, Tokyo. \nDVCon (Design and Verification Conference) is a conference mainly sponsored by Accellera Systems Initiative. DVCon focuses on solving problems in a wide range of areas such as logic design\, architecture study\, functional verification\, HW/SW co-verification\, analog simulation\, functional safety compliance\, security verification\, and application of AI to development flow in semiconductors and systems\, DVCon is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages\, formats\, and methodologies. \nDVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022\, with online and on-demand delivery in 2022 and in-person in 2023. We were able to offer a diverse and in-depth program with a variety of paper presentations\, tutorial sessions\, and exhibits from sponsors and exhibitors. We would like to thank all the audiences\, presenters\, sponsors\, and all those involved. \nDVCon Japan 2024 will be held at a venue that is only a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning sessions will consist of general sessions and panel discussions\, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies\, SystemVerilog\, UVM\, UPF\, SystemC\, PSS\, formal verification methodologies\, HLS\, AMS\, IP-XACT\, and more\, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees\, presenters and attendees\, sponsors\, and Accellera representatives. I \nWe encourage designers\, engineers\, and managers to attend. We look forward to seeing you there. Finally\, I would like to take this opportunity to thank our Gold and Silver Sponsors and Supporters for their support of the event\, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship. \nDVCon Japan 2023 General Chair : Genichi Tanaka \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-japan-2024/ LOCATION:TKP Garde CIty Premium – Shinagawa Takanawa\, Tokyo\, TKP Garden City Premium\, Tokyo\, Japan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Japan-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240825T080000 DTEND;TZID=America/Los_Angeles:20240827T170000 DTSTAMP:20240712T004207Z CREATED:20240712T004207Z LAST-MODIFIED:20240712T004207Z UID:8141-1724572800-1724778000@marketingeda.com SUMMARY:Hot Chips 2024 DESCRIPTION:Hot Chips 2024 will be held as a hybrid conference with in-person attendance at Memorial Auditorium\, Stanford University from August 25 to 27\, 2024. \nConference Format\nHot Chips 2024 is a hybrid conference. You may register to attend Virtually or In-Person. The In-Person conference is held at Memorial Auditorium\, Stanford University. \n\nTutorials: Sunday\, August 25\nConference: Monday-Tuesday\, August 26-27\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs\, and Slack channels for BOTH tutorial and conference days. All talks are transmitted in real time and are also recorded so they may be viewed later. Details are here. \nIn-Person Conference: Includes all on-line access described above for the Virtual Conference. In addition\, In-Person registration includes breakfast\, lunch\, break snacks and receptions on Sunday and Monday evenings. \nIn-Person registrations options: \n\nConference Days only (includes Sunday evening reception)\nBoth Conference and Tutorial Days\n\nThere is no registration option for the Tutorial Day only nor for single session attendance. \nRegistration Deadlines\nEarly Registration Deadline: 11:59 PM (PDT) Friday\, August 02\, 2024. \nPlease Read: General Registration Policies. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hot-chips-2024/ LOCATION:Memorial Auditorium\, 551 Jane Stanford Way\, Stanford\, CA\, 94305\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/1681617277049-HC-Logo-Trasparent.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240806T080000 DTEND;TZID=America/Los_Angeles:20240808T170000 DTSTAMP:20240729T183004Z CREATED:20240723T173747Z LAST-MODIFIED:20240729T183004Z UID:8167-1722931200-1723136400@marketingeda.com SUMMARY:Future of Memory and Storage - 2024 DESCRIPTION:FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions. The scope of FMS will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/future-of-memory-and-storage-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240721T080000 DTEND;TZID=Asia/Kolkata:20240723T170000 DTSTAMP:20240717T213106Z CREATED:20240717T213106Z LAST-MODIFIED:20240717T213106Z UID:8156-1721548800-1721754000@marketingeda.com SUMMARY:ITC India 2024 DESCRIPTION:International Test Conference is the world’s premier venue dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, design-for-test\, design-for-manufacturing\, silicon debug\, manufacturing test\, system test\, diagnosis\, reliability and failure analysis\, and back to process and design improvement. \n\n\n\n\nAt ITC India\, design\, test\, and yield professionals can confront challenges faced by the industry\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \n\n\n\n\nThe 2024 ITC India conference is happening at The Radisson Blu Hotel\, Outer Ring Road\, Bengaluru on 21 to 23 July\, 2024. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/itc-india-2024/ LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240715T080000 DTEND;TZID=America/Los_Angeles:20240719T170000 DTSTAMP:20240710T171300Z CREATED:20240710T170314Z LAST-MODIFIED:20240710T171300Z UID:8125-1721030400-1721408400@marketingeda.com SUMMARY:IEEE SMC-IT/SCC 2024 DESCRIPTION:The International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers\, engineers\, computer architects\, scientists\, practitioners\, and space explorers with the objective of advancing information technology\, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange on all hardware and software aspects of space missions. The joint conferences will focus on current systems practice and challenges as well as emerging hardware and software technologies with applicability for future space missions. \nSystems in all aspects of the space mission will be explored\, including flight systems\, ground systems\, science data processing\, engineering and development tools\, operations\, telecommunications\, radiation-tolerant computing devices\, reliable electronics\, space-qualifiable packaging technologies. The entire information systems lifecycle of the mission development will also be covered\, such as conceptual design\, engineering tools development\, integration and test\, operations\, science analysis\, quality control. \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-smc-it-scc-2024/ LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SMC-ITSCC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240709T080000 DTEND;TZID=America/Los_Angeles:20240711T170000 DTSTAMP:20240327T191153Z CREATED:20240327T191111Z LAST-MODIFIED:20240327T191153Z UID:7778-1720512000-1720717200@marketingeda.com SUMMARY:Semicon West 2024 DESCRIPTION:SEMICON West 2024 is North America’s premier conference and exhibition that gathers the incredibly diverse global electronics supply chain together to address the semiconductor ecosystem’s greatest opportunities and changes. Join industry leaders\, experts\, and visionaries at the Moscone Center\, San Francisco\, CA from July 9–11. \nJoin us to explore groundbreaking technologies transforming the microelectronics sector and enabling smart applications. This is the perfect opportunity for top minds and manufacturers to connect\, collaborate\, innovate\, and STRONGER TOGETHER we’ll unite in our journey towards the $1T milestone! \nPrograms + Events\n\n– CEO Summit/Keynotes\n– Market Trends & Data\n– Sustainability\n– TechTALKS\n– SEMI U—Workshops\n– Test Vision Symposium\n– Smart Manufacturing\, MedTech + Mobility\n– WFD—Workforce Development\n– FLEX Conference & Exhibition\nAnd much more! \nNetworking + Activations\n\n– Lively Receptions\n– Networking Lounges\n– Beer & Wine Garden\n– Award Ceremonies\n– SEMI Booth + SEMI U\n– Private Meeting Rooms\n– Taste of San Francisco\n– Food Truck Fare\n– Media Hub\nAnd much more! \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/semicon-west-2024/ LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semicon-West-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240702T080000 DTEND;TZID=Europe/Berlin:20240704T170000 DTSTAMP:20240628T211817Z CREATED:20240628T211817Z LAST-MODIFIED:20240628T211817Z UID:8111-1719907200-1720112400@marketingeda.com SUMMARY:FPGA Conference Europe DESCRIPTION:The FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is Europe’s leading specialist conference for programmable logic devices. The conference focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. \n\n\n\n\n\n\n\n\nIn increasingly AI-driven cloud data centres\, in telecommunications and many other high-performance applications\, Field Programmable Gate Arrays (FPGA) have proven themselves as flexible and powerful accelerator solutions for a wide range of tasks. \n\n\n\n\n\n\n\n\nFPGAs – The hidden champions of microelectronics\n\n\nFrom tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed during the FPGA Conference Europe in Munich. \n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-conference-europe-2/ LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/fpga-conference-europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240623T080000 DTEND;TZID=America/Los_Angeles:20240627T170000 DTSTAMP:20240327T200918Z CREATED:20240327T194239Z LAST-MODIFIED:20240327T200918Z UID:7782-1719129600-1719507600@marketingeda.com SUMMARY:DAC 2024 DESCRIPTION:The premier event for the design and design automation of electronic chips to systems. \nAutonomous Systems\nElectronics content in modern autonomous systems (e.g.\, automotive\, robotics\, drones\, etc.) is growing at an increasingly rapid pace. Nearly every aspect of these complex systems uses smart electronics and embedded software to make our experiences safer\, more energy-efficient and enjoyable. For example\, premium vehicles can have several million lines of embedded software code running on hundreds of electronic control units. Within autonomous systems\, such as automotive\, these sub systems connect with one another by in-system networks. As the trend towards fully autonomous driving and connectivity accelerates\, the ability to deliver these innovations depends more than ever on advanced electronics and software development. \nDesign\nDAC has served as a meeting place for designers of electronic systems and providers of electronic design automation tools for over five decades. Increasingly\, the challenges faced by the industry require cross-domain interaction of researchers and practitioners working on electronic design (circuit\, architecture\, and embedded systems design) and researchers working on design methodologies and tools. DAC serves this need by covering design as a topic area in the research track\, in addition to organizing a dedicated designer track for practitioners. \nThe design topics covered in the research track include the design of cyber-physical\, SoC architectures\, accelerator-based computing\, emerging models of computation such as brain-inspired and quantum computing\, digital and analog circuits\, and emerging device technologies. \nSeparately the Designer Track allows tool users to share challenges and benefits of different tools\, flows\, and methodologies. In addition\, it provides excellent opportunities for education and networking between end users and tool developers. There is no other way to improve your “design IQ” in such a short amount of time than to attend the Designer Track. \nElectronic Design Automation\nEDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power\, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades\, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems. \nIn addition to the traditional EDA topics ranges from physical design to system architectures\, DAC features high-quality papers on design research\, design practices\, and design automation for cross-cutting topics including low-power\, reliability\, multicore/application specific/heterogeneous architectures\, 3-D integrations\, emerging device technologies\, design automation of “things”\, and their applications. DAC’s EDA technical program has been ensuring the best-in-class solutions that promise to advance EDA. \nEmbedded Systems & Software (ESS)\nEmbedded system design is the art of choosing and designing the proper combination of hardware and software components to achieve system level design goals like speed\, efficiency\, reliability\, security\, and safety. Embedded systems are an increasingly diverse\, disruptive\, and challenging field for designs ranging from mobile devices\, medical devices\, automotive\, robotics\, drones\, industrial and beyond. Embedded software is built into devices that may not necessarily be recognized as computing devices (e.g.\, thermostats\, toys\, defibrillators\, and anti-lock brakes)\, but nevertheless controls the functionality and perceived quality of these devices. \nThe ESS sessions at DAC provide a forum for discussing the challenges of embedded design and an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nAI\nArtificial intelligence (AI) program highlights the advances in the field with a focus on design and design automation at the cross section between AI algorithms and hardware. While artificial intelligence and artificial neural network research has been ongoing for more than half a century\, recent advances in accelerating the pace and scale of machine learning enabled by tensor-flow based gradient optimization in deeply layered convolutional networks (convnets) are revolutionizing the impact of artificial intelligence on every aspect of our daily lives\, ranging from smart consumer electronics and services to self-navigating cars and personalized medicine. \nThe advances in deep learning are fueled by computing architectures tailored to the distributed nature of learning and inference in neural networks\, akin to the distributed nature of neural information processing and synaptic plasticity in the biological brain. Neuromorphic brain-inspired electronics for AI aim at porting the brain’s efficacy\, efficiency\, and resilience to noise and variability to electronic equivalents in standard CMOS and emerging technologies\, offering new design challenges and opportunities to advance computing architecture beyond Moore’s law scaling limits. \nThe AI sessions at DAC focuses on the fundamentals\, accomplishments to date\, and challenges ahead in ML/AI hardware system design and design automation\, providing a forum for researchers and practitioners across all the widely varying disciplines involved to connect\, engage\, and join in shaping the future of this exciting field. \nIP\nIntellectual Property (IP) is increasingly complex\, diverse\, innovative\, and challenging. The complexity is driven by increasing requirements for higher integration levels that are reusable; the diversity to satisfy varying environmental conditions and constraints dictated by the different target markets. In addition\, the evolution of IP is being driven by innovative architectures to address the latency-power-performance needs of new disruptive applications\, such as machine learning.  The IP challenges are to cope with the complexities of advanced technology nodes. \nIP design is the art of choosing and designing the proper combination of analog\, digital\, RF hardware and software components to achieve sub-system-level design goals like speed\, power\, latency\, efficiency\, reliability\, security\, and safety. EDA tools\, automation and methods are continuously improved to help architect\, develop\, verify and manage the ever more complex IP and IP portfolios. \nThe IP Track sessions at DAC provides a forum for presenting and discussing the challenges of IP development\, verification\, integration and management.  It also provides an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nDesign on Cloud\nSystems and semiconductor companies realize the benefits of the cloud and how designing in the cloud can greatly accelerate their design cycle. Semiconductor design simulation\, verification\, lithography\, metrology\, yield analysis\, and many other workloads benefit from the scalability and performance of cloud design. \nFor all aspects of semiconductor design and manufacturing\, the new era of design in the cloud\, can optimize the process and increase yields. Industrial IoT\, data lake\, analytics\, and machine learning solutions allow you to develop smart factories and products\, provide insights to increase your operational efficiency\, and accelerate your pace of innovation. \nThe Design on Cloud sessions will focus on the aspects mentioned above plus high performance design\, verification\, and smart manufacturing\, supporting electronic design automation (EDA) in the cloud. \nSecurity\nSecurity sessions at DAC address an urgent need to create\, analyze\, evaluate\, and improve the hardware\, embedded systems and software base of the contemporary security solutions. Secure and trustworthy software and hardware components\, platforms and supply chains are vital to all domains including financial\, healthcare\, transportation\, and energy. Security of systems is becoming equally important. A revolution is underway in many industries that are “connecting the unconnected”. \nCyber physical systems\, e.g.\, automobiles\, smart grid\, medical devices\, etc.\, are taking advantage of integration of physical systems with the information systems. Not withstanding the numerous benefits\, these systems are appealing targets of attacks. Attacks on the cyber-part of such systems can have disastrous consequences in the physical world. The scope and variety of attacks on these systems present design challenges that span embedded hardware\, software\, networking\, and system design. \nSecurity topics will be featured through invited special sessions\, panels\, and lecture/poster presentations by both practitioners and researchers to share their knowledge and experience on this evolving environment. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dac-2024/ LOCATION:Moscone West\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC61.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240618T083000 DTEND;TZID=Europe/London:20240618T163000 DTSTAMP:20240404T172034Z CREATED:20240222T180733Z LAST-MODIFIED:20240404T172034Z UID:7680-1718699400-1718728200@marketingeda.com SUMMARY:Verification Futures Conference 2024 UK DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \n  \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nThe Ghosts of Challenges Past\, Present and Future \nAndy Bond (Axelera AI)\n\n\n\n\n10:05\nPresentation Title\, Speaker name ( Company name) – TBC\n\n\n\n\n10:20\nChallenges of Developing Silicon for Automotive \nDarren Galpin(UniSemi Power)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Cadence) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser presentations on Formal Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Lubis EDA) – Start – up Sponsor\n\n\n\n\n11:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 1 – TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification- TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Synopsys) – Platinum Sponsor (Keynote Speaker)\n\n\n\n\n14:00\nPresentation Title Speaker Name (Breker Verification Systems) – Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name) – Gold Sponsor\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Tom (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 2- TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification – TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 4 – UVM for MS Verification\n\n\n\n\n15:30\nPeter Grove (Renesas)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nA Semi-formal approach to coverage analysis and System-on-Chip debugging\n– Dr. Surinder Sood\, Principal Verification Engineer\, ARM \nThe most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively\, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios\, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow. \nAnother approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically\, is of the order of hundreds of minutes in many cases. Consequently\, SoC debug\, micro-architectural analysis\, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism. \nThis mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds\, consequently\, making debugging easy. Moreover\, this solution comes with a package of many allied benefits\, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios\, as well as a significant improvement in coverage analysis. \n3 Key Points  \n\nLinear Temporal logic\nFormal verification\nSystem on Chips\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-uk-2/ LOCATION:CA CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2024-UK.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240616T080000 DTEND;TZID=America/New_York:20240621T170000 DTSTAMP:20240528T171711Z CREATED:20240528T171711Z LAST-MODIFIED:20240528T171711Z UID:8056-1718524800-1718989200@marketingeda.com SUMMARY:International Microwave Symposium - IMS 2024 DESCRIPTION:We welcome you to IMS2024 in Washington D.C. The last time D.C. hosted IMS was in 1980. Our industry\, IMS and the city had a lot of changes in the last 44 years! \n\nD.C. is a kaleidoscope of tastes\, flavors\, sounds and sights. From Georgetown’s cobblestone streets and historic houses to the Wharf’s sleek new restaurants and funky music venues\, the District’s many neighborhoods have an identity all their own. Away from the political headlines of the day\, the American capital is throbbing with energy. Whether you’re sleeping blocks away from the White House or dining within the same walls that have hosted leaders from around the world\, Washington will not disappoint you. \nWashington D.C. is the nation’s capital and named after one of the USA’s founding fathers\, George Washington. George Washington later became the first president of the United States. Even today\, Washington\, the city\, is not part of border states\, Maryland\, nor Virginia. It is its own district. The district is called the District of Columbia. Columbia being the female personification of this nation\, hence Washington D.C. \nWashington\, D.C.\, was a planned city\, and many of the District’s street grids were developed in that initial plan. In 1791\, President George Washington commissioned Pierre (Peter) Charles L’Enfant\, a French-born architect and city planner\, to design the new capital\, and enlisted Scottish surveyor Alexander Ralston to help lay out the city plan. The L’Enfant Plan featured broad streets and avenues radiating out from rectangles\, providing room for open space and landscaping. L’Enfant based his design on plans of other major world cities\, including Paris\, Amsterdam\, Karlsruhe\, and Milan. \nIn June\, the weather in D.C. averages a high of 85°F (29°C) and a low of 63°F (17°C). Expect rain once every 3-4 days. We hope you take in the sights\, sounds and smells of D.C. Perhaps join us for a 5k fun run/walk around the city monuments! \nWe also want you to experience the museums in addition to the monuments. Some of our classic social events will take place in prized venues. International Spy Museum\, National Museum of the American Indian\, and National Museum of African American History and Culture all host IMS events. \nMake no mistake! We will get down to business at IMS. We expect to have participation from industry\, government and academia. We are engaged with ARL\, DARPA\, NASA-Goddard\, NRL\, NRO\, NIST\, NSWC\, and ONR to name a few. A number of aerospace and defense companies have offices or facilities in the local area\, for example BAE\, Boeing\, Chemring Sensors\, Collins Aerospace\, DRS\, General Dynamics\, Hughes Networks\, Intelsat\, iDirect\, L3Harris\, Ligado Networks\, Lockheed Martin\, Northrop Grumman\, Orbital ATK\, Raytheon\, Thales Defense and Security\, and ViaSat. \nPlease join us for an IMS you cannot afford to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-microwave-symposium-ims-2024/ LOCATION:Walter E. Washington Convention Center\, 801 Allen Y. Lew Place\, Washington\, DC\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240616T080000 DTEND;TZID=America/Los_Angeles:20240620T170000 DTSTAMP:20240226T234257Z CREATED:20240226T234257Z LAST-MODIFIED:20240226T234257Z UID:7693-1718524800-1718902800@marketingeda.com SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/ LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240612T080000 DTEND;TZID=America/Los_Angeles:20240613T170000 DTSTAMP:20240522T150924Z CREATED:20240522T150924Z LAST-MODIFIED:20240522T150924Z UID:8019-1718179200-1718298000@marketingeda.com SUMMARY:PCI-SIG 2024 DESCRIPTION:The PCI-SIG Developers Conference 2024 returned to Santa Clara on June 12-13\, 2024! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers attended this event. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nThe presentations were captured on video and are available to all members. These recordings provide a valuable opportunity to those who were unable to attend the event and for those who want to re-experience the presentations for more in-depth learning. \nAttendee Registration – Open Now!\nOnline attendee registration is open. All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting\nThe PCI-SIG Annual Meeting will be held on June 12th\, 2024. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nPCI Board Panel \nFollowing a positive response from last year’s panel\, we will be holding another Board Panel at this year’s US DevCon. We are currently accepting questions from members for the Board of Directors to address during the panel discussion. If you have a question you would like to submit\, please email them to pcidevcon@pcisig.com. \nCall for Papers – Closed\nYou will not want to miss this series of presentations as PCI-SIG members present unique tips\, tricks\, and pitfalls learned during their implementation of PCI technology. \nIf you are interested in submitting an abstract for consideration\, we encourage you to review the online Call for Papers instructions and milestones.  \n*Note that registering and submitting materials does not guarantee you will be selected as a speaker at this event. We will follow up with those selected following the associated deadlines and provide notice to those not chosen.  \nSponsorship Registration – Closed\nPCI-SIG member companies will have the opportunity to demonstrate their company’s industry leadership in advancing the PCI landscape by participating as a Sponsor of the PCI-SIG DevCon 2024. Sponsor opportunities offer a variety of benefits including onsite presence and logo promotion. \nTo review sponsor opportunities\, please visit the PCI-SIG Sponsor Opportunities web page. \nConnect with us on LinkedIn and Twitter @pci_sig #PCISIGDevCon24 \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pci-sig-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCI-SIG-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240611T090000 DTEND;TZID=America/Los_Angeles:20240611T170000 DTSTAMP:20240508T184358Z CREATED:20240508T183624Z LAST-MODIFIED:20240508T184358Z UID:7972-1718096400-1718125200@marketingeda.com SUMMARY:2024 ANDES RISC-V CON DESCRIPTION:Recently\, RISC-V\, with its open\, streamlined\, and scalable configuration\, has become the mainstream solution adopted by leading market players\, paving the way for widespread technological innovation. In the RISC-V application field\, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention\, and the need for product information security has also increased. \nAs a Premier member and a leading brand in 32/64-bit embedded CPU cores\, Andes\, a member of RISC-V International\, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends.” The event aims to introduce the market dynamics and development trends of RISC-V\, discuss Andes’ comprehensive product portfolio recently launched\, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities. \nThe seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners\, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts\, paving the way for a diverse application vision! \nHere is our event schedule \n09:00 – 09:25 Registration\n09:25 – 09:30 Opening-Market Watch\, Frankwell Lin\, Chairman & CEO\, Andes Technology\n09:30 – 09:50 Customer Use Case Presentation\n09:50 – 10:25 Unlocking RISC-V’s potential on Intelligence Application Processing\, Dr. Charlie Su\, President & CTO\, Andes Technology\n10:25 – 10:45 Safe and Secure Software Solutions for Andes RISC-V\, Robert Redfield\, Director of Business Development\, Green Hills Software\nGreen Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture\, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills Software’s offering features real-time operating systems\, powerful compilers and advanced C/C++ development tools that leverage the company’s 40-years of microprocessor experience. \n10:45 – 11:05 Lauterbach Debug and Trace of Andes RISC-V Processors\, Dennis Griffiths\, Field Applications Engineer\, Lauterbach\nLauterbach\, the leader in RISC-V debug and trace\, will be discussing and demonstrating the TRACE32 tools for the Andes N27 on the Big Orca reference hardware.Using our TRACE32® tools you can debug and control any RISC-V core (along with all of the other cores) in any SoC via a single debug interface\, all at the same time. TRACE32® tools support real-time on- and off-chip tracing for all major RISC-V trace systems. \n11:05 – 11:35 Break\n11:35 – 11:55 Customer Use Case Presentation\n11:55 – 12:15 Ecosystem Partners Showcase – Siemens EDA\n12:15 – 13:15 Lunch\n13:15 – 14:05 RISC-V Ecosystem Panel: Open-Source is Transforming AI and Hardware\nModerator: Dylan Patel\, Chief Analyst\, SemiAnalysis\nPanelist: Charlie Cheng\, CEO\, Cucina\, Inc.\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\n14:05 – 14:35 Driving Safe and Secure Innovations with Andes RISC-V Solutions\, Andes Technology\n14:35 – 15:05 Break\n15:05 – 15:25 Synopsys Solutions Empower Software Development on Andes Processors\, Larry Lapides\, Business Development Director\, Synopsys\nAndes processor IP is increasingly being used in high performance applications such as AI/ML\, and in use cases where there are reliability\, safety and security requirements. For these and other advanced applications software development is critical. Starting software development early\, before RTL is ready\, can accelerate software tasks by months. Other key pieces of the software task include hardware-software co-verification\, building prototypes and enabling CI/CD software methodology in production. Synopsys tools\, including ImperasFPM fast processor models of the Andes cores\, Virtualizer for virtual prototypes\, and the HAPS and ZeBu hardware-assisted verification tools\, have been supporting and enabling Andes customers for more than 5 years. This talk will discuss software methodology in general\, and provide case studies of Andes-Synopsys joint customers. \n15:25 – 15:45 Are you a professional developer? Then why use amateur tools? Shawn Prestridge\, US FAE Manager\, IAR\nWhat can professional tools bring to a professional developer? Many features that optimize your time\, such as live instruction tracing\, complex and conditional breakpoint types\, functional safety certification\, comprehensive live technical support\, and much more. The optional code analysis tools can also help you quickly spot code issues while you are desk-checking your code to make your code fast and accurate. This session will quickly cover the benefits that each of these features brings in terms of time (and ultimately\, money) savings. Your time isn’t free – optimize it by using tools commensurate with your talent that allow you to deliver your product to market as quickly as possible! \n5:45 – 16:35 RISC-V Ecosystem Panel: Unlocking the RISC-V Application Processor Potential\nThe Application Processor market presents a tens-of-billions annual value opportunity\, which expands by an order of magnitude at the device scope\, and is similarly scaled\, if not more\, at the software application level. The target segments are diverse\, ranging from consumer electronics and industrial computing to automotive\, networking\, and communications. The incumbent compute ISAs for application processors are either Arm or x86\, but RISC-V has emerged as a fast-evolving and maturing alternative\, gaining strong traction across the value chain. This growth is fueled by the advent of AI\, whose support is becoming ubiquitous across all compute platforms\, with RISC-V offering significant value for AI computing. Initiatives like defining and ratifying an iterative set of extensions for the RISC-V application (RVA) profile have established a standard architecture base\, enabling hardware and software vendors to develop interoperable solutions. Efforts by organizations like RISE and major Linux-based and Android-based operating system providers have accelerated the software-based infrastructure support for RISC-V. Despite these advancements\, challenges remain in areas such as ecosystem maturity\, hardware performance and availability\, software compatibility\, and general public perception. This panel discussion will delve into these exciting topics to explore the opportunities\, the progress made\, and how to overcome these challenges to unlock the potential of RISC-V application processors. \nModerator: Mark Himelstein\, Heavenstone\, Inc.\nPanelist: Dr. Charlie Su\, President & CTO\, Andes Technology\nLars Bergstrom\, Director of Engineering\, Android team\, Google\nBarna Ibrahim\, Vice-Chair\, RISE\nDr. Sandro Pinto\, Co-founder\, OSYX Technologies\n16:35 – 17:00 Lucky Draw & Evening Reception \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-andes-risc-v-con/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Zurich:20240606T080000 DTEND;TZID=Europe/Zurich:20240607T170000 DTSTAMP:20240524T163724Z CREATED:20240524T163724Z LAST-MODIFIED:20240524T163724Z UID:8038-1717660800-1717779600@marketingeda.com SUMMARY:International Workshop on Logic and Synthesis - IWLS 2024 DESCRIPTION:The International Workshop on Logic and Synthesis is the premier forum for research in synthesis\, optimization\, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms\, such as nanoscale systems and biological systems\, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development\, without providing complete solutions. The emphasis is on novelty and intellectual rigor. \nTopics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing\, validation\, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling\, analysis\, and synthesis for emerging technologies and platforms are particularly encouraged. \nThe workshop format includes paper presentations\, invited talks\, social lunch and dinner gatherings\, and recreational activities. \nCheck out our call for papers. \nKeynotes\nCan AI Design and Verify Your Design?\nZiyad Hanna\, Cadence Design Systems\, Israel \n\nAbstract: In this talk\, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark\, driven by the rapid growth in key markets in 5G\, Hyperscalers\, autonomous vehicles\, AI\, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge\, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes\, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk\, I will address the inherent challenges in the chip design industry\, analyze the current landscape of automation\, machine learning (ML)\, and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification\, including the automatic generation of programs supported by natural language processing (NLP) and generative AI\, the creation of temporal assertions from design specifications\, the integration of high-level synthesis (HLS) and formal verification\, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance\, power and area. Furthermore\, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. \nZiyad Hanna\, Ph.D.\, is currently a corporate VP at Cadence Design Systems (CDNS)\, and the general manager of Cadence Israel\, leading R&D centers in various countries\, in the electronic design automation domain. Prior to joining Cadence Design Systems\, Dr. Hanna was a Senior VP at Jasper Design Automation\, which was acquired by Cadence in 2014. At Jasper\, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa\, where he was instrumental in the development of several generations of formal verification systems\, which were used on almost all Intel microprocessor designs since early 1990s\, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University\, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence\, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member\, holds over 15 patents\, and has published more than 80 papers and talks.\n\n\nSymmetric Is Better: Can We Exploit Regularities in Logic Synthesis?\nValentina Ciriani\, University of Milano\, Italy \n\nAbstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose\, the algebraic form of the function is manipulated\, as it directly reflects the cost of the corresponding circuit. Depending on the design needs\, different two-level or multi-level forms are considered\, and ad hoc algorithms are used to express and minimize such forms. In all cases\, the functions under consideration encode “real life” problems\, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover\, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally\, we show how regularities can also ease polynomial verification. \nValentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa\, Italy\, in 1998 and 2003\, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa\, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science\, University of Milano\, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures\, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers\, published in international journals\, conference proceedings\, and books chapters.\n\n\n\nToward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?\nLuca Benini\, ETH Zurich / University of Bologna\, Switzerland / Italy \n\nAbstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today\, open-source designs exist targeting a wide range of RISC-V based computing systems\, from tiny microcontrollers to high-performance many-core\, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can\, or even should\, push further\, open sourcing design automation tools and technology libraries\, PDKs\, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories\, drawing from a decade of experience in designing and industrializing open source hardware. \nLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems\, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE\, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award\, the 2020 EDAA achievement Award\, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-workshop-on-logic-and-synthesis-iwls-2024/ LOCATION:ETH Zurich\, Rämistrasse 101\, Zurich\, Switzerland CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWLS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240604T080000 DTEND;TZID=America/Los_Angeles:20240607T170000 DTSTAMP:20240528T161702Z CREATED:20240528T161702Z LAST-MODIFIED:20240528T161702Z UID:8052-1717488000-1717779600@marketingeda.com SUMMARY:PCB East 2024 DESCRIPTION:The Electronics Industry’s East Coast Conference and Exhibition. \n1. Educational opportunities.\nNo matter how experienced you are\, everyone can learn! PCB East is widely acknowledged as the best technical conference in the industry. \n2. Networking with peers.\nCollaboration\, inspiration\, and more! \n3. New vendors and suppliers.\nTools and materials are always changing. Keeping up is paramount. \n4. Position yourself as an expert.\nWhy be the best-kept secret in the industry? \n5. It’s fun!\nAll work and no play gets old and fast. Manage your career growth with a social aspect! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pcb-east-2024/ LOCATION:Boxboro Regency Hotel and Conference Center\, 242 Adams Pl\, Boxborough\, MA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-East-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240603T080000 DTEND;TZID=America/Los_Angeles:20240605T170000 DTSTAMP:20240521T161743Z CREATED:20240521T161743Z LAST-MODIFIED:20240521T161743Z UID:8007-1717401600-1717606800@marketingeda.com SUMMARY:Advantest VOICE 2024 DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \nAdvantest’s annual VOICE Developer Conference is the leading premier forum for the growing international community of users and strategic partners involved with Advantest’s V93000 and T2000 SoC test platforms as well as Advantest memory testers\, handlers and test cell solutions\, product engineering\, and test technology. \nVOICE promises a collaboration of minds and ample opportunities for peer networking. Join us at VOICE for a dynamic and memorable conference experience! \nAttendees gain valuable insights into the newest test solutions and best practices\, forge long-lasting relationships\, learn about the latest and upcoming equipment and technology from Advantest\, and much more through VOICE’s technical information-rich agenda\, which includes: \n\nKeynote speakers\nTechnical paper presentations\nPartners’ Expo\nTechnology Kiosk Showcases\nNetworking\nWorkshop Day\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/advantest-voice-2024/ LOCATION:Hilton La Jolla Torrey Pines\, 10950 N Torrey Pines Rd\, La Jolla\, CA\, United States CATEGORIES:Conference ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VOICE-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240521T080000 DTEND;TZID=America/Los_Angeles:20240523T170000 DTSTAMP:20240327T162206Z CREATED:20240327T162206Z LAST-MODIFIED:20240327T162206Z UID:7771-1716278400-1716483600@marketingeda.com SUMMARY:Embedded Vision Summit 2024 DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy Attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\nJoin us for three days of learning—from tutorials to Deep-Dive Day\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\nFour Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\n\n\nWe’ve been doing this for 13 years.\n\n\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/embedded-vision-summit-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summmit-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240514T100000 DTEND;TZID=America/New_York:20240516T140000 DTSTAMP:20240311T204851Z CREATED:20240311T204851Z LAST-MODIFIED:20240311T204851Z UID:7721-1715680800-1715868000@marketingeda.com SUMMARY:Ansys - Simulation World 2024 DESCRIPTION:Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel\, portable\, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that medical researchers at the University of Zaragoza are relying on multiscale simulation frameworks to model solid tumor growth at the subcellular\, cellular\, tissue\, and organ level to better assess and treat cancer? \nAcross industries\, Ansys customers are using simulation to do some pretty heavy lifting — from electrifying mobility\, to advancing safer medical treatments\, to keeping satellites in orbit\, to name a few. There are few limits to how simulation can be applied. \n\n\n\n\n\n\n\n\nOf course\, all of these innovations have one thing in common. They began with ideas from people just like you\, who\, with the right tools at the right time\, made their industry-changing ideas reality. From May 14-16\, you’ll have the opportunity to hear from many of them during Simulation World 2024\, a virtual event demonstrating how Ansys technologies can put the power of innovation in your hands. \nSimulation World 2024 celebrates our customers’ engineering achievements to inspire you. It connects you with the tools and solvers you need to work smarter\, not harder to test your own theories. And it shows you how Ansys technologies can help you act on your ideas to make your breakthrough ideas reality. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDiscover Where the Power of Ansys Simulation Can Take You in 14 Great Tracks\nThis year’s free\, virtual event takes place over three days\, organized into 14 distinct tracks that speak to the transformative power of simulation to inspire\, equip\, and empower you on the way to technological innovation and exploration: \nDay 1: Inspire\n\nCreate What’s Next in Mobility: Learn how simulation is transforming mobility to address unprecedented challenges and deliver cost-effective\, competitively differentiated solutions\, from safer\, more sustainable designs to the complex electronics and embedded software that define them.\nDigital Engineering for Mission Success: The aerospace and defense industries must operate on the cutting edge to deliver advanced capabilities. Learn how digital engineering helps them increase flexibility\, update legacy programs\, and speed new technology into service.\nAccelerate Cleaner Energy Development: See how industries rely on simulation to streamline production and distribution of safer\, cleaner\, more reliable energy through fuel-to-power conversions\, and to accelerate scaling of low-carbon energy solutions.\nDigitize and Personalize Medicine: Safer medical treatments can require more testing and clinical trials\, making traditional approaches less affordable. Discover how simulation-driven in silico methods reduce market costs and facilitate breakthrough innovation\, without compromising patient safety.\nEnsure First-Time Silicon Success: Hear how integrated chip (IC) designers are tackling significant challenges rising from bespoke silicon trends and 3D-IC packaging technology to ensure first-time silicon success.\n\nDay 2: Empower:\n\nTackle Engineering Complexity with Numerics: This track demonstrates how the application of advanced physics models and numerical methods for multiphysics simulation can tackle difficult design challenges and analyze real-world scenarios to overcome increasing product complexity.\nEngineer without Limits: Learn why having the flexibility and open ecosystem needed to simulate modern\, complex products and systems at scale requires the latest advancements in hyperscale and cloud computing.\nTransform Simulation at the Speed of AI: AI-augmented simulation technology is a real game-changer\, bringing unprecedented speed\, innovation\, and accessibility to engineering. See why it’s not just about accelerating simulation\, it’s about making it more accessible.\nConnect Digital Threads: This track discusses the ability of digital engineering to sort through complexity to reduce time\, cost\, and risk — increasing accuracy and performance with physics rigor to deliver a design infrastructure and open ecosystem along a two-way digital thread.\n\nDay 3: Equip\n\nPower Up Intelligent Connectivity: Discover the power of electromagnetic simulation to successfully model\, analyze\, and design many high- and low-frequency electronics\, including computing platforms\, generators and transformers\, communications systems and satellites\, and advanced driver-assistance systems.\nReinforce Structural Integrity: This track shows how simulation solves complex structural engineering challenges quickly and efficiently through finite element analysis (FEA)\, customized and automated solutions for structural mechanics\, and multiple design scenario analyses to ensure greater product integrity.\nGo with the Computational Flow: Get a better perspective of computational fluid dynamics (CFD) analysis and how it delivers insights to help companies make critical design decisions that reduce energy consumption and improve product performance.\nInnovate at the Speed of Light: See how optics-specific tools and workflows help optical designers innovate across an entire industry to expedite groundbreaking product development and improve performance\, reliability\, and yield — from the nano to the micro scale.\nOptimize Across the Board: Learn how comprehensive multiphysics EM/IR\, thermal\, and electromagnetic simulation are accelerating 3D-IC design\, bespoke silicon\, and intelligent connectivity to increase the speed and efficiency of semiconductor manufacturing.\n\nRegister Now for Simulation World 2024\nAt Simulation World 2024\, you’ll hear from members of the global product development community as they come together to inspire you — and each other — with tales of agility\, innovation\, determination\, and discovery on the way to solving them. \nIn this virtual setting\, you can view and rearrange your schedule before or during live sessions — all from the comfort of your personal workspace. Curate your own agenda based on track or topic\, then view\, download\, and share them with others\, or export them to your calendar. \nEvery day\, Ansys technologies are powering innovations that drive advancement. Simulation World 2024 is a chance for you see how they can help you do the same — whether you’ve got a seed of an idea you’d like to grow\, or are well on your way to innovating something new. And participation is free. \nSo be sure to sign up for Simulation World 2024 today and encourage your colleagues to do the same. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ansys-simulation-world-2024/ LOCATION:CA CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-May-14-16-2024.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240507T080000 DTEND;TZID=America/Los_Angeles:20240508T170000 DTSTAMP:20240503T163652Z CREATED:20240419T171240Z LAST-MODIFIED:20240503T163652Z UID:7877-1715068800-1715187600@marketingeda.com SUMMARY:ChipEx 2024 DESCRIPTION:ChipEx2024\, the largest annual event of the Israeli semiconductor industry\, will be held on May 7-8\, 2024 in Tel Aviv\, Israel. ChipEx2024 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2024 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2024 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2024 exhibition will take place on May 7\, 2024 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2024 technical seminar will take place on May 7\, 2024 at the Tel-Aviv Expo Center. \nChipEx2024 Executive Summit \nThe Closing session of ChipEx2024 will take place on May 8\, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe. \nChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \nWe invite you to take part in ChipEx2024 as an exhibitor\, a speaker and/or as a sponsor. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chipex-2024/ LOCATION:Tel Aviv Convention Center\, Rokach Boulevard 101\, Tel Aviv\, Israel CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240430T080000 DTEND;TZID=America/Los_Angeles:20240501T170000 DTSTAMP:20240416T193144Z CREATED:20240416T193144Z LAST-MODIFIED:20240416T193144Z UID:7866-1714464000-1714582800@marketingeda.com SUMMARY:CXL DevCon 2024 DESCRIPTION:The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1\, 2024\, in Santa Clara\, California! \nCXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training\, view available products and technology demonstrations\, and network with industry peers. \nRegister for the event HERE. \nIf you are not currently a member of the CXL Consortium\, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information. \n  \nCONFERENCE PROGRAM \n\n\n\n\n\n\n\nDevCon 2024 Day 1 – Compliance & Implementation\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 9:00\nRegistration\n\n\n\n9:00 – 9:15\nWelcome\nJim Pappas\, Intel – CXL Chairman\n\n\n9:15 – 9:45\nKeynote – History of CXL\nLarrie Carr\, Rambus – CXL President\n\n\n9:45 – 10:15\nCXL Specifications Overview\nDebendra Das Sharma\, Intel – TTF Co-Chair\n\n\n10:15 – 10:45\nCoffee Break & Exhibit\n\n\n\n10:45 – 11:30\nTechnical Spec Training (1.0/2.0)\nMahesh Wagh\, AMD – TTF Co-Chair\n\n\n11:30 – 12:00\nCXL Use Case – CXL Native Memory\nBill Gervasi\, Wolley\n\n\n12:00 – 1:00\nLunch & Exhibit\n\n\n\n1:00 – 1:20\nProving CXL scale-out and ROI in the data center\nIra Weiny\, Linux\n\n\n1:20 – 1:40\nCXL Software Ecosystem: The Software Stack for CXL\nSteve Scargall\, MemVerge\n\n\n1:40 – 2:00\nExploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework\nMichael Aguilar\, OpenFabrics Alliance – OFA Secretary\n\n\n2:00 – 2:20\nRAS for Resilient Data Centric Platforms using a CXL Memory Controller\nSandeep Dattaprasad\, Astera Labs\n\n\n2:20 – 2:40\nMember Implementation: CXL Memory Latency Measurement Tutorial\nTam Do\, Microchip\n\n\n2:40 – 3:10\nBreak & Exhibit\n\n\n\n3:10 – 3:30\nUnderstanding the Need for Compliance\nAnil Godbole\, Intel\n\n\n3:30 – 3:50\nTesting CXL links using Exercisers & Analyzers\nYamini Shastry\, Viavi\n\n\n3:50 – 4:10\nCXL Testing – Protocol Layers & Testing Examples\nGordon Getty\, Teledyne LeCroy\n\n\n4:10 – 4:40\nFocusing on the Future of CXL Compliance\nNathan White\, Intel – CWG Co-Chair\n\n\n4:40 – 5:00\nDay 1 Open Q&A\nCWG / TTF Panel\n\n\n5:00 – 6:30\nNetworking Reception & Exhibit\n\n\n\n\n  \n\n\n\n\n\n\n\nDevCon 2024 Day 2 – Emerging & Future\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 8:30\nRegistration and Exhibit\n\n\n\n8:30 – 9:30\nTechnical Spec Training (3.0/3.1)\nRob Blankenship\, Intel – PWG Co-Chair\n\n\n9:30 – 10:00\nMember Implementation: Streamlining CXL Adoption for Hyperscale Efficiency\nNilesh Shah\, ZeroPoint Technologies\n\n\n10:00 – 10:30\nTechnical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL\nZongyao Wen\, Synopsys\n\n\n10:30 – 11:00\nCoffee Break & Exhibit\n\n\n\n11:00 – 11:20\nMember Implementation\nDr. Miryeong Kwon\, Panmnesia\n\n\n11:20 – 11:40\nMember Implementation\nGeof Findley\, Montage Technology\n\n\n11:40 – 12:10\nMember Implementation: Using a CXL 2.0 switch for CXL memory expansion\, pooling and sharing\nJianping (JP) Jiang\, PhD\, Xconn Technologies\n\n\n12:10 – 12:30\nMember Implementation: Building Composable and Disaggregated Systems of the Future with CXL 3.0\nRaju Pudota\, Cadence\n\n\n12:30 – 1:30\nLunch & Exhibit\n\n\n\n1:30 – 1:50\nMember Implementation: Improving system memory bandwidth with CXL software interweaving\nRavi Kiran Gummaluri\, Micron\n\n\n1:50 – 2:10\nMember Implementation: Exploring system memory expansion and memory pooling/tiering\nKapil Sethi\, Samsung\n\n\n2:10 -2:30\nMember Implementation: Enabling CXL Memory Module\, Exploring Memory Expansion Use Cases & Beyond\nThomas Won Ha Choi\, PhD\, SK hynix\n\n\n2:30 – 2:50\nMember Implementation: Optical Applications of CXL\nDavid Kulansky\, Alphawave Semi\n\n\n2:50 – 3:30\nBreak & Exhibit\n\n\n\n3:30 – 4:30\nFireside chat – open discussion + audience Q&A\nLeadership Panel\n\n\n4:30 – 5:00\nClosing comments and Call to Action\nKurtis Bowman\, AMD – MWG Co-Chair\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cxl-devcon-2024/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CXL-DevCon-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T080000 DTEND;TZID=America/Los_Angeles:20240425T170000 DTSTAMP:20240410T171939Z CREATED:20240410T171409Z LAST-MODIFIED:20240410T171939Z UID:7830-1714032000-1714064400@marketingeda.com SUMMARY:IP-SoC Silicon Valley 2024 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-silicon-valley-2024/ LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240421T080000 DTEND;TZID=America/Los_Angeles:20240424T170000 DTSTAMP:20240419T164318Z CREATED:20240419T164152Z LAST-MODIFIED:20240419T164318Z UID:7873-1713686400-1713978000@marketingeda.com SUMMARY:CICC 2024 DESCRIPTION:The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cicc-2024/ LOCATION:DoubleTree by Hilton Denver\, 3203 Quebec Street\, Denver\, CO\, United States CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240419T080000 DTEND;TZID=America/Los_Angeles:20240421T170000 DTSTAMP:20240408T222220Z CREATED:20240212T205659Z LAST-MODIFIED:20240408T222220Z UID:7610-1713513600-1713718800@marketingeda.com SUMMARY:Latch-Up 2024: Boston DESCRIPTION:Friday to Sunday April 19–21\, 2024 in Boston\, MA\, USA \nThe Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It’s an event for the open source digital design community\, much like its European sister conference ORConf\, run by the FOSSi Foundation. \n\n\n\n\n\nYou are all invited!\nThe FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston\, MA\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and submit a presentation or proposal if you have a project or idea on the topic to share! \nQuestions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org. \n\n\n\nSubmit a talk\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nTickets and registration\nAttendance of Latch-Up is free of charge. To help us organizing the event\, you are required to register on Eventbrite. Please register as soon as possible\, as we have to close registrations as soon as the room capacity is reached. \nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nFriday\n\n\n\nWhen\nWhat\n\n\n\n\n9:00\nWelcome\n\n\n9:20\nCaster: An Open-source E-Ink Controller\n\n\n9:40\nTeaching Modern EDA using a Tapeout-Centric University Course\n\n\n10:00\nBreak\n\n\n10:20\nCedarEDA for open source silicon\n\n\n10:40\nCohort: Software-Oriented Acceleration for You\, Me\, and Our Heterogeneous SoCs\n\n\n11:00\nTowards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture\n\n\n11:20\nLunch\n\n\n12:20\nTowards Cycle-accurate Simulation of xBGAS\n\n\n12:40\nArtifact Evaluation for the Field Programmable Gate Array Community\n\n\n13:00\nChisel 6 and beyond\n\n\n13:20\nMRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL\n\n\n13:40\nBreak\n\n\n14:40\nRiding The Wave: Building Wave Pipelines in FPGAs\n\n\n15:00\nGiving Students A Byte of Open-Source: Advancing Hardware Education\n\n\n15:20\nBreak\n\n\n15:40\nOpen-source resources for learning the Bluespec HL-HDLs\n\n\n16:00\nPyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface\n\n\n16:20\nTransition to Draper\n\n\n17:00\nTalks(30-40m) at Draper\n\n\n18:00\nTransition to lightning Talks\n\n\n19:00\nLightning Talks\n\n\n20:00\nGo home\n\n\n\nSaturday\n\n\n\nWhen\nWhat\n\n\n\n\n8:40\nWelcome\n\n\n9:00\nOpen source RTL verification with Verilator\n\n\n9:20\nSonata: A development platform to enable exploring the use of CHERI for embedded applications\n\n\n9:40\nTransparent Checkpointing for Fault Tolerance in RISC-V\n\n\n10:00\nBreak\n\n\n10:20\nHDLAgent\, Enhancing Hardware Language in the age of LLMs\n\n\n10:40\nSpade: An HDL Inspired By Modern Software Languages\n\n\n11:00\nSwitchboard: Calling All Hardware Models\n\n\n11:20\nLunch\n\n\n12:20\nFrom an Open-Source ISA to Open-Source HW to Open-Source Silicon\n\n\n12:40\nOpen Source Hardware: Hacking Silicon for Fun (instead of profit)\n\n\n13:00\nA History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation\n\n\n13:20\nUMI: Universal Memory Interface\n\n\n13:40\nBreak\n\n\n14:20\nABC: The Way It Should Have Been Designed\n\n\n14:40\nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\n\n\n15:00\nBeyond EDA lies Edalize\n\n\n15:20\nBreak\n\n\n15:40\nRF Front-end receiver design for 2.4GH/5GHz WiFi application\n\n\n16:00\nCACE Study: Open source analog and mixed-signal design flow\n\n\n16:20\nIHP Open Source PDK: Announcement\, Setup\, Current State and Experiences\, and look ahead\n\n\n16:40\nTiny Tapeout: custom silicon open to all\n\n\n17:20\nMeet at Flattops\n\n\n\nSunday\nComing soon \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/latch-up-2024-boston/ LOCATION:Massachusetts Institute of Technology\, 77 Massachusetts Avenue\, Boston\, MA\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Brussels:20240416T080000 DTEND;TZID=Europe/Brussels:20240417T170000 DTSTAMP:20240410T165555Z CREATED:20240410T165555Z LAST-MODIFIED:20240410T165555Z UID:7826-1713254400-1713373200@marketingeda.com SUMMARY:CS Inernational Conference DESCRIPTION:he 14th CS International builds on the strengths of its predecessors\, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ensuring SiC’s Phenomenal Success; Expanding Horizons for Surface Emitters; Accelerating the Growth of GaN; Taking Power from the Photon; and New Frontiers for the LED. \nThose attending these sessions will be rewarded with greater insight into device technologies while learning of the latest opportunities and trends within the compound semiconductor industry. Delegates will also discover significant advances in tools and processes that enable enhanced yield and throughput. \nAttendees at this two-day conference will also meet a wide variety of key players within the community\, from investors and analysts to fab engineers and managers. \nCS International is part of AngelTech\, which delivers a portfolio of insightful\, informative\, highly valued chip-level conferences. Bringing together 3 conferences with more than 120 presentations\, more than 800 delegates and over 80 exhibitors\, AngelTech is the premier global event covering compound semiconductor\, photonic integrated circuit and power electronic technologies. With a significant overlap between the three conferences\, attendees and exhibitors are exposed to the full relevant supply chains and customer and supplier bases. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cs-inernational-conference/ LOCATION:Sheraton Brussels Airport Hotel\, Brussels\, Belgium CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CS-2024.jpg END:VEVENT END:VCALENDAR