BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20220313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20221106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT 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TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20220313T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20221106T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Jerusalem BEGIN:DAYLIGHT TZOFFSETFROM:+0200 TZOFFSETTO:+0300 TZNAME:IDT DTSTART:20220325T000000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0300 TZOFFSETTO:+0200 TZNAME:IST DTSTART:20221029T230000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0200 TZOFFSETTO:+0300 TZNAME:IDT DTSTART:20230324T000000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0300 TZOFFSETTO:+0200 TZNAME:IST DTSTART:20231028T230000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0200 TZOFFSETTO:+0300 TZNAME:IDT DTSTART:20240329T000000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0300 TZOFFSETTO:+0200 TZNAME:IST DTSTART:20241026T230000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240304T080000 DTEND;TZID=America/Los_Angeles:20240307T170000 DTSTAMP:20240216T181350Z CREATED:20240103T171927Z LAST-MODIFIED:20240216T181350Z UID:7493-1709539200-1709830800@marketingeda.com SUMMARY:DVCon USA 2024 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-usa-2024/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20240226T080000 DTEND;TZID=Europe/Madrid:20240229T170000 DTSTAMP:20240321T221956Z CREATED:20231228T171623Z LAST-MODIFIED:20240321T221956Z UID:7473-1708934400-1709226000@marketingeda.com SUMMARY:MWC 2024 DESCRIPTION:Where technology\, community and commerce converge\n\nMWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months. \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/mwc-2024/ LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240225T080000 DTEND;TZID=America/Los_Angeles:20240229T180000 DTSTAMP:20240221T174538Z CREATED:20240221T174208Z LAST-MODIFIED:20240221T174538Z UID:7659-1708848000-1709229600@marketingeda.com SUMMARY:SPIE Advanced Lithography + Patterning DESCRIPTION:Attend and hear research\, challenges\, and breakthroughs as you gather with colleagues in San Jose \nJoin other leading researchers who are solving challenges in optical and EUV lithography\, patterning technologies\, metrology\, and process integration for semiconductor manufacturing and adjacent applications. \nFive days of exciting content and connecting with your community\n\nPlenary talks\nTechnical presentations\nNetworking sessions\nCourse offerings\nExhibition\n\nCome to hear world-class speakers\nChan Hwang\n\nSamsung (Korea) \nAnn Kelleher\n\nIntel Corp. (United States) \nTodd Younkin\n\nSemiconductor Research Corporation (USA) \nExplore six great conferences\n\nOptical and EUV Nanolithography\nDTCO and Computational Patterning\nMetrology\, Inspection\, and Process Control\nNovel Patterning Technologies\nAdvances in Patterning Materials and Processes\nAdvanced Etch Technology and Process Integration for Nanopatterning\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/spie-advanced-lithography-patterning/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SPIE.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240218T080000 DTEND;TZID=America/Los_Angeles:20240222T170000 DTSTAMP:20231230T004304Z CREATED:20231230T004304Z LAST-MODIFIED:20231230T004304Z UID:7483-1708243200-1708621200@marketingeda.com SUMMARY:ISSCC 2024 DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/isscc-2024/ LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240206T090000 DTEND;TZID=America/New_York:20240206T180000 DTSTAMP:20240129T191342Z CREATED:20240129T191342Z LAST-MODIFIED:20240129T191342Z UID:7559-1707210000-1707242400@marketingeda.com SUMMARY:Canada's Semiconductor Summit DESCRIPTION:Help build Canada’s role in North America’s integrated semiconductor supply chain.\n\n\nFeaturing key industry and government decision-makers from Canada\, the United States\, and international jurisdictions\, your insights at this by-invitation-only event will help us build an effective action plan. The summit will establish priorities and define opportunities to accelerate the growth\, development\, and competitiveness of Canada’s semiconductor sector. \n\nProgram\n\n\n9-9:10 AM Welcome & Introductory Remarks \nMC:  Ruth Rayman\, former Director General\, Advanced Electronics and Photonics Research Centre\, NRC \n\n\n\n\n\n9:10-9:30 AM An Unprecedented Global Recalibration \nSemiconductors are the backbone of the digital economy. As an integrated North American semiconductor supply chain takes shape\, Canada has the opportunity to transform existing\, discrete areas of expertise into a coherent offering\, forge new collaborations and maximize new markets. \nKey topics: \n\nLay of the land\, threats and opportunities etc.\n\nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n9:30-10:45 AM Automotive\, EVs\, and Batteries: Amplifying Our Strengths \nCanada is creating a world class EV supply chain with OEMs and electrification sub-systems. Semiconductors lie at the heart of the 21st century automobile. How can Canada play a larger role in the semiconductor supply chain for EVs? What are the short and long-term opportunities? \nKey topics: \n\nWhat is the size of the automotive semiconductor market in Canada? What is its impact on the automotive manufacturing ecosystem in Canada?\nEV sub-systems: which is the best sub-system to target for Canada to grow the auto semiconductor ecosystem?\nHow can semiconductors complement the increasing investment in EV manufacturing in Canada in the future?\n\nModerator: Kirk Ouellette\,  Vice President\, Strategy Development and Strategic Marketing\, STMicroelectronics \nPanelists: \n\nAndrea Tranchida\, Vice President\, Global Automotive Solutions\, NXP Semiconductors\nBenoit Rousseau\, Vice President – GaN Automotive\, Infineon Technologies\nDaniel Boisvert\, Director of Business Development\, C-MAC Electronics Solutions\nMona Eghanian\, Assistant Vice President\, OVIN\n\n\n\n\n\n\n10:45-11 AM Break \nNetworking and refreshments. \n\n\n\n\n\n11 AM-12:15 PM Advanced Technologies: Leveraging Canadian Capabilities \nCanada needs to strategically leverage existing areas of strength and promising new advanced technologies to integrate with critical capabilities into the global semiconductor supply chain. What future-looking technologies are worth pursuing? What is the market telling us—and what criteria should guide our investments?  \nKey topics: \n\nPhotonics/RF\nAI\nSensors\nCompound semiconductors\nQuantum computing\n\nModerator: Duncan Stewart\, Partner\, Deep Tech Venture Fund\, BDC \nPanelists: \n\nJon Rogers\, Co-founder and SVP Engineering\, Alphawave Semi\nI-Cheng Chen\, Fellow\, Platform Architecture\, AMD Canada\nIgor Arsovski\, Head of Silicon\, Fellow\, Groq\nJim Hjartarson\, President and COO\, Inpho\n\n\n\n\n\n\n12:15-1:15 PM Catered buffet lunch with guest speaker \nSilicon Valley legend\, John East\, former CEO of Actel\, and veteran of AMD and Fairchild Semiconductor\, remembers those formative\, chaotic years in Silicon Valley—and the analogies in Canada today. \nSpeaker: John East\, Chairman of the Board\, SPARK Microsystems \n\n\n\n\n\n1:15-2:30 PM Building a Competitive Semiconductor Ecosystem: Harnessing an Economic Juggernaut \nSilicon Valley\, Taiwan\, South Korea\, Saxony\, IMEC\, Albany etc. Not every successful tech ecosystem has to adhere to the same model. What can Canada learn from successful semiconductor ecosystems? What relationships need to be established with key US hubs? How should the private sector\, academia and government collaborate? \nKey topics: \n\nEcosystem overview\nWhat gave the stimulus to get it off the ground?\nWhat’s the private/government split?\n\nModerator: Normand Bourbonnais\, Président Directeur Général\, Technum Québec \nPanelists: \n\nLode Lauwers\, SVP\, Business Development & Sales\, IMEC\nMarie-Josée Turgeon\, Présidente – Directrice générale\, C2MI\nLaMar Hill\, Director\, NY Creates\nCharles Sturman\, CEO\, TechWorks\n\n\n\n\n\n\n2:30-2:45 PM Break \nNetworking and refreshments. \n\n\n\n\n\n2:45-4PM The Talent Question: Building the Pipeline \nThe semiconductor workforce must double to an estimated half a million people to meet the demands of North American semiconductor reshoring. What mix of training\, apprenticeship programs\, immigration\, financial incentives\, and creative retention strategies will build the pipeline for Canada? \nKey topics: \n\nTraining programs\nImmigration\nFinancial incentives\nApprenticeship programs\nFunding university Chairs\nRetention\nBrain drain\n\nModerator: Dr. Tony Chan Carusone\, CTO\, Alphawave Semi \nPanelists: \n\nDino Toffolon\, SVP of Engineering-Interface IP\, Synopsys\nKate Alcott\, Director of Workforce Programs\, NY Creates\nSylvain Charbonneau\, Vice-President\, Research and Innovation\, University of Ottawa\nArvind Gupta\, Professor at Department of Computer Science\, University of Toronto\n\n\n\n\n\n\n4-5 PM Strategic Initiatives and Next Steps for 2024: Making It Happen \nCanada has a powerful opportunity to establish itself as new niches emerge across the North American corridor. But we need to act fast.  Regional hubs have formed this year and are actively forging new partnerships and market plays.  How can we  ensure Canadian technology and expertise accesses these burgeoning markets?   \nKey topics: \n\nCSC 2024 Federal Budget Proposal\nAnnounced proposals ie. CSC\, FABrIC\, SECTR etc.\nFinancing growth\nPrivate-public partnerships\n\nModerator: Chris Ouslis\, Industrial Technology Advisor\, NRC \nPanelists: \n\nGord Harling\, President & CEO\, CMC Microsystems\nClaude Jean\, Executive Vice President\, Strategy & Partnership\, Teledyne Digital\nVelko Tzolov\, Director General\, Canadian Photonics Fabrication Centre (CPFC)\nDr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council\n\n\n\n\n\n\n5-5:30 PM Wrap Up & Closing Remarks \nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n5:30-6:30 PM Networking Reception \nNetworking and refreshments. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/canadas-semiconductor-summit/ LOCATION:Brookstreet Hotel\, 525 Leggett Drive\, Ottawa\, Canada CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Canada-Semi-Summit-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240206T080000 DTEND;TZID=America/Los_Angeles:20240208T170000 DTSTAMP:20240103T034734Z CREATED:20240103T034448Z LAST-MODIFIED:20240103T034734Z UID:7490-1707206400-1707411600@marketingeda.com SUMMARY:Chiplet Summit DESCRIPTION:The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. \nThey’ll get the scoop on ways to make their chiplets run faster\, scale better\, use less power\, and be more flexible. \nThis unique event gives attendees a place to network with peers\, ask questions of the experts\, and talk to vendors offering a wide variety of products and services. \n\n\nKeynote Speakers\n\n\n\n\n\n\n\n\nSubi Kengeri – Applied Materials \nNitza Basoco – proteanTecs \nDaniel Armbrust – Silicon Catalyst \nBob Brennan – Intel Foundry Services \nSheng Lu – Corigine \nCliff Grossner – Open Compute Project \nBapi Vinnakota – Open Compute Project \n\n\n\n\n\n\n\n\nKEYNOTE SPEAKER DETAILS \nThought-Provoking Panels Where Attendees Can Ask Questions of Leading Experts: \n\nChoosing the Right Architecture for Your Application\nNext Great Breakthrough in Chiplets\nBest Development Platform for Chiplets\nBest Interface for Chiplets\nWhat Standards Are Needed?\nOptimizing Chiplets\n\nATTENDEES \nEngineers and managers who are looking for ways to help meet performance challenges\, handle the move to smaller dimensions\, provide the modularity and scalability today’s chips require\, and develop solutions focused on the latest applications and interfaces.  Designers of enterprise networks\, telecom systems\, high-performance computing\, financial systems\, IoT\, and mil/aero applications all know that chiplets will play a big role in their future. \nBACKGROUND \nChiplets improve chip yields and costs\, but still provide the performance of a large monolithic chip.  Designers can mix-and-match chiplets\, use the process technologies best suited to particular functions\, take advantage of chiplet IP\, simplify moves to new process nodes\,  and avoid wafer waste and manufacturing defects.  Chiplets are the key to producing the extremely high-density\, high-performance chips required for today’s networking\, storage\, AI/ML\, analytics\, media processing\, HPC\, and virtual reality applications. \n\n\n\n\n\n\nExhibit\nPosition Your Company as a Leader in an Emerging Technology.  Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia).  Share Thoughts with Key Experts and Analysts.  Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. \n\n\nOnly event totally dedicated to the skyrocketing chiplet market \n\n\nTop experts\, major keynotes\, and critical topics will draw big-time customers \n\n\nPractical orientation will attract key designers and specifiers \n\n\nVendor-neutral show offers opportunities to everyone \n\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplet-summit-2/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chiplet-Summit-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240130T080000 DTEND;TZID=America/Los_Angeles:20240201T170000 DTSTAMP:20231212T172849Z CREATED:20231212T172135Z LAST-MODIFIED:20231212T172849Z UID:7160-1706601600-1706806800@marketingeda.com SUMMARY:DesignCon 2024 DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers\n\n\n\n\nDesignCon is the premier high-speed communications and system design conference and exposition\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. \n\n\n40 Under 40\n\n\n\n\nCalling all Emerging Engineers and Leaders! \nDesignCon’s 40 Under 40 program launches in 2024 and provides an opportunity for up-and-coming engineers to further their careers through access to DesignCon’s full conference education\, including 14 tracks plus DesignCon’s automotive-focused Drive World conference. \n\nNominate yourself or a fellow engineer. Those accepted receive a complimentary Education Pass plus access to an exclusive networking breakfast with leading engineers and mentors.  Deadline: 12/14/23.   \n» Click here to learn more. \n\n\nThe Conference – A Systematic Approach to Learning & Discovery\n\n\n\n\nAttend the expertly curated 14-track conference created by engineers for engineers featuring technical paper sessions\, tutorials\, and industry panels covering all aspects of chip\, board\, and systems design. \n\n\nThe Expo – Take Your Electronic Design Expertise to the Next Level at DesignCon\n\n\n\n\nBrowse exhibits with hundreds of new products and technologies in the expo hall\, attend educational sessions in the Chiphead Theater\, see interactive demos\, and network with high-caliber industry professionals at multiple social functions. \n\n\nExpanded Drive World Conference Track and Exhibits\n\n\n\n\nDrive World expands in 2024 to support electric vehicle technology in addition to sessions in the areas of automotive electronics and intelligence\, as engineers prepare for unprecedented growth in an automotive electronics market forecast to see revenue surge more 37% 2023-2027. Accelerate the path to autonomous and electric vehicles by attending the Drive World conference track with education on advancing automotive tech. \nNew in 2024 — the Advanced Automotive section of the expo floor highlighting advanced automotive electronics suppliers focused on the autonomous\, EV and energy-storage markets. \n\n\nEngineer of the Year\n\n\n\n\nDesignCon’s “Engineer of the Year” Award is given out each year during the DesignCon event. The award seeks to recognize the best of the best in engineering and new product advancements at the chip\, board\, or system level. \nThe award winner is selected based on his or her leadership\, creativity\, and out-of-the-box thinking brought to design/test of chips\, boards\, or systems\, with particular attention paid to areas of signal and power integrity. \nVoting to choose the 2024 Engineer of the Year is now open. \nCast your vote for the finalist who you feel should be the DesignCon 2024 Engineer of the Year. Voting ends December 19 at noon Pacific. \n» Click to the ballot \nRead about all 5 finalists on Design News \n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/designcon-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240124T080000 DTEND;TZID=Asia/Tokyo:20240126T170000 DTSTAMP:20231227T195553Z CREATED:20231227T195553Z LAST-MODIFIED:20231227T195553Z UID:7462-1706083200-1706288400@marketingeda.com SUMMARY:Automotive World 2024 DESCRIPTION:Combination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics\, connected car\, autonomous driving\, EV/HV/FCV\, lightweight\, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. \n\n1\,650 Exhibitors\n85\,000 Visitors\n170 Speakers\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/automotive-world-2024/ LOCATION:Tokyo Big Sight\, 3 Choe-11-1 Ariake\, Tokyo\, Japan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Automotive-World-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Seoul:20240122T080000 DTEND;TZID=Asia/Seoul:20240125T170000 DTSTAMP:20231229T165332Z CREATED:20231229T165332Z LAST-MODIFIED:20231229T165332Z UID:7479-1705910400-1706202000@marketingeda.com SUMMARY:ASP-DAC 2024 DESCRIPTION:ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions\, one of the most active regions of design\, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists\, engineers\, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/asp-dac-2024/ LOCATION:Incheon Songdo Convensia\, 123 Central Street\, Yeonsu-gu\, Incheon\, Korea\, Democratic People's Republic of CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240116T090000 DTEND;TZID=Asia/Tokyo:20240116T170000 DTSTAMP:20231211T175014Z CREATED:20231211T175014Z LAST-MODIFIED:20231211T175014Z UID:7149-1705395600-1705424400@marketingeda.com SUMMARY:RISC-V Day\, Tokyo 2024 Winter DESCRIPTION:The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday\, January 16\, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center\, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products\, as well as key people and engineers\, and provide business opportunities such as increasing product awareness\, realizing collaboration between companies\, technology exchange\, and information gathering. We look forward to your participation on this occasion! A video of the presentation and information on materials will be posted on the website at a later date. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-day-tokyo-2024-winter/ LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240109T080000 DTEND;TZID=America/Los_Angeles:20240112T170000 DTSTAMP:20231230T005013Z CREATED:20231129T225332Z LAST-MODIFIED:20231230T005013Z UID:7133-1704787200-1705078800@marketingeda.com SUMMARY:CES 2024 DESCRIPTION:Registration is now open for CES® 2024 — taking place Jan. 9-12\, in Las Vegas. \nFlip the switch on global business opportunity with CES\, where you can meet with partners\, customers\, media\, investors\, and policymakers from across the industry and the world all in one place. \nDon’t miss your chance to be a part of the most powerful tech event in the world. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ces-2024/ LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2023-2.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240106T080000 DTEND;TZID=Asia/Kolkata:20240110T170000 DTSTAMP:20231228T190611Z CREATED:20231227T173925Z LAST-MODIFIED:20231228T190611Z UID:7458-1704528000-1704906000@marketingeda.com SUMMARY:VLSID 2024 DESCRIPTION:The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata\, India\, during January 6-10\, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders\, Indian and international industry bodies\, and academic researchers in a common platform. \nIn the present era of automation and connected things\, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift\, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”. \nBrilliant minds across the VLSI domain will brainstorm during the conference to redefine the future course of VLSI Design and Embedded research and application in India. Kolkata (Known as Calcutta during the British Imperial rule) is surrounded by several premier technical and scientific institutes like IIEST Shibpur (B. E. College\, Shibpur)\, IIT Kharagpur\, ISI Calcutta\, Calcutta University\, Jadavpur University etc. \nEast and north-eastern region of our country is a hub of innovation with a focus on emerging technologies. Over the years the region has generated huge number of ESDM professionals and academicians who are right now fueling the growth of ESDM industry. It is high time to operationalize state level high technology clusters in the field of VLSI design\, embedded systems\, cognitive system design and silicon/display/compound fab. VLSID 2024 provides the unique stage where MNCs\, start-ups\, industry bodies and academicians come together and get synergized with what the states of this region have to offer. \nOver a span of five-days of VLSID2024\, the summit will feed brains and nurture minds with state-of-the-art exhibitors\, presentations\, panel discussions\, innovation forums\, and tutorials by established technologists. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/vlsid-2024/ LOCATION:ITC Royal Bengal\, Kolkata\, India CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240105T080000 DTEND;TZID=America/Los_Angeles:20240107T170000 DTSTAMP:20231228T191521Z CREATED:20231228T191521Z LAST-MODIFIED:20231228T191521Z UID:7476-1704441600-1704646800@marketingeda.com SUMMARY:IEEE Rising Stars 2024 DESCRIPTION:The IEEE Rising Stars Conference is designed to inform\, excite\, enthuse\, and bring together the top engineering Young Professionals and Students around the world to network and be inspired by each other. The program includes Technical Innovation Talks\, Professional Development\, Workshops & Competitions\, and Networking Opportunities with industry and peers. \nThe conference gathers Technical Professionals who are experts in emerging technologies such as: Autonomous Vehicles\, Artificial Intelligence\, Space & Manufacturing\, Power & Sustainability\, Cybersecurity\, IoT & more! \nRising Stars attendees will leave the event with better preparation to face the technical and professional challenges presented to them and armed with the appropriate contacts needed to gain the insight to be successful. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-rising-stars-2024/ LOCATION:Tropicana Las Vegas\, 3801 S Las Vegas Blvd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-Rising-Stars-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20231213T080000 DTEND;TZID=Asia/Kolkata:20231217T170000 DTSTAMP:20231101T195305Z CREATED:20231101T195220Z LAST-MODIFIED:20231101T195305Z UID:7022-1702454400-1702832400@marketingeda.com SUMMARY:International Workshop on Physics of Semiconductor Devices - IWPSD 2023 DESCRIPTION:The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops\, started in 1981\, provides a global forum for interaction between scientists and technologists working in the area of semiconductor materials and devices. \nThe topics to be covered in the Workshop are\, but not limited to:\n\n2D Materials and Devices\nCrystal Growth and Epitaxy\nDevice Modelling and Simulation\nDevices for Quantum Technology\nII – VI and Oxide Semiconductors\nIII – V Semiconductors\nMemory and Logic Devices\nMEMS\, NEMS and Sensors\nOrganic and Flexible Electronics\nPhotovoltaics\nPower Semiconductor Devices\nOptoelectronics\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-workshop-on-physics-of-semiconductor-devices-iwpsd-2023/ LOCATION:Research Park\, IIT Madras\, Tamil Nadu 600036\, Chennai\, India CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWPSD-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231209T080000 DTEND;TZID=America/Los_Angeles:20231213T170000 DTSTAMP:20231207T174511Z CREATED:20230920T171734Z LAST-MODIFIED:20231207T174511Z UID:6838-1702108800-1702486800@marketingeda.com SUMMARY:69th International Electron Devices Meeting - IEDM DESCRIPTION:IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology\, design\, manufacturing\, physics\, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology\, advanced memory\, displays\, sensors\, MEMS devices\, novel quantum and nano-scale devices and phenomenology\, optoelectronics\, devices for power and energy harvesting\, high-speed devices\, as well as process technology and device modeling and simulation. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/69th-international-electron-devices-meeting-iedm/ LOCATION:Hilton San Francisco Union Square\, 333 O'Farrell Street\, San Francisco\, 94102\, United States CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEDM-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20231204T090000 DTEND;TZID=Europe/Paris:20231205T170000 DTSTAMP:20231128T173642Z CREATED:20231128T172805Z LAST-MODIFIED:20231128T173642Z UID:7122-1701680400-1701795600@marketingeda.com SUMMARY:IP-SoC Conference 23 - Grenoble DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, Green Electronics\, … \nAnd over all you cannot miss The wine Tasting Party !! \nExhibition tables and “discussion panels” will favor vendor and customer meetings. \nAny question? Please contact us \nRegistration and Exhibition installation opens at 7 am. \n\n\n\n\n\n\nDay 1 – December 4th\, 2023\n\n\n\n\n\n\n\n9.00 am\nIntroduction Session\n\n\n\nWelcome : Innovation in semi conductor industry \nGabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\nEmpowering Innovation in the Age of Custom Silicon \nEric Lalardie\nDirector\nArm Ltd. \nAbout me\n\n\n\n\n9.40 am\nBreak\n\n\n\n10.00 am\nNew technology the lead of innovation\n \nChairperson: Yves Quere – CEA\n\n\n\n\nGreening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology \nPhilippe Flatresse\nProduct Marketing\nSOITEC \nAbout me\n\n\n\n\nTechnologies enabling future mobile connectivity & sensing \nFrancois Brunier\nPartnership Program Manager\nSOITEC \nAbout me\n\n\n\n\nDigital Beamforming design in mmW: A 22nm FDSOI transceiver practical case \nJérôme Prouvée\nLayout Engineer & Project Manager\nCEA \nAbout me\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.20 am\nArtificial Intelligence IP and SoC\n \nChairperson: Costas Conistis – Alphawave Semi\n\n\n\n\nMeeting the Needs of AI Training with HBM3 \nPhilip Van Den Heuvel\nRegional Sales Manager\nRambus\, Inc. \nAbout me\n\n\n\n\nInnovative Integrated IP SoC Design for Edge AI \nTim Menasveta\nDirector of IoT Product Management\nArm Ltd. \nAbout me\n\n\n\n\nTransforming Far-Edge Computer Vision with Energy-Efficient A \nVincent Huard\nChief Technology Officer\nDolphin Design \nAbout me\n\n\n\n\n12.30 pm\nLunch\n\n\n\n1.30 pm\nNew Challenges\n \nChairperson: Eric Lalardie – Arm\n\n\n\n\nThe Lossless Compression Challenge: from Networking to Data centers \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\nAddressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects \nMichael Klempa\nProduct Marking Specialist\nAlphawave Semi \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nSafety Critical Applications\n \nChairperson: Dr. Calliope-Louisa Sotiropoulou – CAST\n\n\n\n\nIP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications \nPhilipp Jacobsohn\nSenior Staff Applications Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nGRLIB: VHDL IP library for fault-tolerant SoC \nFabio Malatesta\nProduct Marketing Engineer\nFrontgrade Gaisler \nAbout me\n\n\n\n\n3.10 pm\nAutomotive Applications\n\n\n\nCAN XL – can safety go in hand with performance? \nJacek Hanke\nCEO\nDigital Core Design \nAbout me\n\n\n\n\nSolve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM \nRuud Derwig\nSenior Staff Engineer for Security IP\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nSecurity Solutions\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nWhich IP for Which Security Certification Standard\, \nLudovic Merrien\nSecurity Certification Leader\nTiempo Secure \nAbout me\n\n\n\n\nLDPC Encoder/Decoder \nManish Mahajan\nFounder\nSecantec\, Inc. \nAbout me\n\n\n\n\nSecurity from chip to cloud with PQC (Post-Quantum Cryptography) \nBrice Gaignoux\nEMEA Pre-Sales Engineer\nSecure-IC \nAbout me\n\n\n\n\n5.20 pm\nBreak\n\n\n\n5.40 pm\nSecurity Solutions – 2\n \nChairperson: Ruud Derwig – Synopsys\, Inc.\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nHow will platform and communication security evolve in the quantum computing era? \nGraeme Hickey\nVP Engineering\nPQShield \nAbout me\n\n\n\n\nThe Power of Physical Unclonable Functions (PUFs) \nChris Jones\nDirector\, Field Application\nCrypto Quantique \nAbout me\n\n\n\n\n7.00 pm\nYou should not miss ! \nWine tasting party sponsored by Soitec\n\n\n\n\n8.00 pm\nBanquet sponsored by D&R\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2 – December 5th\, 2023\n\n\n\n\n\n\n\n9.00 am\nProcessor IP\n \nChairperson: Philippe Quinio – STMicroelectronics\n\n\n\n\nBeyond one-size-fits-all: The power of tailored CPUs \nMike Eftimakis\nVP Strategy & Ecosystem\nCodasip GmbH \nAbout me\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSurvey of market available processor IP \n\n\n\nDagmara Zielinska\nPartnership Program Manager\nD&Rwith Gabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\n\n\n\n\n9.40 – 11.00 am\nFrom Processor IP to Processor or supercomputer chip:  \n\nWhat is needed and what is the next success track ? \nThis panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.\n\nWith the participation of: \n\nFabio Malatesta – Product Marketing Engineer – Frontgrade Gaisler\nMike Eftimakis – VP Strategy and Ecosystem – Codasip GmbH\nLoic Lietar – Co-Founder & CEO – GreenWaves Technologies\nThierry Lelégard – Head of Platform Security – SiPearl\n\n\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.30 am\nAnalog IP\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\nAdaptive Voltage Scaling (AVS): Enhancing Chip Efficiency \nVincent Telandro\nProduct Marketing manager (Power Management IP)\nDolphin Design \nAbout me\n\n\n\n\nTechnology Analysis: what you need to know before embarking on analog design migration \nJean-François Lambert\nDirector of Business Development\nThalia \nAbout me\n\n\n\n\n12.15 pm\nLunch\n\n\n\n1.20 pm\nDesign Platform\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHybrid Cloud Management for IP Development \n\n\n\nSundar M\nDirector\nTessolve Semiconductor Private Limitedwith Pitchumani Guruswamy\nTessolve Semiconductor Private Limited \nAbout me\n\n\n\n\nOnline Only\n\n\n\n\nA novel approach for SoC design resource management and prediction \nChouki Aktouf\nCo-Founder\nInnova Advanced Technologies \nAbout me\n\n\n\n\nMulti-IO co-processor with TSN \nVincent Laporte\nCTO – V.P. BU\nCetraC \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nVerification Platform\n \nChairperson: Patrick Blouet\n\n\n\n\nIP QA Best Practices \nLionel Couder\nSr. Applications Engineer\nSiemens Digital Industries Software \nAbout me\n\n\n\n\nImportant Considerations for Verification of CXL Devices \nNicolas Dai\nApplication Engineer Architect\nCadence Design Systems\, Inc. \nAbout me\n\n\n\n\n3.10 pm\nMonitoring Platform\n\n\n\nChip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology. \nVsevolod Sergeenko\nRFID Team Leader\nNTLab \nAbout me\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nDan Alexandrescu\nR&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nGive Away – Event Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-conference-23-grenoble/ LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-23-Grenoble.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Istanbul:20231204T080000 DTEND;TZID=Europe/Istanbul:20231207T170000 DTSTAMP:20230313T211025Z CREATED:20230313T210903Z LAST-MODIFIED:20230313T211025Z UID:6124-1701676800-1701968400@marketingeda.com SUMMARY:IEEE 30th International Conference on Electronics\, Circuits and Systems (ICECS) DESCRIPTION:The IEEE 30th International Conference on Electronics\, Circuits and Systems (ICECS) will be held in Istanbul\, Turkey 4-7 December 2023. As the flagship conference of IEEE Circuits and Systems Society in Region 8 (Europe\, Middle East\, and Africa)\, ICECS 2023 will consist of tutorials\, plenary lectures\, regular\, special and poster sessions focusing on recent trends\, emerging technologies and advances. \n  \nTracks\n  \n\nAnalog/Mixed-Signal/Microwave Circuits\nBio-Medical\, Bio-Inspired Circuits/Systems\nEDA\, Test and Reliability\nDigital Circuits and Systems\nLinear and Non-Linear Circuits and Systems\nNon-Linear Devices\, Memristors\nLow-Power\, Low-Voltage Design\nEmbedded and Micro/Systems\nNeural Networks\, Machine/Deep Learning\nSensors and Sensing Systems\nSignal Processing\, Image and Video\nVLSI Systems and Applications\nSmart Systems for CAS Applications\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-30th-international-conference-on-electronics-circuits-and-systems-icecs/ LOCATION:Hilton Maslak\, Büyükdere Cd. No:233\, Istanbul\, Turkey CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICECS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231116T080000 DTEND;TZID=Europe/Berlin:20231116T170000 DTSTAMP:20231022T003818Z CREATED:20231022T003818Z LAST-MODIFIED:20231022T003818Z UID:6984-1700121600-1700154000@marketingeda.com SUMMARY:Formal Verification Conference: Osmosis 2023 DESCRIPTION:Elevate your success with osmosis 2023\nOsmosis is about sharing success in using formal techniques to solve verification challenges\, and networking with our R&D experts and other attendees. As such\, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product roadmaps. \nConference program\nCheck-in and continental breakfast – doors open at 8:00 AM\, Program starts at 9:00 AM \n\n\n\nTopic\nPresenter\n\n\nLimits of verification: learnings from catastrophic system failures\nPhilippe Luc – Codasip\n\n\nSpectres\, Meltdowns\, Zombies\, Orcs:  How formal methods could banish the ghosts that haunt our computing systems\nProf. Wolfgang Kunz – RPTU\n\n\nHow to sign-off cryptographic hash implementations with generated formal assertions\nTobias Ludwig – Lubis EDA\n\n\nDebugging enhancements for formal property checking\nHolger Busch – Infineon\n\n\nLunch\n\n\n\nReducing formal verification runtime in SystemC utilizing modular interface\nHideki Kazama – Sony\n\n\nHierarchical verification flow for FPGA design projects\nMamma Benmoussa Garsault – Arcys\n\n\nSafeguarding datapath integrity and compliance with formal security verification\nKeerthi Devarajegowda – Siemens\n\n\nEC-FPGA update (including a sneak preview of new synthesizer support)\nKevin Urish\, Siemens\n\n\nCombined formal and functional verification approach for digitally controlled analog frontend\nMihajlo Katona – Veriest\n\n\nFormal technology update and roadmap\nChris Giles\, Siemens\n\n\n\n\nRegister here: https://onespin.com/osmosis-2023/registration\n\nIf you have any questions (including whether if you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis” keyword in the subject header.\nWe look forward to seeing you!!! \nThe Siemens Formal Verification Team \n* The agenda and speakers are subject to change without notice. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/formal-verification-conference-osmosis-2023/ LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231116T080000 DTEND;TZID=Europe/Berlin:20231116T170000 DTSTAMP:20231004T162914Z CREATED:20231004T162914Z LAST-MODIFIED:20231004T162914Z UID:6916-1700121600-1700154000@marketingeda.com SUMMARY:SystemC Evolution Day 2023 DESCRIPTION:Workshop on the Evolution of SystemC Standards: 16 November 2023 \nThe eight SystemC Evolution Day is a full-day\, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions\, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in Accellera/IEEE standards. \nSystemC Evolution Day is intended as a lean\, user-centric\, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards. \nCall for Contributions is Open!\nYou are invited to submit your abstract or presentation now\, using the following email address: systemc-evolution-day@lists.accellera.org.\nFeel free to contact the organization team for more information on the submission process. \nEvent information\nDate: 16 November 2023 (day after DVCon Europe 2023)\nTime: 09:30 – 17:30 CET\nLocation: Holiday Inn Munich City Centre\, Hochstrasse 3\, 81669 Munich\, Germany \nRegistration\n\nEarly bird registration fee (till 1 October): €35.\nRegistration fee after 1 October: €50.\n\nRegister here. \nOrganization Team:\n\nMartin Barnasconi\, NXP\nJerome Cornet\, STMicroelectronics\nMark Burton\, Qualcomm\nPeter de Jager\, Intel\n\nProgram\nWill be announced soon \nContact us\nsystemc-evolution-day@lists.accellera.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/systemc-evolution-day-2023/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SystemC-Evolution-Day-November-16-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231114T080000 DTEND;TZID=Europe/Berlin:20231115T170000 DTSTAMP:20231108T171041Z CREATED:20230227T173351Z LAST-MODIFIED:20231108T171041Z UID:6021-1699948800-1700067600@marketingeda.com SUMMARY:DVCon Europe 2023 DESCRIPTION:The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system\, software\, design\, verification\, validation and integration. It is a place where the latest methodologies and technologies of tools\, languages\, and standards for integrated and embedded systems and products are shared and discussed. \nApplications of interest include (but not limited to) automotive\, mobile communication\, aerospace\, healthcare\, chip-cards\, consumer and power electronics. DVCon Europe solicits submissions related to industrial application or by research in design and verification. Special interest areas are Digital Twin\, Internet-of-Things\, Functional Safety and Security\, ML/AI\, ADAS and Digitalization. \nDVCon Europe 2023 accepts submissions of industrial and academic papers\, tutorials and panels with highly technical content reflecting real life experiences as well as research topics. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-europe-2023/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCON-Europe-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20231107T090000 DTEND;TZID=Asia/Kolkata:20231108T180000 DTSTAMP:20231103T191339Z CREATED:20231103T191339Z LAST-MODIFIED:20231103T191339Z UID:7036-1699347600-1699466400@marketingeda.com SUMMARY:IESA AI Summit DESCRIPTION:Experience the unprecedented growth opportunities in the semiconductor and electronics industry\, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions\, captivating emerging markets in the realm of AI.\nWitness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI\, igniting a renaissance in the electronics landscape. \nIn the dynamic realm of the Intelligent Electronics & Semiconductor ecosystem\, the India Electronics and Semiconductor Association (IESA) eagerly explores the immense potential of AI in the hardware sector. Unlock the limitless possibilities of AI and shape the future of the semiconductor industry. \nEmbrace cutting-edge technologies\, network with industry experts\, and drive innovation at the forefront of AI’s revolution in hardware. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iesa-ai-summit/ LOCATION:Trident Hotel Hyderabad\, Hyderabad\, India CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IESA-AI-Summit-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231106T080000 DTEND;TZID=America/Los_Angeles:20231108T170000 DTSTAMP:20230905T182638Z CREATED:20230905T182638Z LAST-MODIFIED:20230905T182638Z UID:6779-1699257600-1699462800@marketingeda.com SUMMARY:RISC-V Summit US DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V\, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis November\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies to network and build relationships and to experience much more. \n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo full of community members showcasing their the latest community innovations and offerings.\n\nIt’s community-curated content and innovation at the heart of the next wave of growth for RISC-V. \nFind out what’s happening in Automotive\, Data Centers\, Embedded\, Mobile\, AI/ML\, Security\, Software Stacks\, Development Tools\, Systems on a Chip\, Chiplets and more! It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. Meet your heroes. It’s all during RISC-V Week North America\, this November. Come join us! \nJoin us in Santa Clara\, CA for RISC-V Summit 2023! \nFor more information\, visit https://events.linuxfoundation.org/riscv-summit/. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-us/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-SUMMIT-US-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20231031T083000 DTEND;TZID=America/Chicago:20231031T170000 DTSTAMP:20231024T192426Z CREATED:20231024T192233Z LAST-MODIFIED:20231024T192426Z UID:6991-1698741000-1698771600@marketingeda.com SUMMARY:STAC Summit DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment. \nWHEN\nTuesday\, October 31\, 2023\nSTAC Exchange (Exhibits) opens at 8:30am CDT\nConference starts at 9:00am CDT\nNetworking lunch at ~12:00pm CDT\nConference concludes at ~4:00pm CDT\nReception immediately following \nWHERE\nThe Metropolitan Club\nWillis Tower\n233 South Wacker Drive\n66th Floor\nChicago \n\n\n\n9:00am\nSTAC Update: Historical tick analytics\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present the latest results in STAC-M3 (tick analytics).\n\n\n\n\n\n\n9:15am\nInnovation Roundup\n\n\n\n“How to maximize your GPU investment”\nJeff Chu\, Financial Services Sales\, Penguin Solutions\n\n\n\n“Using a vector database to unlock the power of your data”\nJosh Kalina\, Pre-Sales Engineer\, KX\n\n\n\n“Data at Scale: Overcoming Challenges in Generative AI and LLM Development”\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\n\n\n\n\n\n9:35am\nEnforcing the foundation: Improving data lineage      ;\n\n\n\n\n\nMarc Gale\, Director of Data Engineering\, OncoHealth; former Manager of Data Engineering\, Chicago Trading Company\nJosh Kalina\, Pre-Sales Engineer\, KX\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\nIt’s no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets\, which come from many sources with varying quality. Even worse\, today’s data could be corrected tomorrow\, next week\, or next year. For models to stay stable during rapid innovation\, data engineers must properly track\, maintain\, and leverage the data’s lineage. How should they track change sets\, version data\, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix.\n\n\n\n\n\n\n10:05am\nThe unbearable heaviness of data: Can modern approaches help?\n\n\n\n\n\nVrashank Jain\, Sr. Director of Product Management for Data Management Solutions\, Dell Technologies\n\nIt’s common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users\, capture real-time streams\, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Vrashank has seen financial firms greatly reduce the burden of data maintenance\, allowing technologists to focus on developing data products. Using Dell’s experience with an international bank as a guide\, he’ll show how applying an open data platform\, from edge to core to cloud\, can reduce data movement\, consolidate data intelligently\, and allow access to diverse tools and uses\, all while keeping data secure. Be sure to bring your questions for Vrashank as he covers best practices in data modernization and the benefits they can bring.\n\n\n\n\n\n\n10:30am\nBreak\n\n\n\n\n\n\n11:00am\nSTAC Update: Big compute\n\n\n\n\n\nBishop Brock\, Head of Research\, Strategic Technology Analysis Center\n\nBishop and Peter will present the latest STAC Benchmark Council activities compute critical workloads\, including STAC-A2 (complex deriviatives risk computation) and an update from the STAC-ML Working Group.\n\n\n\n\n\n\n11:10am\nWaste not\, want not: Avoiding idle GPUs\n\n\n\n\n\nTroy Kaster\, VP of AI\, Penguin Solutions\n\nMany financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery\, portfolio management\, and quantitative research. But once they fill the compute gap\, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin’s experience bringing a 16k GPU cluster online for Meta\, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing\, building\, deploying\, and managing large-scale GPU clusters.\n\n\n\n\n\n\n11:35am\nInnovation Roundup\n\n\n\n“Build. Connect. Analyse. Beeks solves your colo and network visibility challenges.”\nMatthew Cretney\, Head of Product Management\, Beeks Group\n\n\n\n“Mechanics of Low Latency Capture”\nPramod Nayak\, Director of Product Management\, Low Latency\, Refinitiv\, an LSEG Business\n\n\n\n“The Smart Way to Configure a Tap Aggregator”\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\n\n\n\n\n\n\n11:50am\nEncrypting our markets: The impact of security on high-performance infrastructures\n\n\n\n\n\nVenkat Doddapuneni\, Senior Director of Software Engineering\, CME Group\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\nAdditional speakers to be announced\n\nSecurity has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections\, and at least one exchange has rolled them out. Encryption can provide a layer of protection\, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance\, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They’ll dive into important aspects\, including what concerns motivate a desire for higher security\, what should be in scope\, the impact on performance\, and how to maintain network-based risk\, compliance\, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.\n\n\n\n\n\n\n12:20pm\nNetworking Luncheon\n\n\n\n\n\n\n1:20pm\nSTAC Update: Network communications\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present on the latest STACT Benchmark Council activities in network communications\, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.\n\n\n\n\n\n\n1:35pm\nInnovation Roundup\n\n\n\n“Leveraging HATI for high resolution timing to FPGA’s.”\nCiaran Kennedy\, Sales\, Safran Timing & Navigation\n\n\n\n“Create a Better and Faster Consolidated View Across Markets Using FPGAs”\nCliff Maddox\, Director of Business Development\, NovaSparks\n\n\n\n“Cancel on Behalf is a Game Changer”\nJohn Hagerman\, VP Marketing and Business Development\, Algo-Logic\n\n\n\n“Using Equivalence Checking to Rapidly Evolve Your Design”\nMartin Rowe\, Sr. Application Engineer\, Siemens\n\n\n\n“Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions”\nJean-François Gagnon\, Ultra-Low Latency FPGA Solutions Architect\, Orthogone\n\n\n\n\n\n\n2:00pm\nTalent shortages in hardware verification: Can ML plug the gaps?\n\n\n\n\n\nAdam Sherer\, Verification Technology Executive\, Cadence\n\nAs discussed at recent STAC Summits\, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions\, but a shortage of experienced\, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that\, given the proper setup\, advances in ML can provide some relief by increasing the productivity of current staff. He’ll dive into tasks that grind on an engineer’s time—like regression optimization\, failure triage analysis\, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.\n\n\n\n\n\n\n2:20pm\nBreak\n\n\n\n\n\n\n2:50pm\nSTAC Update: Fast data\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will discuss the latest test results for STAC-N1 (full stack networking).\n\n\n\n\n\n\n2:55pm\nInnovation Roundup\n\n\n\n“ÜberNIC can do… Can Yours?”\nAlex Stein\, Global Head Business Development\, Liquid-Markets-Solutions\n\n\n\n“Trading at the speed of light – Beyond ultra-low latency with Salience Labs”\nChris Porthouse\, Chief Product Officer\, Salience Labs\n\n\n\n“nxFramework update: Added features and improved latency for the Exegy FPGA development framework”\n Laurent de Barry\, Sr. Director\, Global Head of Solutions Consulting\, Exegy\n\n\n\n\n\n\n3:15pm\nDesigning the right hardware stack for FPGA\n\n\n\n\n\nMichael Gorbovitski\, Executive Director\, Morgan Stanley\nRobert DeWitt\, Director Product Marketing\, AMD\nDarrin Machay\, Principal Engineer\, Arista\n\nFGPAs are a go-to component for firms looking to improve their latencies\, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know\, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack\, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute\, memory\, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities\, and what can we achieve with programmable switches? What’s the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.To kick off\, there will be some brief presentations:\n\n\n\n“Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading”\n Hamid Reza Salehi\, Director Product Marketing\, AMD\n\n\n\n“Arista 7130 Update: Ultra Low Latency 25G”\n Darrin Machay\, Principal Engineer\, Arista\n\n\n\n\n\n\n~4:00pm\nNetworking Reception\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/stac-summit-2/ LOCATION:The Metropolitan Club\, 233 South Wacker Drive\, Chicago\, IL\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-October-31-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231029T080000 DTEND;TZID=America/Los_Angeles:20231102T170000 DTSTAMP:20231010T192402Z CREATED:20231010T192402Z LAST-MODIFIED:20231010T192402Z UID:6933-1698566400-1698944400@marketingeda.com SUMMARY:ICCAD 2023 DESCRIPTION:Jointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a long-standing tradition of producing cutting-edge\, innovative technical program for attendees. \n2023 ICCAD Keynote Speakers\nBill Dally\nNVIDIA & Sanford University \nEDA in the Age of Deep Learning\nDeep Learning is affecting a change in EDA tools. Deep networks can accelerate analysis tools. Reinforcement learning and generative models can increase designer productivity and produce better designs. \nThis talk will survey the application of deep learning to EDA tools and give an outlook for the future. \nRon Rohrer\nCarnegie Mellon University \nLessons learned in 60 years in EDA (& other industries)\nRon Rohrer has held both academic and industrial positions during his career of over sixty years. He has been fortunate to have seen and\, in some cases\, to have impacted the EDA field since the 1960s. \nDuring that period he’s observed that while some things have changed\, some have stayed the same and some may be hindering more rapid progress. The talk will cover experiences\, observations and insights garnered from academic and industry perspectives. \nMargaret Martonosi\nPrinceton University \nMind the Gap: Challenges and Opportunities in Closing the Algorithms-to-Devices Gap in Quantum Computing\nFrom its initial proposal\, Quantum Computing (QC) has had captivating potential\, and scientists have worked on advancing toward that potential. With well-known algorithms as motivation\, and increasingly capable hardware devices\, QC has now reached an interesting and important inflection point. The Algorithms-to-Devices gap in QC refers to the orders of magnitude difference between the quantity and quality of resources needed by QC algorithms\, and what has been successfully built today. \nWhat is needed now are computer scientists and engineers to develop the crucial intermediate tool flows\, abstraction layers\, and programming languages that will help QC systems close this gap and reach practical quantum advantage. My talk will offer some recent results from my group about new applications\, architecture\, and design synthesis approaches for bridging the gap. More broadly\, I will advocate for the role that computer scientists and engineers must play in order for QC to reach its full potential. \nVamsi Boppana\nAMD \nAI and EDA: Powering the Next Frontier of Design\nOver the past several decades\, EDA innovation has been foundational to design progress. Rapid advances in design have\, in turn\, created computational capabilities that are now powering the AI revolution. In this talk\, we discuss key advances that have brought us to this point of inflection\, review state-of-the-art AI platform capabilities\, and look at the exciting road ahead with AI advances powering EDA innovation that enables the next frontier of design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-2023/ LOCATION:Hyatt Regency San Francisco Downtown SoMa\, 50 3rd Street\, San Francisco\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Jerusalem:20231024T080000 DTEND;TZID=Asia/Jerusalem:20231024T170000 DTSTAMP:20231003T164756Z CREATED:20231003T164756Z LAST-MODIFIED:20231003T164756Z UID:6907-1698134400-1698166800@marketingeda.com SUMMARY:SemIsrael Expo 2023 DESCRIPTION:SemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. \nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities.​   \nMeet Our Keynote Speakers\nVivek MishraCorporate Vice President – Product EngineeringCadence \nDr. Charlie SuCo-Founder\, President and CTOAndes Technology \nDr. Yervant ZorianChief Architect and FellowSynopsys \nKay EnjojiPresidentTEL Ventures \nLee HarrisonDirector Tessent Product MarketingSiemens EDA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/semisrael-expo-2023/ LOCATION:Avenue Convention Center\, Airport City\, Israel CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/semisrael-expo-2023-logo-blue-795-455.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231015T080000 DTEND;TZID=America/Los_Angeles:20231018T170000 DTSTAMP:20231016T234413Z CREATED:20231016T234413Z LAST-MODIFIED:20231016T234413Z UID:6959-1697356800-1697648400@marketingeda.com SUMMARY:EPEPS 2023 DESCRIPTION:EPEPS is the premier international conference on advanced and emerging issues in electrical modeling\, analysis and design of electronic interconnections\, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal\, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Electronics Packaging Society\, IEEE Microwave Theory and Techniques Society\, and IEEE Antenna and Propagation Society. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/epeps-2023/ LOCATION:Sonesta San Jose – Milpitas\, 777 Bellew Drive\, Milpitas\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/epeps-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20231014T080000 DTEND;TZID=Asia/Shanghai:20231017T170000 DTSTAMP:20230426T190115Z CREATED:20230426T190115Z LAST-MODIFIED:20230426T190115Z UID:6337-1697270400-1697562000@marketingeda.com SUMMARY:IEEE 32nd Asian Test Symposium DESCRIPTION:With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems\, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things\, cloud computing\, automotive electronics\, etc.\, global proliferation and cooperation is increasingly more important. The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system\, board\, and device testing with design\, manufacturing\, and field consideration in mind. \nATS 2023\, the 32nd in the series\, will be held in Beijing China\, on Oct.14-17\, 2023. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-32nd-asian-test-symposium/ CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ATS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231008T080000 DTEND;TZID=America/Los_Angeles:20231013T170000 DTSTAMP:20230811T182512Z CREATED:20230811T182341Z LAST-MODIFIED:20230811T182512Z UID:6699-1696752000-1697216400@marketingeda.com SUMMARY:International Test Conference 2023 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nITC: A FORUM FOR EXCHANGE… THE HARBINGER OF CHANGE\nIn 1970\, engineers facing the test challenges posed by the then-novel semiconductor memory device organized a symposium on IC testing. That meeting at the Rickshaw Inn in Cherry Hill\, NJ drew a crowd of 147 people. That symposium is now a week-long conference attended by more than 2\,000 engineers from around the world including sister ITC conferences in India and Asia. \nIn its fifty-year history\, International Test Conference has become the world’s leading electronics test conference. No other industry has changed as much – or changed the world as much – in those fifty years as semiconductor technology. ITC has kept pace\, always seeking to develop new and innovative ways to fulfill its primary objective: the exchange of technical information. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-test-conference-2023/ LOCATION:Disneyland Hotel\, 1150 West Magic Way\, Anaheim\, CA\, 92802\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231005T080000 DTEND;TZID=America/Los_Angeles:20231006T170000 DTSTAMP:20230917T004644Z CREATED:20230917T004644Z LAST-MODIFIED:20230917T004644Z UID:6804-1696492800-1696611600@marketingeda.com SUMMARY:EDPS 2023 DESCRIPTION:EDPS 2023 is approaching fast! The program is firming up – please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone\, including speakers\, must register. 2023-ieee-edps.eventbrite.com \nNote that this year we’ll be meeting on the Synopsys Campus.\nSynopsys Building 1\n800 North Mary Avenue\nSunnyvale\, CA\, 94085\n  \nMost of the talks from EDPS 2022 and the last 23 years of EDPS are now available\, and searchable\, on the Prior Years page. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/edps-2023/ LOCATION:Synopsys Building 1\, 800 North Mary Avenue\, Sunnyvale\, CA\, 94085\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231002T080000 DTEND;TZID=America/Los_Angeles:20231005T170000 DTSTAMP:20230929T224251Z CREATED:20230929T224230Z LAST-MODIFIED:20230929T224251Z UID:6903-1696233600-1696525200@marketingeda.com SUMMARY:56th International Microelectronics Assembly and Packaging Society (IMAPS) DESCRIPTION:This packed conference brings together industry engineers\, researchers and top experts involved in advanced packaging and microelectronics assembly.  IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+ speakers and posters covering SiP Design / Manufacturing Optimization; Wafer Level / Panel Level (Advanced RDL); High Performance\, High Reliability; Advanced Packages (Flip Chip\, 2.5D\, 3D\, Optical); and Advanced Process & Materials. \nProfessional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at IMAPS 2023 are designed to help attendees broaden their scope of knowledge. \nThe 2023 PDC courses are offered on Monday\, October 2\, prior to IMAPS 2023. Attendees must register for each course as an add-on to their overall symposium registration – additional fee for each PDC selected. Attendees may select up to one course in each time slot.  Make sure to review your preferred course’s time slot before registration. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/56th-international-microelectronics-assembly-and-packaging-society-imaps/ CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMAPS-2023-1.jpg END:VEVENT END:VCALENDAR