BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20220313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20221106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT 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DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Copenhagen BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Stockholm BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240105T080000 DTEND;TZID=America/Los_Angeles:20240107T170000 DTSTAMP:20231228T191521Z CREATED:20231228T191521Z LAST-MODIFIED:20231228T191521Z UID:7476-1704441600-1704646800@marketingeda.com SUMMARY:IEEE Rising Stars 2024 DESCRIPTION:The IEEE Rising Stars Conference is designed to inform\, excite\, enthuse\, and bring together the top engineering Young Professionals and Students around the world to network and be inspired by each other. The program includes Technical Innovation Talks\, Professional Development\, Workshops & Competitions\, and Networking Opportunities with industry and peers. \nThe conference gathers Technical Professionals who are experts in emerging technologies such as: Autonomous Vehicles\, Artificial Intelligence\, Space & Manufacturing\, Power & Sustainability\, Cybersecurity\, IoT & more! \nRising Stars attendees will leave the event with better preparation to face the technical and professional challenges presented to them and armed with the appropriate contacts needed to gain the insight to be successful. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-rising-stars-2024/ LOCATION:Tropicana Las Vegas\, 3801 S Las Vegas Blvd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-Rising-Stars-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20231213T080000 DTEND;TZID=Asia/Kolkata:20231217T170000 DTSTAMP:20231101T195305Z CREATED:20231101T195220Z LAST-MODIFIED:20231101T195305Z UID:7022-1702454400-1702832400@marketingeda.com SUMMARY:International Workshop on Physics of Semiconductor Devices - IWPSD 2023 DESCRIPTION:The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops\, started in 1981\, provides a global forum for interaction between scientists and technologists working in the area of semiconductor materials and devices. \nThe topics to be covered in the Workshop are\, but not limited to:\n\n2D Materials and Devices\nCrystal Growth and Epitaxy\nDevice Modelling and Simulation\nDevices for Quantum Technology\nII – VI and Oxide Semiconductors\nIII – V Semiconductors\nMemory and Logic Devices\nMEMS\, NEMS and Sensors\nOrganic and Flexible Electronics\nPhotovoltaics\nPower Semiconductor Devices\nOptoelectronics\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-workshop-on-physics-of-semiconductor-devices-iwpsd-2023/ LOCATION:Research Park\, IIT Madras\, Tamil Nadu 600036\, Chennai\, India CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWPSD-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231209T080000 DTEND;TZID=America/Los_Angeles:20231213T170000 DTSTAMP:20231207T174511Z CREATED:20230920T171734Z LAST-MODIFIED:20231207T174511Z UID:6838-1702108800-1702486800@marketingeda.com SUMMARY:69th International Electron Devices Meeting - IEDM DESCRIPTION:IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology\, design\, manufacturing\, physics\, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology\, advanced memory\, displays\, sensors\, MEMS devices\, novel quantum and nano-scale devices and phenomenology\, optoelectronics\, devices for power and energy harvesting\, high-speed devices\, as well as process technology and device modeling and simulation. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/69th-international-electron-devices-meeting-iedm/ LOCATION:Hilton San Francisco Union Square\, 333 O'Farrell Street\, San Francisco\, 94102\, United States CATEGORIES:Conference,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEDM-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20231204T090000 DTEND;TZID=Europe/Paris:20231205T170000 DTSTAMP:20231128T173642Z CREATED:20231128T172805Z LAST-MODIFIED:20231128T173642Z UID:7122-1701680400-1701795600@marketingeda.com SUMMARY:IP-SoC Conference 23 - Grenoble DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, Green Electronics\, … \nAnd over all you cannot miss The wine Tasting Party !! \nExhibition tables and “discussion panels” will favor vendor and customer meetings. \nAny question? Please contact us \nRegistration and Exhibition installation opens at 7 am. \n\n\n\n\n\n\nDay 1 – December 4th\, 2023\n\n\n\n\n\n\n\n9.00 am\nIntroduction Session\n\n\n\nWelcome : Innovation in semi conductor industry \nGabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\nEmpowering Innovation in the Age of Custom Silicon \nEric Lalardie\nDirector\nArm Ltd. \nAbout me\n\n\n\n\n9.40 am\nBreak\n\n\n\n10.00 am\nNew technology the lead of innovation\n \nChairperson: Yves Quere – CEA\n\n\n\n\nGreening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology \nPhilippe Flatresse\nProduct Marketing\nSOITEC \nAbout me\n\n\n\n\nTechnologies enabling future mobile connectivity & sensing \nFrancois Brunier\nPartnership Program Manager\nSOITEC \nAbout me\n\n\n\n\nDigital Beamforming design in mmW: A 22nm FDSOI transceiver practical case \nJérôme Prouvée\nLayout Engineer & Project Manager\nCEA \nAbout me\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.20 am\nArtificial Intelligence IP and SoC\n \nChairperson: Costas Conistis – Alphawave Semi\n\n\n\n\nMeeting the Needs of AI Training with HBM3 \nPhilip Van Den Heuvel\nRegional Sales Manager\nRambus\, Inc. \nAbout me\n\n\n\n\nInnovative Integrated IP SoC Design for Edge AI \nTim Menasveta\nDirector of IoT Product Management\nArm Ltd. \nAbout me\n\n\n\n\nTransforming Far-Edge Computer Vision with Energy-Efficient A \nVincent Huard\nChief Technology Officer\nDolphin Design \nAbout me\n\n\n\n\n12.30 pm\nLunch\n\n\n\n1.30 pm\nNew Challenges\n \nChairperson: Eric Lalardie – Arm\n\n\n\n\nThe Lossless Compression Challenge: from Networking to Data centers \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\nAddressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects \nMichael Klempa\nProduct Marking Specialist\nAlphawave Semi \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nSafety Critical Applications\n \nChairperson: Dr. Calliope-Louisa Sotiropoulou – CAST\n\n\n\n\nIP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications \nPhilipp Jacobsohn\nSenior Staff Applications Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nGRLIB: VHDL IP library for fault-tolerant SoC \nFabio Malatesta\nProduct Marketing Engineer\nFrontgrade Gaisler \nAbout me\n\n\n\n\n3.10 pm\nAutomotive Applications\n\n\n\nCAN XL – can safety go in hand with performance? \nJacek Hanke\nCEO\nDigital Core Design \nAbout me\n\n\n\n\nSolve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM \nRuud Derwig\nSenior Staff Engineer for Security IP\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nSecurity Solutions\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nWhich IP for Which Security Certification Standard\, \nLudovic Merrien\nSecurity Certification Leader\nTiempo Secure \nAbout me\n\n\n\n\nLDPC Encoder/Decoder \nManish Mahajan\nFounder\nSecantec\, Inc. \nAbout me\n\n\n\n\nSecurity from chip to cloud with PQC (Post-Quantum Cryptography) \nBrice Gaignoux\nEMEA Pre-Sales Engineer\nSecure-IC \nAbout me\n\n\n\n\n5.20 pm\nBreak\n\n\n\n5.40 pm\nSecurity Solutions – 2\n \nChairperson: Ruud Derwig – Synopsys\, Inc.\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nHow will platform and communication security evolve in the quantum computing era? \nGraeme Hickey\nVP Engineering\nPQShield \nAbout me\n\n\n\n\nThe Power of Physical Unclonable Functions (PUFs) \nChris Jones\nDirector\, Field Application\nCrypto Quantique \nAbout me\n\n\n\n\n7.00 pm\nYou should not miss ! \nWine tasting party sponsored by Soitec\n\n\n\n\n8.00 pm\nBanquet sponsored by D&R\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2 – December 5th\, 2023\n\n\n\n\n\n\n\n9.00 am\nProcessor IP\n \nChairperson: Philippe Quinio – STMicroelectronics\n\n\n\n\nBeyond one-size-fits-all: The power of tailored CPUs \nMike Eftimakis\nVP Strategy & Ecosystem\nCodasip GmbH \nAbout me\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSurvey of market available processor IP \n\n\n\nDagmara Zielinska\nPartnership Program Manager\nD&Rwith Gabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\n\n\n\n\n9.40 – 11.00 am\nFrom Processor IP to Processor or supercomputer chip:  \n\nWhat is needed and what is the next success track ? \nThis panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.\n\nWith the participation of: \n\nFabio Malatesta – Product Marketing Engineer – Frontgrade Gaisler\nMike Eftimakis – VP Strategy and Ecosystem – Codasip GmbH\nLoic Lietar – Co-Founder & CEO – GreenWaves Technologies\nThierry Lelégard – Head of Platform Security – SiPearl\n\n\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.30 am\nAnalog IP\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\nAdaptive Voltage Scaling (AVS): Enhancing Chip Efficiency \nVincent Telandro\nProduct Marketing manager (Power Management IP)\nDolphin Design \nAbout me\n\n\n\n\nTechnology Analysis: what you need to know before embarking on analog design migration \nJean-François Lambert\nDirector of Business Development\nThalia \nAbout me\n\n\n\n\n12.15 pm\nLunch\n\n\n\n1.20 pm\nDesign Platform\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHybrid Cloud Management for IP Development \n\n\n\nSundar M\nDirector\nTessolve Semiconductor Private Limitedwith Pitchumani Guruswamy\nTessolve Semiconductor Private Limited \nAbout me\n\n\n\n\nOnline Only\n\n\n\n\nA novel approach for SoC design resource management and prediction \nChouki Aktouf\nCo-Founder\nInnova Advanced Technologies \nAbout me\n\n\n\n\nMulti-IO co-processor with TSN \nVincent Laporte\nCTO – V.P. BU\nCetraC \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nVerification Platform\n \nChairperson: Patrick Blouet\n\n\n\n\nIP QA Best Practices \nLionel Couder\nSr. Applications Engineer\nSiemens Digital Industries Software \nAbout me\n\n\n\n\nImportant Considerations for Verification of CXL Devices \nNicolas Dai\nApplication Engineer Architect\nCadence Design Systems\, Inc. \nAbout me\n\n\n\n\n3.10 pm\nMonitoring Platform\n\n\n\nChip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology. \nVsevolod Sergeenko\nRFID Team Leader\nNTLab \nAbout me\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nDan Alexandrescu\nR&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nGive Away – Event Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-conference-23-grenoble/ LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-23-Grenoble.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Istanbul:20231204T080000 DTEND;TZID=Europe/Istanbul:20231207T170000 DTSTAMP:20230313T211025Z CREATED:20230313T210903Z LAST-MODIFIED:20230313T211025Z UID:6124-1701676800-1701968400@marketingeda.com SUMMARY:IEEE 30th International Conference on Electronics\, Circuits and Systems (ICECS) DESCRIPTION:The IEEE 30th International Conference on Electronics\, Circuits and Systems (ICECS) will be held in Istanbul\, Turkey 4-7 December 2023. As the flagship conference of IEEE Circuits and Systems Society in Region 8 (Europe\, Middle East\, and Africa)\, ICECS 2023 will consist of tutorials\, plenary lectures\, regular\, special and poster sessions focusing on recent trends\, emerging technologies and advances. \n  \nTracks\n  \n\nAnalog/Mixed-Signal/Microwave Circuits\nBio-Medical\, Bio-Inspired Circuits/Systems\nEDA\, Test and Reliability\nDigital Circuits and Systems\nLinear and Non-Linear Circuits and Systems\nNon-Linear Devices\, Memristors\nLow-Power\, Low-Voltage Design\nEmbedded and Micro/Systems\nNeural Networks\, Machine/Deep Learning\nSensors and Sensing Systems\nSignal Processing\, Image and Video\nVLSI Systems and Applications\nSmart Systems for CAS Applications\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-30th-international-conference-on-electronics-circuits-and-systems-icecs/ LOCATION:Hilton Maslak\, Büyükdere Cd. No:233\, Istanbul\, Turkey CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICECS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231116T080000 DTEND;TZID=Europe/Berlin:20231116T170000 DTSTAMP:20231022T003818Z CREATED:20231022T003818Z LAST-MODIFIED:20231022T003818Z UID:6984-1700121600-1700154000@marketingeda.com SUMMARY:Formal Verification Conference: Osmosis 2023 DESCRIPTION:Elevate your success with osmosis 2023\nOsmosis is about sharing success in using formal techniques to solve verification challenges\, and networking with our R&D experts and other attendees. As such\, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product roadmaps. \nConference program\nCheck-in and continental breakfast – doors open at 8:00 AM\, Program starts at 9:00 AM \n\n\n\nTopic\nPresenter\n\n\nLimits of verification: learnings from catastrophic system failures\nPhilippe Luc – Codasip\n\n\nSpectres\, Meltdowns\, Zombies\, Orcs:  How formal methods could banish the ghosts that haunt our computing systems\nProf. Wolfgang Kunz – RPTU\n\n\nHow to sign-off cryptographic hash implementations with generated formal assertions\nTobias Ludwig – Lubis EDA\n\n\nDebugging enhancements for formal property checking\nHolger Busch – Infineon\n\n\nLunch\n\n\n\nReducing formal verification runtime in SystemC utilizing modular interface\nHideki Kazama – Sony\n\n\nHierarchical verification flow for FPGA design projects\nMamma Benmoussa Garsault – Arcys\n\n\nSafeguarding datapath integrity and compliance with formal security verification\nKeerthi Devarajegowda – Siemens\n\n\nEC-FPGA update (including a sneak preview of new synthesizer support)\nKevin Urish\, Siemens\n\n\nCombined formal and functional verification approach for digitally controlled analog frontend\nMihajlo Katona – Veriest\n\n\nFormal technology update and roadmap\nChris Giles\, Siemens\n\n\n\n\nRegister here: https://onespin.com/osmosis-2023/registration\n\nIf you have any questions (including whether if you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis” keyword in the subject header.\nWe look forward to seeing you!!! \nThe Siemens Formal Verification Team \n* The agenda and speakers are subject to change without notice. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/formal-verification-conference-osmosis-2023/ LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231116T080000 DTEND;TZID=Europe/Berlin:20231116T170000 DTSTAMP:20231004T162914Z CREATED:20231004T162914Z LAST-MODIFIED:20231004T162914Z UID:6916-1700121600-1700154000@marketingeda.com SUMMARY:SystemC Evolution Day 2023 DESCRIPTION:Workshop on the Evolution of SystemC Standards: 16 November 2023 \nThe eight SystemC Evolution Day is a full-day\, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions\, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in Accellera/IEEE standards. \nSystemC Evolution Day is intended as a lean\, user-centric\, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards. \nCall for Contributions is Open!\nYou are invited to submit your abstract or presentation now\, using the following email address: systemc-evolution-day@lists.accellera.org.\nFeel free to contact the organization team for more information on the submission process. \nEvent information\nDate: 16 November 2023 (day after DVCon Europe 2023)\nTime: 09:30 – 17:30 CET\nLocation: Holiday Inn Munich City Centre\, Hochstrasse 3\, 81669 Munich\, Germany \nRegistration\n\nEarly bird registration fee (till 1 October): €35.\nRegistration fee after 1 October: €50.\n\nRegister here. \nOrganization Team:\n\nMartin Barnasconi\, NXP\nJerome Cornet\, STMicroelectronics\nMark Burton\, Qualcomm\nPeter de Jager\, Intel\n\nProgram\nWill be announced soon \nContact us\nsystemc-evolution-day@lists.accellera.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/systemc-evolution-day-2023/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SystemC-Evolution-Day-November-16-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231114T080000 DTEND;TZID=Europe/Berlin:20231115T170000 DTSTAMP:20231108T171041Z CREATED:20230227T173351Z LAST-MODIFIED:20231108T171041Z UID:6021-1699948800-1700067600@marketingeda.com SUMMARY:DVCon Europe 2023 DESCRIPTION:The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system\, software\, design\, verification\, validation and integration. It is a place where the latest methodologies and technologies of tools\, languages\, and standards for integrated and embedded systems and products are shared and discussed. \nApplications of interest include (but not limited to) automotive\, mobile communication\, aerospace\, healthcare\, chip-cards\, consumer and power electronics. DVCon Europe solicits submissions related to industrial application or by research in design and verification. Special interest areas are Digital Twin\, Internet-of-Things\, Functional Safety and Security\, ML/AI\, ADAS and Digitalization. \nDVCon Europe 2023 accepts submissions of industrial and academic papers\, tutorials and panels with highly technical content reflecting real life experiences as well as research topics. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-europe-2023/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCON-Europe-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20231107T090000 DTEND;TZID=Asia/Kolkata:20231108T180000 DTSTAMP:20231103T191339Z CREATED:20231103T191339Z LAST-MODIFIED:20231103T191339Z UID:7036-1699347600-1699466400@marketingeda.com SUMMARY:IESA AI Summit DESCRIPTION:Experience the unprecedented growth opportunities in the semiconductor and electronics industry\, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions\, captivating emerging markets in the realm of AI.\nWitness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI\, igniting a renaissance in the electronics landscape. \nIn the dynamic realm of the Intelligent Electronics & Semiconductor ecosystem\, the India Electronics and Semiconductor Association (IESA) eagerly explores the immense potential of AI in the hardware sector. Unlock the limitless possibilities of AI and shape the future of the semiconductor industry. \nEmbrace cutting-edge technologies\, network with industry experts\, and drive innovation at the forefront of AI’s revolution in hardware. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iesa-ai-summit/ LOCATION:Trident Hotel Hyderabad\, Hyderabad\, India CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IESA-AI-Summit-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231106T080000 DTEND;TZID=America/Los_Angeles:20231108T170000 DTSTAMP:20230905T182638Z CREATED:20230905T182638Z LAST-MODIFIED:20230905T182638Z UID:6779-1699257600-1699462800@marketingeda.com SUMMARY:RISC-V Summit US DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V\, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis November\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies to network and build relationships and to experience much more. \n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo full of community members showcasing their the latest community innovations and offerings.\n\nIt’s community-curated content and innovation at the heart of the next wave of growth for RISC-V. \nFind out what’s happening in Automotive\, Data Centers\, Embedded\, Mobile\, AI/ML\, Security\, Software Stacks\, Development Tools\, Systems on a Chip\, Chiplets and more! It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. Meet your heroes. It’s all during RISC-V Week North America\, this November. Come join us! \nJoin us in Santa Clara\, CA for RISC-V Summit 2023! \nFor more information\, visit https://events.linuxfoundation.org/riscv-summit/. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-us/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-SUMMIT-US-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20231031T083000 DTEND;TZID=America/Chicago:20231031T170000 DTSTAMP:20231024T192426Z CREATED:20231024T192233Z LAST-MODIFIED:20231024T192426Z UID:6991-1698741000-1698771600@marketingeda.com SUMMARY:STAC Summit DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment. \nWHEN\nTuesday\, October 31\, 2023\nSTAC Exchange (Exhibits) opens at 8:30am CDT\nConference starts at 9:00am CDT\nNetworking lunch at ~12:00pm CDT\nConference concludes at ~4:00pm CDT\nReception immediately following \nWHERE\nThe Metropolitan Club\nWillis Tower\n233 South Wacker Drive\n66th Floor\nChicago \n\n\n\n9:00am\nSTAC Update: Historical tick analytics\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present the latest results in STAC-M3 (tick analytics).\n\n\n\n\n\n\n9:15am\nInnovation Roundup\n\n\n\n“How to maximize your GPU investment”\nJeff Chu\, Financial Services Sales\, Penguin Solutions\n\n\n\n“Using a vector database to unlock the power of your data”\nJosh Kalina\, Pre-Sales Engineer\, KX\n\n\n\n“Data at Scale: Overcoming Challenges in Generative AI and LLM Development”\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\n\n\n\n\n\n9:35am\nEnforcing the foundation: Improving data lineage      ;\n\n\n\n\n\nMarc Gale\, Director of Data Engineering\, OncoHealth; former Manager of Data Engineering\, Chicago Trading Company\nJosh Kalina\, Pre-Sales Engineer\, KX\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\nIt’s no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets\, which come from many sources with varying quality. Even worse\, today’s data could be corrected tomorrow\, next week\, or next year. For models to stay stable during rapid innovation\, data engineers must properly track\, maintain\, and leverage the data’s lineage. How should they track change sets\, version data\, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix.\n\n\n\n\n\n\n10:05am\nThe unbearable heaviness of data: Can modern approaches help?\n\n\n\n\n\nVrashank Jain\, Sr. Director of Product Management for Data Management Solutions\, Dell Technologies\n\nIt’s common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users\, capture real-time streams\, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Vrashank has seen financial firms greatly reduce the burden of data maintenance\, allowing technologists to focus on developing data products. Using Dell’s experience with an international bank as a guide\, he’ll show how applying an open data platform\, from edge to core to cloud\, can reduce data movement\, consolidate data intelligently\, and allow access to diverse tools and uses\, all while keeping data secure. Be sure to bring your questions for Vrashank as he covers best practices in data modernization and the benefits they can bring.\n\n\n\n\n\n\n10:30am\nBreak\n\n\n\n\n\n\n11:00am\nSTAC Update: Big compute\n\n\n\n\n\nBishop Brock\, Head of Research\, Strategic Technology Analysis Center\n\nBishop and Peter will present the latest STAC Benchmark Council activities compute critical workloads\, including STAC-A2 (complex deriviatives risk computation) and an update from the STAC-ML Working Group.\n\n\n\n\n\n\n11:10am\nWaste not\, want not: Avoiding idle GPUs\n\n\n\n\n\nTroy Kaster\, VP of AI\, Penguin Solutions\n\nMany financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery\, portfolio management\, and quantitative research. But once they fill the compute gap\, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin’s experience bringing a 16k GPU cluster online for Meta\, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing\, building\, deploying\, and managing large-scale GPU clusters.\n\n\n\n\n\n\n11:35am\nInnovation Roundup\n\n\n\n“Build. Connect. Analyse. Beeks solves your colo and network visibility challenges.”\nMatthew Cretney\, Head of Product Management\, Beeks Group\n\n\n\n“Mechanics of Low Latency Capture”\nPramod Nayak\, Director of Product Management\, Low Latency\, Refinitiv\, an LSEG Business\n\n\n\n“The Smart Way to Configure a Tap Aggregator”\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\n\n\n\n\n\n\n11:50am\nEncrypting our markets: The impact of security on high-performance infrastructures\n\n\n\n\n\nVenkat Doddapuneni\, Senior Director of Software Engineering\, CME Group\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\nAdditional speakers to be announced\n\nSecurity has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections\, and at least one exchange has rolled them out. Encryption can provide a layer of protection\, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance\, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They’ll dive into important aspects\, including what concerns motivate a desire for higher security\, what should be in scope\, the impact on performance\, and how to maintain network-based risk\, compliance\, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.\n\n\n\n\n\n\n12:20pm\nNetworking Luncheon\n\n\n\n\n\n\n1:20pm\nSTAC Update: Network communications\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present on the latest STACT Benchmark Council activities in network communications\, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.\n\n\n\n\n\n\n1:35pm\nInnovation Roundup\n\n\n\n“Leveraging HATI for high resolution timing to FPGA’s.”\nCiaran Kennedy\, Sales\, Safran Timing & Navigation\n\n\n\n“Create a Better and Faster Consolidated View Across Markets Using FPGAs”\nCliff Maddox\, Director of Business Development\, NovaSparks\n\n\n\n“Cancel on Behalf is a Game Changer”\nJohn Hagerman\, VP Marketing and Business Development\, Algo-Logic\n\n\n\n“Using Equivalence Checking to Rapidly Evolve Your Design”\nMartin Rowe\, Sr. Application Engineer\, Siemens\n\n\n\n“Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions”\nJean-François Gagnon\, Ultra-Low Latency FPGA Solutions Architect\, Orthogone\n\n\n\n\n\n\n2:00pm\nTalent shortages in hardware verification: Can ML plug the gaps?\n\n\n\n\n\nAdam Sherer\, Verification Technology Executive\, Cadence\n\nAs discussed at recent STAC Summits\, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions\, but a shortage of experienced\, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that\, given the proper setup\, advances in ML can provide some relief by increasing the productivity of current staff. He’ll dive into tasks that grind on an engineer’s time—like regression optimization\, failure triage analysis\, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.\n\n\n\n\n\n\n2:20pm\nBreak\n\n\n\n\n\n\n2:50pm\nSTAC Update: Fast data\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will discuss the latest test results for STAC-N1 (full stack networking).\n\n\n\n\n\n\n2:55pm\nInnovation Roundup\n\n\n\n“ÜberNIC can do… Can Yours?”\nAlex Stein\, Global Head Business Development\, Liquid-Markets-Solutions\n\n\n\n“Trading at the speed of light – Beyond ultra-low latency with Salience Labs”\nChris Porthouse\, Chief Product Officer\, Salience Labs\n\n\n\n“nxFramework update: Added features and improved latency for the Exegy FPGA development framework”\n Laurent de Barry\, Sr. Director\, Global Head of Solutions Consulting\, Exegy\n\n\n\n\n\n\n3:15pm\nDesigning the right hardware stack for FPGA\n\n\n\n\n\nMichael Gorbovitski\, Executive Director\, Morgan Stanley\nRobert DeWitt\, Director Product Marketing\, AMD\nDarrin Machay\, Principal Engineer\, Arista\n\nFGPAs are a go-to component for firms looking to improve their latencies\, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know\, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack\, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute\, memory\, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities\, and what can we achieve with programmable switches? What’s the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.To kick off\, there will be some brief presentations:\n\n\n\n“Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading”\n Hamid Reza Salehi\, Director Product Marketing\, AMD\n\n\n\n“Arista 7130 Update: Ultra Low Latency 25G”\n Darrin Machay\, Principal Engineer\, Arista\n\n\n\n\n\n\n~4:00pm\nNetworking Reception\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/stac-summit-2/ LOCATION:The Metropolitan Club\, 233 South Wacker Drive\, Chicago\, IL\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-October-31-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231029T080000 DTEND;TZID=America/Los_Angeles:20231102T170000 DTSTAMP:20231010T192402Z CREATED:20231010T192402Z LAST-MODIFIED:20231010T192402Z UID:6933-1698566400-1698944400@marketingeda.com SUMMARY:ICCAD 2023 DESCRIPTION:Jointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a long-standing tradition of producing cutting-edge\, innovative technical program for attendees. \n2023 ICCAD Keynote Speakers\nBill Dally\nNVIDIA & Sanford University \nEDA in the Age of Deep Learning\nDeep Learning is affecting a change in EDA tools. Deep networks can accelerate analysis tools. Reinforcement learning and generative models can increase designer productivity and produce better designs. \nThis talk will survey the application of deep learning to EDA tools and give an outlook for the future. \nRon Rohrer\nCarnegie Mellon University \nLessons learned in 60 years in EDA (& other industries)\nRon Rohrer has held both academic and industrial positions during his career of over sixty years. He has been fortunate to have seen and\, in some cases\, to have impacted the EDA field since the 1960s. \nDuring that period he’s observed that while some things have changed\, some have stayed the same and some may be hindering more rapid progress. The talk will cover experiences\, observations and insights garnered from academic and industry perspectives. \nMargaret Martonosi\nPrinceton University \nMind the Gap: Challenges and Opportunities in Closing the Algorithms-to-Devices Gap in Quantum Computing\nFrom its initial proposal\, Quantum Computing (QC) has had captivating potential\, and scientists have worked on advancing toward that potential. With well-known algorithms as motivation\, and increasingly capable hardware devices\, QC has now reached an interesting and important inflection point. The Algorithms-to-Devices gap in QC refers to the orders of magnitude difference between the quantity and quality of resources needed by QC algorithms\, and what has been successfully built today. \nWhat is needed now are computer scientists and engineers to develop the crucial intermediate tool flows\, abstraction layers\, and programming languages that will help QC systems close this gap and reach practical quantum advantage. My talk will offer some recent results from my group about new applications\, architecture\, and design synthesis approaches for bridging the gap. More broadly\, I will advocate for the role that computer scientists and engineers must play in order for QC to reach its full potential. \nVamsi Boppana\nAMD \nAI and EDA: Powering the Next Frontier of Design\nOver the past several decades\, EDA innovation has been foundational to design progress. Rapid advances in design have\, in turn\, created computational capabilities that are now powering the AI revolution. In this talk\, we discuss key advances that have brought us to this point of inflection\, review state-of-the-art AI platform capabilities\, and look at the exciting road ahead with AI advances powering EDA innovation that enables the next frontier of design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-2023/ LOCATION:Hyatt Regency San Francisco Downtown SoMa\, 50 3rd Street\, San Francisco\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Jerusalem:20231024T080000 DTEND;TZID=Asia/Jerusalem:20231024T170000 DTSTAMP:20231003T164756Z CREATED:20231003T164756Z LAST-MODIFIED:20231003T164756Z UID:6907-1698134400-1698166800@marketingeda.com SUMMARY:SemIsrael Expo 2023 DESCRIPTION:SemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. \nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities.​   \nMeet Our Keynote Speakers\nVivek MishraCorporate Vice President – Product EngineeringCadence \nDr. Charlie SuCo-Founder\, President and CTOAndes Technology \nDr. Yervant ZorianChief Architect and FellowSynopsys \nKay EnjojiPresidentTEL Ventures \nLee HarrisonDirector Tessent Product MarketingSiemens EDA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/semisrael-expo-2023/ LOCATION:Avenue Convention Center\, Airport City\, Israel CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/semisrael-expo-2023-logo-blue-795-455.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231015T080000 DTEND;TZID=America/Los_Angeles:20231018T170000 DTSTAMP:20231016T234413Z CREATED:20231016T234413Z LAST-MODIFIED:20231016T234413Z UID:6959-1697356800-1697648400@marketingeda.com SUMMARY:EPEPS 2023 DESCRIPTION:EPEPS is the premier international conference on advanced and emerging issues in electrical modeling\, analysis and design of electronic interconnections\, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal\, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Electronics Packaging Society\, IEEE Microwave Theory and Techniques Society\, and IEEE Antenna and Propagation Society. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/epeps-2023/ LOCATION:Sonesta San Jose – Milpitas\, 777 Bellew Drive\, Milpitas\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/epeps-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20231014T080000 DTEND;TZID=Asia/Shanghai:20231017T170000 DTSTAMP:20230426T190115Z CREATED:20230426T190115Z LAST-MODIFIED:20230426T190115Z UID:6337-1697270400-1697562000@marketingeda.com SUMMARY:IEEE 32nd Asian Test Symposium DESCRIPTION:With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems\, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things\, cloud computing\, automotive electronics\, etc.\, global proliferation and cooperation is increasingly more important. The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system\, board\, and device testing with design\, manufacturing\, and field consideration in mind. \nATS 2023\, the 32nd in the series\, will be held in Beijing China\, on Oct.14-17\, 2023. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-32nd-asian-test-symposium/ CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ATS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231008T080000 DTEND;TZID=America/Los_Angeles:20231013T170000 DTSTAMP:20230811T182512Z CREATED:20230811T182341Z LAST-MODIFIED:20230811T182512Z UID:6699-1696752000-1697216400@marketingeda.com SUMMARY:International Test Conference 2023 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nITC: A FORUM FOR EXCHANGE… THE HARBINGER OF CHANGE\nIn 1970\, engineers facing the test challenges posed by the then-novel semiconductor memory device organized a symposium on IC testing. That meeting at the Rickshaw Inn in Cherry Hill\, NJ drew a crowd of 147 people. That symposium is now a week-long conference attended by more than 2\,000 engineers from around the world including sister ITC conferences in India and Asia. \nIn its fifty-year history\, International Test Conference has become the world’s leading electronics test conference. No other industry has changed as much – or changed the world as much – in those fifty years as semiconductor technology. ITC has kept pace\, always seeking to develop new and innovative ways to fulfill its primary objective: the exchange of technical information. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/international-test-conference-2023/ LOCATION:Disneyland Hotel\, 1150 West Magic Way\, Anaheim\, CA\, 92802\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231005T080000 DTEND;TZID=America/Los_Angeles:20231006T170000 DTSTAMP:20230917T004644Z CREATED:20230917T004644Z LAST-MODIFIED:20230917T004644Z UID:6804-1696492800-1696611600@marketingeda.com SUMMARY:EDPS 2023 DESCRIPTION:EDPS 2023 is approaching fast! The program is firming up – please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone\, including speakers\, must register. 2023-ieee-edps.eventbrite.com \nNote that this year we’ll be meeting on the Synopsys Campus.\nSynopsys Building 1\n800 North Mary Avenue\nSunnyvale\, CA\, 94085\n  \nMost of the talks from EDPS 2022 and the last 23 years of EDPS are now available\, and searchable\, on the Prior Years page. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/edps-2023/ LOCATION:Synopsys Building 1\, 800 North Mary Avenue\, Sunnyvale\, CA\, 94085\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231002T080000 DTEND;TZID=America/Los_Angeles:20231005T170000 DTSTAMP:20230929T224251Z CREATED:20230929T224230Z LAST-MODIFIED:20230929T224251Z UID:6903-1696233600-1696525200@marketingeda.com SUMMARY:56th International Microelectronics Assembly and Packaging Society (IMAPS) DESCRIPTION:This packed conference brings together industry engineers\, researchers and top experts involved in advanced packaging and microelectronics assembly.  IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+ speakers and posters covering SiP Design / Manufacturing Optimization; Wafer Level / Panel Level (Advanced RDL); High Performance\, High Reliability; Advanced Packages (Flip Chip\, 2.5D\, 3D\, Optical); and Advanced Process & Materials. \nProfessional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at IMAPS 2023 are designed to help attendees broaden their scope of knowledge. \nThe 2023 PDC courses are offered on Monday\, October 2\, prior to IMAPS 2023. Attendees must register for each course as an add-on to their overall symposium registration – additional fee for each PDC selected. Attendees may select up to one course in each time slot.  Make sure to review your preferred course’s time slot before registration. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/56th-international-microelectronics-assembly-and-packaging-society-imaps/ CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMAPS-2023-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20230925T080000 DTEND;TZID=Asia/Tokyo:20230927T170000 DTSTAMP:20230922T165957Z CREATED:20230922T165957Z LAST-MODIFIED:20230922T165957Z UID:6861-1695628800-1695834000@marketingeda.com SUMMARY:20th International Conference on IC Design and Technology (ICICDT) DESCRIPTION:2023 ICICDT is the twentieth edition (20th) in the series of the International Conference on IC Design and Technology\, organized since 2004. 2023 ICICDT will be co-organized and held at the University of Tokyo\, Tokyo\, Japan from September 25-27\, 2023. Design and technology co-optimization (DTCO) plays a critical role in the era of big data with an explosion of new applications in the prominent fields of artificial intelligence (AI) and 5G. To meet the ever-growing demand for speed and power efficiency in data computing and transmission\, separating design and technology\, as is done in traditional integrated circuit (IC) engineering\, encounters significant challenges. The ever-increasing complexity and variability require close interaction and collaboration for best optimization and trade-off by design\, device\, process and materials. Savvy IC engineers also require a deeper understanding of the interdependencies between design and technology options to expand the product optimization window. ICICDT is\, by design\, a forum for engineers\, researchers\, graduate students\, and professors\, to cross the design-technology boundary by bringing design\, technology\, and process experts together. ICICDT has a unique format where each paper has a short presentation and a poster to encourage inquisitive discussions and the sharing of knowledge on a one-to-one basis during the poster session. This conference workshop style provides an excellent opportunity for all attendees to exchange breakthrough ideas and collaborate efficiently. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/20th-international-conference-on-ic-design-and-technology-icicdt/ LOCATION:University of Tokyo\, 7 Chome-3-1 Hongo\, Tokyo\, Japan CATEGORIES:Conference ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICICDT-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230919T080000 DTEND;TZID=America/Los_Angeles:20230922T170000 DTSTAMP:20230918T231423Z CREATED:20230918T231423Z LAST-MODIFIED:20230918T231423Z UID:6821-1695110400-1695402000@marketingeda.com SUMMARY:PCB West 2023 DESCRIPTION:The Largest Conference and Exhibition for Printed Circuit Board Design\,\nFabrication and Assembly in the Silicon Valley \n\n\n\n\n\n\nFor more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics! \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pcb-west-2023/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Brussels:20230919T080000 DTEND;TZID=Europe/Brussels:20230921T170000 DTSTAMP:20230801T171626Z CREATED:20230801T171626Z LAST-MODIFIED:20230801T171626Z UID:6634-1695110400-1695315600@marketingeda.com SUMMARY:AutoSens Brussels 2023 DESCRIPTION:We’re bringing AutoSens to Autoworld in Brussels once again to meet and shape the future of ADAS and AV. \nYou can look forward to the freshest agenda of over 60 speakers across expert panels\, technical case studies\, and sessions covering 12 key themes. You will experience an exhibition full of demos from technology companies at the forefront of sensors and computer vision to explore. \nJoin us on 19-21 September 2023 at the Autoworld Museum in Brussels. \n\n\nWindshield Technology\n\n\n\n\nEvery vehicle has one\, but are they optimised for ADAS/AD? A plenary session will consider the challenges of light\, heat\, tilt and yaw\, measurement\, and other important factors when pairing cameras with windshields. \n\n\nInfrastructure\n\n\n\n\nA keynote session will explore infrastructure from a perception and observation perspective\, as well as the communication between vehicles and the world around them (V2I and V2X). \n\n\nCyber Security & Data Privacy\n\n\n\n\nWith L4 and L5 drawing closer\, we must consider the ‘hackability’ of vehicles more than ever before\, not only for occupant safety\, but to prevent (or at least minimise) the weaponisation of autonomous vehicles.  \n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/autosens-brussels-2023/ LOCATION:Autoworld Museum\, 1000 Brussels\, Brussels\, Belgium CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Brussels-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20230915T080000 DTEND;TZID=Europe/Berlin:20230917T170000 DTSTAMP:20230522T195247Z CREATED:20230522T195211Z LAST-MODIFIED:20230522T195247Z UID:6422-1694764800-1694970000@marketingeda.com SUMMARY:ORConf 2023 DESCRIPTION:FOSSi Foundation are pleased to announce ORConf 2023 will be taking place in beautiful Munich\, Germany on September\, 15th to 17th\, 2023. It will start Friday morning and Sunday is currently reserved for tutorials and workshops. \n\nORConf is an annual conference for open source digital\, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space. \nWe invite anyone with an interest in the field to join us and also consider a presentation\, big or small\, on your experience as a developer or a user of open source digital design projects. \nORConf remains to be free to attend thanks to each year’s sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf! \nORConf is organized by the Free and Open Source Silicon (FOSSi) Foundation. \nQuestions? Contact the organisers. \nSubmit a talk\n\nWe encourage anyone involved in the open source semiconductor engineering space to come along and give share your work or experience. \nThis year we’re offering lightning talk and 15-minute speaking slots\, with the choice of opting in to be considered for an extended slot of 30-40 minutes. We are intentionally reducing the standard speaking slot length this year to ensure we can accommodate all of the exceptional talk submissions we receive\, and to maximize face-to-face time throughout the event. We encourage speakers to skip the technical deep-dive presentations and instead provide high-level introductions and overviews of what makes their work great\, and prepare a poster or hardware demo for people to come and discuss details during the breaks. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2023/ LOCATION:Hochschule Munchen University of Applied Sciences\, Lothstr. 64\, Munich\, Germany CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Copenhagen:20230914T080000 DTEND;TZID=Europe/Copenhagen:20230914T170000 DTSTAMP:20230901T173607Z CREATED:20230901T173607Z LAST-MODIFIED:20230901T173607Z UID:6773-1694678400-1694710800@marketingeda.com SUMMARY:FPGAworld Conference 2023 - Copenhagen DESCRIPTION:The FPGAworld Conference is an international forum for researchers\, engineers\, teachers\, students\, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems\, FPGA/ASIC-based products\, educational & industrial cases\, and more. Registration for attendees is free and includes 2*coffee\, lunch and go-home drink. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpgaworld-conference-2023-copenhagen-2/ LOCATION:DTU Science Park\, 2800 Kongens\, Lyngby\, Denmark CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGAworld-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20230914T080000 DTEND;TZID=America/Chicago:20230914T170000 DTSTAMP:20230808T170957Z CREATED:20230619T165240Z LAST-MODIFIED:20230808T170957Z UID:6524-1694678400-1694710800@marketingeda.com SUMMARY:Verification Futures 2023 Austin DESCRIPTION:The Verification Futures conferences is dedicated to discussing the challenges faced in hardware and software verification. \nTo view the agenda for this event please visit the VF2023 Event Page. \nThe full conference program includes 17 talks covering verification challenges and solutions\, formal verification\,  RISC-V\,  System Verilog\, UVM for AMS Verification\, and VHDL Verification \nView the full conference agenda below. \n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nSafety and Security challenges in hardware IP development \nVivek Vedula (Arm Ltd.)\n\n\n\n\n\nUser Top Verification Challenges\n\n\n\n\n10:15\nEricsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life \nAlex Duhovich (Ericsson)\n\n\n\n\n10:30\nEngines\, Logistics and AI \nBahadir Erimli (Cadence Design Systems) Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser Presentations\n\n\n\n\n11:30\n10 years of Verification Challenges \nMike Bartley(Tessolve Semiconductor Ltd)\n\n\n\n\n11:40\nRISCV CPU Verification – Opportunities and Challenges \nDivyang Agrawal(Tenstorrent\, Inc)\n\n\n\n\n12:10\nValidation of Hybrid Architectures \nSuneil Mohan(Intel Corporation)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nWhat Can Formal Do For Me? \nDoug Smith (Doulos) Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nRenesas’s Submission to the UVM-(A)MS working group \nPeter Grove\, Steven Holloway (Renesas)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nA Modern Fable: The Lost Art of Processor Verification \nLarry Lapides (Imperas Software Ltd.) Platinum Sponsor\n\n\n\n\n14:00\nAdvanced RISC-V Verification Technique Learnings for SoC Validation \nAdnan Hamid (Breker Verification Systems) Gold Sponsor\n\n\n\n\n14:20\nImprove the Quality of the Testbenches using specialized PySlint solutions \nBalram Naik Meghavath (Broadcom ltd.\,)\n\n\n\n\n14:40\nVerification by Documentation \nHemendra Talesara (Independent Board Member)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nLeveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs \nAditya Devarakonda (NXP Semiconductor)\n\n\n\n\n15:50\nSigmasense\n\n\n\n\n16:10\nMethodology focused testbench generation \nBenjamin Delsol (UVMGen)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nUsing Non-Determinism with Formal \nDoug Smith(Doulos) Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification\n\n\n\n\n15:30\nOSVVM in a NutShell\, VHDL’s #1 Verification Methodology \nJim Lewis (SynthWorks Design Inc)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-2023-austin/ LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2023-Austin.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20230913T080000 DTEND;TZID=Asia/Kolkata:20230914T170000 DTSTAMP:20230907T175227Z CREATED:20230727T164506Z LAST-MODIFIED:20230907T175227Z UID:6617-1694592000-1694710800@marketingeda.com SUMMARY:DVCon India 2023 DESCRIPTION:On behalf of the DVCon India 2023 steering committee\, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference.  We want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThis year’s edition will have a good blend of Vision and Keynote talks\, lively panel discussions tutorials and technical sessions spread across both the days. We are looking at some of the feedback and see how to set an agenda that provides key takeaways to everyone at the conference. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling and New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co- verification. We want to remind you that this isn’t just a Verification conference\, but a Design AND Verification conference and we want to ensure that the Design community has greater participation. \nThis year\, we will be expanding our Technical Program Committee and we want to make it even stronger than what it is now. The entire team is planning and putting in the extra hours to ensure we deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, engage\, share learnings with the rest of the community and take an enthusiastic part in DVCon India 2023 and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2023 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-india-2023/ LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230912T080000 DTEND;TZID=America/Los_Angeles:20230914T170000 DTSTAMP:20230424T172221Z CREATED:20230424T172221Z LAST-MODIFIED:20230424T172221Z UID:6320-1694505600-1694710800@marketingeda.com SUMMARY:AI Hardware & Edge AI Summit DESCRIPTION:The combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. \nFor Enterprise ML Experts: Attend a unique AI systems event that will give you both hardware and software tools and techniques for training\, deploying\, and serving machine learning – the program contains a mixture of state-of-the-art topics and practical tutorials\, so you know what is out there\, and what you can use. 40% of our audience are enterprise ML practitioners just like you! \nFor Technology Vendors: Attend the premier event for the AI infrastructure ecosystem\, which blends systems\, software\, tooling and applications for a unique proposition that focuses on making ML faster\, more efficient and more affordable. If your product fits into this category\, your peers and customers are here! \n2023 LUMINARY KEYNOTE ANNOUNCEMENTS\nAndrew Ng\, Founder & CEO\, Landing AI \nJim Keller\, CEO\, Tenstorrent \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Summit-2023.jpg ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20230912T080000 DTEND;TZID=Europe/Stockholm:20230912T170000 DTSTAMP:20230216T012619Z CREATED:20230216T011624Z LAST-MODIFIED:20230216T012619Z UID:5985-1694505600-1694538000@marketingeda.com SUMMARY:FPGAworld Conference 2023 - Stockholm DESCRIPTION:The FPGAworld Conference is an international forum for researchers\, engineers\, teachers\, students\, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems\, FPGA/ASIC-based products\, educational & industrial cases\, and more. Registration for attendees is free and includes 2*coffee\, lunch and go-home drink. \n\nKeynote Speaker Copenhagen and Stockholm 2023\n\n\nKeynote speaker: Martin Kellermann \, Microchip Technology GmbH\, Munich\n\n\nTitle: RISC-V: Paving the Path Together to a Safe\, Secure and Reliable Future\n\n\nAbstract: RISC-V is an open-source instruction set that has created opportunities for companies of all sizes to innovate and make decisions independently. It is predicted to shape the future of computing for the next 50 years by providing a processor architecture that allows for more processing with a smaller carbon footprint\, more features with less development resources\, and new ways to combat threats with existing technologies. Companies are already utilizing RISC-V to develop applications such as High-Performance Spaceflight Computing (HPSC) processors. This keynote will explore how companies can benefit from this independence and how the ecosystems can enable easy adoption and scalability. It will also highlight companies that are already a part of this revolution and discuss how they can help create a safe and secure future. Through RISC-V\, companies can reach their goals and protect their future. Together\, we can move mountains. \nCV: Martin Kellermann is an experienced FPGA and SoC engineer with a diploma in Electrical Engineering from the Landshut University of Applied Sciences. He has expertise in high-speed serial data transmission\, signal integrity\, and hardware debugging\, successfully delivering projects in the industrial\, automotive\, and data-center domains. As Marketing Manager at Microchip Technology GmbH\, Munich\, he works with the European Sales and Field Application team to showcase the strengths of their FPGAs and SoCs. \n\nKeynote Speakers Stockholm 2023\n\n\nKeynote speaker: Mark Frost\, Intel’s Programmable Solutions Group (previously Altera)\, England\n\n\nTitle: Key Factors for Success in Today’s and Tomorrow’s Markets\n\n\nAbstract: This presentation will explore the key areas that FPGA suppliers must consider in order to succeed: industry-leading supply chain management\, product leadership\, and an up-to-date developer experience. We will examine the current supply chain landscape\, which is facing an unprecedented imbalance in demand and supply\, leading to long lead times and product allocations. We will also discuss the need for FPGA companies to make strategic investments to achieve product leadership and remain competitive. Furthermore\, we will look at the importance of having up-to-date knowledge and skills\, fast and appropriate EDA tools\, the right SoCs\, and the right RTL\, SW\, and hardware IP from generation to generation for FPGA developers to be productive. The presentation will then provide an overview of the different options available to FPGA vendors\, preferred standards\, and flows. Finally\, we will look at how FPGA technology is being used in different parts of the world and provide a prediction of its future. \nCV: Mark is the FPGA Security and 5G Technical Marketing Manager within Intel’s Programmable Solutions Group (previously Altera). Within this role Mark liaises between customers\, sales and engineering teams worldwide for security and 5G communication topics\, and works to create market awareness of Intel’s portfolio. During his 11 years with Intel he has held roles in both marketing and as a field application engineer covering programmable technology. Prior to Intel\, Mark had worked for over 15 years in a variety of engineering roles\, spanning telecommunications through to designing instruments for ESA satellites. Mark has a BEng in Electrical Engineering from the University of Plymouth. \nSeptember 14 details in Copenhagen \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpgaworld-conference-2023/ LOCATION:ÅF\, Frösundaleden 2A\, 169 70 Solna\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/FPGAworld-2023.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20230907T080000 DTEND;TZID=Asia/Taipei:20230907T170000 DTSTAMP:20230406T174802Z CREATED:20230406T174802Z LAST-MODIFIED:20230406T174802Z UID:6241-1694073600-1694106000@marketingeda.com SUMMARY:DVCon Taiwan 2023 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. \nConference Sponsor: Accellera \nGlobal Sponsors: Synospys\, Cadence\, Siemens \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-taiwan-2023/ LOCATION:National Yang Ming Chiao Tung University\, 300\, Hsinchu City\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Taiwan-2023-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230905T080000 DTEND;TZID=America/Los_Angeles:20230908T170000 DTSTAMP:20230413T202528Z CREATED:20230413T202528Z LAST-MODIFIED:20230413T202528Z UID:6272-1693900800-1694192400@marketingeda.com SUMMARY:IEEE SOCC 2023 DESCRIPTION:SoCs and SiPs for Edge Intelligence and Accelerated Computing \nSystem-on-Chip (SoC) and System-in-Package (SiP) devices\, comprising digital\, analog\, optical\, RF\, and Micro-Electro-Mechanical Systems (MEMS) are foundations of ubiquitous embedded high-performance computing (HPC). Such systems will provide solutions in communication\, entertainment\, medical and smart mobility technologies underpinning emerging “Digital Societies”. \nRecent advances in systems\, packaging and process technologies are enabling the computation of hundreds of teraflops per chip and chiplet system integration unleashing the massive rise of AI-based edge devices\, various accelerators\, new products and applications. This enormous demand for computing per silicon-based SoC and SiP integration creates new challenges with respect to storage\, memory\, security\, reliability\, power\, on- and off-chip communication\, packaging including reliable design and verification. \nFor over 35 years the IEEE International System-on-Chip Conference (SOCC) has been a premier forum for sharing latest advancements in SoC architectures\, systems\, logic and circuit design\, process technology\, test\, design tools\, and application scenarios. We consequently continue this tradition with the 2023 conference at the heart of Silicon Valley in Santa Clara\, CA. \nThe 36th SOCC offers a three days technical program including keynote and plenary speeches\, oral and poster presentations\, hot-topic panel sessions\, and one day of industrial talks. In addition\, SOCC has a long tradition of high-class social events complementing the technical program\, helping you to discuss your work with your colleagues\, and enhancing your professional network. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-socc-2023/ LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SOCC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230827T080000 DTEND;TZID=America/Los_Angeles:20230829T170000 DTSTAMP:20230613T165859Z CREATED:20230613T165859Z LAST-MODIFIED:20230613T165859Z UID:6490-1693123200-1693328400@marketingeda.com SUMMARY:Hot Chips 2023 DESCRIPTION:Hot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29\, 2023. \nConference Format\nHot Chips 2023 will be a hybrid conference. You may register to attend virtual or in-person. The conference venue is the Dinkelspiel Auditorium on the Stanford University Conference. \n\nSunday (August 27) is a Tutorial Day.\nMonday and Tuesday (August 28 and 29) are Conference Days.\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs and Slack Channels for both Tutuorial and Conference Days. All talks are transmitted in real time and are also recorded so that you also may view them at a time convenient for your time zone. Details are here. \nIn-Person Conference: You may register for Conference Days only or both Conference and Tutorial Days. In either case you will have full access to Videos\, presentation PDFs and Slack channels. The conference fee includes breakfast\, lunch\, coffee breaks and receptions. Details are here. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hot-chips-2023/ LOCATION:Stanford University\, 471 Lagunita Drive\, Stanford\, CA\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/14054931_10155065287553998_1856342906013349235_n.jpg END:VEVENT END:VCALENDAR