BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.18//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20260308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20261101T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20260329T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20261025T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20240101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Hong_Kong BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:HKT DTSTART:20240101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250319T080000 DTEND;TZID=America/Los_Angeles:20250320T170000 DTSTAMP:20260405T233248 CREATED:20241220T215313Z LAST-MODIFIED:20241220T215313Z UID:8694-1742371200-1742490000@marketingeda.com SUMMARY:SNUG Silicon Valley 2025 DESCRIPTION:Connecting the Synopsys User Community\n\n\n\n\n\n\n\n\n\n\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2025 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nWe are thrilled to announce that SNUG Silicon Valley is celebrating its 35th year of innovation\, and we invite you to be a part of this milestone event. Have you used Synopsys technology to overcome difficult design issues or tackle one of those key challenges facing the industry? We’d like to hear from you! Showcase your work and share your experience with the community by submitting your proposal through the call for content process. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/snug-silicon-valley-2025/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Silicon-Valley-2025.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250224T080000 DTEND;TZID=America/Los_Angeles:20250227T170000 DTSTAMP:20260405T233248 CREATED:20241213T183758Z LAST-MODIFIED:20241213T183758Z UID:8595-1740384000-1740675600@marketingeda.com SUMMARY:DVCON US 2025 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/dvcon-us-2025/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/DVCON-US-2025.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250220T080000 DTEND;TZID=America/Los_Angeles:20250220T190000 DTSTAMP:20260405T233248 CREATED:20241212T171448Z LAST-MODIFIED:20241212T171517Z UID:8572-1740038400-1740078000@marketingeda.com SUMMARY:GSA Mena Executive Summit DESCRIPTION:On February 20\, 2025 in Cairo\, Egypt\, we are hosting the GSA MENA Executive Summit to look beyond the current divisions and rather recognize the Middle East North Africa regional potential as a source of capital and destination for innovative tech developments. \nThis semiconductor and tech-focused exec forum will take place in a stunning brand-new venue: the Grand Egyptian Museum (GEM)\, an outstanding new destination for history and archeology lovers on par with the world’s very best museums\, near the Giza pyramid complex. \nBeside ample opportunities for networking\, including with government officials from the entire region\, we will cover topics including: \n\nthe state of the global semiconductor industry\nthe regional potential as a source of capital and destination for innovative tech development centers\nthe state of Entrepreneurship in the region\, with a moderated panel discussion of Venture Capital firms.\nProgress in Automotive\, as a crucial industry for the whole EMEA region\nkey technological updates\, on AI (GenAI\, Edge AI\, Cloud AI)\, New Chip Design Paradigms (Chiplets\, 3D packaging\, EDA advancements)\, Cybersecurity\, Quantum\, and more.\n\nThis event is hosted in cooperation with the Egyptian Information Technology Industry Development Agency (ITIDA) and the Egyptian Information & Communication Technology Association (EiTESAL). \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/gsa-mena-executive-summit/ LOCATION:Grand Egypian Museum\, Alexandria Desert Rd\, Kafr Nassar\, Al Haram\, Giza Governorate\, Cairo\, Egypt CATEGORIES:EDA,Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-February-20-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250129T130000 DTEND;TZID=Europe/London:20250129T173000 DTSTAMP:20260405T233248 CREATED:20241220T033019Z LAST-MODIFIED:20241220T033019Z UID:8642-1738155600-1738171800@marketingeda.com SUMMARY:DVClub Europe - Mixed Signal Verification DESCRIPTION:Analog mixed signal chips continue to grow in both demand and complexity\, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the University of Edinburgh and the university students will be attending. The first half of the DVClub will focus concepts of digital and analog verification\, as well as an overview of the work the university is doing on AI in semiconductors through the APRIL hub\, focusing on the verification activities. \nIn the second half of this DVClub\, local companies will focus on challenges and solutions for mixed signal verification at SoC\, system and in safety-related applications. \nAgenda (GMT) \n13.00: Arrival and Registration with Coffee and Snacks \n\nmainly for students but local companies also welcome\n\n13:25: Mike: Welcome \n13.30: Introduction from the University \n14.00: Mike – Introduction to Digital Verification \n14:30: Peter/Graeme – Mixed Signal Verification Part I \n15.00: Break – Coffee and Snacks \n\n Delegates can also attend for 2nd half only if preferred\n\n15:30: Peter/Graeme – Mixed Signal Verification II \n16:00: Michael O’Sullivan & Marcel Ahmedzai\, Cadence Design Systems – SoC Verification \n16:30: System and Safety Verification: (TBC) \n17:00: Mike: wrap up and next steps for students/local companies to collaborate \n17:10: Drinks and Pizza\n \nAdditional Information\nFor additional information please visit the Tessolve DVClub webpage for this event. \nSponsors\nDVClub Europe\, Edinburgh is made possible through the generous support of our sponsors:  Cadence\, Partner: TechWorks \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/dvclub-europe-mixed-signal-verification/ LOCATION:Edinburgh City Centre\, Edinburgh\, United Kingdom CATEGORIES:EDA,Forum,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-29-January-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250125T080000 DTEND;TZID=America/Los_Angeles:20250130T170000 DTSTAMP:20260405T233248 CREATED:20241220T214552Z LAST-MODIFIED:20241220T214552Z UID:8691-1737792000-1738256400@marketingeda.com SUMMARY:SPIE Photonics West DESCRIPTION:Browse the 2025 program; discover all the ways you’ll connect with colleagues \n\nJoin the world’s largest photonics technologies event. Learn the most cutting-edge research in biomedical optics\, biophotonics\, industrial lasers\, optoelectronics\, microfabrication\, displays\, quantum technologies\, and more. \nReview the lineup of outstanding plenary speakers from around the globe. Select advanced training from more than 50 courses. Discuss your product requirements with top optics and photonics suppliers at any of the four exhibitions throughout the week\, and participate in the strong industry program. The week is full of important engagements\, and we look forward to seeing you there. \nConferences and courses: 25–30 January 2025\nBiOS Expo: 25–26 January 2025\nQuantum West Expo: 28–29 January 2025\nPhotonics West Exhibition: 28–30 January 2025 \nCo-located with SPIE AR | VR | MR 2025\nand SPIE Global Business Forum 2025 \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/spie-photonics-west/ LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SPIE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250123T150000 DTEND;TZID=Europe/London:20250123T160000 DTSTAMP:20260405T233248 CREATED:20250107T192555Z LAST-MODIFIED:20250107T192555Z UID:8875-1737644400-1737648000@marketingeda.com SUMMARY:Mastering SoC Design and Verification for DO-254 Compliance DESCRIPTION:System on Chip (SoC) devices are transforming the landscape of advanced aviation systems\, offering unparalleled integration of multiple functionalities within a single chip. These compact powerhouses bring numerous advantages\, from reduced power consumption to enhanced performance. Yet\, their inherent complexity introduces unique safety assurance challenges that must be addressed to meet DO-254 standards. \nJoin this co-webinar with friends and partners\, ConsuNova\, to dive deep into the role of SoC devices in aviation\, where we’ll discuss the benefits\, challenges\, and critical considerations for successful implementation. We’ll cover various SoC architectures\, their safety implications\, and practical strategies for design and verification to ensure compliance. Gain insights into applicable certification guidance for both hardware and software\, along with best practices for overcoming development and verification hurdles. \nAgenda: \n\nUnderstanding SoC\n\nWhat is an SoC\, and why is it used?\nTypical architectures and components (IPs)\n\n\nNavigating Certification\n\nRelevant hardware and software guidance\nDevelopment and verification issues\n\n\nEnsuring Compliance\n\nIntegration strategies to meet DO-254 standards\n\n\n\nWebinar Duration: \n\n45 min presentation\n15 min Q&A\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBios: \n\n\nMartin Beeby is the Head of Advanced Avionics Systems and Managing Director of ConsuNova EU. With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is\, and has been\, also an active contributor to many industry standard working groups developing new guidance for avionics development and is an active CVE on a number of different programs in Europe. \n\n\n\n\n\nJanusz Kitel is the DO-254 program manager at Aldec with over 18 years of experience in software and hardware design and verification. He has developed expertise in DO-254 compliance for over 10 years\, ensuring Aldec products meet aerospace regulations and supporting customers with their tooling challenges in AEH projects.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/mastering-soc-design-and-verification-for-do-254-compliance/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-January-23-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20250123T100000 DTEND;TZID=Asia/Tokyo:20250123T170000 DTSTAMP:20260405T233248 CREATED:20241217T174422Z LAST-MODIFIED:20241217T174422Z UID:8611-1737626400-1737651600@marketingeda.com SUMMARY:Silvaco UseRs Global Event - Japan\, 2025 DESCRIPTION:SURGE (Silvaco UseRs Global Event) is a worldwide event held by Silvaco.\nSURGE is an event for discussing new technologies\, sharing user experiences\, and discovering innovative techniques for advanced semiconductor design in the fields of TCAD\, EDA\, and IP. The event will be held online. We look forward to your participation.\n\n\nWe will randomly select 8 lucky winners from those who participate on the day and fill out the questionnaire to receive a special prize.\n(Domestic shipping only.)\n\nPlease take this opportunity to register for SURGE Japan.\n\n\n\n\n\n\n\nDistribution : Online\ndistribution service : Zoom Meeting\nParticipation fee : Free\nLanguage : English \nAfter you register\, you will receive a notification email. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15 AM\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15 AM\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna\n\n\n11:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45 AM\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco\n\n\n12:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco\n\n\n12:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n1:00 PM\nLUNCH BREAK\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)\n\n\n2:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco\n\n\n2:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n2:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n3:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n3:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra\n\n\n3:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco\n\n\n4:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n4:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco\n\n\n4:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-japan-2025/ CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250123T100000 DTEND;TZID=America/Los_Angeles:20250123T110000 DTSTAMP:20260405T233248 CREATED:20250109T181629Z LAST-MODIFIED:20250109T181629Z UID:8887-1737626400-1737630000@marketingeda.com SUMMARY:Simulating Auto Systems & E/E Architectures for power and performance using VisualSim DESCRIPTION:Estimating latency and power for different use-cases in Systems\, ECU and Networks \nOverview: This session will focus on a common system-level simulation platform that can be shared by Semiconductor companies\, Tier One Suppliers\, OEMs in designing the entire E/E architecture.  The transition to everything digital and electronics is causing a number of design challenges across the ECU\, processors\, semiconductors\, software and networks. Current systems engineering solutions are focused on the correctness of algorithms\, requirements management and SysML behavior model.  What is required is accurate latency\, throughput\, buffer occupancy\, optimal scheduling and power consumption measurement\, prior to development. \nWe will delve into the design challenges associated with the new generation automotive system design\, changes in the power efficiency and latency requirements\, and handling of Distributed\, Zonal\, and Centralized Architecture computational. We show examples with use cases that originate at the SysML and refine all the way to micro-architecture.  The examples will showcase the comparison and results for different use cases\, topology\, different SoC architectures\, hardware modeling abstraction\, software task graphs and traffic workload. We will look at applications such as braking\, lighting\, comfort\, ADAS\, EV\, battery and safety system. \nKey Discussion Points: \n\nE/E Architecture Evolution:\n\nComparing the cost\, performance and power consumed by the same use cases on Distributed\, Zonal and Centralised architectures.\nMethodology to trade-off software complexity with compute resources\, scheduling\, multi-core distribution and network architecture\nIntegrating legacy systems and meeting-bandwidth\, low-latency communication.\n\n\nSystems and Semiconductors Exploration\n\nSelect the hardware\, network and software to meet the requirements\nOptimize the system and semiconductor definition to share with OEMs and semiconductor suppliers\nDetect system bottlenecks\, latency and power consumption for different use cases\n\n\nIdentify System Bottlenecks prior to Integration:\n\nEvaluate responses to failures and validate ISO 26262 and SOTIF requirements.\nTrade-off between latency\, power consumption\, and computational efficiency.\nOptimal task mapping and resource allocation in multi-core processor systems.\n\n\nRole of VisualSim in Architecture Design:\n\nLearn how VisualSim system-level IPs accelerate model construction and enable rapid architecture trade-offs.\nThe methodology to debug system behaviors and failures\nRegression simulation to identify and optimize the system specification\n\n\nCase Studies and Real-World Applications:\n\nExamples of how VisualSim has been used to model different use cases on the hardware\, software\, OS and network to optimize automotive E/E systems.\nInsights into achieving significant reductions in latency and power through architectural refinements.\n\n\nFuture Trends in E/E Architectures:\n\nThe impact of emerging technologies such as AI-driven optimizations and multi-core ECUs.\nAdvancements in centralized architecture to increase modularity and scalability.\n\n\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/simulating-auto-systems-e-e-architectures-for-power-and-performance-using-visualsim/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-January-23-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250121T100000 DTEND;TZID=Europe/London:20250121T170000 DTSTAMP:20260405T233248 CREATED:20241217T174109Z LAST-MODIFIED:20241217T174512Z UID:8609-1737453600-1737478800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - EMEA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 21\, 2025. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45M\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n11:30\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n12:05\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n12:25\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n13:00\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n14:00\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n14:20\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n14:40\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n15:00\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n15:15\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n15:35\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n16:00\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n16:20\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n16:35\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-emea-2025/ CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20250120T080000 DTEND;TZID=Asia/Tokyo:20250123T170000 DTSTAMP:20260405T233248 CREATED:20241213T182220Z LAST-MODIFIED:20241213T182220Z UID:8592-1737360000-1737651600@marketingeda.com SUMMARY:ASP-DAC 2025 DESCRIPTION:ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2025 is 30th conference. ASP-DAC 2025 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2025. \n\nDate: Jan. 20-23\, 2025\nPlace: Tokyo Odaiba Miraikan\, Japan\nGeneral Chair: Yuichi Nakamura (NEC)\nTechnical Program Chair: Yu Wang (Tsinghua University)\nDesign Contest Co-Chairs: Mahfuzul Islam (Institute of Science Tokyo)\, Shinya Takamaeda Yamazaki (The University of Tokyo)\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/asp-dac-2025/ LOCATION:Tokyo Odaiba Miraikan\, 2 Chome-3-6 Aomi\, Tokyo\, Koto CIty\, 135-0064\, Japan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ASP-DAC-2025.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Hong_Kong:20250117T130000 DTEND;TZID=Asia/Hong_Kong:20250117T170000 DTSTAMP:20260405T233248 CREATED:20241217T173838Z LAST-MODIFIED:20241217T174747Z UID:8606-1737118800-1737133200@marketingeda.com SUMMARY:Silvaco UseRs Global Event - China\, 2025 DESCRIPTION:We sincerely invite you to attend the annual Silvaco Global User Conference – SURGE. This year’s SURGE China will be held online from 13:00 to 17:00 Beijing time on Friday\, January 17\, 2025. \nSURGE aims to provide a sustainable learning and exchange platform for global customers to share the latest technologies and user experience in the fields of TCAD\, EDA and IP\, and explore innovative technologies for advanced semiconductor design. \nLucky Draw: \nThe event has a lucky draw session\, and we have carefully prepared prizes. All users participating online have the chance to win! \n\n\nEvent Schedule\n\n\n\n\n\n\n\ntime\nMain venue\n\n\n13:00\nCEO Speech – Babak Taheri\, Silvaco\, CEO and Board Member​\n\n\n13:15\nHow AI will take EDA to new heights – Wally Rhines\, President and CEO of Cornami\, Board Member of Silvaco\n\n\n13:30\nSpeech Topic – Sumeet Pandey\, Micron Technologies\n\n\n13:45\nLucky draw and rest\n\n\n\n\n\n\ntime\nSemiconductor Process and Devices Session\n\n\n14:15\nTCAD Update – Dr. Eric Guichard\, Silvaco Vice President and General Manager of TCAD Division\n\n\n14:30\nStudying Low-Temperature Properties of Nanowire Transistors with Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n14:45\nMachine Learning for Multiscale Plasma Process Integration and Optimization – Dr. Lado Filipovic\, Associate\n\n\n15:00\nSpeech topic – Dr. Gao Peixiong\, CanSemi\, TCAD Simulation Manager\n\n\n15:15\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Application Engineer\n\n\n15:35\nPhysics and AI-based digital twins to accelerate SiC power device design optimization and manufacturing – Dr. David Green\, Silvaco\n\n\n15:55\nPower Device SPICE Modeling – Study on SiC DMOS Parameter Extraction Method – Dr. Bogdan Tudor\, Silvaco\, Modeling Leader​\n\n\n16:15\nEDA Solutions for Power Device Physical Design – Stefano Pettazzi\, Silvaco\, Application Engineer\n\n\n16:30\nLucky Draw and Closing\n\n\n\n\n\n\ntime\nIC Design Session\n\n\n14:15\nEDA and IP Updates – Dan Fitzpatrick\, Silvaco\, Vice President and General Manager of the EDA Division – Ben Louie\, Silvaco\, Vice President and General Manager\n\n\n14:35\nJivaro Pro Advanced Parasitic Reduction – Silicon Creation​\n\n\n14:55\nUsing Viso to Explore\, Analyze\, and Solve Advanced Parasitic Problems – Carlos Berlitz\, Applications Engineer\, Silvaco\n\n\n15:10\nChallenges and Improvements in Characterization of Standard Cell Libraries – Siti Mariyam\, Senior IP Engineer\n\n\n15:30\nLow Voltage Standard Cell Library Design at 3nm – Fernando Carrion\, Silvaco\, R&D Engineer\n\n\n15:55\nAdvanced Node Cell Library Development Using Cello FinFET – Felipe Bortolon\, Silvaco\, Engineering Manager​\n\n\n16:15\nLDO and Bandgap Benchmarks for Low Voltage Design – Ahmad S. Mazumder\, Shaikh A Shams\, Silvaco\n\n\n16:30\nIntroduction to CAN-XL Automotive Bus IP – Mauricio Brochi\, Silvaco\, Director of Automotive IP\n\n\n16:45\nLucky Draw and Closing\n\n\n\n\n\n\n\n\n\n\n*Please refer to the schedule announced on the day of the event. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-china-2025/ CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250115T090000 DTEND;TZID=America/Los_Angeles:20250115T160000 DTSTAMP:20260405T233248 CREATED:20241217T173045Z LAST-MODIFIED:20241217T173045Z UID:8603-1736931600-1736956800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - USA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 15\, 2025.  \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \nEveryone that registers will be entered into a drawing to win one of 2 pairs of Apple AirPods Pro 2. \nAll attendees will be entered into a drawing to win one Apple iPad Air 11″ M2. \n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n9:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n9:15 AM​\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n9:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n9:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n10:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n10:15 AM​\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n10:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n10:45 AM​\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n11:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n11:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n12:00 PM​\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n1:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n1:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n1:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n2:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n2:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n2:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n3:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n3:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n3:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-usa-2025/ CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250107T080000 DTEND;TZID=America/Los_Angeles:20250110T170000 DTSTAMP:20260405T233248 CREATED:20241004T181728Z LAST-MODIFIED:20241209T181610Z UID:8380-1736236800-1736528400@marketingeda.com SUMMARY:CES 2025 DESCRIPTION:The world’s most powerful tech event is your place to experience the innovations transforming how we live. \n\n\n\n\nThis is where global brands get business done\, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Registration for CES 2025 is now open. \n\n\nCES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges. \n\n\n\n\n\nCES connects innovators\, decision makers\, media\, influencers\, visionaries\, and potential customers across the entire tech ecosystem. \nDon’t be left in the past as we shape the future.\n\nGlobally showcase your technology products\nStand side-by-side with the world’s most disruptive innovators\nPromote your brand through curated opportunities to connect with influencers and prospective partners\n\nCES is owned and produced by the Consumer Technology Association (CTA)®\, which provides the ultimate platform for technology leaders to connect\, collaborate\, and propel consumer technology forward. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ces-2025/ LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241219T090000 DTEND;TZID=America/New_York:20241219T100000 DTSTAMP:20260405T233248 CREATED:20241217T192611Z LAST-MODIFIED:20241217T192611Z UID:8614-1734598800-1734602400@marketingeda.com SUMMARY:Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration DESCRIPTION:Abstract\n\nThe integrated circuit industry faces new challenges as chip complexity and area have been increasing to prohibitive ranges. Some segments have been adopting then a relatively new paradigm for heterogeneous integration based on chiplets at the first package level in combination with advanced 2.5 and 3D packaging technologies. \nThe chiplet approach has the advantage of reducing the single die complexity and size\, which is compatible with a high silicon yield\, but also allows a faster evolution of electronics systems by a selective redesign of certain chips within a disaggregated solution\, or the customization of the system by certain chiplet combinations. Nevertheless\, this dense packaging integration imposes signal and power integrity challenges\, as well as the necessity of new circuitry and novel validation and test methodologies to handle parallel-massive communication across dies. \nThis lecture discusses the challenges associated with advanced packaging technologies and chiplet integration from the electrical integrity perspective\, where high-density and high-speed signaling\, and narrow areas for power distribution impose some interesting trade-offs among performance and reliability\, together with the need of a new kind of interface\, called the embedded IO (EIO)\, for chip-to-chip communication. \n\n\nDescription\n\nThis talk will take place on 19 December 2024 at 09:00 AM EST (-5:00 UTC) and features a talk by Renato Rimolo-Donadio\, titled “Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration”. \nRegistration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register\, you can also attend the webinar via LinkedIn Live or access webinar recordings on the IEEE CASS Resource Center. \nRegistration for this series is entirely free and will be limited to the first 1\,000 registrants per event. If you cannot register\, you can also attend the webinar via LinkedIn Live. Following the webinar\, the recording will be available on the CASS Resource Center and as a lesson in the CASS Microlearning (CASS MiLe) e-learning platform. In CASS MiLe\, interested practitioners can learn through short didactic units (micro-lessons) with practical questions\, and upon lesson completion\, learners receive digital badges/certificates. \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/signal-and-power-integrity-challenges-in-advanced-packaging-technologies-for-disaggregated-integration/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-CAS-December-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241219T090000 DTEND;TZID=America/Los_Angeles:20241219T100000 DTSTAMP:20260405T233248 CREATED:20241211T175317Z LAST-MODIFIED:20241211T175403Z UID:8567-1734598800-1734602400@marketingeda.com SUMMARY:Advantages of using IP-XACT and TGI for SoC Development DESCRIPTION:Are you looking for ways to simplify your SoC development process\, reduce rework\, and accelerate time-to-market? \nJoin us for an insightful webinar\, “Advantages of using IP-XACT and TGI for SoC Development\,” where we’ll explore how the latest features of IP-XACT 2022 can revolutionize your SoC design workflows. \nWhat’s on the Agenda?\n\nIntroduction to IP-XACT: A detailed overview of the standard and its core benefits.\nWhat’s New in IP-XACT 2022: Exploring the latest updates and how they empower developers.\nTGI API: Enabling programmability and automation for resource optimization.\nIP Packaging and Integration: Techniques to package IPs efficiently and integrate them into SoCs.\nCapturing Connectivity: Leveraging busInterfaces and adhocConnections effectively.\nVendor Extensions: How to use custom data capturing for specialized needs.\nBest Practices for SoC Development: Real-world tips for leveraging IP-XACT in your projects.\n\nDate: December 19th\, 2024\nTime: 9:00 PST/ 16:00 GMT \nRegister now and learn how IP-XACT can transform your SoC development process. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/advantages-of-using-ip-xact-and-tgi-for-soc-development/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20241217T080000 DTEND;TZID=Asia/Kolkata:20241220T170000 DTSTAMP:20260405T233248 CREATED:20241122T213230Z LAST-MODIFIED:20241122T213230Z UID:8530-1734422400-1734714000@marketingeda.com SUMMARY:IEEE Asian Test Symposium 2024 DESCRIPTION:The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the world\, not just from Asia\, to present and discuss various aspects of system\, board and device testing with design\, manufacturing and field considerations in mind. \nThe 33th IEEE Asian Test Symposium (ATS 2024)\nDecember 17-20\, 2024\, Ahmedabad\, Gujarat\, India \n  \n\nThe Asian Test Symposium started 1992 in Hiroshima\, Japan\, as an annual symposium in the Asia Pacific region. Since then\, the symposium has continued its growth and development\, visiting various historic cities in Asia. This year it is marking its 33rd anniversary to Ahmedabad\, India. We welcome all the contributors to the heritage city of India.\n\n\nThe walled city of Ahmadabad was founded by Sultan Ahmad Shah in 1411 AD on the eastern bank of the Sabarmati River. On July 8th\, 2017\, a remarkable moment unfolded as Ahmedabad earned the title of India’s first-ever UNESCO World Heritage City.\n\n\nScope\n\n\n\nThe Asian Test Symposium (ATS) provides an international forum for engineers and researchers from all countries of the world\, especially from Asia\, to present and discuss various aspects of device\, board and system testing with design\, manufacturing and field considerations in mind. \n\n\n\n\nMajor topics including\, but not limited to: \n\n\n\n\n\n\n\n\n\nAutomatic Test Pattern Generation (ATPG)\nAnalog Test / Mixed-Signal Test\nBoundary Scan Test\nBoard and System Test\nBuilt-In Self-Test\nDesign for Testability (DFT)\nDesign Verification and Validation\nDefect-Based Testing\nDelay and Performance Test\nDiagnosis and Debug\nDependable System\nEconomics of Test\n\n\n\n\n\n\n\n\n\n\nFault Modeling and Simulation\nFault Tolerance\nHigh-Speed I/O Test / RF Testing\nMemory Test / FPGA Test\nOn-Line Test\nSystem-on-a-Chip Test\nSystem-in-package (SiP) / 3D Test\nSoftware Testing / Software Design for Testing\nTest Compression\nTemperature / Power-aware Test\nTest Quality\nYield Analysis and Enhancement\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ieee-asian-test-symposium-2024/ LOCATION:Courtyard by Marriott\, Ahmedabad\, Sindhu Bhawan Roa\, Ahmedabad\, India CATEGORIES:EDA,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ATS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20241217T080000 DTEND;TZID=Asia/Kolkata:20241219T170000 DTSTAMP:20260405T233248 CREATED:20241207T004316Z LAST-MODIFIED:20241207T004316Z UID:8560-1734422400-1734627600@marketingeda.com SUMMARY:EDAPS 2024 DESCRIPTION:The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) symposium\, a flagship event in the Asia-Pacific region\, has consistently served as a platform for dissemmination of latest research in the areas of electrical design of chip\, package and system. Designers and researchers across the world come forth to share and discuss their work on all aspects of electrical packaging including modeling\, design and simulation\, fabrication and characterization. This symposium consists of technical paper presentation\, poster sessions\, industry exhibits\, workshops and tutorials. \n  \nEDAPS is sponsored by the IEEE Electronic Packaging Society. \nEDAPS will be an excellent forum to highlight the latest advances in the high-speed and high-performance semiconductor industry. Engineers and researchers will engage in the 3 full day conference and workshop\, to be held during December 17-19 at the Taj Yeshwantpur\, in Bangalore\, India. The forum offers a great opportunity for sponsorships and for the related companies to build their brands in this leading international platform. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/edaps-2024/ LOCATION:Taj Yeshawantpur\, 2275 Tumkur Road\, Yeshwantpur\, Bangalore\, India CATEGORIES:EDA,Semiconductor,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260405T233248 CREATED:20241127T180212Z LAST-MODIFIED:20241127T180212Z UID:8540-1733997600-1734001200@marketingeda.com SUMMARY:Learn How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data DESCRIPTION:Abstract\nPhysics-based design using technology computer-aided design (TCAD) has provided fundamental contributions to R&D in the semiconductor industry. Traditionally\, TCAD modeling is mostly developed manually by expert designers using a trial-and-error procedure. However\, the imperative acceleration of time-to-market to reduce development expenses calls for renovation of these conventional TCAD approaches. \nMachine learning (ML) and artificial intelligence (AI) techniques are currently considered to be essential enhancements for TCAD strategies. Silvaco\, a prominent provider of TCAD\, EDA software\, and SIP solutions used to enable semiconductor design\, is at the forefront in developing AI-powered TCAD. \nIn this webinar\, an ML-TCAD combined strategy is presented to boost the calibration of TCAD parameters to benchmark TCAD simulations against experimental data. This is achieved through a seamless flow between two of the latest tools from the Victory suite: Victory Design Of Experiment (DOE) and Victory Analytics. \nVDOE is a powerful project manager for efficiently running DOE with TCAD simulations. This essential step allows users to collect the TCAD outputs to be fed into Victory Analytics. Then\, Victory Analytics uses ML-modeling to optimize TCAD parameters to fit the experimental data. Calibration of TCAD parameters of AlGaN/GaN HEMT will be used to showcase this procedure as a case study. \nWhat You Will Learn\n\nBrief overview of TCAD calibration\nOverview of Victory TCAD tools\nVictory DoE\nVictory Analytics\nCalibration methodology using Victory Analytics and machine learning\nOverview of simulation\nGenerating DoEs using Victory DoE\nViewing and modeling results in Victory Analytics\nOptimizing parameters to fit experimental data\nVerifying results\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Stefania Carapezzi is currently a Field Applications Engineer at Silvaco France. She joined in March 2023. She obtained a PhD in Physics at University of Bologna\, Italy\, in 2014. Then\, she was Post-Doc Researcher for several years at Advanced Research Center on Electronic System\, Bologna\, Italy and at LIRMM\, University of Montpellier\, CNRS\, Montpellier\, France. Her research work has been focused on TCAD simulation of Beyond CMOS devices and quantum effects in nanoscaled transistors. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/learn-how-to-utilize-victory-analytics-and-machine-learning-to-calibrate-tcad-data/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260405T233248 CREATED:20241125T180804Z LAST-MODIFIED:20241125T180804Z UID:8537-1733997600-1734001200@marketingeda.com SUMMARY:Accelerating SoC Automotive Design with Chiplets DESCRIPTION:Step into the forefront of innovation with our upcoming webinar\, which explores how chiplet technology is revolutionizing the automotive industry and setting new benchmarks. Discover how Cadence is empowering customers to achieve unparalleled success with chiplets. Here’s what you can look forward to: \n\nMastering Chiplet Architecture: Dive into the intricacies of mastering chiplet architecture\, where you’ll learn how to integrate multiple chiplets\, including processing\, memory\, I/O\, and accelerators\, into a single\, streamlined solution. Understand the critical importance of chiplet interoperability and how Cadence and Arm collaborate on standards like the Arm Chiplet System Architecture to ensure seamless integration.\nThe Impact of Chiplets on Automotive Designs: Explore the transformative impact of chiplets on automotive designs\, particularly in building scalable and extendable systems for key functions such as ADAS. Learn about Cadence’s ADAS chiplet reference design and how it can accelerate product development with fewer engineering resources\, driving innovation in the automotive sector.\nCadence Chiplet Designs: Discover Cadence’s cutting-edge chiplet designs\, including the recent successful tapeout of Cadence’s first system chiplet. Learn how Cadence tools like the Helium Virtual Platform and 3D-IC are key enablers for quickly designing chiplet solutions\, helping customers bring their products to market faster and with greater efficiency.\n\nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to embarking on this exciting journey together! \nWho Should Attend:\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers and business leaders seeking to optimize their design flow and technology infrastructure. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-soc-automotive-design-with-chiplets/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260405T233248 CREATED:20241112T212446Z LAST-MODIFIED:20241112T212446Z UID:8503-1733997600-1734001200@marketingeda.com SUMMARY:CadenceTECHTALK: Driving Intelligent System Design with 3D-IC Multiphysics DESCRIPTION:As the industry reaches the limits of device scaling at advanced nodes\, there is a growing demand for increased computing performance and data transfer in hyperscale data centers and AI designs. Advanced systems-on-chip (SoCs) are approaching the maximum size limits\, and there is a need to find innovative solutions to continue scaling according to Moore’s law and achieve better performance with lower power consumption. Stacking chips in the same package (3D) and using a multi-chiplet system with silicon interposers on the same package (2.5D) are emerging as preferred solutions\, but they come with their own challenges. \nThis webinar will discuss the requirements\, challenges\, and solutions for 3D-IC design and analysis achieved through an integrated 3D-IC platform. By receiving early feedback from system-level analysis processes\, 3D-IC designers can benefit from a system-driven approach to power\, performance\, and area (PPA) and avoid overdesigning individual chipsets. \nYou will learn about: \n\nThe requirements\, challenges\, and solutions for 3D-IC design\nHow the analysis of 3D-ICs is done through an integrated 3D-IC design platform\nHow feedback from early system-level analysis provides a system-driven approach to PPA\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cadencetechtalk-driving-intelligent-system-design-with-3d-ic-multiphysics/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T090000 DTEND;TZID=America/Los_Angeles:20241212T100000 DTSTAMP:20260405T233248 CREATED:20241122T193816Z LAST-MODIFIED:20241122T193816Z UID:8527-1733994000-1733997600@marketingeda.com SUMMARY:From Concept to QoR: Practical Generative AI for ASIC Managers and Engineers DESCRIPTION:Be among the first to see how Generative AI is advancing hardware design workflows\, providing solutions that reduce complexity and enable better results without steep learning curves. Witness how these tools offer immediate\, practical benefits for real-world use cases. \n\n\nWhat You’ll Learn:\n\n\n\n\nThis session offers a unique opportunity to explore how Generative AI solutions with Rise Design Automation are reshaping hardware design and verification workflows. Attendees will learn advanced techniques for enhancing design quality\, accelerating IP and module development\, and making more informed design trade-offs with minimal learning curves. Designed for engineers and managers with a background in hardware design\, this session is ideal for those eager to adopt innovative methods and witness how these tools perform in practical scenarios.  \nKey Takeaways:\nGenerative AI and Accelerated IP Development \n\nUnderstand the value of adopting a shift-left approach to enhance design abstraction and streamline processes beyond traditional RTL methods. \n\n\nLearn how project timelines can be reduced\, enabling faster IP/module development and delivering improved Quality of Results (QoR). \n\n  \nDesign Generation \n\nExplore how AI automates the creation of RTL code from natural or high-level languages\, such as SystemVerilog\, SystemC\, and C++. \n\n\nDiscover tools for AI-powered code completion\, generation\, and refactoring that ensure maintainable\, high-quality code with less manual effort and help RTL designers achieve excellent QoR without deep HLS expertise. \n\n  \nIntegrated Design Optimization \n\nEarly Design Exploration: Understand intelligent and iterative refinement techniques that help minimize late-stage design surprises. \nGradual Refinement: Explore workflows that support continuous refinement of high-level designs\, incorporating backend metrics and physical insights as they progress. \n\n\nCritical Parameter Optimization: Learn about AI-powered Design Space Exploration (DSE) to evaluate and optimize configurations such as loop unrolling\, pipelining\, and memory synthesis for superior Power\, Performance\, and Area (PPA). \n\n\nIntegrated EDA flows: Discover how Rise’s Generative AI integrates with both Synopsys and Cadence RTL Verilog workflows\, bridging early design exploration with downstream verification and physical implementation. \n\n\nReal-World Applications  \n\nHardware Design: Learn how Gen AI allows designers to focus on architectural innovations rather than manual coding. \n\n\nVerification Processes: Examine ways for AI to automate early verification steps to detect issues earlier\, with metrics and reduce the rework in later stages. \n\n\nCollaborative Approaches: See how AI-driven tools enhance collaboration among system architects\, hardware designers\, and verification engineers\, creating more cohesive and efficient workflows. \n\n\nFlexible Deployment Options  \n\nDeployment Support: Understand compatibility with cloud platforms like Amazon Bedrock and Microsoft Azure\, as well as options for on-premises environments that can be tailored to different operational and organizational needs. \n\n\nLegal Considerations: Review best practices for addressing data privacy\, intellectual property concerns\, and compliance with regulatory frameworks when leveraging AI-driven methodologies. \n\n\n\n\n\nWho Should Attend:\n\n\n\n\n\nDesign Engineers: Discover AI-guided strategies to improve control paths\, data flow\, and overall performance. \n\n\nVerification Engineers: Learn techniques to integrate early verification processes\, reducing risks and enhancing efficiency. \n\n\nProject Leads: Gain insights into managing trade-offs in power\, performance\, and area while introducing innovative AI tools into existing workflows. \nSystem Architects: Explore approaches for early modeling and validation of architectural decisions\, optimizing outcomes and preventing late-stage challenges. \nDesign Managers/Methodology team: Understand how AI combined with raising design abstraction can dramatically improve the overall productivity\, quality and ability for your design teams to deliver on new projects\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/from-concept-to-qor-practical-generative-ai-for-asic-managers-and-engineers/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241211T100000 DTEND;TZID=America/Los_Angeles:20241211T140000 DTSTAMP:20260405T233248 CREATED:20241122T231141Z LAST-MODIFIED:20241122T231141Z UID:8534-1733911200-1733925600@marketingeda.com SUMMARY:Mastering EMC Simulations for Electronic Designs DESCRIPTION:Electromagnetic Compatibility (EMC) simulation ensures that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases\, the importance of EMC simulation grows\, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. \nOverview\nIt can be challenging for EMC and product design engineers to understand how to use simulation tools effectively. This hands-on session with experts in full-device simulation offers a unique opportunity for engineers to dive into the world of EMC simulation. This session will provide practical experience\, demystifying the simulation process and empowering engineers with the knowledge to implement simulations early in the design phase. Experts will offer insights into best practices\, common pitfalls to avoid\, and strategies for interpreting simulation results. \nBy participating in such a session\, engineers can gain a deeper understanding of the nuances of EMC simulation. They learn to set up simulations that model their products’ real-world behavior\, identify potential EMI issues\, and explore design modifications to enhance EMC performance. This proactive approach ensures compliance with regulatory standards and contributes to the final product’s reliability and quality. \nEMC simulation is more than just a checkbox for compliance; it’s a strategic tool that\, when used effectively\, can significantly improve product design. Join this hands-on session guided by experts created for engineers looking to master EMC simulation and integrate it into their design process. It’s an investment in knowledge that will pay dividends throughout the product’s lifecycle\, ensuring that your efforts today will lead to better products in the future. \n  \nWhat attendees will learn\n\nCAD File Preparation: Master the process of importing mechanical CAD designs\, assigning materials\, and preparing for simulations.\nPCB and Package Setup: Discover the steps to import electronic design files for PCBs and packages\, including automation of the setup process.\nCable Specification: Gain hands-on experience in defining cables through the co-simulation with multi-conductor transmission line solvers.\nComponent Modeling: Understand how to represent components using ideal or SPICE circuit models for co-simulation with 3D geometries.\nPerformance Evaluation: Learn to transform simulation results into formats that facilitate comparison with standard measurements for device performance assessment.\n\n  \nWho should attend\nElectromagnetic Compatibility Engineers\, Mechanical Design Engineers\, RF Engineers\, Electrical Engineers \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/mastering-emc-simulations-for-electronic-designs-2/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-December-11-2024-.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241211T090000 DTEND;TZID=America/Los_Angeles:20241211T120000 DTSTAMP:20260405T233248 CREATED:20241210T174710Z LAST-MODIFIED:20241210T174710Z UID:8564-1733907600-1733918400@marketingeda.com SUMMARY:17th International MOS-AK Workshop\, Silicon Valley DESCRIPTION:Modeling of Systems and Parameter Extraction Working Group \n\n\n\nT_0\nMOS-AK Welcome and Opening\nLong Ma and Wladek Grabinski\nKeysight Technologies (US) and MOS-AK (EU)\n\n\nT_1\nWhat’s New in Keysight Device Modeling 2025\nLong Ma\nKeysight Technologies (US)\n\n\nT_2\nSi2 Compact Model Coalition 2024 Updates\nPeter M. Lee\nCMC Chairman (US)\n\n\nT_3\nOpenVAF – status update\, ecosystem\, and a roadmap\nArpad Burmen\nFE Uni Ljubljana (SI)\n\n\nT_4\nA Wrapper Model for ESD-FET Simulation and Analysis\nHarshit Agarwal\nIIT Jodhpur (IN)\n\n\nT_5\nCompact Modelling of Memristors Toward Analog Neuromorphic Circuit Simulations\nThomas Ratier\, Jean-Charles\, Delvenne\, Denis Flandre\, Leopold Van Brandt\nUC Louvain (B)\n\n\nT_6\nInductor Modeling and Generation Flow for Verified RFIC Layouts Using Open-Source PDKs\nFrancisco Brito-Filho\, Hugo Dias Gilo and Iranildo Alves Sales\nUFERSA (BR)\n\n\nT_7\nCharacterization and modelling of low-frequency noise in polysilicon thin-film source-gated transistors from subthreshold to saturation\nQi Chen*\, Valeriya Kilchytska\, Eva Bestelink\, Radu A. Sporea\, Denis Flandre\, Leopold Van Brandt\nICTEAM\, UCLouvain (B)\n\n\nT_8\nGm/ID-Based Analog Circuit Sizing Using Ngspice and Python\nBoris Murmann\nUniversity of Hawaii (US)\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/17th-international-mos-ak-workshop-silicon-valley/ CATEGORIES:EDA,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MOS-AK-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20241211T080000 DTEND;TZID=Asia/Shanghai:20241212T170000 DTSTAMP:20260405T233248 CREATED:20241206T210925Z LAST-MODIFIED:20241206T211410Z UID:8556-1733904000-1734022800@marketingeda.com SUMMARY:ICCAD-Expo 2024 DESCRIPTION:The China Integrated Circuit Design Industry Exhibition (ICCAD-Expo) has always played an important role in promoting industrial agglomeration\, connecting industrial resources\, and mastering industry trends. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/iccad-expo-2024/ LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-Expo-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241210T183000 DTEND;TZID=America/Los_Angeles:20241210T203000 DTSTAMP:20260405T233248 CREATED:20241121T224138Z LAST-MODIFIED:20241121T224138Z UID:8520-1733855400-1733862600@marketingeda.com SUMMARY:Synopsys TCAD Winter Reception DESCRIPTION:Join us in person at the Synopsys TCAD Winter Reception on December 10\, 2024. You have a chance to meet with our executives and product experts to learn about the latest insights on how Synopsys TCAD products can unleash the power of smart technology modeling – from atoms to circuits. Sign up and learn about the application of Synopsys TCAD solutions to accelerate the research\, development\, and optimization of semiconductor technologies. \nVenue: Hotel Nikko\, 222 Mason St\, San Francisco\, CA 94102 (across the IEDM Conference @ Hilton SF Union Square)\nRoom: Peninsula\, 25th floor\nRSVP: By Dec 6\, 2024 \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/synopsys-tcad-winter-reception/ LOCATION:Hotel Nikko\, 222 Mason Street\, San Francisco\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241207T080000 DTEND;TZID=America/Los_Angeles:20241211T170000 DTSTAMP:20260405T233248 CREATED:20241008T155901Z LAST-MODIFIED:20241018T161813Z UID:8386-1733558400-1733936400@marketingeda.com SUMMARY:70th Annual IEEE International Electron Devices Meeting - IEDM 2024 DESCRIPTION:IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology\, design\, manufacturing\, physics\, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology\, advanced memory\, displays\, sensors\, MEMS devices\, novel quantum and nano-scale devices and phenomenology\, optoelectronics\, devices for power and energy harvesting\, high-speed devices\, as well as process technology and device modeling and simulation. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/70th-annual-ieee-international-electron-devices-meeting/ LOCATION:Hilton San Francisco Union Square\, 333 O'Farrell Street\, San Francisco\, 94102\, United States CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/70thiedmcolor.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241205T090000 DTEND;TZID=America/Los_Angeles:20241205T100000 DTSTAMP:20260405T233248 CREATED:20241203T172119Z LAST-MODIFIED:20241203T172119Z UID:8544-1733389200-1733392800@marketingeda.com SUMMARY:Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips DESCRIPTION:Efficient management of registers and memory maps is critical for the success of modern System-on-Chip (SoC) designs. System Register Description Language (SystemRDL)\, combined with Agnisys’s IDesignSpec Suite\, provides an advanced solution to automate and simplify these complex processes. In this webinar\, “Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips\,” we will demonstrate how the IDesignSpec Suite leverages SystemRDL to accelerate register design\, improve design quality\, and streamline SoC development. You’ll gain insights into best practices\, learn how to automate crucial tasks\, and see how our tools ensure compliance with industry standards. \nYou’ll learn:\n• Best Practices for register design and memory map management using SystemRDL.\n• How the IDesignSpec Suite accelerates SoC development with automation\, reducing manual errors and ensuring compliance with industry standards.\n• Practical use cases\, including generating design files\, firmware headers\, and comprehensive documentation for seamless hardware-software integration. \nExclusive Features and Highlights:\n• Explore how Agnisys’s SystemRDL VS Code Extension enhances your design workflow.\n• Discover the Agnisys PSS Compiler and its ability to simplify Portable Stimulus generation.\n• See real-world examples\, such as the Power Controller use case\, demonstrating the suite’s capabilities in addressing industrial challenges. \nWhat’s on the Agenda? \nThe webinar will guide you through every facet of SystemRDL and its integration with IDesignSpec:\n• Core Concepts: Registers\, Memory\, Address Maps\, and Parameters.\n• Advanced Techniques: Constraint Management\, Verification Constructs\, and Structural Testing.\n• Comprehensive Outputs: From HDL Path generation to SoC assembly and IP packaging.\n• Bonus: Insights into SoC Hardware-Software Interface (HSI) and device driver generation. \nReserve your spot today and join us for this hands-on\, practical session! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimizing-hardware-design-with-systemrdl-tools-techniques-and-tips/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241203T100000 DTEND;TZID=America/Los_Angeles:20241203T170000 DTSTAMP:20260405T233248 CREATED:20241106T234135Z LAST-MODIFIED:20241106T234135Z UID:8481-1733220000-1733245200@marketingeda.com SUMMARY:Keysight EDA 2025 Launch event DESCRIPTION:New EDA Tools for 5G and AI Infrastructure Design\n\n\n\n\n\nWe are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain insights and workflows enhanced by artificial intelligence (AI). \nGet the Roadmap\nThe webinar will kick off with an overview of the Keysight EDA 2025 roadmap from Richard Duvall\, senior EDA marketing manager. Then\, you can choose the discussion topic that interests you most. Explore product release highlights\, watch demo videos\, and participate in question-and-answer sessions. After the live webinar\, use the same registration link to watch other topics on demand. \nTrack 1: What’s New in Advanced System Design (ADS) for RF Circuit Design \n\n\n\nLearn how RF circuit design tools with Python APIs enable open workflows that help you address the complex design challenges of sub-terahertz chipsets.\nWatch advanced RF simulation enable a multi-domain co-design cockpit\, essential for troubleshooting designs with nonlinear\, power\, electromagnetic\, thermal\, and wideband 5G digital modulation.\nHarness the latest AI and machine learning (ML) technology to create reliable power amplifier simulation models with minimal effort using artificial neural networks.\n\nTrack 2: What’s New in ADS for High-Speed Digital Circuit Design \n\n\n\nDiscover how to use the Keysight Chiplet PHY Designer to predict the true end-to-end link margin and verify compliance with cross talk analysis and quarter-rate clock support.\nLearn how the Keysight PCIe® Designer can help you perform complete PCIe system analysis and simulation-driven virtual compliance tests with a streamlined workflow.\nWatch the Keysight Power Integrity Designer enable simulations that deliver thousands of amps to the next generation of custom multi-die packages\, AI chips\, and cloud server applications.\n\nTrack 3: What’s New in Device Modeling and Characterization \n\nLearn how new AI / ML-based algorithms in IC-CAP can help fully automate the model recentering process and increase productivity by 10 times\, from days to hours.\nSee how the Keysight Model Builder Pro leverages Python to automate the modeling process\, helping standardize the modeling flow and reducing turnaround time.\nLearn how the Keysight Model Generator framework enables a turnkey workflow that is 30% faster with less programming and more automation.\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/keysight-eda-2025-launch-event/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-December-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241127T150000 DTEND;TZID=Europe/London:20241127T153000 DTSTAMP:20260405T233248 CREATED:20241105T181903Z LAST-MODIFIED:20241105T181903Z UID:8475-1732719600-1732721400@marketingeda.com SUMMARY:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases DESCRIPTION:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases \nWith the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI assisted advanced DV Flow and Use cases\n\nAI Training Bots\nAI Assistance\, CoPilot\nAI Code CoPilot\nRAG\nRAG Assessment\nAI Agents\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-3-tessolve-ai-assisted-advanced-dv-flow-and-use-cases/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-27-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241126T120000 DTEND;TZID=Europe/London:20241126T130000 DTSTAMP:20260405T233248 CREATED:20241022T165229Z LAST-MODIFIED:20241107T165901Z UID:8444-1732622400-1732626000@marketingeda.com SUMMARY:DVClub Europe - AI/ML in Verification DESCRIPTION:This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. \n\n\nAgenda (GMT):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction – Mike Bartley\, Tessolve \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nHardik Raina\, Agnisys\, Inc – Genetic Algorithms for Automated Verification from VCD Data.\n\n\n\n\n12.20 GMT\nPaula Mathias\, Cadence Design System – AI-based SVA Generation\n\n\n\n\n12.40 GMT\nDavid Kelf\, Breker Verification Systems – VerifyGPT! Is it possible and what do we need in place?\n\n\n\n\n13.00 GMT\n  \nClose\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/dvclub-europe-ai-ml-in-verification-2/ CATEGORIES:EDA,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-26-2024.jpg END:VEVENT END:VCALENDAR