BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.0//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Zurich
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Jerusalem
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20230324T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20231028T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20240329T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20241026T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20250328T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20251025T230000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240709T120000
DTEND;TZID=Asia/Kolkata:20240709T160000
DTSTAMP:20240621T162414Z
CREATED:20240621T162353Z
LAST-MODIFIED:20240621T162414Z
UID:8103-1720526400-1720540800@marketingeda.com
SUMMARY:Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve
URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Symposium,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T090000
DTEND;TZID=America/Los_Angeles:20240709T100000
DTSTAMP:20240618T194728Z
CREATED:20240618T194728Z
LAST-MODIFIED:20240618T194728Z
UID:8098-1720515600-1720519200@marketingeda.com
SUMMARY:How to Reduce Thousands of False Errors in 15 Minutes
DESCRIPTION:Analyzing electrical errors across an IP or a SoC at top level\, can be a painful and long process\, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. \nTo address this challenge\, Aniah developed OneCheck\, a formal analysis tool capable of detecting 100% of electrical errors at the transistor level. With intelligent features\, it reduces false positives and groups replicated errors by root cause. \nJoin our webinar for an in-depth look at Aniah OneCheck and its SmartClustering technology\, presented by CEO Vincent Bligny. Through a live demo on a 20 million transistor SoC design\, you’ll witness OneCheck’s powerful formal analysis and SmartClustering capabilities in action\, streamlining setup\, processing\, and analysis. \nDiscover in this insightful session for technical experts how modern Electrical Rules Checking solution\, with SmartClustering intelligence can transform your verification workflows. \nSpeaker Bio :\nVincent Bligny is a renowned expert in mixed-signal verification\, particularly with transistor-level formal techniques. He spent 15 years in this industry\, mainly within STMicroelectronics’ design and verification teams\, allowing him to understand the challenges and opportunities of the EDA field. In 2019\, Vincent co-founded Aniah with the vision of delivering an ERC tool that empowers 100% of designers to find 100% of errors efficiently. Driven by a designer-centric approach\, Aniah’s tool for ERC aims to improve the verification process and bring products to market more effectively\, while simplifying the lives of designers! \n*This webinar is in partnership with SemiWiki and Aniah
URL:https://marketingeda.com/event/how-to-reduce-thousands-of-false-errors-in-15-minutes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aniah-July-9-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240702T080000
DTEND;TZID=Europe/Berlin:20240704T170000
DTSTAMP:20240628T211817Z
CREATED:20240628T211817Z
LAST-MODIFIED:20240628T211817Z
UID:8111-1719907200-1720112400@marketingeda.com
SUMMARY:FPGA Conference Europe
DESCRIPTION:The FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is Europe’s leading specialist conference for programmable logic devices. The conference focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. \n\n\n\n\n\n\n\n\nIn increasingly AI-driven cloud data centres\, in telecommunications and many other high-performance applications\, Field Programmable Gate Arrays (FPGA) have proven themselves as flexible and powerful accelerator solutions for a wide range of tasks. \n\n\n\n\n\n\n\n\nFPGAs – The hidden champions of microelectronics\n\n\nFrom tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed during the FPGA Conference Europe in Munich.
URL:https://marketingeda.com/event/fpga-conference-europe-2/
LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/fpga-conference-europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240612T164153Z
CREATED:20240612T164153Z
LAST-MODIFIED:20240612T164153Z
UID:8090-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency.
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-design-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240529T185102Z
CREATED:20240529T185102Z
LAST-MODIFIED:20240529T185102Z
UID:8070-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nThis Virtual Webinar is from 10:00-11:00am PT. \n 
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240624T080000
DTEND;TZID=Europe/Berlin:20240628T170000
DTSTAMP:20240304T193822Z
CREATED:20240304T193822Z
LAST-MODIFIED:20240304T193822Z
UID:7702-1719216000-1719594000@marketingeda.com
SUMMARY:RISC-V Summit Europe 2024
DESCRIPTION:The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry\, government\, research\, academia and ecosystem support – that are building the future of innovation on RISC-V. \nRISC-V\, the open standard instruction set architecture (ISA)\, is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success\, with one-third of RISC-V’s global community based in Europe. \nRISC-V Summit Europe takes place from Monday 24th to Friday 28th June\, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe\, and for this reason the conference is designed to help attendees to explore both commercial and research applications. \nRISC-V Summit Europe is an opportunity not to be missed. Come to Munich to be part of the new wave of European computing innovation!
URL:https://marketingeda.com/event/risc-v-summit-europe-2024/
LOCATION:MOC Conference\, Lilienthalallee 40\, Munich\, Germany
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240623T080000
DTEND;TZID=America/Los_Angeles:20240627T170000
DTSTAMP:20240327T200918Z
CREATED:20240327T194239Z
LAST-MODIFIED:20240327T200918Z
UID:7782-1719129600-1719507600@marketingeda.com
SUMMARY:DAC 2024
DESCRIPTION:The premier event for the design and design automation of electronic chips to systems. \nAutonomous Systems\nElectronics content in modern autonomous systems (e.g.\, automotive\, robotics\, drones\, etc.) is growing at an increasingly rapid pace. Nearly every aspect of these complex systems uses smart electronics and embedded software to make our experiences safer\, more energy-efficient and enjoyable. For example\, premium vehicles can have several million lines of embedded software code running on hundreds of electronic control units. Within autonomous systems\, such as automotive\, these sub systems connect with one another by in-system networks. As the trend towards fully autonomous driving and connectivity accelerates\, the ability to deliver these innovations depends more than ever on advanced electronics and software development. \nDesign\nDAC has served as a meeting place for designers of electronic systems and providers of electronic design automation tools for over five decades. Increasingly\, the challenges faced by the industry require cross-domain interaction of researchers and practitioners working on electronic design (circuit\, architecture\, and embedded systems design) and researchers working on design methodologies and tools. DAC serves this need by covering design as a topic area in the research track\, in addition to organizing a dedicated designer track for practitioners. \nThe design topics covered in the research track include the design of cyber-physical\, SoC architectures\, accelerator-based computing\, emerging models of computation such as brain-inspired and quantum computing\, digital and analog circuits\, and emerging device technologies. \nSeparately the Designer Track allows tool users to share challenges and benefits of different tools\, flows\, and methodologies. In addition\, it provides excellent opportunities for education and networking between end users and tool developers. There is no other way to improve your “design IQ” in such a short amount of time than to attend the Designer Track. \nElectronic Design Automation\nEDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power\, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades\, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems. \nIn addition to the traditional EDA topics ranges from physical design to system architectures\, DAC features high-quality papers on design research\, design practices\, and design automation for cross-cutting topics including low-power\, reliability\, multicore/application specific/heterogeneous architectures\, 3-D integrations\, emerging device technologies\, design automation of “things”\, and their applications. DAC’s EDA technical program has been ensuring the best-in-class solutions that promise to advance EDA. \nEmbedded Systems & Software (ESS)\nEmbedded system design is the art of choosing and designing the proper combination of hardware and software components to achieve system level design goals like speed\, efficiency\, reliability\, security\, and safety. Embedded systems are an increasingly diverse\, disruptive\, and challenging field for designs ranging from mobile devices\, medical devices\, automotive\, robotics\, drones\, industrial and beyond. Embedded software is built into devices that may not necessarily be recognized as computing devices (e.g.\, thermostats\, toys\, defibrillators\, and anti-lock brakes)\, but nevertheless controls the functionality and perceived quality of these devices. \nThe ESS sessions at DAC provide a forum for discussing the challenges of embedded design and an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nAI\nArtificial intelligence (AI) program highlights the advances in the field with a focus on design and design automation at the cross section between AI algorithms and hardware. While artificial intelligence and artificial neural network research has been ongoing for more than half a century\, recent advances in accelerating the pace and scale of machine learning enabled by tensor-flow based gradient optimization in deeply layered convolutional networks (convnets) are revolutionizing the impact of artificial intelligence on every aspect of our daily lives\, ranging from smart consumer electronics and services to self-navigating cars and personalized medicine. \nThe advances in deep learning are fueled by computing architectures tailored to the distributed nature of learning and inference in neural networks\, akin to the distributed nature of neural information processing and synaptic plasticity in the biological brain. Neuromorphic brain-inspired electronics for AI aim at porting the brain’s efficacy\, efficiency\, and resilience to noise and variability to electronic equivalents in standard CMOS and emerging technologies\, offering new design challenges and opportunities to advance computing architecture beyond Moore’s law scaling limits. \nThe AI sessions at DAC focuses on the fundamentals\, accomplishments to date\, and challenges ahead in ML/AI hardware system design and design automation\, providing a forum for researchers and practitioners across all the widely varying disciplines involved to connect\, engage\, and join in shaping the future of this exciting field. \nIP\nIntellectual Property (IP) is increasingly complex\, diverse\, innovative\, and challenging. The complexity is driven by increasing requirements for higher integration levels that are reusable; the diversity to satisfy varying environmental conditions and constraints dictated by the different target markets. In addition\, the evolution of IP is being driven by innovative architectures to address the latency-power-performance needs of new disruptive applications\, such as machine learning.  The IP challenges are to cope with the complexities of advanced technology nodes. \nIP design is the art of choosing and designing the proper combination of analog\, digital\, RF hardware and software components to achieve sub-system-level design goals like speed\, power\, latency\, efficiency\, reliability\, security\, and safety. EDA tools\, automation and methods are continuously improved to help architect\, develop\, verify and manage the ever more complex IP and IP portfolios. \nThe IP Track sessions at DAC provides a forum for presenting and discussing the challenges of IP development\, verification\, integration and management.  It also provides an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nDesign on Cloud\nSystems and semiconductor companies realize the benefits of the cloud and how designing in the cloud can greatly accelerate their design cycle. Semiconductor design simulation\, verification\, lithography\, metrology\, yield analysis\, and many other workloads benefit from the scalability and performance of cloud design. \nFor all aspects of semiconductor design and manufacturing\, the new era of design in the cloud\, can optimize the process and increase yields. Industrial IoT\, data lake\, analytics\, and machine learning solutions allow you to develop smart factories and products\, provide insights to increase your operational efficiency\, and accelerate your pace of innovation. \nThe Design on Cloud sessions will focus on the aspects mentioned above plus high performance design\, verification\, and smart manufacturing\, supporting electronic design automation (EDA) in the cloud. \nSecurity\nSecurity sessions at DAC address an urgent need to create\, analyze\, evaluate\, and improve the hardware\, embedded systems and software base of the contemporary security solutions. Secure and trustworthy software and hardware components\, platforms and supply chains are vital to all domains including financial\, healthcare\, transportation\, and energy. Security of systems is becoming equally important. A revolution is underway in many industries that are “connecting the unconnected”. \nCyber physical systems\, e.g.\, automobiles\, smart grid\, medical devices\, etc.\, are taking advantage of integration of physical systems with the information systems. Not withstanding the numerous benefits\, these systems are appealing targets of attacks. Attacks on the cyber-part of such systems can have disastrous consequences in the physical world. The scope and variety of attacks on these systems present design challenges that span embedded hardware\, software\, networking\, and system design. \nSecurity topics will be featured through invited special sessions\, panels\, and lecture/poster presentations by both practitioners and researchers to share their knowledge and experience on this evolving environment.
URL:https://marketingeda.com/event/dac-2024/
LOCATION:Moscone West\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC61.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240620T083000
DTEND;TZID=America/Los_Angeles:20240620T113000
DTSTAMP:20240605T155921Z
CREATED:20240605T155921Z
LAST-MODIFIED:20240605T155921Z
UID:8073-1718872200-1718883000@marketingeda.com
SUMMARY:VC Formal Virtual Workshop - North America & Europe
DESCRIPTION:Location: Virtual workshop with hands-on labs. This workshop is best suited for attendees based in North America and Western Europe. \nFor attendees based in Eastern Europe or Asia\, please register for this workshop being held on June 21st instead. \n\n\n\n\n\n\n\n\n\n\nRegistration will close on June 14th. Space is limited!\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDo you want to harness the force of formal verification to ensure your mission-critical designs are ready for takeoff? Then join us for this virtual workshop! \nIn this 3-hour workshop\, attendees will experience: \n\nRunning simple formal checks or exploring functional behavior to find bugs early – no testbench\, no SVA\, and no formal knowledge required\nEngage in hands-on labs to find dead code\, FSM deadlock\, initialization issues\, X-propagation\, protocol violations\, explore design behavior and find bugs early\nSee a demo on how Generative AI can assist you in becoming even more productive with formal verification and RTL development\n\nThis workshop will be presented by Synopsys formal experts. Attendees will gain hands-on experience in live labs and walk away with the confidence to use these functionalities in current and upcoming projects. \n\n\n\n\n\n\n\n\n\n\n\n\n\nWorkshop Agenda\n*Subject to change \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nWelcome/introduction + review designer tasks\, challenges and how formal verification can help \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nDeadcode analysis\, FSM livelock and deadlock checks using automatic formal checks \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nInstructor-led hands-on lab #1 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nBreak \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nX-propagation checking \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nVerifying standard protocol interfaces \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nFormal design exploration and instructor-led hands-on lab #2 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n10 min \n\n\n\n\n\n\n\n\n\n\n\n\nGenerative AI demos \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n5 min \n\n\n\n\n\n\n\n\n\n\n\n\nWrap-up + Q&A
URL:https://marketingeda.com/event/vc-formal-virtual-workshop-north-america-europe/
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240619T080000
DTEND;TZID=America/Los_Angeles:20240619T090000
DTSTAMP:20240605T162435Z
CREATED:20240605T162435Z
LAST-MODIFIED:20240605T162435Z
UID:8076-1718784000-1718787600@marketingeda.com
SUMMARY:Design\, Manage\, and Share Data with OrCAD X Cloud Workspaces
DESCRIPTION:The OrCAD X platform allows you to manage and collaborate throughout the PCB design process. The cloud workspaces are available out-of-the-box without any additional setup of internal/external server dependencies. If you are a Librarian\, Electrical Engineer\, or a member of the PCB design team\, \nJoin us for this webinar to learn more about library and design data management within the OrCAD X platform. \n\nIn this webinar\, you will learn about: \n PCB design flow collaboration \n\nCreating a team library and sharing It with your team over cloud\nCreating a team workspace\nAccess control within the team workspace\nCollaborating on a PCB design across teams with\n\nElectrical engineers\nAnalysis engineers\nPCB designers\n\n\nDesign data management\n\nView/restore the version history of components and CAD data\nView/Restore the version history of PCB projects\n\n\n\n\nSPEAKERS: \nNitin Thapliyal\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/design-manage-and-share-data-with-orcad-x-cloud-workspaces/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240618T083000
DTEND;TZID=Europe/London:20240618T163000
DTSTAMP:20240404T172034Z
CREATED:20240222T180733Z
LAST-MODIFIED:20240404T172034Z
UID:7680-1718699400-1718728200@marketingeda.com
SUMMARY:Verification Futures Conference 2024 UK
DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \n  \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nThe Ghosts of Challenges Past\, Present and Future \nAndy Bond (Axelera AI)\n\n\n\n\n10:05\nPresentation Title\, Speaker name ( Company name) – TBC\n\n\n\n\n10:20\nChallenges of Developing Silicon for Automotive \nDarren Galpin(UniSemi Power)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Cadence) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser presentations on Formal Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Lubis EDA) – Start – up Sponsor\n\n\n\n\n11:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 1 – TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification- TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Synopsys) – Platinum Sponsor (Keynote Speaker)\n\n\n\n\n14:00\nPresentation Title Speaker Name (Breker Verification Systems) – Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name) – Gold Sponsor\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Tom (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 2- TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification – TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 4 – UVM for MS Verification\n\n\n\n\n15:30\nPeter Grove (Renesas)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nA Semi-formal approach to coverage analysis and System-on-Chip debugging\n– Dr. Surinder Sood\, Principal Verification Engineer\, ARM \nThe most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively\, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios\, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow. \nAnother approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically\, is of the order of hundreds of minutes in many cases. Consequently\, SoC debug\, micro-architectural analysis\, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism. \nThis mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds\, consequently\, making debugging easy. Moreover\, this solution comes with a package of many allied benefits\, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios\, as well as a significant improvement in coverage analysis. \n3 Key Points  \n\nLinear Temporal logic\nFormal verification\nSystem on Chips
URL:https://marketingeda.com/event/verification-futures-conference-2024-uk-2/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2024-UK.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240618T080000
DTEND;TZID=Europe/Paris:20240618T170000
DTSTAMP:20240528T182135Z
CREATED:20240528T182135Z
LAST-MODIFIED:20240528T182135Z
UID:8066-1718697600-1718730000@marketingeda.com
SUMMARY:Open-source silicon and EDA workshop 2024
DESCRIPTION:The chip design ecosystem in Europe is challenged by expensive development tools\, legal constraints\, lock-in threats and dependency on external supply chains. \nOpen-source Electronic Design Automation (EDA) tools and open-source silicon chips are emerging as possible solutions to these problems. It is increasingly recognised that open-source development offers not only faster and cheaper development but also better products. The open-source model moreover resonates well with the core aims of the European Chips Act of reinforcing the Union’s semiconductor ecosystem by reducing dependencies\, enhancing digital sovereignty\, stimulating investment\, increasing design capacity and the resilience of the Union’s semiconductor supply chain. \nEven though some IP building blocks\, such as those based on the RISC-V open instruction set\, are already witnessing overwhelming success and industrial adoption\, the open-source EDA and chip ecosystems are still in their infancy. Their development is further hindered by the high costs of manufacturing silicon chips and by the complexity of the ecosystem which involves heterogeneous participants (from designers to EDA developers\, to foundries).
URL:https://marketingeda.com/event/open-source-silicon-and-eda-workshop-2024/
LOCATION:Sorbonne Université\, 15-21 Rue de l'École de Médecine\, Paris\, France
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240616T080000
DTEND;TZID=America/New_York:20240621T170000
DTSTAMP:20240528T171711Z
CREATED:20240528T171711Z
LAST-MODIFIED:20240528T171711Z
UID:8056-1718524800-1718989200@marketingeda.com
SUMMARY:International Microwave Symposium - IMS 2024
DESCRIPTION:We welcome you to IMS2024 in Washington D.C. The last time D.C. hosted IMS was in 1980. Our industry\, IMS and the city had a lot of changes in the last 44 years! \n\nD.C. is a kaleidoscope of tastes\, flavors\, sounds and sights. From Georgetown’s cobblestone streets and historic houses to the Wharf’s sleek new restaurants and funky music venues\, the District’s many neighborhoods have an identity all their own. Away from the political headlines of the day\, the American capital is throbbing with energy. Whether you’re sleeping blocks away from the White House or dining within the same walls that have hosted leaders from around the world\, Washington will not disappoint you. \nWashington D.C. is the nation’s capital and named after one of the USA’s founding fathers\, George Washington. George Washington later became the first president of the United States. Even today\, Washington\, the city\, is not part of border states\, Maryland\, nor Virginia. It is its own district. The district is called the District of Columbia. Columbia being the female personification of this nation\, hence Washington D.C. \nWashington\, D.C.\, was a planned city\, and many of the District’s street grids were developed in that initial plan. In 1791\, President George Washington commissioned Pierre (Peter) Charles L’Enfant\, a French-born architect and city planner\, to design the new capital\, and enlisted Scottish surveyor Alexander Ralston to help lay out the city plan. The L’Enfant Plan featured broad streets and avenues radiating out from rectangles\, providing room for open space and landscaping. L’Enfant based his design on plans of other major world cities\, including Paris\, Amsterdam\, Karlsruhe\, and Milan. \nIn June\, the weather in D.C. averages a high of 85°F (29°C) and a low of 63°F (17°C). Expect rain once every 3-4 days. We hope you take in the sights\, sounds and smells of D.C. Perhaps join us for a 5k fun run/walk around the city monuments! \nWe also want you to experience the museums in addition to the monuments. Some of our classic social events will take place in prized venues. International Spy Museum\, National Museum of the American Indian\, and National Museum of African American History and Culture all host IMS events. \nMake no mistake! We will get down to business at IMS. We expect to have participation from industry\, government and academia. We are engaged with ARL\, DARPA\, NASA-Goddard\, NRL\, NRO\, NIST\, NSWC\, and ONR to name a few. A number of aerospace and defense companies have offices or facilities in the local area\, for example BAE\, Boeing\, Chemring Sensors\, Collins Aerospace\, DRS\, General Dynamics\, Hughes Networks\, Intelsat\, iDirect\, L3Harris\, Ligado Networks\, Lockheed Martin\, Northrop Grumman\, Orbital ATK\, Raytheon\, Thales Defense and Security\, and ViaSat. \nPlease join us for an IMS you cannot afford to miss!
URL:https://marketingeda.com/event/international-microwave-symposium-ims-2024/
LOCATION:Walter E. Washington Convention Center\, 801 Allen Y. Lew Place\, Washington\, DC\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240616T080000
DTEND;TZID=America/Los_Angeles:20240620T170000
DTSTAMP:20240226T234257Z
CREATED:20240226T234257Z
LAST-MODIFIED:20240226T234257Z
UID:7693-1718524800-1718902800@marketingeda.com
SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS
DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles.
URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/
LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240610T080000
DTEND;TZID=Europe/Berlin:20240611T170000
DTSTAMP:20240503T162031Z
CREATED:20240503T162031Z
LAST-MODIFIED:20240503T162031Z
UID:7940-1718006400-1718125200@marketingeda.com
SUMMARY:SNUG Europe 2024
DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas
URL:https://marketingeda.com/event/snug-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240606T100000
DTEND;TZID=America/Los_Angeles:20240606T110000
DTSTAMP:20240524T015255Z
CREATED:20240524T015255Z
LAST-MODIFIED:20240524T015255Z
UID:8034-1717668000-1717671600@marketingeda.com
SUMMARY:Addressing Thermal Stress and Warpage Challenges in 3D-IC Designs
DESCRIPTION:Thermal stress analysis plays a crucial role in the design and performance optimization of packaging materials and boards\, especially in industries where temperature variations are significant. This webinar presents a comprehensive overview of recent developments in the newly-introduced Cadence Celsius Studio AI-enabled multiphysics thermal platform to solve today’s thermal stress and warpage analysis in 3D-ICs. \nCelsius Studio offers support for linear and nonlinear material structural models as well as static and quasi-static solvers for warpage and stress analysis and a moisture solver and high-temperature\, high-humidity (HTHH) analysis. Designers can perform multi-stage simulations for the design assembly process and material failure and reliability analysis. There are global and local models for 3D-IC warpage/stress simulation. \nYou will learn about: \n\nRecent developments in Celsius Studio that address thermal stress and warpage analysis in 3D-ICs\, including die-to-die sacking\, packing\, and boards warpage\nKey methods that can be used to address factors affecting thermal stress\, including nonlinear material properties\, geometric configuration\, and environmental conditions\nExample models for 3D-IC warpage/stress simulation
URL:https://marketingeda.com/event/addressing-thermal-stress-and-warpage-challenges-in-3d-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Zurich:20240606T080000
DTEND;TZID=Europe/Zurich:20240607T170000
DTSTAMP:20240524T163724Z
CREATED:20240524T163724Z
LAST-MODIFIED:20240524T163724Z
UID:8038-1717660800-1717779600@marketingeda.com
SUMMARY:International Workshop on Logic and Synthesis - IWLS 2024
DESCRIPTION:The International Workshop on Logic and Synthesis is the premier forum for research in synthesis\, optimization\, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms\, such as nanoscale systems and biological systems\, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development\, without providing complete solutions. The emphasis is on novelty and intellectual rigor. \nTopics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing\, validation\, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling\, analysis\, and synthesis for emerging technologies and platforms are particularly encouraged. \nThe workshop format includes paper presentations\, invited talks\, social lunch and dinner gatherings\, and recreational activities. \nCheck out our call for papers. \nKeynotes\nCan AI Design and Verify Your Design?\nZiyad Hanna\, Cadence Design Systems\, Israel \n\nAbstract: In this talk\, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark\, driven by the rapid growth in key markets in 5G\, Hyperscalers\, autonomous vehicles\, AI\, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge\, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes\, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk\, I will address the inherent challenges in the chip design industry\, analyze the current landscape of automation\, machine learning (ML)\, and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification\, including the automatic generation of programs supported by natural language processing (NLP) and generative AI\, the creation of temporal assertions from design specifications\, the integration of high-level synthesis (HLS) and formal verification\, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance\, power and area. Furthermore\, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. \nZiyad Hanna\, Ph.D.\, is currently a corporate VP at Cadence Design Systems (CDNS)\, and the general manager of Cadence Israel\, leading R&D centers in various countries\, in the electronic design automation domain. Prior to joining Cadence Design Systems\, Dr. Hanna was a Senior VP at Jasper Design Automation\, which was acquired by Cadence in 2014. At Jasper\, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa\, where he was instrumental in the development of several generations of formal verification systems\, which were used on almost all Intel microprocessor designs since early 1990s\, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University\, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence\, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member\, holds over 15 patents\, and has published more than 80 papers and talks.\n\n\nSymmetric Is Better: Can We Exploit Regularities in Logic Synthesis?\nValentina Ciriani\, University of Milano\, Italy \n\nAbstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose\, the algebraic form of the function is manipulated\, as it directly reflects the cost of the corresponding circuit. Depending on the design needs\, different two-level or multi-level forms are considered\, and ad hoc algorithms are used to express and minimize such forms. In all cases\, the functions under consideration encode “real life” problems\, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover\, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally\, we show how regularities can also ease polynomial verification. \nValentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa\, Italy\, in 1998 and 2003\, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa\, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science\, University of Milano\, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures\, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers\, published in international journals\, conference proceedings\, and books chapters.\n\n\n\nToward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?\nLuca Benini\, ETH Zurich / University of Bologna\, Switzerland / Italy \n\nAbstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today\, open-source designs exist targeting a wide range of RISC-V based computing systems\, from tiny microcontrollers to high-performance many-core\, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can\, or even should\, push further\, open sourcing design automation tools and technology libraries\, PDKs\, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories\, drawing from a decade of experience in designing and industrializing open source hardware. \nLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems\, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE\, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award\, the 2020 EDAA achievement Award\, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.
URL:https://marketingeda.com/event/international-workshop-on-logic-and-synthesis-iwls-2024/
LOCATION:ETH Zurich\, Rämistrasse 101\, Zurich\, Switzerland
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWLS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240606T080000
DTEND;TZID=America/Chicago:20240606T170000
DTSTAMP:20240506T222541Z
CREATED:20240506T222446Z
LAST-MODIFIED:20240506T222541Z
UID:7961-1717660800-1717693200@marketingeda.com
SUMMARY:Verification Academy Live: Huntsville
DESCRIPTION:Siemens Training Center\n360E Quality Circle\, Suite 500\nHuntsville\, AL 35806\n+1 (256) 705-2501 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-huntsville/
LOCATION:Siemens Training Center\, 360E Quality Circle\, Suite 500\, Huntsville\, AL\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T100000
DTEND;TZID=America/Los_Angeles:20240604T110000
DTSTAMP:20240524T203508Z
CREATED:20240524T203431Z
LAST-MODIFIED:20240524T203508Z
UID:8046-1717495200-1717498800@marketingeda.com
SUMMARY:Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
DESCRIPTION:Today’s advanced node chip designs are faced with many new complexities which require more verification\, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design\, test and manufacturing (petabytes)\, analyze the data\, and provide actionable insights on that data. \nPart of the Synopsys.da AI analytics tools\,  Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges by increasing engineering productivity\, improving silicon efficiency and providing the tool scalability needed for today’s advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle. \nIn this presentation\, Mr. Anti Tseng\, Senior Manager at MediaTek\, will explain how Silicon.da’s volume diagnostics feature identified systematic issues more efficiently than traditional methods by providing very accurate failure locations within the silicon resulting in improved yield by a single digit percentage and in a shorter amount of time – from weeks to days. Mr. Tseng will also further discuss how utilizing this volume diagnosis analysis technology improves the foundry process for advanced nodes resulting in millions of dollars of cost savings through high volume chip production for fabless companies. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng\n\n\nSenior Manager\nMediaTek \n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng has been with MediaTek for 16 years and mainly covered three categories: CPU implementation/DFT/MBIST\, silicon speed binning & manufacture process debug\, in-house data platform & CAD flow development. His current focus is to enable smooth mass production of first advanced process node in MediaTek by exploring next-generation DFT architecture\, ATPG & diagnosis flow\, and AI-based data analysis. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez is principal\, product management at Synopsys. His marketing career spans over 25 years where he has held various marketing positions including technical\, product/solution\, channel/field\, integrated/corporate\, alliance and business development for companies such as Synopsys\, Cadence\, VMware and Optimal+. Prior to that he spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing)\, and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes\, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise\, Cortez was a pre- and post-sales applications engineer\, and also doubled as the company’s instructor.
URL:https://marketingeda.com/event/silicon-da-the-first-integrated-slm-analytics-solution-from-design-through-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240604T093000
DTEND;TZID=America/New_York:20240604T160000
DTSTAMP:20240506T221850Z
CREATED:20240506T221850Z
LAST-MODIFIED:20240506T221850Z
UID:7957-1717493400-1717516800@marketingeda.com
SUMMARY:Verification Academy Live: Westford (Boston Area)
DESCRIPTION:Westford Regency Inn and Conference Center\n219 Littleton Rd\nWestford\, MA 01886\n+1 (978) 692-8200 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-westford-boston-area/
LOCATION:Westford Regency Inn and Conference Center\, 219 Littleton Rd\, Westford\, MA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T080000
DTEND;TZID=America/Los_Angeles:20240607T170000
DTSTAMP:20240528T161702Z
CREATED:20240528T161702Z
LAST-MODIFIED:20240528T161702Z
UID:8052-1717488000-1717779600@marketingeda.com
SUMMARY:PCB East 2024
DESCRIPTION:The Electronics Industry’s East Coast Conference and Exhibition. \n1. Educational opportunities.\nNo matter how experienced you are\, everyone can learn! PCB East is widely acknowledged as the best technical conference in the industry. \n2. Networking with peers.\nCollaboration\, inspiration\, and more! \n3. New vendors and suppliers.\nTools and materials are always changing. Keeping up is paramount. \n4. Position yourself as an expert.\nWhy be the best-kept secret in the industry? \n5. It’s fun!\nAll work and no play gets old and fast. Manage your career growth with a social aspect!
URL:https://marketingeda.com/event/pcb-east-2024/
LOCATION:Boxboro Regency Hotel and Conference Center\, 242 Adams Pl\, Boxborough\, MA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-East-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T080000
DTEND;TZID=America/Los_Angeles:20240530T090000
DTSTAMP:20240521T162703Z
CREATED:20240521T162703Z
LAST-MODIFIED:20240521T162703Z
UID:8011-1717056000-1717059600@marketingeda.com
SUMMARY:Optimizing connectivity between Xpedition and HFSS for RF systems design
DESCRIPTION:In today’s fast-paced technological landscape\, seamless integration between design and simulation tools is crucial for accelerating product development cycles and ensuring optimal performance of electronics\, especially RF systems. Siemens Xpedition and Ansys HFSS stand as pillars in their respective domains\, offering powerful capabilities for electronic design and electromagnetic simulation. \nIn this live conversation\, Sara Louie from Ansys and Per Viklund from Siemens will describe the two-way connectivity between Siemens Xpedition and Ansys HFSS\, revolutionizing the electronic design and simulation workflow. We delve into the details of bidirectional data exchange\, enabling engineers to seamlessly transfer layout geometries and parameters between the two platforms.
URL:https://marketingeda.com/event/optimizing-connectivity-between-xpedition-and-hfss-for-rf-systems-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Xpedition-HFSS-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20240528T093000
DTEND;TZID=Asia/Jerusalem:20240528T173000
DTSTAMP:20240522T193335Z
CREATED:20240522T193335Z
LAST-MODIFIED:20240522T193335Z
UID:8027-1716888600-1716917400@marketingeda.com
SUMMARY:FV-Israel\, Summit 2024
DESCRIPTION:Connect with industry experts\, academics\, and enthusiasts for discussions on FV in Israel. \nExplore new developments from top semiconductor firms\, advanced EDA tools\, and academic research. \nEngage with leaders\, exchange insights\, and help shape the future of FV in Israel and globally. \nDistinguished Speaker \nDadi Perlmutter\nTechnology and social entrepreneur and former VP at Intel
URL:https://marketingeda.com/event/fv-israel-summit-2024/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FV-Israel-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240528T090000
DTEND;TZID=Asia/Shanghai:20240528T160000
DTSTAMP:20240522T200534Z
CREATED:20240522T194800Z
LAST-MODIFIED:20240522T200534Z
UID:8030-1716886800-1716912000@marketingeda.com
SUMMARY:TSMC 2024 China Technology Symposium
DESCRIPTION:Get the latest on:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC Technology Symposium! \n\n\n\n09:00 – 10:00\nRegistration & Ecosystem Pavilion\n\n\n10:00 – 10:10\nWelcome & Opening Remarks\n\n\n10:10 – 10:30\nMarket Update and Outlook\n\n\n10:30 – 11:00\nTechnology Leadership\n\n\n11:00 – 11:25\nCoffee Break & Ecosystem Pavilion\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 12:15\nAdvanced Technology Design Solutions\n\n\n12:15 – 13:25\nLunch & Ecosystem Pavilion\n\n\n13:25 – 13:45\nAdvanced Technology\n\n\n13:45 – 14:05\n3DFabric Technology\n\n\n14:05 – 14:40\nCoffee Break & Ecosystem Pavilion\n\n\n14:40 – 15:00\nAutomotive & eNVM Technology\n\n\n15:00 – 15:20\nIoT Technology\n\n\n15:20 – 15:40\nAdvanced RF and Analog Technology\n\n\n15:40 – 16:00\nLucky Draw
URL:https://marketingeda.com/event/tsmc-2024-china-technology-symposium/
LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240523T093000
DTEND;TZID=America/Los_Angeles:20240523T160000
DTSTAMP:20240506T221326Z
CREATED:20240506T221326Z
LAST-MODIFIED:20240506T221326Z
UID:7953-1716456600-1716480000@marketingeda.com
SUMMARY:Verification Academy Live: San Diego
DESCRIPTION:Siemens Digital Industries Software\n12348 High Bluff Drive\, Suite 250\nSan Diego\, CA 92130\n+1 (512) 221-7460 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-san-diego/
LOCATION:Siemens Digital Industries Software\, 12348 High Bluff Drive\, Suite 250\, San Diego\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process.
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
END:VEVENT
END:VCALENDAR