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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240616T080000
DTEND;TZID=America/Los_Angeles:20240620T170000
DTSTAMP:20240226T234257Z
CREATED:20240226T234257Z
LAST-MODIFIED:20240226T234257Z
UID:7693-1718524800-1718902800@marketingeda.com
SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS
DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles.
URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/
LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240610T080000
DTEND;TZID=Europe/Berlin:20240611T170000
DTSTAMP:20240503T162031Z
CREATED:20240503T162031Z
LAST-MODIFIED:20240503T162031Z
UID:7940-1718006400-1718125200@marketingeda.com
SUMMARY:SNUG Europe 2024
DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas
URL:https://marketingeda.com/event/snug-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240606T100000
DTEND;TZID=America/Los_Angeles:20240606T110000
DTSTAMP:20240524T015255Z
CREATED:20240524T015255Z
LAST-MODIFIED:20240524T015255Z
UID:8034-1717668000-1717671600@marketingeda.com
SUMMARY:Addressing Thermal Stress and Warpage Challenges in 3D-IC Designs
DESCRIPTION:Thermal stress analysis plays a crucial role in the design and performance optimization of packaging materials and boards\, especially in industries where temperature variations are significant. This webinar presents a comprehensive overview of recent developments in the newly-introduced Cadence Celsius Studio AI-enabled multiphysics thermal platform to solve today’s thermal stress and warpage analysis in 3D-ICs. \nCelsius Studio offers support for linear and nonlinear material structural models as well as static and quasi-static solvers for warpage and stress analysis and a moisture solver and high-temperature\, high-humidity (HTHH) analysis. Designers can perform multi-stage simulations for the design assembly process and material failure and reliability analysis. There are global and local models for 3D-IC warpage/stress simulation. \nYou will learn about: \n\nRecent developments in Celsius Studio that address thermal stress and warpage analysis in 3D-ICs\, including die-to-die sacking\, packing\, and boards warpage\nKey methods that can be used to address factors affecting thermal stress\, including nonlinear material properties\, geometric configuration\, and environmental conditions\nExample models for 3D-IC warpage/stress simulation
URL:https://marketingeda.com/event/addressing-thermal-stress-and-warpage-challenges-in-3d-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Zurich:20240606T080000
DTEND;TZID=Europe/Zurich:20240607T170000
DTSTAMP:20240524T163724Z
CREATED:20240524T163724Z
LAST-MODIFIED:20240524T163724Z
UID:8038-1717660800-1717779600@marketingeda.com
SUMMARY:International Workshop on Logic and Synthesis - IWLS 2024
DESCRIPTION:The International Workshop on Logic and Synthesis is the premier forum for research in synthesis\, optimization\, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms\, such as nanoscale systems and biological systems\, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development\, without providing complete solutions. The emphasis is on novelty and intellectual rigor. \nTopics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing\, validation\, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling\, analysis\, and synthesis for emerging technologies and platforms are particularly encouraged. \nThe workshop format includes paper presentations\, invited talks\, social lunch and dinner gatherings\, and recreational activities. \nCheck out our call for papers. \nKeynotes\nCan AI Design and Verify Your Design?\nZiyad Hanna\, Cadence Design Systems\, Israel \n\nAbstract: In this talk\, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark\, driven by the rapid growth in key markets in 5G\, Hyperscalers\, autonomous vehicles\, AI\, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge\, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes\, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk\, I will address the inherent challenges in the chip design industry\, analyze the current landscape of automation\, machine learning (ML)\, and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification\, including the automatic generation of programs supported by natural language processing (NLP) and generative AI\, the creation of temporal assertions from design specifications\, the integration of high-level synthesis (HLS) and formal verification\, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance\, power and area. Furthermore\, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. \nZiyad Hanna\, Ph.D.\, is currently a corporate VP at Cadence Design Systems (CDNS)\, and the general manager of Cadence Israel\, leading R&D centers in various countries\, in the electronic design automation domain. Prior to joining Cadence Design Systems\, Dr. Hanna was a Senior VP at Jasper Design Automation\, which was acquired by Cadence in 2014. At Jasper\, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa\, where he was instrumental in the development of several generations of formal verification systems\, which were used on almost all Intel microprocessor designs since early 1990s\, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University\, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence\, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member\, holds over 15 patents\, and has published more than 80 papers and talks.\n\n\nSymmetric Is Better: Can We Exploit Regularities in Logic Synthesis?\nValentina Ciriani\, University of Milano\, Italy \n\nAbstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose\, the algebraic form of the function is manipulated\, as it directly reflects the cost of the corresponding circuit. Depending on the design needs\, different two-level or multi-level forms are considered\, and ad hoc algorithms are used to express and minimize such forms. In all cases\, the functions under consideration encode “real life” problems\, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover\, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally\, we show how regularities can also ease polynomial verification. \nValentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa\, Italy\, in 1998 and 2003\, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa\, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science\, University of Milano\, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures\, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers\, published in international journals\, conference proceedings\, and books chapters.\n\n\n\nToward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?\nLuca Benini\, ETH Zurich / University of Bologna\, Switzerland / Italy \n\nAbstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today\, open-source designs exist targeting a wide range of RISC-V based computing systems\, from tiny microcontrollers to high-performance many-core\, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can\, or even should\, push further\, open sourcing design automation tools and technology libraries\, PDKs\, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories\, drawing from a decade of experience in designing and industrializing open source hardware. \nLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems\, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE\, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award\, the 2020 EDAA achievement Award\, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.
URL:https://marketingeda.com/event/international-workshop-on-logic-and-synthesis-iwls-2024/
LOCATION:ETH Zurich\, Rämistrasse 101\, Zurich\, Switzerland
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWLS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240606T080000
DTEND;TZID=America/Chicago:20240606T170000
DTSTAMP:20240506T222541Z
CREATED:20240506T222446Z
LAST-MODIFIED:20240506T222541Z
UID:7961-1717660800-1717693200@marketingeda.com
SUMMARY:Verification Academy Live: Huntsville
DESCRIPTION:Siemens Training Center\n360E Quality Circle\, Suite 500\nHuntsville\, AL 35806\n+1 (256) 705-2501 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-huntsville/
LOCATION:Siemens Training Center\, 360E Quality Circle\, Suite 500\, Huntsville\, AL\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T100000
DTEND;TZID=America/Los_Angeles:20240604T110000
DTSTAMP:20240524T203508Z
CREATED:20240524T203431Z
LAST-MODIFIED:20240524T203508Z
UID:8046-1717495200-1717498800@marketingeda.com
SUMMARY:Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
DESCRIPTION:Today’s advanced node chip designs are faced with many new complexities which require more verification\, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design\, test and manufacturing (petabytes)\, analyze the data\, and provide actionable insights on that data. \nPart of the Synopsys.da AI analytics tools\,  Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges by increasing engineering productivity\, improving silicon efficiency and providing the tool scalability needed for today’s advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle. \nIn this presentation\, Mr. Anti Tseng\, Senior Manager at MediaTek\, will explain how Silicon.da’s volume diagnostics feature identified systematic issues more efficiently than traditional methods by providing very accurate failure locations within the silicon resulting in improved yield by a single digit percentage and in a shorter amount of time – from weeks to days. Mr. Tseng will also further discuss how utilizing this volume diagnosis analysis technology improves the foundry process for advanced nodes resulting in millions of dollars of cost savings through high volume chip production for fabless companies. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng\n\n\nSenior Manager\nMediaTek \n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng has been with MediaTek for 16 years and mainly covered three categories: CPU implementation/DFT/MBIST\, silicon speed binning & manufacture process debug\, in-house data platform & CAD flow development. His current focus is to enable smooth mass production of first advanced process node in MediaTek by exploring next-generation DFT architecture\, ATPG & diagnosis flow\, and AI-based data analysis. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez is principal\, product management at Synopsys. His marketing career spans over 25 years where he has held various marketing positions including technical\, product/solution\, channel/field\, integrated/corporate\, alliance and business development for companies such as Synopsys\, Cadence\, VMware and Optimal+. Prior to that he spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing)\, and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes\, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise\, Cortez was a pre- and post-sales applications engineer\, and also doubled as the company’s instructor.
URL:https://marketingeda.com/event/silicon-da-the-first-integrated-slm-analytics-solution-from-design-through-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240604T093000
DTEND;TZID=America/New_York:20240604T160000
DTSTAMP:20240506T221850Z
CREATED:20240506T221850Z
LAST-MODIFIED:20240506T221850Z
UID:7957-1717493400-1717516800@marketingeda.com
SUMMARY:Verification Academy Live: Westford (Boston Area)
DESCRIPTION:Westford Regency Inn and Conference Center\n219 Littleton Rd\nWestford\, MA 01886\n+1 (978) 692-8200 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-westford-boston-area/
LOCATION:Westford Regency Inn and Conference Center\, 219 Littleton Rd\, Westford\, MA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T080000
DTEND;TZID=America/Los_Angeles:20240607T170000
DTSTAMP:20240528T161702Z
CREATED:20240528T161702Z
LAST-MODIFIED:20240528T161702Z
UID:8052-1717488000-1717779600@marketingeda.com
SUMMARY:PCB East 2024
DESCRIPTION:The Electronics Industry’s East Coast Conference and Exhibition. \n1. Educational opportunities.\nNo matter how experienced you are\, everyone can learn! PCB East is widely acknowledged as the best technical conference in the industry. \n2. Networking with peers.\nCollaboration\, inspiration\, and more! \n3. New vendors and suppliers.\nTools and materials are always changing. Keeping up is paramount. \n4. Position yourself as an expert.\nWhy be the best-kept secret in the industry? \n5. It’s fun!\nAll work and no play gets old and fast. Manage your career growth with a social aspect!
URL:https://marketingeda.com/event/pcb-east-2024/
LOCATION:Boxboro Regency Hotel and Conference Center\, 242 Adams Pl\, Boxborough\, MA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-East-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T080000
DTEND;TZID=America/Los_Angeles:20240530T090000
DTSTAMP:20240521T162703Z
CREATED:20240521T162703Z
LAST-MODIFIED:20240521T162703Z
UID:8011-1717056000-1717059600@marketingeda.com
SUMMARY:Optimizing connectivity between Xpedition and HFSS for RF systems design
DESCRIPTION:In today’s fast-paced technological landscape\, seamless integration between design and simulation tools is crucial for accelerating product development cycles and ensuring optimal performance of electronics\, especially RF systems. Siemens Xpedition and Ansys HFSS stand as pillars in their respective domains\, offering powerful capabilities for electronic design and electromagnetic simulation. \nIn this live conversation\, Sara Louie from Ansys and Per Viklund from Siemens will describe the two-way connectivity between Siemens Xpedition and Ansys HFSS\, revolutionizing the electronic design and simulation workflow. We delve into the details of bidirectional data exchange\, enabling engineers to seamlessly transfer layout geometries and parameters between the two platforms.
URL:https://marketingeda.com/event/optimizing-connectivity-between-xpedition-and-hfss-for-rf-systems-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Xpedition-HFSS-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20240528T093000
DTEND;TZID=Asia/Jerusalem:20240528T173000
DTSTAMP:20240522T193335Z
CREATED:20240522T193335Z
LAST-MODIFIED:20240522T193335Z
UID:8027-1716888600-1716917400@marketingeda.com
SUMMARY:FV-Israel\, Summit 2024
DESCRIPTION:Connect with industry experts\, academics\, and enthusiasts for discussions on FV in Israel. \nExplore new developments from top semiconductor firms\, advanced EDA tools\, and academic research. \nEngage with leaders\, exchange insights\, and help shape the future of FV in Israel and globally. \nDistinguished Speaker \nDadi Perlmutter\nTechnology and social entrepreneur and former VP at Intel
URL:https://marketingeda.com/event/fv-israel-summit-2024/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FV-Israel-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240528T090000
DTEND;TZID=Asia/Shanghai:20240528T160000
DTSTAMP:20240522T200534Z
CREATED:20240522T194800Z
LAST-MODIFIED:20240522T200534Z
UID:8030-1716886800-1716912000@marketingeda.com
SUMMARY:TSMC 2024 China Technology Symposium
DESCRIPTION:Get the latest on:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC Technology Symposium! \n\n\n\n09:00 – 10:00\nRegistration & Ecosystem Pavilion\n\n\n10:00 – 10:10\nWelcome & Opening Remarks\n\n\n10:10 – 10:30\nMarket Update and Outlook\n\n\n10:30 – 11:00\nTechnology Leadership\n\n\n11:00 – 11:25\nCoffee Break & Ecosystem Pavilion\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 12:15\nAdvanced Technology Design Solutions\n\n\n12:15 – 13:25\nLunch & Ecosystem Pavilion\n\n\n13:25 – 13:45\nAdvanced Technology\n\n\n13:45 – 14:05\n3DFabric Technology\n\n\n14:05 – 14:40\nCoffee Break & Ecosystem Pavilion\n\n\n14:40 – 15:00\nAutomotive & eNVM Technology\n\n\n15:00 – 15:20\nIoT Technology\n\n\n15:20 – 15:40\nAdvanced RF and Analog Technology\n\n\n15:40 – 16:00\nLucky Draw
URL:https://marketingeda.com/event/tsmc-2024-china-technology-symposium/
LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240523T093000
DTEND;TZID=America/Los_Angeles:20240523T160000
DTSTAMP:20240506T221326Z
CREATED:20240506T221326Z
LAST-MODIFIED:20240506T221326Z
UID:7953-1716456600-1716480000@marketingeda.com
SUMMARY:Verification Academy Live: San Diego
DESCRIPTION:Siemens Digital Industries Software\n12348 High Bluff Drive\, Suite 250\nSan Diego\, CA 92130\n+1 (512) 221-7460 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-san-diego/
LOCATION:Siemens Digital Industries Software\, 12348 High Bluff Drive\, Suite 250\, San Diego\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process.
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T100000
DTEND;TZID=America/Los_Angeles:20240521T110000
DTSTAMP:20240503T190402Z
CREATED:20240503T190402Z
LAST-MODIFIED:20240503T190402Z
UID:7943-1716285600-1716289200@marketingeda.com
SUMMARY:The Next Generation of 3DIC Interposer/InFO Design
DESCRIPTION:In recent years\, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm\, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets. \n  \nWhat Attendees Will Learn: \nSynopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform\, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow\, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning\, construction\, extraction\, and signoff. Finally\, we’ll wrap up with conclusions and future work. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKenneth Larsen\n\n\nProduct Management\, Sr Director\nSynopsys \n\n\n\n\n\n\n\n\nKenneth Larsen is a director of product management in the EDA Group at Synopsys\, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys\, Kenneth was worldwide senior technical director at Mentor. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale\n\n\nPrincipal Member of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nNitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology\, though he has previously also worked on design automation that ranges across STA\, EM/IR\, Thermal\, ESD\, SOC Floorplanning & Construction\, IP Management\, Netlisting\, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside of work\, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAkshata Sonnad\n\n\nMember of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nAkshata Sonnad is a Member of Technical Staff at AMD\, working on developing methodologies and flows for floor planning\, signoff\, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs\, before making a transition to 3DIC Design Methodology.
URL:https://marketingeda.com/event/the-next-generation-of-3dic-interposer-info-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T093000
DTEND;TZID=America/Los_Angeles:20240521T160000
DTSTAMP:20240506T220409Z
CREATED:20240506T220409Z
LAST-MODIFIED:20240506T220409Z
UID:7949-1716283800-1716307200@marketingeda.com
SUMMARY:Verification Academy Live: El Segundo
DESCRIPTION:Embassy Suites by Hilton\, LAX South\n1440 East Imperial Avenue\nEl Segundo\, CA 90245\n+1 (310) 640-3600 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-el-segundo/
LOCATION:Embassy Suites by Hilton\, LAX South\, 1440 East Imperial Avenue\, El Segundo\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T080000
DTEND;TZID=America/Los_Angeles:20240523T170000
DTSTAMP:20240327T162206Z
CREATED:20240327T162206Z
LAST-MODIFIED:20240327T162206Z
UID:7771-1716278400-1716483600@marketingeda.com
SUMMARY:Embedded Vision Summit 2024
DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy Attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\nJoin us for three days of learning—from tutorials to Deep-Dive Day\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\nFour Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\n\n\nWe’ve been doing this for 13 years.\n\n\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.
URL:https://marketingeda.com/event/embedded-vision-summit-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summmit-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T100000
DTEND;TZID=America/Los_Angeles:20240516T110000
DTSTAMP:20240221T175436Z
CREATED:20240221T175436Z
LAST-MODIFIED:20240221T175436Z
UID:7667-1715853600-1715857200@marketingeda.com
SUMMARY:AI-Driven EM-IR Design Closure
DESCRIPTION:IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly\, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge\, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology. \nIn this webinar\, we will present an AI-driven EM-IR closure solution integrated into the implementation flow. This solution uses AI methods to automatically root cause the IR drop violations and selects the most efficient PPA- and DRC-aware methods to fix the IR drop issues. The solution also uses AI models to enable fast incremental IR inferencing to validate the benefit of the design improvements. \nCome learn about this breakthrough solution that will significantly improve your IR drop closure TAT.
URL:https://marketingeda.com/event/ai-driven-em-ir-design-closure/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T093000
DTEND;TZID=America/Los_Angeles:20240516T140000
DTSTAMP:20240424T162625Z
CREATED:20240424T162625Z
LAST-MODIFIED:20240424T162625Z
UID:7907-1715851800-1715868000@marketingeda.com
SUMMARY:Keysight EDA Connect Tour - Burlington
DESCRIPTION:As AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nAgenda\n\n\n\n09:30 a.m.\nDoors open\n\n\n10:00 a.m.\nWelcome\n\n\n10:10 a.m.\nRapid EM-Circuit Co-Design of Microwave ICs\, Packages\, and Modules\n\n\n11:00 a.m.\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs/ Chiplets\n\n\n11:45 a.m.\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n12:30 p.m.\nNew System Verification Tools in ADS for Circuit Designers\n\n\n1:00 p.m.\nLunch Session- Keysight Eggplant- Software Test Automation\n\n\n\n\n\n\n1:30 p.m.\nKeysight Design Data and IP Management
URL:https://marketingeda.com/event/keysight-eda-connect-tour-burlington/
LOCATION:Eddie V’s Restaurant\, 50 South Avenue\, Burlington\, MA\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240515T130000
DTEND;TZID=America/Los_Angeles:20240515T140000
DTSTAMP:20240508T233014Z
CREATED:20240508T233014Z
LAST-MODIFIED:20240508T233014Z
UID:7977-1715778000-1715781600@marketingeda.com
SUMMARY:Innovative Technologies\, Tools\, and Methodologies for Space Applications
DESCRIPTION:In the world of space applications\, reliability is paramount. As the space sector continues to experience rapid growth and evolution\, new challenges are emerging to meet the demands of various mission types and requirements\, such as robust functional safety protections\, high reliability\, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor\, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development. \nSpeakers \nJim T.\, Business Development\, Lattice Semiconductor\nKhalid Khan\, Directory of Applications Engineer\, Synopsys\nMelanie Berg\, Founder and CEO\, Space R3
URL:https://marketingeda.com/event/innovative-technologies-tools-and-methodologies-for-space-applications/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Lattice-May-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240514T100000
DTEND;TZID=America/New_York:20240516T140000
DTSTAMP:20240311T204851Z
CREATED:20240311T204851Z
LAST-MODIFIED:20240311T204851Z
UID:7721-1715680800-1715868000@marketingeda.com
SUMMARY:Ansys - Simulation World 2024
DESCRIPTION:Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel\, portable\, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that medical researchers at the University of Zaragoza are relying on multiscale simulation frameworks to model solid tumor growth at the subcellular\, cellular\, tissue\, and organ level to better assess and treat cancer? \nAcross industries\, Ansys customers are using simulation to do some pretty heavy lifting — from electrifying mobility\, to advancing safer medical treatments\, to keeping satellites in orbit\, to name a few. There are few limits to how simulation can be applied. \n\n\n\n\n\n\n\n\nOf course\, all of these innovations have one thing in common. They began with ideas from people just like you\, who\, with the right tools at the right time\, made their industry-changing ideas reality. From May 14-16\, you’ll have the opportunity to hear from many of them during Simulation World 2024\, a virtual event demonstrating how Ansys technologies can put the power of innovation in your hands. \nSimulation World 2024 celebrates our customers’ engineering achievements to inspire you. It connects you with the tools and solvers you need to work smarter\, not harder to test your own theories. And it shows you how Ansys technologies can help you act on your ideas to make your breakthrough ideas reality. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDiscover Where the Power of Ansys Simulation Can Take You in 14 Great Tracks\nThis year’s free\, virtual event takes place over three days\, organized into 14 distinct tracks that speak to the transformative power of simulation to inspire\, equip\, and empower you on the way to technological innovation and exploration: \nDay 1: Inspire\n\nCreate What’s Next in Mobility: Learn how simulation is transforming mobility to address unprecedented challenges and deliver cost-effective\, competitively differentiated solutions\, from safer\, more sustainable designs to the complex electronics and embedded software that define them.\nDigital Engineering for Mission Success: The aerospace and defense industries must operate on the cutting edge to deliver advanced capabilities. Learn how digital engineering helps them increase flexibility\, update legacy programs\, and speed new technology into service.\nAccelerate Cleaner Energy Development: See how industries rely on simulation to streamline production and distribution of safer\, cleaner\, more reliable energy through fuel-to-power conversions\, and to accelerate scaling of low-carbon energy solutions.\nDigitize and Personalize Medicine: Safer medical treatments can require more testing and clinical trials\, making traditional approaches less affordable. Discover how simulation-driven in silico methods reduce market costs and facilitate breakthrough innovation\, without compromising patient safety.\nEnsure First-Time Silicon Success: Hear how integrated chip (IC) designers are tackling significant challenges rising from bespoke silicon trends and 3D-IC packaging technology to ensure first-time silicon success.\n\nDay 2: Empower:\n\nTackle Engineering Complexity with Numerics: This track demonstrates how the application of advanced physics models and numerical methods for multiphysics simulation can tackle difficult design challenges and analyze real-world scenarios to overcome increasing product complexity.\nEngineer without Limits: Learn why having the flexibility and open ecosystem needed to simulate modern\, complex products and systems at scale requires the latest advancements in hyperscale and cloud computing.\nTransform Simulation at the Speed of AI: AI-augmented simulation technology is a real game-changer\, bringing unprecedented speed\, innovation\, and accessibility to engineering. See why it’s not just about accelerating simulation\, it’s about making it more accessible.\nConnect Digital Threads: This track discusses the ability of digital engineering to sort through complexity to reduce time\, cost\, and risk — increasing accuracy and performance with physics rigor to deliver a design infrastructure and open ecosystem along a two-way digital thread.\n\nDay 3: Equip\n\nPower Up Intelligent Connectivity: Discover the power of electromagnetic simulation to successfully model\, analyze\, and design many high- and low-frequency electronics\, including computing platforms\, generators and transformers\, communications systems and satellites\, and advanced driver-assistance systems.\nReinforce Structural Integrity: This track shows how simulation solves complex structural engineering challenges quickly and efficiently through finite element analysis (FEA)\, customized and automated solutions for structural mechanics\, and multiple design scenario analyses to ensure greater product integrity.\nGo with the Computational Flow: Get a better perspective of computational fluid dynamics (CFD) analysis and how it delivers insights to help companies make critical design decisions that reduce energy consumption and improve product performance.\nInnovate at the Speed of Light: See how optics-specific tools and workflows help optical designers innovate across an entire industry to expedite groundbreaking product development and improve performance\, reliability\, and yield — from the nano to the micro scale.\nOptimize Across the Board: Learn how comprehensive multiphysics EM/IR\, thermal\, and electromagnetic simulation are accelerating 3D-IC design\, bespoke silicon\, and intelligent connectivity to increase the speed and efficiency of semiconductor manufacturing.\n\nRegister Now for Simulation World 2024\nAt Simulation World 2024\, you’ll hear from members of the global product development community as they come together to inspire you — and each other — with tales of agility\, innovation\, determination\, and discovery on the way to solving them. \nIn this virtual setting\, you can view and rearrange your schedule before or during live sessions — all from the comfort of your personal workspace. Curate your own agenda based on track or topic\, then view\, download\, and share them with others\, or export them to your calendar. \nEvery day\, Ansys technologies are powering innovations that drive advancement. Simulation World 2024 is a chance for you see how they can help you do the same — whether you’ve got a seed of an idea you’d like to grow\, or are well on your way to innovating something new. And participation is free. \nSo be sure to sign up for Simulation World 2024 today and encourage your colleagues to do the same.
URL:https://marketingeda.com/event/ansys-simulation-world-2024/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-May-14-16-2024.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20240514T100000
DTEND;TZID=Europe/Rome:20240514T120000
DTSTAMP:20240423T010041Z
CREATED:20240423T010017Z
LAST-MODIFIED:20240423T010041Z
UID:7896-1715680800-1715688000@marketingeda.com
SUMMARY:Introduction to the Open-source EDA Ecosystem
DESCRIPTION:Open-source hardware in the European Chips Act\nMatthew Xuereb\, European Commission \nFree and open-source semiconductor ecosystem\nLuca Alloatti\, Free Silicon Foundation ETS \nOpen-source EDA software and semiconductor design\nJean-Paul Chaput\, Sorbonne University\, Coriolis Foundation \nEuropean roadmap on the advancement of open-source EDA tools\nRihards Novickis\, Latvian Institute of Electronics and Computer Science
URL:https://marketingeda.com/event/introduction-to-the-open-source-eda-ecosystem/
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-EDA-ecosystem.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240513T080000
DTEND;TZID=America/Los_Angeles:20240517T170000
DTSTAMP:20240514T181939Z
CREATED:20240514T181805Z
LAST-MODIFIED:20240514T181939Z
UID:7992-1715587200-1715965200@marketingeda.com
SUMMARY:SEE\, MAPLD 2024
DESCRIPTION:Our workshop will feature content including\, but not limited to\, the following areas: \n\n\n\n\nArtificial Intelligence & Machine Learning (AI / ML)\n\nContinuing Education & Workforce Development\n\n\n\nDesigning with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices\n\nFPGA & SoC Assurance\n\n\n\nGuidelines and Standards\n\nOn-Orbit Experiments & Model Validation\n\n\n\nRadiation Hardness Assurance (RHA)\n\nSEE Test Facilities\n\n\n\nSEE in Devices & Circuits / Mechanisms & Modeling\n\nSpace Environments
URL:https://marketingeda.com/event/see-mapld-2024/
LOCATION:Marriott La Jolla\, 4240 La Jolla Village Drive\, La Jolla\, CA\, United States
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEE-MAPLD.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T173000
DTEND;TZID=America/Los_Angeles:20240509T203000
DTSTAMP:20240328T160417Z
CREATED:20240328T160417Z
LAST-MODIFIED:20240328T160417Z
UID:7787-1715275800-1715286600@marketingeda.com
SUMMARY:ESD Alliance CEO/Executive Outlook
DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners.
URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240429T161925Z
CREATED:20240429T161925Z
LAST-MODIFIED:20240429T161925Z
UID:7925-1715248800-1715252400@marketingeda.com
SUMMARY:Cracking the Power Code: Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/cracking-the-power-code-innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024-USA.jpg
END:VEVENT
END:VCALENDAR