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DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process.
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T100000
DTEND;TZID=America/Los_Angeles:20240521T110000
DTSTAMP:20240503T190402Z
CREATED:20240503T190402Z
LAST-MODIFIED:20240503T190402Z
UID:7943-1716285600-1716289200@marketingeda.com
SUMMARY:The Next Generation of 3DIC Interposer/InFO Design
DESCRIPTION:In recent years\, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm\, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets. \n  \nWhat Attendees Will Learn: \nSynopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform\, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow\, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning\, construction\, extraction\, and signoff. Finally\, we’ll wrap up with conclusions and future work. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKenneth Larsen\n\n\nProduct Management\, Sr Director\nSynopsys \n\n\n\n\n\n\n\n\nKenneth Larsen is a director of product management in the EDA Group at Synopsys\, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys\, Kenneth was worldwide senior technical director at Mentor. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale\n\n\nPrincipal Member of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nNitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology\, though he has previously also worked on design automation that ranges across STA\, EM/IR\, Thermal\, ESD\, SOC Floorplanning & Construction\, IP Management\, Netlisting\, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside of work\, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAkshata Sonnad\n\n\nMember of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nAkshata Sonnad is a Member of Technical Staff at AMD\, working on developing methodologies and flows for floor planning\, signoff\, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs\, before making a transition to 3DIC Design Methodology.
URL:https://marketingeda.com/event/the-next-generation-of-3dic-interposer-info-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T093000
DTEND;TZID=America/Los_Angeles:20240521T160000
DTSTAMP:20240506T220409Z
CREATED:20240506T220409Z
LAST-MODIFIED:20240506T220409Z
UID:7949-1716283800-1716307200@marketingeda.com
SUMMARY:Verification Academy Live: El Segundo
DESCRIPTION:Embassy Suites by Hilton\, LAX South\n1440 East Imperial Avenue\nEl Segundo\, CA 90245\n+1 (310) 640-3600 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-el-segundo/
LOCATION:Embassy Suites by Hilton\, LAX South\, 1440 East Imperial Avenue\, El Segundo\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T080000
DTEND;TZID=America/Los_Angeles:20240523T170000
DTSTAMP:20240327T162206Z
CREATED:20240327T162206Z
LAST-MODIFIED:20240327T162206Z
UID:7771-1716278400-1716483600@marketingeda.com
SUMMARY:Embedded Vision Summit 2024
DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy Attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\nJoin us for three days of learning—from tutorials to Deep-Dive Day\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\nFour Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\n\n\nWe’ve been doing this for 13 years.\n\n\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.
URL:https://marketingeda.com/event/embedded-vision-summit-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summmit-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T100000
DTEND;TZID=America/Los_Angeles:20240516T110000
DTSTAMP:20240221T175436Z
CREATED:20240221T175436Z
LAST-MODIFIED:20240221T175436Z
UID:7667-1715853600-1715857200@marketingeda.com
SUMMARY:AI-Driven EM-IR Design Closure
DESCRIPTION:IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly\, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge\, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology. \nIn this webinar\, we will present an AI-driven EM-IR closure solution integrated into the implementation flow. This solution uses AI methods to automatically root cause the IR drop violations and selects the most efficient PPA- and DRC-aware methods to fix the IR drop issues. The solution also uses AI models to enable fast incremental IR inferencing to validate the benefit of the design improvements. \nCome learn about this breakthrough solution that will significantly improve your IR drop closure TAT.
URL:https://marketingeda.com/event/ai-driven-em-ir-design-closure/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T093000
DTEND;TZID=America/Los_Angeles:20240516T140000
DTSTAMP:20240424T162625Z
CREATED:20240424T162625Z
LAST-MODIFIED:20240424T162625Z
UID:7907-1715851800-1715868000@marketingeda.com
SUMMARY:Keysight EDA Connect Tour - Burlington
DESCRIPTION:As AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nAgenda\n\n\n\n09:30 a.m.\nDoors open\n\n\n10:00 a.m.\nWelcome\n\n\n10:10 a.m.\nRapid EM-Circuit Co-Design of Microwave ICs\, Packages\, and Modules\n\n\n11:00 a.m.\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs/ Chiplets\n\n\n11:45 a.m.\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n12:30 p.m.\nNew System Verification Tools in ADS for Circuit Designers\n\n\n1:00 p.m.\nLunch Session- Keysight Eggplant- Software Test Automation\n\n\n\n\n\n\n1:30 p.m.\nKeysight Design Data and IP Management
URL:https://marketingeda.com/event/keysight-eda-connect-tour-burlington/
LOCATION:Eddie V’s Restaurant\, 50 South Avenue\, Burlington\, MA\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240515T130000
DTEND;TZID=America/Los_Angeles:20240515T140000
DTSTAMP:20240508T233014Z
CREATED:20240508T233014Z
LAST-MODIFIED:20240508T233014Z
UID:7977-1715778000-1715781600@marketingeda.com
SUMMARY:Innovative Technologies\, Tools\, and Methodologies for Space Applications
DESCRIPTION:In the world of space applications\, reliability is paramount. As the space sector continues to experience rapid growth and evolution\, new challenges are emerging to meet the demands of various mission types and requirements\, such as robust functional safety protections\, high reliability\, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor\, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development. \nSpeakers \nJim T.\, Business Development\, Lattice Semiconductor\nKhalid Khan\, Directory of Applications Engineer\, Synopsys\nMelanie Berg\, Founder and CEO\, Space R3
URL:https://marketingeda.com/event/innovative-technologies-tools-and-methodologies-for-space-applications/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Lattice-May-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240514T100000
DTEND;TZID=America/New_York:20240516T140000
DTSTAMP:20240311T204851Z
CREATED:20240311T204851Z
LAST-MODIFIED:20240311T204851Z
UID:7721-1715680800-1715868000@marketingeda.com
SUMMARY:Ansys - Simulation World 2024
DESCRIPTION:Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel\, portable\, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that medical researchers at the University of Zaragoza are relying on multiscale simulation frameworks to model solid tumor growth at the subcellular\, cellular\, tissue\, and organ level to better assess and treat cancer? \nAcross industries\, Ansys customers are using simulation to do some pretty heavy lifting — from electrifying mobility\, to advancing safer medical treatments\, to keeping satellites in orbit\, to name a few. There are few limits to how simulation can be applied. \n\n\n\n\n\n\n\n\nOf course\, all of these innovations have one thing in common. They began with ideas from people just like you\, who\, with the right tools at the right time\, made their industry-changing ideas reality. From May 14-16\, you’ll have the opportunity to hear from many of them during Simulation World 2024\, a virtual event demonstrating how Ansys technologies can put the power of innovation in your hands. \nSimulation World 2024 celebrates our customers’ engineering achievements to inspire you. It connects you with the tools and solvers you need to work smarter\, not harder to test your own theories. And it shows you how Ansys technologies can help you act on your ideas to make your breakthrough ideas reality. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDiscover Where the Power of Ansys Simulation Can Take You in 14 Great Tracks\nThis year’s free\, virtual event takes place over three days\, organized into 14 distinct tracks that speak to the transformative power of simulation to inspire\, equip\, and empower you on the way to technological innovation and exploration: \nDay 1: Inspire\n\nCreate What’s Next in Mobility: Learn how simulation is transforming mobility to address unprecedented challenges and deliver cost-effective\, competitively differentiated solutions\, from safer\, more sustainable designs to the complex electronics and embedded software that define them.\nDigital Engineering for Mission Success: The aerospace and defense industries must operate on the cutting edge to deliver advanced capabilities. Learn how digital engineering helps them increase flexibility\, update legacy programs\, and speed new technology into service.\nAccelerate Cleaner Energy Development: See how industries rely on simulation to streamline production and distribution of safer\, cleaner\, more reliable energy through fuel-to-power conversions\, and to accelerate scaling of low-carbon energy solutions.\nDigitize and Personalize Medicine: Safer medical treatments can require more testing and clinical trials\, making traditional approaches less affordable. Discover how simulation-driven in silico methods reduce market costs and facilitate breakthrough innovation\, without compromising patient safety.\nEnsure First-Time Silicon Success: Hear how integrated chip (IC) designers are tackling significant challenges rising from bespoke silicon trends and 3D-IC packaging technology to ensure first-time silicon success.\n\nDay 2: Empower:\n\nTackle Engineering Complexity with Numerics: This track demonstrates how the application of advanced physics models and numerical methods for multiphysics simulation can tackle difficult design challenges and analyze real-world scenarios to overcome increasing product complexity.\nEngineer without Limits: Learn why having the flexibility and open ecosystem needed to simulate modern\, complex products and systems at scale requires the latest advancements in hyperscale and cloud computing.\nTransform Simulation at the Speed of AI: AI-augmented simulation technology is a real game-changer\, bringing unprecedented speed\, innovation\, and accessibility to engineering. See why it’s not just about accelerating simulation\, it’s about making it more accessible.\nConnect Digital Threads: This track discusses the ability of digital engineering to sort through complexity to reduce time\, cost\, and risk — increasing accuracy and performance with physics rigor to deliver a design infrastructure and open ecosystem along a two-way digital thread.\n\nDay 3: Equip\n\nPower Up Intelligent Connectivity: Discover the power of electromagnetic simulation to successfully model\, analyze\, and design many high- and low-frequency electronics\, including computing platforms\, generators and transformers\, communications systems and satellites\, and advanced driver-assistance systems.\nReinforce Structural Integrity: This track shows how simulation solves complex structural engineering challenges quickly and efficiently through finite element analysis (FEA)\, customized and automated solutions for structural mechanics\, and multiple design scenario analyses to ensure greater product integrity.\nGo with the Computational Flow: Get a better perspective of computational fluid dynamics (CFD) analysis and how it delivers insights to help companies make critical design decisions that reduce energy consumption and improve product performance.\nInnovate at the Speed of Light: See how optics-specific tools and workflows help optical designers innovate across an entire industry to expedite groundbreaking product development and improve performance\, reliability\, and yield — from the nano to the micro scale.\nOptimize Across the Board: Learn how comprehensive multiphysics EM/IR\, thermal\, and electromagnetic simulation are accelerating 3D-IC design\, bespoke silicon\, and intelligent connectivity to increase the speed and efficiency of semiconductor manufacturing.\n\nRegister Now for Simulation World 2024\nAt Simulation World 2024\, you’ll hear from members of the global product development community as they come together to inspire you — and each other — with tales of agility\, innovation\, determination\, and discovery on the way to solving them. \nIn this virtual setting\, you can view and rearrange your schedule before or during live sessions — all from the comfort of your personal workspace. Curate your own agenda based on track or topic\, then view\, download\, and share them with others\, or export them to your calendar. \nEvery day\, Ansys technologies are powering innovations that drive advancement. Simulation World 2024 is a chance for you see how they can help you do the same — whether you’ve got a seed of an idea you’d like to grow\, or are well on your way to innovating something new. And participation is free. \nSo be sure to sign up for Simulation World 2024 today and encourage your colleagues to do the same.
URL:https://marketingeda.com/event/ansys-simulation-world-2024/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-May-14-16-2024.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20240514T100000
DTEND;TZID=Europe/Rome:20240514T120000
DTSTAMP:20240423T010041Z
CREATED:20240423T010017Z
LAST-MODIFIED:20240423T010041Z
UID:7896-1715680800-1715688000@marketingeda.com
SUMMARY:Introduction to the Open-source EDA Ecosystem
DESCRIPTION:Open-source hardware in the European Chips Act\nMatthew Xuereb\, European Commission \nFree and open-source semiconductor ecosystem\nLuca Alloatti\, Free Silicon Foundation ETS \nOpen-source EDA software and semiconductor design\nJean-Paul Chaput\, Sorbonne University\, Coriolis Foundation \nEuropean roadmap on the advancement of open-source EDA tools\nRihards Novickis\, Latvian Institute of Electronics and Computer Science
URL:https://marketingeda.com/event/introduction-to-the-open-source-eda-ecosystem/
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-EDA-ecosystem.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240513T080000
DTEND;TZID=America/Los_Angeles:20240517T170000
DTSTAMP:20240514T181939Z
CREATED:20240514T181805Z
LAST-MODIFIED:20240514T181939Z
UID:7992-1715587200-1715965200@marketingeda.com
SUMMARY:SEE\, MAPLD 2024
DESCRIPTION:Our workshop will feature content including\, but not limited to\, the following areas: \n\n\n\n\nArtificial Intelligence & Machine Learning (AI / ML)\n\nContinuing Education & Workforce Development\n\n\n\nDesigning with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices\n\nFPGA & SoC Assurance\n\n\n\nGuidelines and Standards\n\nOn-Orbit Experiments & Model Validation\n\n\n\nRadiation Hardness Assurance (RHA)\n\nSEE Test Facilities\n\n\n\nSEE in Devices & Circuits / Mechanisms & Modeling\n\nSpace Environments
URL:https://marketingeda.com/event/see-mapld-2024/
LOCATION:Marriott La Jolla\, 4240 La Jolla Village Drive\, La Jolla\, CA\, United States
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEE-MAPLD.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T173000
DTEND;TZID=America/Los_Angeles:20240509T203000
DTSTAMP:20240328T160417Z
CREATED:20240328T160417Z
LAST-MODIFIED:20240328T160417Z
UID:7787-1715275800-1715286600@marketingeda.com
SUMMARY:ESD Alliance CEO/Executive Outlook
DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners.
URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240429T161925Z
CREATED:20240429T161925Z
LAST-MODIFIED:20240429T161925Z
UID:7925-1715248800-1715252400@marketingeda.com
SUMMARY:Cracking the Power Code: Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/cracking-the-power-code-innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024-USA.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240419T172547Z
CREATED:20240419T172547Z
LAST-MODIFIED:20240419T172547Z
UID:7883-1715248800-1715252400@marketingeda.com
SUMMARY:AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
DESCRIPTION:Antenna/RF design problems often involve the optimization of many variables\, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent\, accurate\, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. \nLeveraging an advanced AI-enabled methodology\, the Cadence Optimality Intelligent System Explorer delivers quality results leading to the optimal performance of electrical systems. Optimality Explorer utilizes a novel surrogate model-aware mechanism that significantly reduces the number of required EM simulations. In addition\, the seamless integration between different Cadence solver technologies (Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer) enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems. \nWith the integration of Clarity 3D Solver and AWR Microwave Office\, RF/antenna designers will have ready access to high-capacity EM analysis for design verification and signoff of large\, complex RF mixed-signal systems beyond the capabilities offered by conventional solvers thanks to the Clarity distributed multiprocessing technology. \nThis webinar demonstrates the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems. \nKey takeaways: \n\nOptimality Explorer leverages an advanced AI-enabled methodology to deliver quality results leading to the optimal performance of electrical systems\nThe seamless integration between Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems\nDemonstration of the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems
URL:https://marketingeda.com/event/ai-driven-3d-system-analysis-optimization-for-em-antenna-rf-problems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T083000
DTEND;TZID=America/Los_Angeles:20240509T170000
DTSTAMP:20240415T181329Z
CREATED:20240415T181329Z
LAST-MODIFIED:20240415T181329Z
UID:7853-1715243400-1715274000@marketingeda.com
SUMMARY:TSMC Technology Workshop 2024 - Boston
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour
URL:https://marketingeda.com/event/tsmc-technology-workshop-2024-boston/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,Foundry,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240507T090000
DTEND;TZID=Europe/Berlin:20240507T220000
DTSTAMP:20240429T170320Z
CREATED:20240429T170320Z
LAST-MODIFIED:20240429T170320Z
UID:7928-1715072400-1715119200@marketingeda.com
SUMMARY:User2User Europe 2024
DESCRIPTION:User2User is the perfect opportunity to learn\, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. \nDedicated to end-users of Siemens EDA solutions\, this conference is free to attend and includes innovative keynotes from industry leaders\, enriching technical sessions as well as a chance to network with colleagues and peers. \nThe full programme includes papers on these topics\n\nDesign For Test & Embedded Analytics\nElectronic System Design/PCB Design analysis and manufacturing\nFunctional Design & Verification\nHardware Assisted Verification\nHigh Level Synthesis: Digital design in C++/SystemC\nCustom IC Verification\nIC Backend\nSemiconductor packaging design\, analysis and manufacturing\n\nKeynotes\nEnabling imagination – An integrated approach to system design – Mike Ellow \nMike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America. \nDelivering Silicon at Cloud Scale – Ronen Laviv \nRonen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel. \nTechnical breakouts\n\nIC Backend Track 1\n\nImproving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning\nSignoff with Calibre as platform independent application\nUtilizing Calibre Tools for Chipfinishing within a Markefile\n\n\nIC Backend Track 2\n\nPERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies\nMission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower\n\n\nCustom IC Verification\n\nSymphony Pro enablement in STMicroelectronics SmartPower Technologies\nHow AWS cloud compute helps scale custom IC verification workloads\nPLL Design and Simulation using the Advanced SPICE technology\nAccelerating verification of high frequency PLLs for Wireless Application in a Smarter World\n\n\nDesign for Test & Embedded Analytics\n\nAdvancing DFT with the Power of AI: Grand challenges
URL:https://marketingeda.com/event/user2user-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240507T080000
DTEND;TZID=America/Los_Angeles:20240508T170000
DTSTAMP:20240503T163652Z
CREATED:20240419T171240Z
LAST-MODIFIED:20240503T163652Z
UID:7877-1715068800-1715187600@marketingeda.com
SUMMARY:ChipEx 2024
DESCRIPTION:ChipEx2024\, the largest annual event of the Israeli semiconductor industry\, will be held on May 7-8\, 2024 in Tel Aviv\, Israel. ChipEx2024 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2024 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2024 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2024 exhibition will take place on May 7\, 2024 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2024 technical seminar will take place on May 7\, 2024 at the Tel-Aviv Expo Center. \nChipEx2024 Executive Summit \nThe Closing session of ChipEx2024 will take place on May 8\, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe. \nChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \nWe invite you to take part in ChipEx2024 as an exhibitor\, a speaker and/or as a sponsor.
URL:https://marketingeda.com/event/chipex-2024/
LOCATION:Tel Aviv Convention Center\, Rokach Boulevard 101\, Tel Aviv\, Israel
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T093000
DTEND;TZID=America/Los_Angeles:20240502T160000
DTSTAMP:20240424T162043Z
CREATED:20240424T162005Z
LAST-MODIFIED:20240424T162043Z
UID:7901-1714642200-1714665600@marketingeda.com
SUMMARY:Keysight EDA Connect Tour - Austin
DESCRIPTION:Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin\, TX and Burlington\, MA. \nSave the dates for our upcoming events in Austin\, TX on May 2 or Burlington\, MA on May 16\, where we’ll explore the future of AI in 6G to 3D Module integration. \nThese technical sessions promise to recharge your design productivity\, refresh your knowledge base\, and renew contacts with fellow design professionals. \nDon’t miss out on this opportunity to be at the forefront of innovation with Keysight. \nAs AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nLight breakfast and lunch will be provided. \nAgenda\n\n\n\n09:30\nCheck-in & Breakfast\n\n\n10:00\nWelcome – Keynote\n\n\n10:10\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs\n\n\n11:00\nRF System Design / New System Verification Tools in ADS for Circuit Designers\n\n\n12:00\nSolving 3D Module Integration Challenges for High-Performance Microwave Design (Integration is our differentiator)\n\n\n12:45\nRF Switch Design with Keysight ADS\n\n\n1:30-4:00\nLunch Break / Golf
URL:https://marketingeda.com/event/keysight-eda-connect-tour-austin/
LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T090000
DTEND;TZID=America/Los_Angeles:20240502T100000
DTSTAMP:20240422T161648Z
CREATED:20240422T161648Z
LAST-MODIFIED:20240422T161648Z
UID:7886-1714640400-1714644000@marketingeda.com
SUMMARY:Smart methods for DFT chip architecture & validation
DESCRIPTION:Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers\, including those for emulation and IC test\, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. \nThe Veloce hardware-assisted verification system can efficiently handle large\, full-chip GLE designs. Tessent Streaming Scan Network (SSN)\, a once-in-a-decade technology\, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN\, as well as other test functions such as TestKompress\, BIST pattern validation\, functional fault grading\, power profiling and estimation\, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success. \nTarget audience: \n\nDFT Engineers\nDFT Managers\nProduct and Test Engineers and Managers\n\nWhat you will learn: \n\nIntroduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns\nDFT Power Profiling and Fault grading using Veloce Power App\nApplying SSN to solve the Veloce chip design challenges\n\n\n\nSpeakers:\n\n\n\n\n\n\nRobert Serphillips\nProduct Manager\, Verification\, Siemens EDA\n\n\n\n\nRobert Serphillips has worked in the pre-silicon verification\, post-silicon validation\, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer\, automotive\, industrial\, military\, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit. \n\n\n\n\n\n\n\nRon Press\nSr. Director of Technology Enablement\, Tessent\, Siemens EDA – Tessent\n\n\n\n\nRon Press\, a 30-year veteran of the test and DFT industry\, is a member of the International Test Conference (ITC) Steering Committee\, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing\, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995.
URL:https://marketingeda.com/event/smart-methods-for-dft-chip-architecture-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T083000
DTEND;TZID=America/Los_Angeles:20240502T173000
DTSTAMP:20240415T181052Z
CREATED:20240415T181052Z
LAST-MODIFIED:20240415T181052Z
UID:7850-1714638600-1714671000@marketingeda.com
SUMMARY:TSMC 2024 Technology Workshop – Austin
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour
URL:https://marketingeda.com/event/tsmc-2024-technology-workshop-austin/
LOCATION:JW Marriott Austin\, 110 E 2nd St\, Austin\, TX\, United States
CATEGORIES:EDA,Foundry,IP,Semiconductor,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T060000
DTEND;TZID=America/Los_Angeles:20240430T070000
DTSTAMP:20240416T003939Z
CREATED:20240416T003939Z
LAST-MODIFIED:20240416T003939Z
UID:7858-1714456800-1714460400@marketingeda.com
SUMMARY:DFT for chiplets & 3D ICs using Tessent Multi-die
DESCRIPTION:3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1\, IEEE 1500\, IEEE 1687\, and IEEE 1838. \nWho should attend:\n\nAnyone planning to implement chiplets\, 2.5D/3D designs and would like to learn about design for test.\nDFT Engineers\nDFT Managers\nDesign Engineers\nTest Engineers\nProject Managers for ASIC/design\n\nWhat you will learn:\n\nHow Tessent Multi-die will aid in 3D IC design for test\nIntro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)\nHow in 2.5D device\, boundary scan-based interconnect test can be performed with Tessent Multi-die\n\n\n\nSpeaker:\n\n\n\n\n\n\nItamar Tsachi\nEurope DFT Manager\, Siemens EDA\n\n\n\n\nItamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics\, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom\, BrightCom technologies and Silicon Value\, where he began his chip design career in a variety of roles\, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.”
URL:https://marketingeda.com/event/dft-for-chiplets-3d-ics-using-tessent-multi-die/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T111500
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240411T001153Z
CREATED:20240411T001153Z
LAST-MODIFIED:20240411T001153Z
UID:7836-1714043700-1714064400@marketingeda.com
SUMMARY:Tech Summit: ASC Sunstone & Screaming Circuits
DESCRIPTION:Calling all PCB designers and engineers to join us for an exclusive Technical Summit and Casino Excursion for Designers & Engineers! \nThis summit is crafted to bring together PCB engineers and technical professionals for a day of immersive learning\, cutting-edge insights\, and many networking opportunities. \nJoin us to expand your knowledge\, establish invaluable connections\, and stay at the forefront of PCB innovation! Dive into the latest advancements\, share knowledge\, and forge meaningful connections within the PCB design and engineering community. \nOnce we have all had a chance to share and digest\, we will board a bus to Ilani Casino for some fun and entertainment! We’ll even have you back at a decent hour so you can be fresh for work on Friday. \n11:15 AM – 11:45 AM \nIntroduction/Box Lunch \nAnaya Vardya \nMatt Stevenson \n\nAnaya – CEO American Standar Circuits/Sunstone Circuits -CEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. Matt Stevenson – VP and General Mgr ASC Sunstone Circuits – has extensive experience in the PCB industry and has proven his skill and dedication to Sunstone by continuing to grow the company’s revenue and enhance the customer experience. \n11:45 AM – 12:30 PM \nBest Practices – PCB Design \nStephen Chavez \n\nSenior Product Marketing Manager – SME PCB Design\, MIT\, CID+\, CPCD – Chairman – Printed Circuit Engineering Association (PCEA) – Steph is a senior printed circuit engineer with three decades’ experience. He spent the past 12 years as a Principal Engineer and global subject matter expert of PCB design for Collins Aerospace (Raytheon Technologies). He is an IPC Certified Master Instructor Trainer (MIT) for PCB design\, an IPC Certified Advanced PCB Designer (CID+)\, and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA) where his focus is on the continuous improvement\, professional development\, and the evolution of the printed circuit engineer throughout the industry. An active IPC member since 2003\, he is currently involved in several subcommittees including specifications IPC-6012\, IPC-2221/2222. Chavez is recognized as an industry subject matter expert in PCB design by PCEA\, IPC\, and several leading industry publications. \n12:35 PM – 1:15 PM \nDFM/DFA\nMike Galloway \nMike Galloway has extensive experience in the electronics manufacturing industry\, specializing in prototype process development with a focus on Surface Mount Technology (SMT). With over 15 years at Screaming Circuits as a Senior Manufacturing Engineer\, he plays a crucial role in prototyping and providing short-run production support. Before joining Screaming Circuits\, Mike built his experience at various Contract Manufacturers (CMs) and Original Equipment Manufacturers (OEMs) as well as working with tooling firms serving the electronics industry. Mike’s expertise lies in optimizing manufacturing processes for prototypes\, particularly in the realm of SMT and scaling into production volumes. \n1:30 PM – 2:10 PM \nThermal Management\nAnaya Vardya \nCEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. He has over a decade of executive management experience in public companies manufacturing PWBs. In addition\, he writes about a variety of subjects but he us particularly focused on partnerships\, technology and manufacturing techniques. \n2:15 PM – 3:00 PM \nUltra HDI\nJohn Johnson \nDirector of Quality at American Standard Circuits – John has a long tenure in Material and Printed Circuit manufacturing. After obtaining an Masters of Science in Organic Chemistry from The Ohio State University\, he has held positions as an R&D Chemist\, Quality Engineer\, Sr. Process Engineer\, Quality Manager\, Sales Rep\, Director of Sales\, General Manager\, President/CEO. Prior to joining ASC as a Director of Business Development\, he was VP of Sales and Customer Support at Averatek Corp and focused on Ultra Fine Line technology. John currently serves as ASC’s Director of Quality and is ASC’s Technology Expert on Ultra High Density Interconnects. \n3:05 PM – 3:45 PM\nFlex/Rigid-Flex PCBs \nJoe Fjelstad \nFounder/President Verdant Electronics – is an international authority and innovator in the field of electronic interconnection and packaging technologies with more than 185 U.S. patents issued or pending. He is the author of Flexible Circuit Technology and author\, co-author or editor of several other books including Chip Scale Packaging for Modern Electronics. He has also authored numerous technical papers and articles. He frequently presents seminars on PCB\, flex circuit and chip scale packaging technologies at industry conferences. \n4:00 PM – 5:00 PM\nPanel Discussion \nOpen floor for Q & A with all speakers. Any questions not able to fit in can be emailed to marketing@sunstone.com. \n5:00 PM – 10:00 PM \nOptional Bus to Ilani Casino with Casino Bucks – Ridgefield Wa
URL:https://marketingeda.com/event/tech-summit-asc-sunstone-screaming-circuits/
LOCATION:Holiday Inn Portland – Columbia Riverfront\, 909 North Hayden Island Drive\, Portland\, OR\, 97217\, United States
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tech-Summit-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T110000
DTEND;TZID=America/New_York:20240425T120000
DTSTAMP:20240401T181039Z
CREATED:20240401T181039Z
LAST-MODIFIED:20240401T181039Z
UID:7800-1714042800-1714046400@marketingeda.com
SUMMARY:Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
DESCRIPTION:Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. \nJoin us on Thursday\, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. \nOverview\nAccurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation\, which can address various physical interactions and phenomena. By encompassing factors from contamination challenges to ensuring uniform product outcomes\, engineers can leverage such simulations to generate innovative ideas for optimized processes and cutting-edge solutions in semiconductor fabrication. \nThis webinar will demonstrate the practical application of Ansys tools in understanding the impact of various parameters on diverse wafer fabrication processes and fine-tuning them to improve yields and reduce wafer cycle time. \nWhat you will learn\n\nImportance of simulation in fabrication processes\nReduce wafer cycle time\nModel fabrication process with Ansys tools\nOptimize of fabrication processes\nSystem-level modeling of fabrication processes\n\nWho should attend\nEngineers and Engineering Managers/Directors\, Manufacturing teams\, Etch teams\, Deposition teams\, NPI teams and Aftermarket teams \nSpeaker\n\nNima Bohlooli\, Senior Application Engineer\, Ansys
URL:https://marketingeda.com/event/improving-semiconductor-wafer-fabrication-process-efficiencies-using-ansys-solutions/
CATEGORIES:EDA,Semiconductor,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/April-25-2024-Ansys.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T090000
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240423T003845Z
CREATED:20240423T003845Z
LAST-MODIFIED:20240423T003845Z
UID:7893-1714035600-1714064400@marketingeda.com
SUMMARY:Siemens User2User Verification Forum 2024 India
DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST.
URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india-2/
LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
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END:VCALENDAR