BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.0//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240410T100000
DTEND;TZID=America/Los_Angeles:20240410T110000
DTSTAMP:20240221T221535Z
CREATED:20240221T221535Z
LAST-MODIFIED:20240221T221535Z
UID:7677-1712743200-1712746800@marketingeda.com
SUMMARY:Virtuoso - Finding Hidden Treasures to Accelerate Routing Your Layout
DESCRIPTION:Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand\, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand\, you need to guide the connections carefully while weaving your own creative magic – too tough to tell the auto-router the exact constraints. With the assisted routing features in your familiar layout editor in Virtuoso Studio\, you have the Swiss army knife to finish your routing tasks more than 10X faster. Finish more work in the same amount of time or regain your work-life balance with the assisted routing functionality. \nThis webinar takes you on a treasure hunt to find the hidden gems – some you already had but didn’t know\, and some that are part of Virtuoso Studio. Strap your seat belts and learn about: \n\nHow simulation-driven routing goes a step ahead than the create-verify-fix paradigm\nReplicate complicated yet similar bus structures with more than just a simple shape copy\n Fast interactive routing with auto twigs feature\nOptimal routing widths in advanced node with WSP compliance\, wire stranding and wire stacking\nAuto Via Assistant\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-finding-hidden-treasures-to-accelerate-routing-your-layout/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240409T080000
DTEND;TZID=Europe/Berlin:20240411T170000
DTSTAMP:20240403T194345Z
CREATED:20240119T022657Z
LAST-MODIFIED:20240403T194345Z
UID:7529-1712649600-1712854800@marketingeda.com
SUMMARY:Embedded World 2024
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nKnowledge platform #ew24\nKnow-how at the highest level\nAt the embedded world Conference and the electronic displays Conference\, top-class speakers from research\, development and practice will share their knowledge with you. They discuss the state of the art and possible future developments in the industry. The exhibitor’s forums and top-class discussion panels in the halls also contribute to the high-quality transfer of knowledge. Current topics will be highlighted in numerous expert lectures and panels. And\, of course\, there will be opportunities for intensive technical discussions. \nGuided tours\, tours for trainees and students and special presentations as well as the networking event for women in the embedded systems industry #women4ew complete the offer. \nThe No. 1 hub for the international embedded community\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts!
URL:https://marketingeda.com/event/embedded-world-2024/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-World-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T170000
DTSTAMP:20240401T175124Z
CREATED:20240401T175124Z
LAST-MODIFIED:20240401T175124Z
UID:7794-1712649600-1712682000@marketingeda.com
SUMMARY:Ansys 2024 R1: High Frequency Electronics What’s New
DESCRIPTION:Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF\, automotive\, A&D\, and consumer electronics designs that our subject matter experts will discuss. \n\n\nOverview\nThis Ansys 2024 R1 webinar will review the high-frequency electronics tool updates\, enhancements\, and new features – HFSS\, Q3D\, SIwave\, and NuHertz. Engineers developing PCBs\, antennas\, and other RF capabilities for telecommunications\, HPC\, automotive\, A&D\, and IoT applications will find many new capabilities and improvements in this update. \nWhat you will learn\n\nEncrypted technology file support in HFSS 3D Layout IC Mode\nEnhanced support for FlexPCB in HFSS 3D\nHFSS Finite Array metadata export and mask automation\nIcepak Thermal Mesh Fusion\nSolver enhancements for SIwave and Q3D\nImprovements to HPC/Distributed Computing support for all products\n\nWho should attend and why\nEngineers involved in new product development for any electronics market \nSpeaker\n\nJuliano Mologni\n\n\n\n\n\nJuliano Mologni is a Lead Product Manager in the Electronics Business Unit at Ansys\, responsible for all HF electronics products. He has over 20 years of experience in computational electromagnetics and is the author of multiple patents and more than 60 journal and conference papers. Juliano is involved in many RF and EMC projects with top automotive\, A&D\, appliances\, and high tech companies. He holds a BSc degree in telecommunication engineering and an MSc in microelectronics and has authored a PhD thesis on automotive EMC and signal integrity.
URL:https://marketingeda.com/event/ansys-2024-r1-high-frequency-electronics-whats-new/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T090000
DTSTAMP:20240402T170530Z
CREATED:20240402T170530Z
LAST-MODIFIED:20240402T170530Z
UID:7803-1712649600-1712653200@marketingeda.com
SUMMARY:Guiding your aerospace electrical journey
DESCRIPTION:Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile\, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly\, cost-effectively and efficiently has become a central focus of manufacturers. \nSiemens has the solutions and partnerships to guide the development of best-in-class solutions to these problems. This session will highlight how Capital plays a part in these solutions. \nMeet the speaker\n\n\n\n\n\n\nSIEMENS IES\nChad Holley\nTechnical Product Manager \n\nChad Holley is a Technical Product Manager in IES supporting our Connectivity offerings. He has been working for Siemens for over 8 years and has supported many customers in their Capital deployments. Prior to Siemens\, Chad has held varying positions in wiring and systems design in both the automotive and aerospace and defense industries. Chad is a veteran of the United States Navy as an electrician and holds a bachelor’s degree in Electrical Engineering from Michigan State University.
URL:https://marketingeda.com/event/guiding-your-aerospace-electrical-journey/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T110000
DTEND;TZID=America/Los_Angeles:20240404T120000
DTSTAMP:20240311T212213Z
CREATED:20240311T212000Z
LAST-MODIFIED:20240311T212213Z
UID:7730-1712228400-1712232000@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Libero and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \n  \nAbstract: \nIn the concluding part of this three-part webinar series\, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints\, Xtrace\, Drivers/Readers and Advanced Dataflow. \nAgenda\n\nWorkflow with Libero SoC and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Design Profiler\nBreakpoints\, Xtrace and Advanced Dataflow\, Drivers and Readers\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-libero-and-active-hdl/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240318T163105Z
CREATED:20240318T163105Z
LAST-MODIFIED:20240318T163105Z
UID:7740-1712224800-1712228400@marketingeda.com
SUMMARY:Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
DESCRIPTION:Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy\, identification\, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone task. \nLearn how the Cadence EMX Planar 3D Solver black-box flow lets you specify hierarchical layout cells to be excluded from the EM analysis\, saving design time and eliminating errors. Automate the flow and integrate with Virtuoso ADE Suite and Spectre Simulation platforms for more control during circuit analysis. \nLearn through real-life circuit examples how to achieve: \n\nFaster design cycles: Streamline your analysis process and free up time for innovation.\nReduced errors and rework: Eliminate manual tasks and minimize the risk of mistakes.\nEnhanced confidence in your designs: Gain superior control over signal integrity for optimal performance.
URL:https://marketingeda.com/event/hierarchical-analysis-of-em-crosstalk-with-emx-planar-3d-solver/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240221T221413Z
CREATED:20240221T221413Z
LAST-MODIFIED:20240221T221413Z
UID:7675-1712224800-1712228400@marketingeda.com
SUMMARY:Maximizing the Benefits of Virtuoso Layout Suite XL
DESCRIPTION:Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio\, launched in 2023\, with new features that empower you to achieve tasks much faster. In this webinar\, you will learn about: \n\nNew features such as Schematic Assistant\, Incremental Check Against Source\nWhether Group Array can solve your historical problem of mosaics conflicting with Virtuoso Layout Suite XL\nStreamlining the daunting task of managing the sanctity of review process using the design review feature in Virtuoso Studio\nPerformance improvements you will gain if you switch to Virtuoso Studio\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/maximizing-the-benefits-of-virtuoso-layout-suite-xl/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240403T080000
DTEND;TZID=America/Los_Angeles:20240405T170000
DTSTAMP:20240326T185839Z
CREATED:20230918T162548Z
LAST-MODIFIED:20240326T185839Z
UID:6808-1712131200-1712336400@marketingeda.com
SUMMARY:ISQED Symposium 2024
DESCRIPTION:A pioneer and leading interdisciplinary conference\, the 25thInternational Symposium on Quality Electronic Design (ISQED’24) accepts and promotes original and unpublished papers related to the topics shown below. \nISQED’24 theme is AI/ML& Electronic Design\, Hardware Security\, Quantum Computing\, 3D Integration\, and IoT. Authors are invited to submit papers in following topics (please visit the website for detail list of all tracks and subjects): \n\nHardware and System Security\nElectronic Design Automation Tools and Methodologies\nDesign for Test and Verification\nEmerging Device and Process Technologies and Applications\nCircuit Design\, 3D Integration and Advanced Packaging\nSystem-level Design and Methodologies\nCognitive Computing Hardware\n\nThis must-attend conference starts on Wednesday April 3\, and continues until the early afternoon of Friday April 5. The program includes keynote speeches\, embedded tutorials\, invited talks\, panel discussion\, and many peer-reviewed technical presentations. \nKeynote Speakers\n\nCross-Layer Optimization of Energy Harvesting and Storage\nDr. Naehyuck Chang\nExecutive Vice President\, Samsung SDI America\nWhy we did not have flying cars for 100 years\nJim Dukhovny\nCEO\, Alef Aeronautics\nReflections on Microelectronic and Microelectromechanical Technologies and the Challenges of Implementing Emerging Technologies\nClare D. Thiem\nAir Force Research Laboratory/RITB\n\nEmbedded Tutorials\n\nAdvanced Packaging for Heterogenous Integration\nDr. Tolga Acikalin\nIntel Labs\nSecuring Ubiquitous Devices with Lightweight Circuit Primitives\nProf. Kaiyuan Yang\nRice University\n\nPanel Discussion\n\nAI Hardware: Opportunities and Challenges\n\nTechnical Sessions\nTechnical program consists of over 20 technical sessions featuring over 100 peer-reviewed and invited technical presentations on various challenging topics related to AI/ML & Electronic Design\, Security\, IoT\, Quantum Computing\, etc. See the ISQED 2024 program for details. \nISQED Awards\nISQED best paper award ceremony will be held during plenary session on the morning of Wednesday April 3.
URL:https://marketingeda.com/event/isqed-symposium-2024/
LOCATION:Seven Hills Conference Center\, 800 Font Blvd\, San Francisco\, CA\, 94132\, United States
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISQED-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240403T080000
DTEND;TZID=America/Los_Angeles:20240404T170000
DTSTAMP:20240212T202640Z
CREATED:20240212T202640Z
LAST-MODIFIED:20240212T202640Z
UID:7607-1712131200-1712250000@marketingeda.com
SUMMARY:Siemens EDA User2User Conference
DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive!
URL:https://marketingeda.com/event/siemens-eda-user2user-conference/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240402T100000
DTEND;TZID=America/Los_Angeles:20240402T110000
DTSTAMP:20240327T160224Z
CREATED:20240327T160224Z
LAST-MODIFIED:20240327T160224Z
UID:7768-1712052000-1712055600@marketingeda.com
SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power
DESCRIPTION:*Work email required for registration*  \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp.  \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS  \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS*
URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T110000
DTEND;TZID=America/Los_Angeles:20240328T120000
DTSTAMP:20240311T211521Z
CREATED:20240311T211521Z
LAST-MODIFIED:20240311T211521Z
UID:7727-1711623600-1711627200@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Quartus and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part two of this three-part webinar series\, we will show how to simulate an Altera design example. We will generate a design example from Quartus and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show how you to do a post-simulation debug using Waveform Viewer\, Hierarchy\, Object and Watch windows. \n\nAgenda\n\nWorkflow with Quartus and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nPost-simulation debugging with Waveform Viewer\, Hierarchy and Watch window\nLive demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-quartus-and-active-hdl/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Akdec-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T100000
DTEND;TZID=America/Los_Angeles:20240328T110000
DTSTAMP:20240322T224737Z
CREATED:20240322T224737Z
LAST-MODIFIED:20240322T224737Z
UID:7753-1711620000-1711623600@marketingeda.com
SUMMARY:Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
DESCRIPTION:Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices\nDuring SiC device switching operations\, it is possible that devices could be reaching abnormal overload conditions\, which is why some applications require “robustness” specifications (e.g.\, Short Circuit and UIS tests). Such overload phenomena can be simulated by mixed-mode circuits and an accurate tuning of simulation parameters\, thanks to simulation/experiment information exchange. This allows us to predict electrothermal behavior during a dynamic phase. As an example\, we report here a study of short circuit phenomenon. The impact of a short circuit of a defect localized in active area has been investigated by means of TCAD simulations performed with Silvaco software. Different cases have been studied in which the defect dot was localized at flat interface body/drain\, at SiC/oxide interface in the channel region\, and at curved interface body/drain. A sensitivity with position has also been performed. \nWhat You Will Learn\n\nWide bandgap (WBG) technologies and key features of SiC\nSiC MOSFET switching operation and ruggedness\nTCAD simulations and device reliability\nShort circuit: Impact of surface defect dot\n\n\n\n\n\n\nPresenter\n\n\n\n\nSalvatore Cascino\, SiC R&D Engineer\, ST Microelectronics \nSalvatore Cascino was born in Palermo (Italy) in 1970. He obtained a Degree in Physics from the University of Palermo. He was involved at ENEA (Frascati – Rome) with Nuclear Fusion Department (FTU project) and with the Fusion Research group in Padua (RFX project). He is currently at STMicroelectronics (Catania) with the R&D Group and his current research interest is aimed to technology development for Silicon Carbide devices. In the past he worked on development of devices for sensing applications and radiofrequency\, too. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/analyze-the-impact-of-surface-defect-dot-on-short-circuit-phenomena-in-sic-devices/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240327T100000
DTEND;TZID=America/Los_Angeles:20240327T110000
DTSTAMP:20240306T173441Z
CREATED:20240306T173441Z
LAST-MODIFIED:20240306T173441Z
UID:7713-1711533600-1711537200@marketingeda.com
SUMMARY:Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
DESCRIPTION:Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up\, reset operation\, timing\, multi-cycle paths\, and power estimation. However\, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the equivalent RTL simulations. Additionally\, GLS bring-up and debug is slow and manual. In GLS\, engineers spend time cleaning up sources of unknowns (Xs).  Xs can be caused by uninitialized inputs\, registers\, and simulation artifacts such as X-pessimism. Ad-hoc methods to handle Xs in GLS could mask problems. \nThis webinar will describe a reliable formal-based method to manage Xs in GLS.  It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator. \nWhat You Will Learn:  \n\nX mitigation techniques to use in RTL\nHow to eliminate X-pessimism in GLS for a streamlined bring-up\nGenerate fixes for unknowns in a fraction of time compared to manual debug\nThe SimXACT workflow\n\nWho Should Attend:  \n\nDesigners and Design Verification engineers\nDesign Managers and Directors responsible for project tapeout schedule\n\nWhat/Which Products are Covered:   \n\nSiemens Avery SimXACT\nQuesta simulation\n\n\n\nSpeakers:\n\n\n\n\n\n\nRick Koster\nLow Power Specialist\, Siemens EDA\n\n\n\n\nRick Koster is the North America Low Power Specialist for verification tools at Siemens EDA.  Rick started his career at Texas Instruments and has held engineering positions at the US Army\, Bytex Corporation.  For more than 25 years\, Rick has worked in verification at Siemens EDA through Mentor Graphics and Ikos Systems. \n\n\n\n\n\n\n\nKai-hui Chang\nSiemens EDA\n\n\n\n\nKai-hui Chang is the architect of the SimXACT tool. He has been with Avery Design Systems for 20 years and recently joined Siemens through the Avery acquisition. His work focuses on simulation technologies and formal verification. He has a Ph. D. in computer science and engineering from the University of Michigan\, Ann Arbor.
URL:https://marketingeda.com/event/reduce-gate-level-simulation-bring-up-time-with-semi-formal-x-verification/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-27-202.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T110000
DTEND;TZID=America/Los_Angeles:20240321T120000
DTSTAMP:20240311T211030Z
CREATED:20240311T211030Z
LAST-MODIFIED:20240311T211030Z
UID:7724-1711018800-1711022400@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Vivado and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part one of this three-part webinar series\, we will show you how to simulate an AMD example design. We will generate a design example from Vivado and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show you advanced debugging capabilities using our advanced waveform viewer. We will also turn on code coverage and analyze the results in html format. \n\nAgenda\n\nWorkflow with Vivado and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nAdvanced Debugging with Waveform Viewer\nCode Coverage\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-vivado-and-active-hdl/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T153000
DTSTAMP:20240222T182630Z
CREATED:20240222T182630Z
LAST-MODIFIED:20240222T182630Z
UID:7686-1711015200-1711035000@marketingeda.com
SUMMARY:AI-Powered Electromagnetics Symposium
DESCRIPTION:Accelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization \nHow are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such as electromagnetic interference (EMI)\, electromagnetic compatibility (EMC)\, power integrity\, and signal integrity play? \nDiscover how Cadence is transforming electromagnetic (EM) simulation for optimal design performance with innovative\, AI-driven multiphysics optimization software and breakthrough 3D EM analysis. \nJoin our CadenceCONNECT: AI-Powered EM Symposium\, where industry experts\, including Cadence\, Meta\, Microsoft\, and more\, will share insights highlighting how the Cadence Clarity 3D Solver and Optimality Intelligent Explorer workflow streamlines design results in optimized electronic product designs. \n\n\n\n\n\n\n\n\n\n\n\n\nAgenda \n10:00am – 10:30am               Registration | Light Breakfast \n10:30am – 12:00pm               Morning Sessions \n12:00pm – 1:00pm                 Lunch | Live Demonstrations \n1:00pm – 2:30pm                   Afternoon Sessions \n2:30pm – 3:30pm                   Networking Event | Live Demonstrations
URL:https://marketingeda.com/event/ai-powered-electromagnetics-symposium/
LOCATION:Cadence Design Systems\, Building 5\, 2655 Seely Avenue\, San Jose\, CA\, 95131\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T110000
DTSTAMP:20240229T180535Z
CREATED:20240229T180535Z
LAST-MODIFIED:20240229T180535Z
UID:7696-1711015200-1711018800@marketingeda.com
SUMMARY:Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
DESCRIPTION:With the growing complexities of 3D-ICs\, chiplets\, advanced packaging\, and high-performance boards\, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently\, providing confidence in system signoff. \nJoin our webinar as we present the new Cadence Celsius Studio the industry’s first complete thermal platform for electronic systems developed specifically to address thermal analysis\, thermal stress\, and electronics cooling design issues. This solution provides accurate system-level thermal analysis by combining finite element method (FEM) with computational fluid dynamics (CFD) technologies for full-system thermal analysis from chip to packaging to board through to the end-system product. \nAttendees will learn: \n\nHow Celsius Studio provides AI-enabled thermal analysis for electro-mechanical systems design\nHow the convergence of FEM and CFD engines addresses thermal challenges spanning from the chip to the packaging and out to the board and end system
URL:https://marketingeda.com/event/shift-left-thermal-analysis-with-ai-enabled-celsius-studio-platform/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240320T080000
DTEND;TZID=America/Los_Angeles:20240321T170000
DTSTAMP:20240305T220415Z
CREATED:20240305T220415Z
LAST-MODIFIED:20240305T220415Z
UID:7710-1710921600-1711040400@marketingeda.com
SUMMARY:SNUG Silicon Valley 2024
DESCRIPTION:Connecting the Synopsys User Community\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nTechnical Committee\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. \nTechnical Committee Chair: \nDon Mills\, Microchip \nCommittee Members: \nAnand Iyer\, Synopsys \nAndy Copperhall\, Independent \nAnwarul Hasan\, Independent \nBrian Kane\, Northrop Grumman \nBryan Morris\, Ciena \nChris Kiegle\, Marvell Semiconductor \nCliff Cummings\, Paradigm Works \nFirouzeh Nourkhalaj\, Synopsys \nGlen McDonnell\, Broadcom \nHongda Lu\, SARC \nJack Dong\, Intel \nJason Rziha\, Microchip \nJeff Montesano\, Meta \nJing Zhang\, Intel \nJohn Thomson\, NVIDIA \nJohn Wei\, Independent \nJon Colburn\, NVIDIA \nJT Longino\, Tesla \nKarthik Rajan\, Microchip \nLeah Clark\, Synopsys \nMark Sprague\, Intel \nNaveen Mysore\, Intel \nNeel Sonara\, Broadcom \nNitin Navale\, AMD \nOlivia Poon\, Marvell Semiconductor \nPinal Patel\, eInfochips \nRavikishore Gandikota\, NVIDIA \nRonald Goodstein\, Lockheed Martin \nRonald Kalim\, Intel \nSachin Parikh\, Broadcom \nSangeetha Chandran Sarala\, Micron \nSathappan Palaniappan\, Broadcom \nSaurabh Bhadoriya\, NVIDIA \nSavita Banerjee\, Meta \nShaiful Alam\, Intel \nStella Matarrese\, Synopsys \nTom Mahatdejkul\, Arm \nTony Todesco\, AMD \nUpasna Vishnoi\, Marvell Semiconductor \nVictoria Kolesov\, Intel \nZafar Hasan\, NVIDIA
URL:https://marketingeda.com/event/snug-silicon-valley-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNG-Silicon-Valley-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240319T130000
DTEND;TZID=Europe/London:20240319T140000
DTSTAMP:20240410T161048Z
CREATED:20240216T190810Z
LAST-MODIFIED:20240410T161048Z
UID:7624-1710853200-1710856800@marketingeda.com
SUMMARY:DVClub Europe: Latest VHDL Verification Techniques
DESCRIPTION:This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM \nAgenda (GMT) \n13:00   Welcome and Introduction – Mike Bartley\, Tessolve \n13:00   Epsen Tallaksen\, EmLogic – Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) \n13:30   Jim Lewis\, SynthWorks – OSVVM in a NutShell\, VHDL’s #1 Verification Methodology \n14:00    Close \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe webpage for this event. \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: Agnisys\, Cadence\, Breker Verification System\, Synopsys
URL:https://marketingeda.com/event/dvclub-europe-latest-vhdl-verification-techniques/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-19-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240319T100000
DTEND;TZID=America/Los_Angeles:20240319T110000
DTSTAMP:20240221T221244Z
CREATED:20240221T221244Z
LAST-MODIFIED:20240221T221244Z
UID:7673-1710842400-1710846000@marketingeda.com
SUMMARY:Virtuoso - Save on Signoff Effort with In-Design DRC and Fill
DESCRIPTION:Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However\, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes at a cost – time and money. Not anymore. With iPegasus Verification System for Virtuoso Studio\, you can get signoff-quality physical verification within the Virtuoso Layout Suite. This webinar will teach you how: \n\nyou can avoid late surprises during signoff and save your efforts using iPegasus system for Virtuoso Studio\nthe new unified toolbar and settings simplifies your design checks with signoff quality\nthe enhanced Annotation Browser gives you an integrated solution for reviewing and fixing errors\nflexible run scope helps you in DRC fixing without losing focus\n\nMetal fill is an important step in the layout creation process that has gained significance in recent times. Crucial analog portions of the IP need careful handling with symmetry and non-minimum spacing to ensure that metal fills do not degrade circuit performance. iPegasus fill for Virtuoso Studio elevates the user experience by bringing metal fill using signoff rule decks closer to the layout. Natively integrated into Virtuoso Studio\, iPegasus fill provides control\, accuracy\, and performance benefits over running a standalone loosely tied-up flow. \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-save-on-signoff-effort-with-in-design-drc-and-fill/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240318T080000
DTEND;TZID=America/Los_Angeles:20240321T170000
DTSTAMP:20240206T194409Z
CREATED:20240206T192804Z
LAST-MODIFIED:20240206T194409Z
UID:7584-1710748800-1711040400@marketingeda.com
SUMMARY:GOMACTech 2024
DESCRIPTION:GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews.
URL:https://marketingeda.com/event/gomactech-2024/
LOCATION:Embassy Suites by Hilton\, Charleston Convention Center\, Charleston\, SC\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240314T080000
DTEND;TZID=America/Los_Angeles:20240314T090000
DTSTAMP:20240222T181810Z
CREATED:20240222T181810Z
LAST-MODIFIED:20240222T181810Z
UID:7683-1710403200-1710406800@marketingeda.com
SUMMARY:New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
DESCRIPTION:Designers increasingly use complex reset signaling architectures to meet high-performance\, low-latency\, and low-power requirements. Specifically\, independent reset domains are created by complex reset sequences\, reset circuitry\, and the intermixing of IPs with different reset schemas\, power-management domains\, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that are straining “gen one” RDC solutions.\n‌\nIn this webinar we will show new\, advanced RDC techniques\, methodology\, and automation for:\n‌ \n\nHow to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows\nAI/ML-based automation that pinpoints where to place synchronizers\, and in parallel to aggressively minimize false positives (e.g. automatically minimizing “noise”)\nCreating custom synchronizers for proprietary synchronization styles\nWaiver management flows to efficiently address violations and waiver tracking throughout the project\nConsiderations for low power designs with UPF\n\n‌\nWhat you will learn: \nA short review of the basics of Clock and Reset Domain Crossing issues that may cause meta-stability\, glitch or data coherency.\nWhat’s the right methodology for a comprehensive RDC analysis?\nQuesta RDC solutions \nWho should attend: \nDesign Engineers\, CAD Engineers\, Project Leads who are using/supporting static verification flows.\nWorking knowledge of Verilog\, SystemVerilog\, or VHDL will presumed. \nSpeaker:\n\n\n\n\n\n\nAtul Sharma\nLead Product Engineer\, Siemens EDA\n\n\n\n\nAtul Sharma is Lead Product Engineer for Questa Static and Formal Solutions in Design Verification Technology Division of Siemens Electronic Design Automation (EDA) and is primarily responsible for CDC\, RDC\, SignOff CDC and Lint products. Atul has 16 years of experience in design and verification\, design methodologies\, technical marketing and applications engineering. Prior to Siemens EDA\, Atul has held design verification role for a design company\, and Product expert role in an EDA company\, for multiple products covering different aspects of static and functional verification. \nWith 16 years of total experience\, he has spent over a decade in customer facing role to solve Static Verification issues (CDC\, RDC\, Lint\, DFT\, Power Estimation/Reduction & Power Verification) and to create customer methodologies\, use models for multiple EDA products.
URL:https://marketingeda.com/event/new-advanced-techniques-for-reset-domain-crossing-rdc-analysis/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240313T080000
DTEND;TZID=Europe/London:20240314T170000
DTSTAMP:20240122T194453Z
CREATED:20240122T194453Z
LAST-MODIFIED:20240122T194453Z
UID:7549-1710316800-1710435600@marketingeda.com
SUMMARY:GSA International Semiconductor Conference
DESCRIPTION:Inaugural GSA event in partnership with the UK Government.  \nMeet senior business leaders\, investors\, and public policy officials from around the world. \nAcross two days\, join us for exciting discussions on semiconductor innovation for a NetZero economy\, with a view on the dramatically changing supply chain\, government interventions and industry outlook. \n  \nSemiconductor Innovation for NetZero (March 13-14) \n\nSupply Chain Resilience and national approaches to Semiconductor Policy\nDifferent government approaches to semiconductor policy\, supply chains and stimulating industry growth\nResource and talent development\, including raising the role of women in the industry\nCapital funding and IP strategies for start-ups and scale-ups\n\nWLI EMEA Kick-Off Event (March 13 morning) \n\nThe first GSA Women Leadership Initiative in Europe\nDiscuss the raising role of women in semiconductors\nHear lessons learned from women who have excelled in navigating a traditionally male-dominated industry\n\n\nTicket will cover both days\, all sections\nVIP Dinner will be held on the evening of March 13th: a separate ticket is required\, very limited seating available!
URL:https://marketingeda.com/event/gsa-international-semiconductor-conference/
LOCATION:Here East\, 14 E Bay Lane\, London\, United Kingdom
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-March-13-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240312T100000
DTEND;TZID=America/Los_Angeles:20240312T110000
DTSTAMP:20240221T220803Z
CREATED:20240221T220803Z
LAST-MODIFIED:20240221T220803Z
UID:7670-1710237600-1710241200@marketingeda.com
SUMMARY:What’s New About Virtuoso Layout Suite?
DESCRIPTION:Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio\n\n\n\nHow can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation engines in Virtuoso Studio\, device-level layout\, standard cells and blocks\, chip assembly\, and memory can automatically be designed from the same interface using the right tool underneath for the right job. \nBy including an intuitive spreadsheet-style constraint management interface\, pre-routing checkers\, and support for custom routing constraints\, all layout users will find APR technology easy to use\, not just the expert ones. In this webinar\, we will showcase the following flows: \n\nCustom device-level APR for advanced node\nStandard cell APR for custom digital designs leveraging seamless integration of Innovus Implementation System’s GigaPlace placement engine and NanoRoute routing engine\nChip assembly and specialty routing for mature nodes\n\nAutomating the placement and routing of custom and analog designs with thousands of nets lets you finish the layout in minutes! \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/whats-new-about-virtuoso-layout-suite/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T100000
DTEND;TZID=America/Los_Angeles:20240307T110000
DTSTAMP:20240216T204434Z
CREATED:20240216T204434Z
LAST-MODIFIED:20240216T204434Z
UID:7634-1709805600-1709809200@marketingeda.com
SUMMARY:Efficient Design Methodology for 112G Interface Compliance
DESCRIPTION:As 112G+ data transfer becomes the new normal\, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition\, with the precision required to meet 112G compliance\, companies can take extra steps to avoid design re-spins. \n\nThis webinar will: \n\nHighlight the workflow required to overcome the new challenges associated with 112G\nHow Cadence integrated design and analysis technology provides a unique and powerful solution
URL:https://marketingeda.com/event/efficient-design-methodology-for-112g-interface-compliance/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T090000
DTEND;TZID=America/Los_Angeles:20240307T100000
DTSTAMP:20240226T233450Z
CREATED:20240226T233450Z
LAST-MODIFIED:20240226T233450Z
UID:7690-1709802000-1709805600@marketingeda.com
SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure
DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.
URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240306T100000
DTEND;TZID=Europe/London:20240306T190000
DTSTAMP:20240219T174522Z
CREATED:20240219T174522Z
LAST-MODIFIED:20240219T174522Z
UID:7641-1709719200-1709751600@marketingeda.com
SUMMARY:Agile Analog Technology Showcase Event
DESCRIPTION:Learn how innovative analog IP can help analog design engineers. \nAgile Analog is transforming the analog IP industry\, with Composa\, our configurable\, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion\, Power Management\, IC Monitoring\, Security and Always-On IPs. Applications include High Performance Computing (HPC)\, IoT\, AI\, automotive and aerospace. \nAnalog IP the way you want it\nWorking with customers across the world on a broad range of technologies\, we partner with all the major foundries. Our customizable\, digitally wrapped and verified solutions can be seamlessly integrated into any SoC\, helping chip designers by significantly reducing complexity\, time and costs. \nTechnology Deep Dive Day\nWe are coming to Scotland to showcase our cutting-edge analog IP technology and expanding product portfolio to electronics engineers in the region\, and to explain how we can simplify analog design and accelerate the integration process.\n‍\nThis event will be an informal and relaxed environment for you to discover how we are revolutionizing the world of analog IP. It’s the ideal opportunity to: \nSee a demo of our Composa technology\nDelve deeper into the finer technical details\nChat with some of our team face-to-face\nEvent Time:\nMorning Session:\n10.00-12.00: Demo & Discussions\n12.00-14.00: Networking Lunch \nAfternoon Session:\n15.00-17.00: Demo & Discussions\n17.00-19.00: Networking Drinks \nEvent Venue:\nThe Royal Society of Edinburgh\nScott Room\,\n22-26 George St\,\nEdinburgh. EH2 2PQ.
URL:https://marketingeda.com/event/agile-analog-technology-showcase-event/
LOCATION:The Royal Society of Edinburgh\, 22-26 George Street\, Edinburgh\, EH2 2PQ\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agile-Analog-6-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240304T080000
DTEND;TZID=America/Los_Angeles:20240307T170000
DTSTAMP:20240216T181350Z
CREATED:20240103T171927Z
LAST-MODIFIED:20240216T181350Z
UID:7493-1709539200-1709830800@marketingeda.com
SUMMARY:DVCon USA 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.
URL:https://marketingeda.com/event/dvcon-usa-2024/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240229T100000
DTEND;TZID=America/Chicago:20240229T110000
DTSTAMP:20240208T174710Z
CREATED:20240208T174710Z
LAST-MODIFIED:20240208T174710Z
UID:7596-1709200800-1709204400@marketingeda.com
SUMMARY:Manufacturing driven design - DFM within an Xpedition Flow
DESCRIPTION:We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years\, many OEMs have implemented DFM as a final check in their release process\, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate back to the designer for resolution. \n‌ \nJoin PCB Design experts for a live discussion and demonstration of the recommended PCB design best practice of identifying and resolving DFM issues at the earliest possible stage in the PCB design process. They will showcase how Xpedition DFM\, an integrated solution that operates right within the Xpedition environment\, provides designers with specific DFM analysis that can be performed at the appropriate design stage. This ensures your design is optimized for manufacturing before proceeding to the next stage of design. This greatly reduces the bottlenecks common with post-layout DFM. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on February 29th\, 2024. 
URL:https://marketingeda.com/event/manufacturing-driven-design-dfm-within-an-xpedition-flow/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240229T093000
DTEND;TZID=America/Los_Angeles:20240229T150000
DTSTAMP:20240220T012904Z
CREATED:20240220T012758Z
LAST-MODIFIED:20240220T012904Z
UID:7650-1709199000-1709218800@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara - RF Day
DESCRIPTION:Shift Left with the Modern Design Center\n\n\nArtificial intelligence (AI) is redefining communication and connectivity. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, RF designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\n\nLearn and experience modern RF circuit and system design\, including electromagnetic-circuit co-simulation and AI / ML in simulation.\nGain practical insights from case studies presented by local customers.\nConnect with peers and technical experts in the heart of Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nRF Design Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome / Keynote\n\n\n10:10 – 11:00\nRF System design\n\n\n11:00 – 11:45\nNew System Verification Tools in ADS for Circuit Designers\n\n\n11:45 – 12:30\nSolving 3D Module Integration Challenges for High-Performance Microwave Design\n\n\n12:30 – 1:15\nLunch Break – Keysight Design Data and IP Management\n\n\n1:15 – 2:00\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n2:00 – 2:45\nExpanding Robust\, High-Yield Design Techniques from Circuit to EM\n\n\n2:45 – 3:00\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-rf-day/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240228T093000
DTEND;TZID=America/Los_Angeles:20240228T151500
DTSTAMP:20240220T012253Z
CREATED:20240220T012253Z
LAST-MODIFIED:20240220T012253Z
UID:7646-1709112600-1709133300@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara – High Speed Digital
DESCRIPTION:Shift Left with the Modern Design Center\n\nArtificial intelligence (AI) is redefining high-speed digital designs. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, digital designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\nLearn and experience advanced digital design solutions\, including die-to-die simulation for chiplets\, SerDes and memory design for AI/ML\, and more.\n\n\nGain practical insights from case studies presented by local customers.\n\n\nConnect with peers and technical experts at the heart of the Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nHigh Speed Digital Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome/Keynote\n\n\n10:10 – 10:45\nChiplet PHY Designer- Analyze D2D to D2D\n\n\n10:45 – 11:30\nAdvances in memory and SerDes applications\n\n\n11:30 – 12:30\nSimulation-driven compliance solutions for PCIe and USB standards\n\n\n12:30 – 1:30\nLunch Break – Keysight Design Data and IP Management\n\n\n1:30 – 2:15\nEM modeling of high-speed interconnects using SIPro\n\n\n2:15 – 3:00\nEnd-to-End Power Integrity Simulations with Digital Twin EM Models\n\n\n3:00 – 3:15\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-high-speed-digital/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
END:VCALENDAR