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DTSTART;TZID=America/Los_Angeles:20240327T100000
DTEND;TZID=America/Los_Angeles:20240327T110000
DTSTAMP:20240306T173441Z
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LAST-MODIFIED:20240306T173441Z
UID:7713-1711533600-1711537200@marketingeda.com
SUMMARY:Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
DESCRIPTION:Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up\, reset operation\, timing\, multi-cycle paths\, and power estimation. However\, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the equivalent RTL simulations. Additionally\, GLS bring-up and debug is slow and manual. In GLS\, engineers spend time cleaning up sources of unknowns (Xs).  Xs can be caused by uninitialized inputs\, registers\, and simulation artifacts such as X-pessimism. Ad-hoc methods to handle Xs in GLS could mask problems. \nThis webinar will describe a reliable formal-based method to manage Xs in GLS.  It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator. \nWhat You Will Learn:  \n\nX mitigation techniques to use in RTL\nHow to eliminate X-pessimism in GLS for a streamlined bring-up\nGenerate fixes for unknowns in a fraction of time compared to manual debug\nThe SimXACT workflow\n\nWho Should Attend:  \n\nDesigners and Design Verification engineers\nDesign Managers and Directors responsible for project tapeout schedule\n\nWhat/Which Products are Covered:   \n\nSiemens Avery SimXACT\nQuesta simulation\n\n\n\nSpeakers:\n\n\n\n\n\n\nRick Koster\nLow Power Specialist\, Siemens EDA\n\n\n\n\nRick Koster is the North America Low Power Specialist for verification tools at Siemens EDA.  Rick started his career at Texas Instruments and has held engineering positions at the US Army\, Bytex Corporation.  For more than 25 years\, Rick has worked in verification at Siemens EDA through Mentor Graphics and Ikos Systems. \n\n\n\n\n\n\n\nKai-hui Chang\nSiemens EDA\n\n\n\n\nKai-hui Chang is the architect of the SimXACT tool. He has been with Avery Design Systems for 20 years and recently joined Siemens through the Avery acquisition. His work focuses on simulation technologies and formal verification. He has a Ph. D. in computer science and engineering from the University of Michigan\, Ann Arbor.
URL:https://marketingeda.com/event/reduce-gate-level-simulation-bring-up-time-with-semi-formal-x-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-27-202.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T110000
DTEND;TZID=America/Los_Angeles:20240321T120000
DTSTAMP:20240311T211030Z
CREATED:20240311T211030Z
LAST-MODIFIED:20240311T211030Z
UID:7724-1711018800-1711022400@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Vivado and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part one of this three-part webinar series\, we will show you how to simulate an AMD example design. We will generate a design example from Vivado and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show you advanced debugging capabilities using our advanced waveform viewer. We will also turn on code coverage and analyze the results in html format. \n\nAgenda\n\nWorkflow with Vivado and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nAdvanced Debugging with Waveform Viewer\nCode Coverage\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-vivado-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T153000
DTSTAMP:20240222T182630Z
CREATED:20240222T182630Z
LAST-MODIFIED:20240222T182630Z
UID:7686-1711015200-1711035000@marketingeda.com
SUMMARY:AI-Powered Electromagnetics Symposium
DESCRIPTION:Accelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization \nHow are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such as electromagnetic interference (EMI)\, electromagnetic compatibility (EMC)\, power integrity\, and signal integrity play? \nDiscover how Cadence is transforming electromagnetic (EM) simulation for optimal design performance with innovative\, AI-driven multiphysics optimization software and breakthrough 3D EM analysis. \nJoin our CadenceCONNECT: AI-Powered EM Symposium\, where industry experts\, including Cadence\, Meta\, Microsoft\, and more\, will share insights highlighting how the Cadence Clarity 3D Solver and Optimality Intelligent Explorer workflow streamlines design results in optimized electronic product designs. \n\n\n\n\n\n\n\n\n\n\n\n\nAgenda \n10:00am – 10:30am               Registration | Light Breakfast \n10:30am – 12:00pm               Morning Sessions \n12:00pm – 1:00pm                 Lunch | Live Demonstrations \n1:00pm – 2:30pm                   Afternoon Sessions \n2:30pm – 3:30pm                   Networking Event | Live Demonstrations
URL:https://marketingeda.com/event/ai-powered-electromagnetics-symposium/
LOCATION:Cadence Design Systems\, Building 5\, 2655 Seely Avenue\, San Jose\, CA\, 95131\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T110000
DTSTAMP:20240229T180535Z
CREATED:20240229T180535Z
LAST-MODIFIED:20240229T180535Z
UID:7696-1711015200-1711018800@marketingeda.com
SUMMARY:Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
DESCRIPTION:With the growing complexities of 3D-ICs\, chiplets\, advanced packaging\, and high-performance boards\, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently\, providing confidence in system signoff. \nJoin our webinar as we present the new Cadence Celsius Studio the industry’s first complete thermal platform for electronic systems developed specifically to address thermal analysis\, thermal stress\, and electronics cooling design issues. This solution provides accurate system-level thermal analysis by combining finite element method (FEM) with computational fluid dynamics (CFD) technologies for full-system thermal analysis from chip to packaging to board through to the end-system product. \nAttendees will learn: \n\nHow Celsius Studio provides AI-enabled thermal analysis for electro-mechanical systems design\nHow the convergence of FEM and CFD engines addresses thermal challenges spanning from the chip to the packaging and out to the board and end system
URL:https://marketingeda.com/event/shift-left-thermal-analysis-with-ai-enabled-celsius-studio-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240320T080000
DTEND;TZID=America/Los_Angeles:20240321T170000
DTSTAMP:20240305T220415Z
CREATED:20240305T220415Z
LAST-MODIFIED:20240305T220415Z
UID:7710-1710921600-1711040400@marketingeda.com
SUMMARY:SNUG Silicon Valley 2024
DESCRIPTION:Connecting the Synopsys User Community\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nTechnical Committee\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. \nTechnical Committee Chair: \nDon Mills\, Microchip \nCommittee Members: \nAnand Iyer\, Synopsys \nAndy Copperhall\, Independent \nAnwarul Hasan\, Independent \nBrian Kane\, Northrop Grumman \nBryan Morris\, Ciena \nChris Kiegle\, Marvell Semiconductor \nCliff Cummings\, Paradigm Works \nFirouzeh Nourkhalaj\, Synopsys \nGlen McDonnell\, Broadcom \nHongda Lu\, SARC \nJack Dong\, Intel \nJason Rziha\, Microchip \nJeff Montesano\, Meta \nJing Zhang\, Intel \nJohn Thomson\, NVIDIA \nJohn Wei\, Independent \nJon Colburn\, NVIDIA \nJT Longino\, Tesla \nKarthik Rajan\, Microchip \nLeah Clark\, Synopsys \nMark Sprague\, Intel \nNaveen Mysore\, Intel \nNeel Sonara\, Broadcom \nNitin Navale\, AMD \nOlivia Poon\, Marvell Semiconductor \nPinal Patel\, eInfochips \nRavikishore Gandikota\, NVIDIA \nRonald Goodstein\, Lockheed Martin \nRonald Kalim\, Intel \nSachin Parikh\, Broadcom \nSangeetha Chandran Sarala\, Micron \nSathappan Palaniappan\, Broadcom \nSaurabh Bhadoriya\, NVIDIA \nSavita Banerjee\, Meta \nShaiful Alam\, Intel \nStella Matarrese\, Synopsys \nTom Mahatdejkul\, Arm \nTony Todesco\, AMD \nUpasna Vishnoi\, Marvell Semiconductor \nVictoria Kolesov\, Intel \nZafar Hasan\, NVIDIA
URL:https://marketingeda.com/event/snug-silicon-valley-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNG-Silicon-Valley-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240319T130000
DTEND;TZID=Europe/London:20240319T140000
DTSTAMP:20240410T161048Z
CREATED:20240216T190810Z
LAST-MODIFIED:20240410T161048Z
UID:7624-1710853200-1710856800@marketingeda.com
SUMMARY:DVClub Europe: Latest VHDL Verification Techniques
DESCRIPTION:This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM \nAgenda (GMT) \n13:00   Welcome and Introduction – Mike Bartley\, Tessolve \n13:00   Epsen Tallaksen\, EmLogic – Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) \n13:30   Jim Lewis\, SynthWorks – OSVVM in a NutShell\, VHDL’s #1 Verification Methodology \n14:00    Close \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe webpage for this event. \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: Agnisys\, Cadence\, Breker Verification System\, Synopsys
URL:https://marketingeda.com/event/dvclub-europe-latest-vhdl-verification-techniques/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-19-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240319T100000
DTEND;TZID=America/Los_Angeles:20240319T110000
DTSTAMP:20240221T221244Z
CREATED:20240221T221244Z
LAST-MODIFIED:20240221T221244Z
UID:7673-1710842400-1710846000@marketingeda.com
SUMMARY:Virtuoso - Save on Signoff Effort with In-Design DRC and Fill
DESCRIPTION:Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However\, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes at a cost – time and money. Not anymore. With iPegasus Verification System for Virtuoso Studio\, you can get signoff-quality physical verification within the Virtuoso Layout Suite. This webinar will teach you how: \n\nyou can avoid late surprises during signoff and save your efforts using iPegasus system for Virtuoso Studio\nthe new unified toolbar and settings simplifies your design checks with signoff quality\nthe enhanced Annotation Browser gives you an integrated solution for reviewing and fixing errors\nflexible run scope helps you in DRC fixing without losing focus\n\nMetal fill is an important step in the layout creation process that has gained significance in recent times. Crucial analog portions of the IP need careful handling with symmetry and non-minimum spacing to ensure that metal fills do not degrade circuit performance. iPegasus fill for Virtuoso Studio elevates the user experience by bringing metal fill using signoff rule decks closer to the layout. Natively integrated into Virtuoso Studio\, iPegasus fill provides control\, accuracy\, and performance benefits over running a standalone loosely tied-up flow. \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-save-on-signoff-effort-with-in-design-drc-and-fill/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240318T080000
DTEND;TZID=America/Los_Angeles:20240321T170000
DTSTAMP:20240206T194409Z
CREATED:20240206T192804Z
LAST-MODIFIED:20240206T194409Z
UID:7584-1710748800-1711040400@marketingeda.com
SUMMARY:GOMACTech 2024
DESCRIPTION:GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews.
URL:https://marketingeda.com/event/gomactech-2024/
LOCATION:Embassy Suites by Hilton\, Charleston Convention Center\, Charleston\, SC\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240314T080000
DTEND;TZID=America/Los_Angeles:20240314T090000
DTSTAMP:20240222T181810Z
CREATED:20240222T181810Z
LAST-MODIFIED:20240222T181810Z
UID:7683-1710403200-1710406800@marketingeda.com
SUMMARY:New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
DESCRIPTION:Designers increasingly use complex reset signaling architectures to meet high-performance\, low-latency\, and low-power requirements. Specifically\, independent reset domains are created by complex reset sequences\, reset circuitry\, and the intermixing of IPs with different reset schemas\, power-management domains\, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that are straining “gen one” RDC solutions.\n‌\nIn this webinar we will show new\, advanced RDC techniques\, methodology\, and automation for:\n‌ \n\nHow to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows\nAI/ML-based automation that pinpoints where to place synchronizers\, and in parallel to aggressively minimize false positives (e.g. automatically minimizing “noise”)\nCreating custom synchronizers for proprietary synchronization styles\nWaiver management flows to efficiently address violations and waiver tracking throughout the project\nConsiderations for low power designs with UPF\n\n‌\nWhat you will learn: \nA short review of the basics of Clock and Reset Domain Crossing issues that may cause meta-stability\, glitch or data coherency.\nWhat’s the right methodology for a comprehensive RDC analysis?\nQuesta RDC solutions \nWho should attend: \nDesign Engineers\, CAD Engineers\, Project Leads who are using/supporting static verification flows.\nWorking knowledge of Verilog\, SystemVerilog\, or VHDL will presumed. \nSpeaker:\n\n\n\n\n\n\nAtul Sharma\nLead Product Engineer\, Siemens EDA\n\n\n\n\nAtul Sharma is Lead Product Engineer for Questa Static and Formal Solutions in Design Verification Technology Division of Siemens Electronic Design Automation (EDA) and is primarily responsible for CDC\, RDC\, SignOff CDC and Lint products. Atul has 16 years of experience in design and verification\, design methodologies\, technical marketing and applications engineering. Prior to Siemens EDA\, Atul has held design verification role for a design company\, and Product expert role in an EDA company\, for multiple products covering different aspects of static and functional verification. \nWith 16 years of total experience\, he has spent over a decade in customer facing role to solve Static Verification issues (CDC\, RDC\, Lint\, DFT\, Power Estimation/Reduction & Power Verification) and to create customer methodologies\, use models for multiple EDA products.
URL:https://marketingeda.com/event/new-advanced-techniques-for-reset-domain-crossing-rdc-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240313T080000
DTEND;TZID=Europe/London:20240314T170000
DTSTAMP:20240122T194453Z
CREATED:20240122T194453Z
LAST-MODIFIED:20240122T194453Z
UID:7549-1710316800-1710435600@marketingeda.com
SUMMARY:GSA International Semiconductor Conference
DESCRIPTION:Inaugural GSA event in partnership with the UK Government.  \nMeet senior business leaders\, investors\, and public policy officials from around the world. \nAcross two days\, join us for exciting discussions on semiconductor innovation for a NetZero economy\, with a view on the dramatically changing supply chain\, government interventions and industry outlook. \n  \nSemiconductor Innovation for NetZero (March 13-14) \n\nSupply Chain Resilience and national approaches to Semiconductor Policy\nDifferent government approaches to semiconductor policy\, supply chains and stimulating industry growth\nResource and talent development\, including raising the role of women in the industry\nCapital funding and IP strategies for start-ups and scale-ups\n\nWLI EMEA Kick-Off Event (March 13 morning) \n\nThe first GSA Women Leadership Initiative in Europe\nDiscuss the raising role of women in semiconductors\nHear lessons learned from women who have excelled in navigating a traditionally male-dominated industry\n\n\nTicket will cover both days\, all sections\nVIP Dinner will be held on the evening of March 13th: a separate ticket is required\, very limited seating available!
URL:https://marketingeda.com/event/gsa-international-semiconductor-conference/
LOCATION:Here East\, 14 E Bay Lane\, London\, United Kingdom
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-March-13-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240312T100000
DTEND;TZID=America/Los_Angeles:20240312T110000
DTSTAMP:20240221T220803Z
CREATED:20240221T220803Z
LAST-MODIFIED:20240221T220803Z
UID:7670-1710237600-1710241200@marketingeda.com
SUMMARY:What’s New About Virtuoso Layout Suite?
DESCRIPTION:Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio\n\n\n\nHow can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation engines in Virtuoso Studio\, device-level layout\, standard cells and blocks\, chip assembly\, and memory can automatically be designed from the same interface using the right tool underneath for the right job. \nBy including an intuitive spreadsheet-style constraint management interface\, pre-routing checkers\, and support for custom routing constraints\, all layout users will find APR technology easy to use\, not just the expert ones. In this webinar\, we will showcase the following flows: \n\nCustom device-level APR for advanced node\nStandard cell APR for custom digital designs leveraging seamless integration of Innovus Implementation System’s GigaPlace placement engine and NanoRoute routing engine\nChip assembly and specialty routing for mature nodes\n\nAutomating the placement and routing of custom and analog designs with thousands of nets lets you finish the layout in minutes! \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/whats-new-about-virtuoso-layout-suite/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T100000
DTEND;TZID=America/Los_Angeles:20240307T110000
DTSTAMP:20240216T204434Z
CREATED:20240216T204434Z
LAST-MODIFIED:20240216T204434Z
UID:7634-1709805600-1709809200@marketingeda.com
SUMMARY:Efficient Design Methodology for 112G Interface Compliance
DESCRIPTION:As 112G+ data transfer becomes the new normal\, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition\, with the precision required to meet 112G compliance\, companies can take extra steps to avoid design re-spins. \n\nThis webinar will: \n\nHighlight the workflow required to overcome the new challenges associated with 112G\nHow Cadence integrated design and analysis technology provides a unique and powerful solution
URL:https://marketingeda.com/event/efficient-design-methodology-for-112g-interface-compliance/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T090000
DTEND;TZID=America/Los_Angeles:20240307T100000
DTSTAMP:20240226T233450Z
CREATED:20240226T233450Z
LAST-MODIFIED:20240226T233450Z
UID:7690-1709802000-1709805600@marketingeda.com
SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure
DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.
URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240306T100000
DTEND;TZID=Europe/London:20240306T190000
DTSTAMP:20240219T174522Z
CREATED:20240219T174522Z
LAST-MODIFIED:20240219T174522Z
UID:7641-1709719200-1709751600@marketingeda.com
SUMMARY:Agile Analog Technology Showcase Event
DESCRIPTION:Learn how innovative analog IP can help analog design engineers. \nAgile Analog is transforming the analog IP industry\, with Composa\, our configurable\, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion\, Power Management\, IC Monitoring\, Security and Always-On IPs. Applications include High Performance Computing (HPC)\, IoT\, AI\, automotive and aerospace. \nAnalog IP the way you want it\nWorking with customers across the world on a broad range of technologies\, we partner with all the major foundries. Our customizable\, digitally wrapped and verified solutions can be seamlessly integrated into any SoC\, helping chip designers by significantly reducing complexity\, time and costs. \nTechnology Deep Dive Day\nWe are coming to Scotland to showcase our cutting-edge analog IP technology and expanding product portfolio to electronics engineers in the region\, and to explain how we can simplify analog design and accelerate the integration process.\n‍\nThis event will be an informal and relaxed environment for you to discover how we are revolutionizing the world of analog IP. It’s the ideal opportunity to: \nSee a demo of our Composa technology\nDelve deeper into the finer technical details\nChat with some of our team face-to-face\nEvent Time:\nMorning Session:\n10.00-12.00: Demo & Discussions\n12.00-14.00: Networking Lunch \nAfternoon Session:\n15.00-17.00: Demo & Discussions\n17.00-19.00: Networking Drinks \nEvent Venue:\nThe Royal Society of Edinburgh\nScott Room\,\n22-26 George St\,\nEdinburgh. EH2 2PQ.
URL:https://marketingeda.com/event/agile-analog-technology-showcase-event/
LOCATION:The Royal Society of Edinburgh\, 22-26 George Street\, Edinburgh\, EH2 2PQ\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agile-Analog-6-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240304T080000
DTEND;TZID=America/Los_Angeles:20240307T170000
DTSTAMP:20240216T181350Z
CREATED:20240103T171927Z
LAST-MODIFIED:20240216T181350Z
UID:7493-1709539200-1709830800@marketingeda.com
SUMMARY:DVCon USA 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.
URL:https://marketingeda.com/event/dvcon-usa-2024/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240229T100000
DTEND;TZID=America/Chicago:20240229T110000
DTSTAMP:20240208T174710Z
CREATED:20240208T174710Z
LAST-MODIFIED:20240208T174710Z
UID:7596-1709200800-1709204400@marketingeda.com
SUMMARY:Manufacturing driven design - DFM within an Xpedition Flow
DESCRIPTION:We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years\, many OEMs have implemented DFM as a final check in their release process\, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate back to the designer for resolution. \n‌ \nJoin PCB Design experts for a live discussion and demonstration of the recommended PCB design best practice of identifying and resolving DFM issues at the earliest possible stage in the PCB design process. They will showcase how Xpedition DFM\, an integrated solution that operates right within the Xpedition environment\, provides designers with specific DFM analysis that can be performed at the appropriate design stage. This ensures your design is optimized for manufacturing before proceeding to the next stage of design. This greatly reduces the bottlenecks common with post-layout DFM. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on February 29th\, 2024. 
URL:https://marketingeda.com/event/manufacturing-driven-design-dfm-within-an-xpedition-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240229T093000
DTEND;TZID=America/Los_Angeles:20240229T150000
DTSTAMP:20240220T012904Z
CREATED:20240220T012758Z
LAST-MODIFIED:20240220T012904Z
UID:7650-1709199000-1709218800@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara - RF Day
DESCRIPTION:Shift Left with the Modern Design Center\n\n\nArtificial intelligence (AI) is redefining communication and connectivity. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, RF designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\n\nLearn and experience modern RF circuit and system design\, including electromagnetic-circuit co-simulation and AI / ML in simulation.\nGain practical insights from case studies presented by local customers.\nConnect with peers and technical experts in the heart of Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nRF Design Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome / Keynote\n\n\n10:10 – 11:00\nRF System design\n\n\n11:00 – 11:45\nNew System Verification Tools in ADS for Circuit Designers\n\n\n11:45 – 12:30\nSolving 3D Module Integration Challenges for High-Performance Microwave Design\n\n\n12:30 – 1:15\nLunch Break – Keysight Design Data and IP Management\n\n\n1:15 – 2:00\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n2:00 – 2:45\nExpanding Robust\, High-Yield Design Techniques from Circuit to EM\n\n\n2:45 – 3:00\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-rf-day/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240228T093000
DTEND;TZID=America/Los_Angeles:20240228T151500
DTSTAMP:20240220T012253Z
CREATED:20240220T012253Z
LAST-MODIFIED:20240220T012253Z
UID:7646-1709112600-1709133300@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara – High Speed Digital
DESCRIPTION:Shift Left with the Modern Design Center\n\nArtificial intelligence (AI) is redefining high-speed digital designs. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, digital designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\nLearn and experience advanced digital design solutions\, including die-to-die simulation for chiplets\, SerDes and memory design for AI/ML\, and more.\n\n\nGain practical insights from case studies presented by local customers.\n\n\nConnect with peers and technical experts at the heart of the Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nHigh Speed Digital Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome/Keynote\n\n\n10:10 – 10:45\nChiplet PHY Designer- Analyze D2D to D2D\n\n\n10:45 – 11:30\nAdvances in memory and SerDes applications\n\n\n11:30 – 12:30\nSimulation-driven compliance solutions for PCIe and USB standards\n\n\n12:30 – 1:30\nLunch Break – Keysight Design Data and IP Management\n\n\n1:30 – 2:15\nEM modeling of high-speed interconnects using SIPro\n\n\n2:15 – 3:00\nEnd-to-End Power Integrity Simulations with Digital Twin EM Models\n\n\n3:00 – 3:15\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-high-speed-digital/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240227T090000
DTEND;TZID=America/New_York:20240227T100000
DTSTAMP:20240216T202136Z
CREATED:20240216T202136Z
LAST-MODIFIED:20240216T202136Z
UID:7631-1709024400-1709028000@marketingeda.com
SUMMARY:From code to solution: tools and tactics for aerospace fault code troubleshooting
DESCRIPTION:Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting\, unveiling the power of Capital™ Service Explorer. \nDiscover innovative strategies to diagnose issues swiftly\, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple fault codes\, empowering technicians to expedite resolutions. \nWe will also demonstrate its ability to seamlessly integrate 3D visualization data\, providing a comprehensive solution for efficient and intelligent troubleshooting in the aerospace and defense industry. \nMeet the speakers\nOjaswa Sharma\nSenior Product Manager\, IES \n\nHe is a Senior Product Manager with 15 years of experience in the Automotive Industry. With expertise in the design and development of Electrical Distribution Systems\, he has successfully led teams across various Original Equipment Manufacturers (OEMs) to deliver exceptional EE content for a wide range of vehicle platforms. \nDavid Gamba\nProduct Owner\, IES \n\nAs a Product Owner for Documentation & Diagnostics within the Integrated Electrical Systems\, he has spent the past 10 years deploying Capital tools in both the aerospace and automotive sectors. His expertise lies in usability\, customer deployments\, and proposing growth-driving solutions. Through collaboration with customers\, engineers\, and users\, he has contributed to the development of intuitive products that have transformed the industry.
URL:https://marketingeda.com/event/from-code-to-solution-tools-and-tactics-for-aerospace-fault-code-troubleshooting/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Februay-27-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240226T123000
DTEND;TZID=America/Los_Angeles:20240226T164500
DTSTAMP:20240125T175450Z
CREATED:20240125T175450Z
LAST-MODIFIED:20240125T175450Z
UID:7556-1708950600-1708965900@marketingeda.com
SUMMARY:Synopsys Technical Forum 2024
DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception
URL:https://marketingeda.com/event/synopsys-technical-forum-2024/
LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240225T080000
DTEND;TZID=America/Los_Angeles:20240229T180000
DTSTAMP:20240221T174538Z
CREATED:20240221T174208Z
LAST-MODIFIED:20240221T174538Z
UID:7659-1708848000-1709229600@marketingeda.com
SUMMARY:SPIE Advanced Lithography + Patterning
DESCRIPTION:Attend and hear research\, challenges\, and breakthroughs as you gather with colleagues in San Jose \nJoin other leading researchers who are solving challenges in optical and EUV lithography\, patterning technologies\, metrology\, and process integration for semiconductor manufacturing and adjacent applications. \nFive days of exciting content and connecting with your community\n\nPlenary talks\nTechnical presentations\nNetworking sessions\nCourse offerings\nExhibition\n\nCome to hear world-class speakers\nChan Hwang\n\nSamsung (Korea) \nAnn Kelleher\n\nIntel Corp. (United States) \nTodd Younkin\n\nSemiconductor Research Corporation (USA) \nExplore six great conferences\n\nOptical and EUV Nanolithography\nDTCO and Computational Patterning\nMetrology\, Inspection\, and Process Control\nNovel Patterning Technologies\nAdvances in Patterning Materials and Processes\nAdvanced Etch Technology and Process Integration for Nanopatterning
URL:https://marketingeda.com/event/spie-advanced-lithography-patterning/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SPIE.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240222T183000
DTEND;TZID=America/Los_Angeles:20240222T213000
DTSTAMP:20240104T175833Z
CREATED:20240104T175833Z
LAST-MODIFIED:20240104T175833Z
UID:7506-1708626600-1708637400@marketingeda.com
SUMMARY:Phil Kaufman Award & Banquet
DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \nDR. LAWRENCE T. PILEGGI\nCoraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University with the \n2023 PHIL KAUFMAN AWARD\n\n \n\nDr. Lawrence T. Pileggi is being honored with the 2023 Phil Kaufman Award in recognition of his pioneering contributions that have enabled the industry to address the challenges of interconnect delay dominated designs\, including: \nInterconnect Modeling\nPhysical Synthesis\nLithography Directed Design & Manufacturability\nCo-design and Co-optimization of Logic and Layout\nPower Grid Simulation and Optimization \nDr. Pileggi continues to provide significant and lasting leadership in Electrical & Computer Engineering (ECE) education.
URL:https://marketingeda.com/event/phil-kaufman-award-banquet-2/
LOCATION:The GlassHouse\, 2 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Award,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semi-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T090000
DTEND;TZID=America/Los_Angeles:20240221T100000
DTSTAMP:20240212T201810Z
CREATED:20240212T201810Z
LAST-MODIFIED:20240212T201810Z
UID:7604-1708506000-1708509600@marketingeda.com
SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering.
URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T080000
DTEND;TZID=America/Los_Angeles:20240221T180000
DTSTAMP:20240216T221430Z
CREATED:20240216T221430Z
LAST-MODIFIED:20240216T221430Z
UID:7637-1708502400-1708538400@marketingeda.com
SUMMARY:Intel Foundry Services (IFS) Direct Connect
DESCRIPTION:Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world’s first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick around for a panel discussion\, including industry leaders Rene Haas (Arm)\, Yuan Xing Lee (Broadcom)\, and Eric Fisher (MediaTek). \n\n\n\nWhat to Expect\n\n\n\n\n\n\n\n\n\nAll times in PST\nWednesday\, February 21\, 2024\n\n\n\n\n7:30am – 8:30am\nRegistration\, Breakfast\, and Demo Showcase\n\n\n8:30am – 9:30am\nPat Gelsinger and Stu Pann: A Systems Foundry for the AI Era with special appearances by: \n\nGina M. Raimondo\, United States Secretary of Commerce\nSatya Nadella\, Chairman and CEO\, Microsoft\nRene Haas\, CEO\, Arm\n\n\n\n\n9:30am – 10:00am\nCustomer Fireside Chat featuring: \n\nYuan Xing Lee\, VP of Central Engineering\, Broadcom\nEric Fisher\, President\, MediaTek North America\n\n\n\n\n10:00am – 10:30am\nAM Break and Demo Showcase\n\n\n10:30am – 12:00pm\nEcosystem Spotlight featuring: \n\nAart de Geus\, Executive Chair and Founder\, Synopsys\nMike Ellow\, Executive Vice President\, Siemens Digital Industries Software\nJohn Lee\, General Manager and Vice President for Electronics\, Semiconductors and Optics BU\, Ansys\nAnirudh Devgan\, President and CEO\, Cadence Design System\n\n\n\n\n12:00pm – 1:00pm\nNetworking Lunch and Demo Showcase\n\n\n1:00pm – 2:15pm\nDr. Ann Kelleher and Dr. Gary Patton: Delivering the Present and Inventing the Future: A Look Beyond 5N4Y\n\n\n2:15pm – 3:00pm\nDr. Choon Lee: Advanced Packaging and Test Solutions\n\n\n3:00pm – 3:20pm\nPM Break and Demo Showcase\n\n\n3:20pm – 3:50pm\nKeyvan Esfarjani: Transforming Intel Manufacturing featuring: \n\nJason Wang\, President\, UMC\n\n\n\n\n3:50pm – 4:00pm\nStu Pann: Wrap Up\n\n\n4:00pm – 4:45pm\nFireside Chat featuring: \n\nSam Altman\, Co-founder and CEO\, OpenAI\n\n\n\n\n4:45pm – 6:15pm\nNetworking Reception and Demo Showcase
URL:https://marketingeda.com/event/intel-foundry-services-ifs-direct-connect/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IFS-Direct-Connect.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240220T150000
DTEND;TZID=Asia/Kolkata:20240220T170000
DTSTAMP:20240122T182008Z
CREATED:20240122T181727Z
LAST-MODIFIED:20240122T182008Z
UID:7542-1708441200-1708448400@marketingeda.com
SUMMARY:DVClub India - Using AI/ML in Design Verification
DESCRIPTION:This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. \nVenue – Cadence Design System\, Bengaluru & Online\n\n\n\nTime\nSession\n\n\n15:00 GMT\nWelcome and introduction – Mike Bartley\, Tessolve\n\n\n15:00 GMT\nCadence\n\n\n16:00 GMT\nTessolve\n\n\n16:30 GMT\nTBD\n\n\n17:00 GMT\nClose\n\n\n\nAbout DVClub\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/dvclub-india-using-ai-ml-in-design-verification/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-February-20-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240220T080000
DTEND;TZID=America/Los_Angeles:20240220T090000
DTSTAMP:20240216T185704Z
CREATED:20240216T185704Z
LAST-MODIFIED:20240216T185704Z
UID:7621-1708416000-1708419600@marketingeda.com
SUMMARY:SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
DESCRIPTION:The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power\, performance\, area\, and yield\, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process\, voltage\, and temperature corners\, as well as local variation. \nWhere traditional brute-force Monte Carlo solutions are insufficient to scale to meet these escalating design requirements\, an effective SPICE-level verification methodology can provide a robust solution to meet these growing demands in shorter design and verification cycles. \nI invite you to join me in this webinar\, where we’ll delve into the evolving challenges of variation-aware verification in IC design\, uncover the most effective best practices\, and explore how a methodology leveraging Solido Design Environment’s AI technologies can enhance SPICE-level variation-aware verification\, accelerating verification runtime while enhancing coverage and accuracy. \nWhat you will learn:\nIn this masterclass you’ll gain a comprehensive understanding of design variations and effective techniques to manage them. Explore Solido Design Environment’s AI-powered tools\, and discover how they streamline design verification\, ensuring improved speed and accuracy. \nFeatured Products: Solido Design Environment \nSpeaker:\n\nMohamed Atoua\nProduct Manager\, Siemens EDA \nMohamed Atoua is a Product Manager for Solido Design Environment at Siemens EDA with more than 7 years of experience in the EDA industry. With a track record of blending technical solutions with business acumen\, his current mission is to help circuit designers address the challenges of meeting higher design complexity faster with less effort through Siemens’ Solido Design Environment software. \nHis journey began at Cairo University\, where he earned a bachelor’s degree in electrical engineering\, specializing in electronics with a minor in computer engineering. Atoua is currently pursuing his master’s degree in business administration at the University of Illinois Urbana-Champaign\, he thrives at the intersection of technology and management.
URL:https://marketingeda.com/event/spice-accurate-variation-aware-verification-best-practices-with-solido-ai-powered-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-20-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240218T080000
DTEND;TZID=America/Los_Angeles:20240222T170000
DTSTAMP:20231230T004304Z
CREATED:20231230T004304Z
LAST-MODIFIED:20231230T004304Z
UID:7483-1708243200-1708621200@marketingeda.com
SUMMARY:ISSCC 2024
DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts.
URL:https://marketingeda.com/event/isscc-2024/
LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240215T110000
DTEND;TZID=America/Los_Angeles:20240215T120000
DTSTAMP:20240202T185233Z
CREATED:20240202T185233Z
LAST-MODIFIED:20240202T185233Z
UID:7574-1707994800-1707998400@marketingeda.com
SUMMARY:Essential Steps to Simplify VHDL Testbenches Using OSVVM
DESCRIPTION:This “Getting Started” webinar focuses on the first\, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing\, self-checking tests\, messaging\, reports\, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. \n  \nThe “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development\, increase reuse\, and reduce maintenance costs. \n  \nSelf-checking is essential in test cases as checking waveform output manually is time consuming\, error prone\, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection\, some of which might be in a different entity) we will need to sum them up and generate an error report. However\, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. \n  \nMessaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities\, we need controls that have a wide scope. Furthermore\, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. \n  \nTest reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run\, and the OSVVM test case report provides details on the self-checking\, functional coverage\, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing)\, these reports help us quickly find which test cases failed and why. \n  \nThe OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation\, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. \n  \nAbout OSVVM \nOSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex\, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.\nGetting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. \n  \nWebinar Duration: \n\n45 min presentation/live demo\n10 min Q&A\n\n  \nPresenter BIO \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and spacecraft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/essential-steps-to-simplify-vhdl-testbenches-using-osvvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Oslo:20240214T080000
DTEND;TZID=Europe/Oslo:20240215T170000
DTSTAMP:20240209T180613Z
CREATED:20240209T180613Z
LAST-MODIFIED:20240209T180613Z
UID:7599-1707897600-1708016400@marketingeda.com
SUMMARY:FPGA Forum 2024 - Norway
DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication.
URL:https://marketingeda.com/event/fpga-forum-2024-norway/
LOCATION:Royal Garden\, Trondheim\, Norway
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240213T110000
DTEND;TZID=America/New_York:20240213T120000
DTSTAMP:20240206T191819Z
CREATED:20240206T191819Z
LAST-MODIFIED:20240206T191819Z
UID:7581-1707822000-1707825600@marketingeda.com
SUMMARY:Introducing Ansys AI: A New Chapter in Engineering Simulation
DESCRIPTION:Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We’re revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI\, AnsysGPT\, and Ansys AI+. \nOverview\nAt Ansys\, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer\, bringing unprecedented speed\, innovation\, and accessibility to the engineering world. With Ansys AI\, we enable product engineers to leverage their previous simulation and measurement data to reliably assess the performance of new designs in minutes instead of hours. We are not just accelerating simulations but transforming how engineers work\, making simulation simple\, natural\, and accessible. \nWhat you will learn\n\nFirst\, we’ll introduce Ansys SimAI\, a machine learning platform for engineers who must rapidly explore and predict the performance of new concepts across design phases. SimAI provides reliable and fast results\, accessible through user-friendly cloud-native application\, targeting a broad engineering audience that includes all simulation engineers and designers.\nSecond\, we’ll showcase the AnsysGPT chatbot\, which re-imagines the user and support experience through simple\, natural language interaction.\nFinally\, we’ll demonstrate how Ansys AI+ add-ons augment the product capabilities across the Ansys collection\, starting with optiSLang AI+ and Granta MI AI+.\n\nWho should attend\nCAE/CAD Engineers / Designers / Simulation Analyst / Engineers\, Computation Engineers \nSpeaker\nIlya Tolchinsky
URL:https://marketingeda.com/event/introducing-ansys-ai-a-new-chapter-in-engineering-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024-1.jpg
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