BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.0//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Oslo
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T090000
DTEND;TZID=America/Los_Angeles:20240307T100000
DTSTAMP:20240226T233450Z
CREATED:20240226T233450Z
LAST-MODIFIED:20240226T233450Z
UID:7690-1709802000-1709805600@marketingeda.com
SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure
DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.
URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240306T100000
DTEND;TZID=Europe/London:20240306T190000
DTSTAMP:20240219T174522Z
CREATED:20240219T174522Z
LAST-MODIFIED:20240219T174522Z
UID:7641-1709719200-1709751600@marketingeda.com
SUMMARY:Agile Analog Technology Showcase Event
DESCRIPTION:Learn how innovative analog IP can help analog design engineers. \nAgile Analog is transforming the analog IP industry\, with Composa\, our configurable\, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion\, Power Management\, IC Monitoring\, Security and Always-On IPs. Applications include High Performance Computing (HPC)\, IoT\, AI\, automotive and aerospace. \nAnalog IP the way you want it\nWorking with customers across the world on a broad range of technologies\, we partner with all the major foundries. Our customizable\, digitally wrapped and verified solutions can be seamlessly integrated into any SoC\, helping chip designers by significantly reducing complexity\, time and costs. \nTechnology Deep Dive Day\nWe are coming to Scotland to showcase our cutting-edge analog IP technology and expanding product portfolio to electronics engineers in the region\, and to explain how we can simplify analog design and accelerate the integration process.\n‍\nThis event will be an informal and relaxed environment for you to discover how we are revolutionizing the world of analog IP. It’s the ideal opportunity to: \nSee a demo of our Composa technology\nDelve deeper into the finer technical details\nChat with some of our team face-to-face\nEvent Time:\nMorning Session:\n10.00-12.00: Demo & Discussions\n12.00-14.00: Networking Lunch \nAfternoon Session:\n15.00-17.00: Demo & Discussions\n17.00-19.00: Networking Drinks \nEvent Venue:\nThe Royal Society of Edinburgh\nScott Room\,\n22-26 George St\,\nEdinburgh. EH2 2PQ.
URL:https://marketingeda.com/event/agile-analog-technology-showcase-event/
LOCATION:The Royal Society of Edinburgh\, 22-26 George Street\, Edinburgh\, EH2 2PQ\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agile-Analog-6-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240304T080000
DTEND;TZID=America/Los_Angeles:20240307T170000
DTSTAMP:20240216T181350Z
CREATED:20240103T171927Z
LAST-MODIFIED:20240216T181350Z
UID:7493-1709539200-1709830800@marketingeda.com
SUMMARY:DVCon USA 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.
URL:https://marketingeda.com/event/dvcon-usa-2024/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240229T100000
DTEND;TZID=America/Chicago:20240229T110000
DTSTAMP:20240208T174710Z
CREATED:20240208T174710Z
LAST-MODIFIED:20240208T174710Z
UID:7596-1709200800-1709204400@marketingeda.com
SUMMARY:Manufacturing driven design - DFM within an Xpedition Flow
DESCRIPTION:We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years\, many OEMs have implemented DFM as a final check in their release process\, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate back to the designer for resolution. \n‌ \nJoin PCB Design experts for a live discussion and demonstration of the recommended PCB design best practice of identifying and resolving DFM issues at the earliest possible stage in the PCB design process. They will showcase how Xpedition DFM\, an integrated solution that operates right within the Xpedition environment\, provides designers with specific DFM analysis that can be performed at the appropriate design stage. This ensures your design is optimized for manufacturing before proceeding to the next stage of design. This greatly reduces the bottlenecks common with post-layout DFM. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on February 29th\, 2024. 
URL:https://marketingeda.com/event/manufacturing-driven-design-dfm-within-an-xpedition-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240229T093000
DTEND;TZID=America/Los_Angeles:20240229T150000
DTSTAMP:20240220T012904Z
CREATED:20240220T012758Z
LAST-MODIFIED:20240220T012904Z
UID:7650-1709199000-1709218800@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara - RF Day
DESCRIPTION:Shift Left with the Modern Design Center\n\n\nArtificial intelligence (AI) is redefining communication and connectivity. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, RF designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\n\nLearn and experience modern RF circuit and system design\, including electromagnetic-circuit co-simulation and AI / ML in simulation.\nGain practical insights from case studies presented by local customers.\nConnect with peers and technical experts in the heart of Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nRF Design Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome / Keynote\n\n\n10:10 – 11:00\nRF System design\n\n\n11:00 – 11:45\nNew System Verification Tools in ADS for Circuit Designers\n\n\n11:45 – 12:30\nSolving 3D Module Integration Challenges for High-Performance Microwave Design\n\n\n12:30 – 1:15\nLunch Break – Keysight Design Data and IP Management\n\n\n1:15 – 2:00\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n2:00 – 2:45\nExpanding Robust\, High-Yield Design Techniques from Circuit to EM\n\n\n2:45 – 3:00\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-rf-day/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240228T093000
DTEND;TZID=America/Los_Angeles:20240228T151500
DTSTAMP:20240220T012253Z
CREATED:20240220T012253Z
LAST-MODIFIED:20240220T012253Z
UID:7646-1709112600-1709133300@marketingeda.com
SUMMARY:Keysight EDA Connect World Tour: Santa Clara – High Speed Digital
DESCRIPTION:Shift Left with the Modern Design Center\n\nArtificial intelligence (AI) is redefining high-speed digital designs. Your ability to design\, simulate\, and test — using an automated\, integrated workflow — is what will set you apart. \nWhether you are a design team leader\, digital designer\, or system engineer\, this one-day event is for you. We have assembled speakers and sessions for every skill level to take your company and career to the new frontier. Sign up now to do the following: \n\nLearn and experience advanced digital design solutions\, including die-to-die simulation for chiplets\, SerDes and memory design for AI/ML\, and more.\n\n\nGain practical insights from case studies presented by local customers.\n\n\nConnect with peers and technical experts at the heart of the Silicon Valley.\n\nRegister now to secure your seat.\n\n\n\n\n\nAgenda\nHigh Speed Digital Focused\n\n\n09:30 – 10:00\nCheck-in\n\n\n10:00 – 10:10\nWelcome/Keynote\n\n\n10:10 – 10:45\nChiplet PHY Designer- Analyze D2D to D2D\n\n\n10:45 – 11:30\nAdvances in memory and SerDes applications\n\n\n11:30 – 12:30\nSimulation-driven compliance solutions for PCIe and USB standards\n\n\n12:30 – 1:30\nLunch Break – Keysight Design Data and IP Management\n\n\n1:30 – 2:15\nEM modeling of high-speed interconnects using SIPro\n\n\n2:15 – 3:00\nEnd-to-End Power Integrity Simulations with Digital Twin EM Models\n\n\n3:00 – 3:15\nClosing remarks / Survey
URL:https://marketingeda.com/event/keysight-eda-connect-world-tour-santa-clara-high-speed-digital/
LOCATION:Keysight Technologies\, 5301 Stevens Creek Boulevard\, Santa Clara\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-February-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240227T090000
DTEND;TZID=America/New_York:20240227T100000
DTSTAMP:20240216T202136Z
CREATED:20240216T202136Z
LAST-MODIFIED:20240216T202136Z
UID:7631-1709024400-1709028000@marketingeda.com
SUMMARY:From code to solution: tools and tactics for aerospace fault code troubleshooting
DESCRIPTION:Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting\, unveiling the power of Capital™ Service Explorer. \nDiscover innovative strategies to diagnose issues swiftly\, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple fault codes\, empowering technicians to expedite resolutions. \nWe will also demonstrate its ability to seamlessly integrate 3D visualization data\, providing a comprehensive solution for efficient and intelligent troubleshooting in the aerospace and defense industry. \nMeet the speakers\nOjaswa Sharma\nSenior Product Manager\, IES \n\nHe is a Senior Product Manager with 15 years of experience in the Automotive Industry. With expertise in the design and development of Electrical Distribution Systems\, he has successfully led teams across various Original Equipment Manufacturers (OEMs) to deliver exceptional EE content for a wide range of vehicle platforms. \nDavid Gamba\nProduct Owner\, IES \n\nAs a Product Owner for Documentation & Diagnostics within the Integrated Electrical Systems\, he has spent the past 10 years deploying Capital tools in both the aerospace and automotive sectors. His expertise lies in usability\, customer deployments\, and proposing growth-driving solutions. Through collaboration with customers\, engineers\, and users\, he has contributed to the development of intuitive products that have transformed the industry.
URL:https://marketingeda.com/event/from-code-to-solution-tools-and-tactics-for-aerospace-fault-code-troubleshooting/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Februay-27-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240226T123000
DTEND;TZID=America/Los_Angeles:20240226T164500
DTSTAMP:20240125T175450Z
CREATED:20240125T175450Z
LAST-MODIFIED:20240125T175450Z
UID:7556-1708950600-1708965900@marketingeda.com
SUMMARY:Synopsys Technical Forum 2024
DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception
URL:https://marketingeda.com/event/synopsys-technical-forum-2024/
LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240225T080000
DTEND;TZID=America/Los_Angeles:20240229T180000
DTSTAMP:20240221T174538Z
CREATED:20240221T174208Z
LAST-MODIFIED:20240221T174538Z
UID:7659-1708848000-1709229600@marketingeda.com
SUMMARY:SPIE Advanced Lithography + Patterning
DESCRIPTION:Attend and hear research\, challenges\, and breakthroughs as you gather with colleagues in San Jose \nJoin other leading researchers who are solving challenges in optical and EUV lithography\, patterning technologies\, metrology\, and process integration for semiconductor manufacturing and adjacent applications. \nFive days of exciting content and connecting with your community\n\nPlenary talks\nTechnical presentations\nNetworking sessions\nCourse offerings\nExhibition\n\nCome to hear world-class speakers\nChan Hwang\n\nSamsung (Korea) \nAnn Kelleher\n\nIntel Corp. (United States) \nTodd Younkin\n\nSemiconductor Research Corporation (USA) \nExplore six great conferences\n\nOptical and EUV Nanolithography\nDTCO and Computational Patterning\nMetrology\, Inspection\, and Process Control\nNovel Patterning Technologies\nAdvances in Patterning Materials and Processes\nAdvanced Etch Technology and Process Integration for Nanopatterning
URL:https://marketingeda.com/event/spie-advanced-lithography-patterning/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SPIE.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240222T183000
DTEND;TZID=America/Los_Angeles:20240222T213000
DTSTAMP:20240104T175833Z
CREATED:20240104T175833Z
LAST-MODIFIED:20240104T175833Z
UID:7506-1708626600-1708637400@marketingeda.com
SUMMARY:Phil Kaufman Award & Banquet
DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \nDR. LAWRENCE T. PILEGGI\nCoraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University with the \n2023 PHIL KAUFMAN AWARD\n\n \n\nDr. Lawrence T. Pileggi is being honored with the 2023 Phil Kaufman Award in recognition of his pioneering contributions that have enabled the industry to address the challenges of interconnect delay dominated designs\, including: \nInterconnect Modeling\nPhysical Synthesis\nLithography Directed Design & Manufacturability\nCo-design and Co-optimization of Logic and Layout\nPower Grid Simulation and Optimization \nDr. Pileggi continues to provide significant and lasting leadership in Electrical & Computer Engineering (ECE) education.
URL:https://marketingeda.com/event/phil-kaufman-award-banquet-2/
LOCATION:The GlassHouse\, 2 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Award,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semi-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T090000
DTEND;TZID=America/Los_Angeles:20240221T100000
DTSTAMP:20240212T201810Z
CREATED:20240212T201810Z
LAST-MODIFIED:20240212T201810Z
UID:7604-1708506000-1708509600@marketingeda.com
SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering.
URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T080000
DTEND;TZID=America/Los_Angeles:20240221T180000
DTSTAMP:20240216T221430Z
CREATED:20240216T221430Z
LAST-MODIFIED:20240216T221430Z
UID:7637-1708502400-1708538400@marketingeda.com
SUMMARY:Intel Foundry Services (IFS) Direct Connect
DESCRIPTION:Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world’s first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick around for a panel discussion\, including industry leaders Rene Haas (Arm)\, Yuan Xing Lee (Broadcom)\, and Eric Fisher (MediaTek). \n\n\n\nWhat to Expect\n\n\n\n\n\n\n\n\n\nAll times in PST\nWednesday\, February 21\, 2024\n\n\n\n\n7:30am – 8:30am\nRegistration\, Breakfast\, and Demo Showcase\n\n\n8:30am – 9:30am\nPat Gelsinger and Stu Pann: A Systems Foundry for the AI Era with special appearances by: \n\nGina M. Raimondo\, United States Secretary of Commerce\nSatya Nadella\, Chairman and CEO\, Microsoft\nRene Haas\, CEO\, Arm\n\n\n\n\n9:30am – 10:00am\nCustomer Fireside Chat featuring: \n\nYuan Xing Lee\, VP of Central Engineering\, Broadcom\nEric Fisher\, President\, MediaTek North America\n\n\n\n\n10:00am – 10:30am\nAM Break and Demo Showcase\n\n\n10:30am – 12:00pm\nEcosystem Spotlight featuring: \n\nAart de Geus\, Executive Chair and Founder\, Synopsys\nMike Ellow\, Executive Vice President\, Siemens Digital Industries Software\nJohn Lee\, General Manager and Vice President for Electronics\, Semiconductors and Optics BU\, Ansys\nAnirudh Devgan\, President and CEO\, Cadence Design System\n\n\n\n\n12:00pm – 1:00pm\nNetworking Lunch and Demo Showcase\n\n\n1:00pm – 2:15pm\nDr. Ann Kelleher and Dr. Gary Patton: Delivering the Present and Inventing the Future: A Look Beyond 5N4Y\n\n\n2:15pm – 3:00pm\nDr. Choon Lee: Advanced Packaging and Test Solutions\n\n\n3:00pm – 3:20pm\nPM Break and Demo Showcase\n\n\n3:20pm – 3:50pm\nKeyvan Esfarjani: Transforming Intel Manufacturing featuring: \n\nJason Wang\, President\, UMC\n\n\n\n\n3:50pm – 4:00pm\nStu Pann: Wrap Up\n\n\n4:00pm – 4:45pm\nFireside Chat featuring: \n\nSam Altman\, Co-founder and CEO\, OpenAI\n\n\n\n\n4:45pm – 6:15pm\nNetworking Reception and Demo Showcase
URL:https://marketingeda.com/event/intel-foundry-services-ifs-direct-connect/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IFS-Direct-Connect.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240220T150000
DTEND;TZID=Asia/Kolkata:20240220T170000
DTSTAMP:20240122T182008Z
CREATED:20240122T181727Z
LAST-MODIFIED:20240122T182008Z
UID:7542-1708441200-1708448400@marketingeda.com
SUMMARY:DVClub India - Using AI/ML in Design Verification
DESCRIPTION:This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. \nVenue – Cadence Design System\, Bengaluru & Online\n\n\n\nTime\nSession\n\n\n15:00 GMT\nWelcome and introduction – Mike Bartley\, Tessolve\n\n\n15:00 GMT\nCadence\n\n\n16:00 GMT\nTessolve\n\n\n16:30 GMT\nTBD\n\n\n17:00 GMT\nClose\n\n\n\nAbout DVClub\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/dvclub-india-using-ai-ml-in-design-verification/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-February-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240220T080000
DTEND;TZID=America/Los_Angeles:20240220T090000
DTSTAMP:20240216T185704Z
CREATED:20240216T185704Z
LAST-MODIFIED:20240216T185704Z
UID:7621-1708416000-1708419600@marketingeda.com
SUMMARY:SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
DESCRIPTION:The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power\, performance\, area\, and yield\, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process\, voltage\, and temperature corners\, as well as local variation. \nWhere traditional brute-force Monte Carlo solutions are insufficient to scale to meet these escalating design requirements\, an effective SPICE-level verification methodology can provide a robust solution to meet these growing demands in shorter design and verification cycles. \nI invite you to join me in this webinar\, where we’ll delve into the evolving challenges of variation-aware verification in IC design\, uncover the most effective best practices\, and explore how a methodology leveraging Solido Design Environment’s AI technologies can enhance SPICE-level variation-aware verification\, accelerating verification runtime while enhancing coverage and accuracy. \nWhat you will learn:\nIn this masterclass you’ll gain a comprehensive understanding of design variations and effective techniques to manage them. Explore Solido Design Environment’s AI-powered tools\, and discover how they streamline design verification\, ensuring improved speed and accuracy. \nFeatured Products: Solido Design Environment \nSpeaker:\n\nMohamed Atoua\nProduct Manager\, Siemens EDA \nMohamed Atoua is a Product Manager for Solido Design Environment at Siemens EDA with more than 7 years of experience in the EDA industry. With a track record of blending technical solutions with business acumen\, his current mission is to help circuit designers address the challenges of meeting higher design complexity faster with less effort through Siemens’ Solido Design Environment software. \nHis journey began at Cairo University\, where he earned a bachelor’s degree in electrical engineering\, specializing in electronics with a minor in computer engineering. Atoua is currently pursuing his master’s degree in business administration at the University of Illinois Urbana-Champaign\, he thrives at the intersection of technology and management.
URL:https://marketingeda.com/event/spice-accurate-variation-aware-verification-best-practices-with-solido-ai-powered-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240218T080000
DTEND;TZID=America/Los_Angeles:20240222T170000
DTSTAMP:20231230T004304Z
CREATED:20231230T004304Z
LAST-MODIFIED:20231230T004304Z
UID:7483-1708243200-1708621200@marketingeda.com
SUMMARY:ISSCC 2024
DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts.
URL:https://marketingeda.com/event/isscc-2024/
LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240215T110000
DTEND;TZID=America/Los_Angeles:20240215T120000
DTSTAMP:20240202T185233Z
CREATED:20240202T185233Z
LAST-MODIFIED:20240202T185233Z
UID:7574-1707994800-1707998400@marketingeda.com
SUMMARY:Essential Steps to Simplify VHDL Testbenches Using OSVVM
DESCRIPTION:This “Getting Started” webinar focuses on the first\, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing\, self-checking tests\, messaging\, reports\, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. \n  \nThe “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development\, increase reuse\, and reduce maintenance costs. \n  \nSelf-checking is essential in test cases as checking waveform output manually is time consuming\, error prone\, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection\, some of which might be in a different entity) we will need to sum them up and generate an error report. However\, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. \n  \nMessaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities\, we need controls that have a wide scope. Furthermore\, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. \n  \nTest reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run\, and the OSVVM test case report provides details on the self-checking\, functional coverage\, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing)\, these reports help us quickly find which test cases failed and why. \n  \nThe OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation\, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. \n  \nAbout OSVVM \nOSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex\, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.\nGetting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. \n  \nWebinar Duration: \n\n45 min presentation/live demo\n10 min Q&A\n\n  \nPresenter BIO \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and spacecraft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/essential-steps-to-simplify-vhdl-testbenches-using-osvvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Oslo:20240214T080000
DTEND;TZID=Europe/Oslo:20240215T170000
DTSTAMP:20240209T180613Z
CREATED:20240209T180613Z
LAST-MODIFIED:20240209T180613Z
UID:7599-1707897600-1708016400@marketingeda.com
SUMMARY:FPGA Forum 2024 - Norway
DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication.
URL:https://marketingeda.com/event/fpga-forum-2024-norway/
LOCATION:Royal Garden\, Trondheim\, Norway
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240213T110000
DTEND;TZID=America/New_York:20240213T120000
DTSTAMP:20240206T191819Z
CREATED:20240206T191819Z
LAST-MODIFIED:20240206T191819Z
UID:7581-1707822000-1707825600@marketingeda.com
SUMMARY:Introducing Ansys AI: A New Chapter in Engineering Simulation
DESCRIPTION:Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We’re revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI\, AnsysGPT\, and Ansys AI+. \nOverview\nAt Ansys\, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer\, bringing unprecedented speed\, innovation\, and accessibility to the engineering world. With Ansys AI\, we enable product engineers to leverage their previous simulation and measurement data to reliably assess the performance of new designs in minutes instead of hours. We are not just accelerating simulations but transforming how engineers work\, making simulation simple\, natural\, and accessible. \nWhat you will learn\n\nFirst\, we’ll introduce Ansys SimAI\, a machine learning platform for engineers who must rapidly explore and predict the performance of new concepts across design phases. SimAI provides reliable and fast results\, accessible through user-friendly cloud-native application\, targeting a broad engineering audience that includes all simulation engineers and designers.\nSecond\, we’ll showcase the AnsysGPT chatbot\, which re-imagines the user and support experience through simple\, natural language interaction.\nFinally\, we’ll demonstrate how Ansys AI+ add-ons augment the product capabilities across the Ansys collection\, starting with optiSLang AI+ and Granta MI AI+.\n\nWho should attend\nCAE/CAD Engineers / Designers / Simulation Analyst / Engineers\, Computation Engineers \nSpeaker\nIlya Tolchinsky
URL:https://marketingeda.com/event/introducing-ansys-ai-a-new-chapter-in-engineering-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240213T100000
DTEND;TZID=Europe/Paris:20240213T110000
DTSTAMP:20240205T215030Z
CREATED:20240205T215030Z
LAST-MODIFIED:20240205T215030Z
UID:7578-1707818400-1707822000@marketingeda.com
SUMMARY:Power Innovations in Consumer Electronics Using LF EM Solutions
DESCRIPTION:This webinar will cover how the Ansys simulation tools are now widely used in many low-frequency (LF) EM applications\, such as wireless charging\, power supplies\, transformers\, magnetic latches and actuators\, PCB/ECAD\, and more. Discover how Ansys Maxwell enables rapid and accurate simulation of EM fields in electronic and consumer devices to reduce design iterations\, component footprint\, size\, and time to market. \n\n\n\n\nWhat You Will Learn\n\nComponent design considerations for consumer electronics devices (i.e.\,smartphones\, tablets\, watches\, earbuds\, and digital cameras)\nAnsys Maxwell solution for EM component design\nNew Maxwell capabilities for PCB and ECAD\nMultiphysics workflows for coupling EM with structural/kinematic\, NVH\, and thermal for comprehensive product design\n\nWho should attend?\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeakers\nIrene Woyna
URL:https://marketingeda.com/event/power-innovations-in-consumer-electronics-using-lf-em-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T110000
DTSTAMP:20240122T184006Z
CREATED:20240122T183940Z
LAST-MODIFIED:20240122T184006Z
UID:7546-1707386400-1707390000@marketingeda.com
SUMMARY:Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
DESCRIPTION:Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed\, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process\, leading to faster signoff of designs. With analysis shifting left in the design cycle\, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks\, gigabit-speed serializer/deserializer (SerDes)\, and the latest double-data rate (DDR) memory interfaces. \nLearn about three key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes)\, power analysis\, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology\, including Sigrity Aurora\, Sigrity SystemSI\, and Allegro technologies\, empowers EEs to create successful products on time and on budget.\nAttendees will learn to address: \n\nSerDes compliance\nPower analysis\nDDR memory interface compliance
URL:https://marketingeda.com/event/seamless-si-pi-signoff-of-allegro-pcb-designs-driven-by-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T103000
DTSTAMP:20240118T213134Z
CREATED:20240118T213134Z
LAST-MODIFIED:20240118T213134Z
UID:7526-1707386400-1707388200@marketingeda.com
SUMMARY:Power Devices SPICE Modeling for Si\, GaN and SiC Technologies
DESCRIPTION:We start by examining the different technologies used in the manufacturing of power devices\, including Si\, GaN\, and SiC\, considering their respective particularities and advantages.\nWe will then analyze various approaches to the SPICE modeling of power devices\, including compact models and macromodels.\nA significant portion of our presentation will be dedicated to the topic of power FET modeling. In particular we will illustrate how to properly address its specific bias-dependent capacitances and how to deal with model tuning based on dynamic characteristics.\nFinally\, we will share some of our expertise in dealing with the unique challenges of power devices\, including parasitic elements and model accuracy. \nWhat You Will Learn\n\nSPICE models for GaN and SiC FET\nModeling power FET-specific capacitances\nGeneral power FET model extraction methodology\nAdvantages of TCAD-based SPICE modeling\nSPICE modeling examples of Si\, GaN\, and SiC devices\n\n\n\n\n\n\nPresenter\n\n\n\n\nBogdan Tudor\, Senior Manager\, Device Characterization \nBogdan Tudor is Head of Device Characterization for Silvaco\, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/power-devices-spice-modeling-for-si-gan-and-sic-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240207T090000
DTEND;TZID=America/New_York:20240207T100000
DTSTAMP:20240202T014858Z
CREATED:20240202T014858Z
LAST-MODIFIED:20240202T014858Z
UID:7571-1707296400-1707300000@marketingeda.com
SUMMARY:Design Exploration of RF GaN Amplifier\, 3D Packaging\, and Thermal Analysis
DESCRIPTION:Join us for this webinar on RF GaN amplifier design using electromagnetic/thermal 3D solvers. We will discuss the step-by-step process of building a GaN amplifier\, beginning with the transistor model in the circuit simulator. The webinar will outline the steps required to convert this to a physical layout for electromagnetic simulation and verification while integrating packaging and thermal effects co-simulation to analyze a complete packaged system. Discover how this comprehensive approach yields innovative solutions\, important design insights\, and their potential impact on packaged performance. \nTime:\nFebruary 7\, 2024\n9 AM EST / 3 PM CET / 7:30 PM IST \nVenue:\nDigital
URL:https://marketingeda.com/event/design-exploration-of-rf-gan-amplifier-3d-packaging-and-thermal-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Feb-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240206T100000
DTEND;TZID=America/Los_Angeles:20240206T110000
DTSTAMP:20240116T175320Z
CREATED:20240116T175320Z
LAST-MODIFIED:20240116T175320Z
UID:7520-1707213600-1707217200@marketingeda.com
SUMMARY:Functional Verification workflow for Trusted and Assured Microelectronics
DESCRIPTION:In a world of increasing trust and assurance challenges for microelectronic devices\, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies\, built upon a foundation of world-class simulation and formal engines\, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs. In this presentation\, we will introduce apps that provide advanced automated functional checking\, secure data path verification\, trustworthiness assessment\, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today. \n  \nWhat You Will Learn: \n\nHow to identify security threats and vulnerabilities in your ASIC/FPGA microelectronic designs\nHow to identify and mitigate Common Weakness Enumeration (CWE) threats in your ASIC/FPGA designs\nHow to meet reporting requirements for your Trust and Assurance verification\n\nWho Should Attend: \n\nHardware Assurance & Security Experts\nSystems Engineers\nASIC\, FPGA & Program Manager\nDesign & Verification Engineers\n\n  \nWhat/Which Products are Covered:  \n\nQuesta Inspect\nQuesta Verify Secure\nQuesta Verify Trust\nQuesta Equivalent FPGA\n\n\n\nSpeaker:\n\n\n\n\n\n\nJohn Hallman\nAerospace and Defense Solutions Manager\, Siemens EDA\n\n\n\n\nMr. John Hallman is the Aerospace and Defense Solutions Manager with Siemens EDA focusing on verification workflows for A&D customers. His experience spans multiple defense industrial base organizations and EDA companies and includes ASIC/FPGA design\, verification\, application of formal technologies\, and microelectronics trustworthiness research. Today his responsibilities include enabling the development of automated tools for Trust and Assurance\, as well as enhancing productivity for the defense workforce. John is active in several organizations\, such as SAE\, IEEE\, and NDIA\, and has interests in numerous standards activities that raise the bar for microelectronic trust\, assurance and security.
URL:https://marketingeda.com/event/functional-verification-workflow-for-trusted-and-assured-microelectronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240206T090000
DTEND;TZID=America/New_York:20240206T180000
DTSTAMP:20240129T191342Z
CREATED:20240129T191342Z
LAST-MODIFIED:20240129T191342Z
UID:7559-1707210000-1707242400@marketingeda.com
SUMMARY:Canada's Semiconductor Summit
DESCRIPTION:Help build Canada’s role in North America’s integrated semiconductor supply chain.\n\n\nFeaturing key industry and government decision-makers from Canada\, the United States\, and international jurisdictions\, your insights at this by-invitation-only event will help us build an effective action plan. The summit will establish priorities and define opportunities to accelerate the growth\, development\, and competitiveness of Canada’s semiconductor sector. \n\nProgram\n\n\n9-9:10 AM Welcome & Introductory Remarks \nMC:  Ruth Rayman\, former Director General\, Advanced Electronics and Photonics Research Centre\, NRC \n\n\n\n\n\n9:10-9:30 AM An Unprecedented Global Recalibration \nSemiconductors are the backbone of the digital economy. As an integrated North American semiconductor supply chain takes shape\, Canada has the opportunity to transform existing\, discrete areas of expertise into a coherent offering\, forge new collaborations and maximize new markets. \nKey topics: \n\nLay of the land\, threats and opportunities etc.\n\nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n9:30-10:45 AM Automotive\, EVs\, and Batteries: Amplifying Our Strengths \nCanada is creating a world class EV supply chain with OEMs and electrification sub-systems. Semiconductors lie at the heart of the 21st century automobile. How can Canada play a larger role in the semiconductor supply chain for EVs? What are the short and long-term opportunities? \nKey topics: \n\nWhat is the size of the automotive semiconductor market in Canada? What is its impact on the automotive manufacturing ecosystem in Canada?\nEV sub-systems: which is the best sub-system to target for Canada to grow the auto semiconductor ecosystem?\nHow can semiconductors complement the increasing investment in EV manufacturing in Canada in the future?\n\nModerator: Kirk Ouellette\,  Vice President\, Strategy Development and Strategic Marketing\, STMicroelectronics \nPanelists: \n\nAndrea Tranchida\, Vice President\, Global Automotive Solutions\, NXP Semiconductors\nBenoit Rousseau\, Vice President – GaN Automotive\, Infineon Technologies\nDaniel Boisvert\, Director of Business Development\, C-MAC Electronics Solutions\nMona Eghanian\, Assistant Vice President\, OVIN\n\n\n\n\n\n\n10:45-11 AM Break \nNetworking and refreshments. \n\n\n\n\n\n11 AM-12:15 PM Advanced Technologies: Leveraging Canadian Capabilities \nCanada needs to strategically leverage existing areas of strength and promising new advanced technologies to integrate with critical capabilities into the global semiconductor supply chain. What future-looking technologies are worth pursuing? What is the market telling us—and what criteria should guide our investments?  \nKey topics: \n\nPhotonics/RF\nAI\nSensors\nCompound semiconductors\nQuantum computing\n\nModerator: Duncan Stewart\, Partner\, Deep Tech Venture Fund\, BDC \nPanelists: \n\nJon Rogers\, Co-founder and SVP Engineering\, Alphawave Semi\nI-Cheng Chen\, Fellow\, Platform Architecture\, AMD Canada\nIgor Arsovski\, Head of Silicon\, Fellow\, Groq\nJim Hjartarson\, President and COO\, Inpho\n\n\n\n\n\n\n12:15-1:15 PM Catered buffet lunch with guest speaker \nSilicon Valley legend\, John East\, former CEO of Actel\, and veteran of AMD and Fairchild Semiconductor\, remembers those formative\, chaotic years in Silicon Valley—and the analogies in Canada today. \nSpeaker: John East\, Chairman of the Board\, SPARK Microsystems \n\n\n\n\n\n1:15-2:30 PM Building a Competitive Semiconductor Ecosystem: Harnessing an Economic Juggernaut \nSilicon Valley\, Taiwan\, South Korea\, Saxony\, IMEC\, Albany etc. Not every successful tech ecosystem has to adhere to the same model. What can Canada learn from successful semiconductor ecosystems? What relationships need to be established with key US hubs? How should the private sector\, academia and government collaborate? \nKey topics: \n\nEcosystem overview\nWhat gave the stimulus to get it off the ground?\nWhat’s the private/government split?\n\nModerator: Normand Bourbonnais\, Président Directeur Général\, Technum Québec \nPanelists: \n\nLode Lauwers\, SVP\, Business Development & Sales\, IMEC\nMarie-Josée Turgeon\, Présidente – Directrice générale\, C2MI\nLaMar Hill\, Director\, NY Creates\nCharles Sturman\, CEO\, TechWorks\n\n\n\n\n\n\n2:30-2:45 PM Break \nNetworking and refreshments. \n\n\n\n\n\n2:45-4PM The Talent Question: Building the Pipeline \nThe semiconductor workforce must double to an estimated half a million people to meet the demands of North American semiconductor reshoring. What mix of training\, apprenticeship programs\, immigration\, financial incentives\, and creative retention strategies will build the pipeline for Canada? \nKey topics: \n\nTraining programs\nImmigration\nFinancial incentives\nApprenticeship programs\nFunding university Chairs\nRetention\nBrain drain\n\nModerator: Dr. Tony Chan Carusone\, CTO\, Alphawave Semi \nPanelists: \n\nDino Toffolon\, SVP of Engineering-Interface IP\, Synopsys\nKate Alcott\, Director of Workforce Programs\, NY Creates\nSylvain Charbonneau\, Vice-President\, Research and Innovation\, University of Ottawa\nArvind Gupta\, Professor at Department of Computer Science\, University of Toronto\n\n\n\n\n\n\n4-5 PM Strategic Initiatives and Next Steps for 2024: Making It Happen \nCanada has a powerful opportunity to establish itself as new niches emerge across the North American corridor. But we need to act fast.  Regional hubs have formed this year and are actively forging new partnerships and market plays.  How can we  ensure Canadian technology and expertise accesses these burgeoning markets?   \nKey topics: \n\nCSC 2024 Federal Budget Proposal\nAnnounced proposals ie. CSC\, FABrIC\, SECTR etc.\nFinancing growth\nPrivate-public partnerships\n\nModerator: Chris Ouslis\, Industrial Technology Advisor\, NRC \nPanelists: \n\nGord Harling\, President & CEO\, CMC Microsystems\nClaude Jean\, Executive Vice President\, Strategy & Partnership\, Teledyne Digital\nVelko Tzolov\, Director General\, Canadian Photonics Fabrication Centre (CPFC)\nDr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council\n\n\n\n\n\n\n5-5:30 PM Wrap Up & Closing Remarks \nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n5:30-6:30 PM Networking Reception \nNetworking and refreshments.
URL:https://marketingeda.com/event/canadas-semiconductor-summit/
LOCATION:Brookstreet Hotel\, 525 Leggett Drive\, Ottawa\, Canada
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Canada-Semi-Summit-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240131T183000
DTEND;TZID=America/Los_Angeles:20240131T210000
DTSTAMP:20231212T174026Z
CREATED:20231212T173907Z
LAST-MODIFIED:20231212T174026Z
UID:7163-1706725800-1706734800@marketingeda.com
SUMMARY:Signal & Power Integrity Special Interest Group
DESCRIPTION:Dear SIPI Engineer\, \nAs a member of the engineering community\, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. \nThis event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will provide the opportunity for networking and interactive discussion with other SIPI engineers to exchange ideas and strategies on signal and power integrity challenges and solutions. \nWe will offer Synopsys and partner product demonstrations during our cocktail hour\, followed by a sit-down dinner with invited guest speakers and conclude with a panel discussion. Stay to the end for a chance to win a raffle prize! \nWe are excited to see you in-person once again. Please be sure to reserve your spot today as seating is limited.
URL:https://marketingeda.com/event/signal-power-integrity-special-interest-group/
LOCATION:Hilton Santa Clara\, 4949 Great America Parkway\, Santa Clara\, CA\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-January-31-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240130T080000
DTEND;TZID=America/Los_Angeles:20240201T170000
DTSTAMP:20231212T172849Z
CREATED:20231212T172135Z
LAST-MODIFIED:20231212T172849Z
UID:7160-1706601600-1706806800@marketingeda.com
SUMMARY:DesignCon 2024
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers\n\n\n\n\nDesignCon is the premier high-speed communications and system design conference and exposition\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. \n\n\n40 Under 40\n\n\n\n\nCalling all Emerging Engineers and Leaders! \nDesignCon’s 40 Under 40 program launches in 2024 and provides an opportunity for up-and-coming engineers to further their careers through access to DesignCon’s full conference education\, including 14 tracks plus DesignCon’s automotive-focused Drive World conference. \n\nNominate yourself or a fellow engineer. Those accepted receive a complimentary Education Pass plus access to an exclusive networking breakfast with leading engineers and mentors.  Deadline: 12/14/23.   \n» Click here to learn more. \n\n\nThe Conference – A Systematic Approach to Learning & Discovery\n\n\n\n\nAttend the expertly curated 14-track conference created by engineers for engineers featuring technical paper sessions\, tutorials\, and industry panels covering all aspects of chip\, board\, and systems design. \n\n\nThe Expo – Take Your Electronic Design Expertise to the Next Level at DesignCon\n\n\n\n\nBrowse exhibits with hundreds of new products and technologies in the expo hall\, attend educational sessions in the Chiphead Theater\, see interactive demos\, and network with high-caliber industry professionals at multiple social functions. \n\n\nExpanded Drive World Conference Track and Exhibits\n\n\n\n\nDrive World expands in 2024 to support electric vehicle technology in addition to sessions in the areas of automotive electronics and intelligence\, as engineers prepare for unprecedented growth in an automotive electronics market forecast to see revenue surge more 37% 2023-2027. Accelerate the path to autonomous and electric vehicles by attending the Drive World conference track with education on advancing automotive tech. \nNew in 2024 — the Advanced Automotive section of the expo floor highlighting advanced automotive electronics suppliers focused on the autonomous\, EV and energy-storage markets. \n\n\nEngineer of the Year\n\n\n\n\nDesignCon’s “Engineer of the Year” Award is given out each year during the DesignCon event. The award seeks to recognize the best of the best in engineering and new product advancements at the chip\, board\, or system level. \nThe award winner is selected based on his or her leadership\, creativity\, and out-of-the-box thinking brought to design/test of chips\, boards\, or systems\, with particular attention paid to areas of signal and power integrity. \nVoting to choose the 2024 Engineer of the Year is now open. \nCast your vote for the finalist who you feel should be the DesignCon 2024 Engineer of the Year. Voting ends December 19 at noon Pacific. \n» Click to the ballot \nRead about all 5 finalists on Design News
URL:https://marketingeda.com/event/designcon-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T110000
DTEND;TZID=America/Los_Angeles:20240125T120000
DTSTAMP:20240122T173407Z
CREATED:20240122T173407Z
LAST-MODIFIED:20240122T173407Z
UID:7533-1706180400-1706184000@marketingeda.com
SUMMARY:Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
DESCRIPTION:AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract\, review and statically verify AXI bus interfaces. In addition\, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects\, Aldec provides FPGA vendor-agnostic AXI Bus Functional Models (BFM) as well as Riviera-PRO functional verification platform. \nIn this webinar\, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then\, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally\, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification. \nAgenda: \n\nBus interfaces extraction\nBus interfaces static verification \nTest harness development (script-based) \nAldec AXI BFM overview\nDynamic verification of AXI interconnect design using Aldec AXI BFM and Riviera-PRO\nLive demo\nConclusion\nQ&A\n\nWebinar Duration \n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n\nBio: \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/verifying-axi-interconnects-with-alint-pro-and-riviera-pro/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-January-252024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T100000
DTEND;TZID=America/Los_Angeles:20240125T110000
DTSTAMP:20240111T184907Z
CREATED:20240111T184907Z
LAST-MODIFIED:20240111T184907Z
UID:7512-1706176800-1706180400@marketingeda.com
SUMMARY:Validating Clarity 3D Solver Accuracy Through Measurement Correlation
DESCRIPTION:Cadence’s Clarity 3D Solver is an industry-leading EM simulation platform used by hundreds of design teams to address signal and power integrity (SI/PI) challenges. By solving bigger problems on more efficient compute resources\, Clarity 3D Solver users have reimagined what can be done with 3D finite element method (FEM) solver technology. However\, EM extraction results to 50GHz and beyond require correlation to lab measurement. \n\nThis webinar presents a case study that shares the experience and best practices for achieving measurement-to-simulation correlation with Clarity based on the Wild River CMP-50 IEEE P370 compliant test fixture\, where lab measurements have been taken from DC to 50GHz. Topics covered include material property identification\, correlation challenges\, the influence of connector models\, manufacturing tolerance/variation\, and more. \n\nThe audience will learn: \n\nBest practices for using Clarity to achieve measurement-to-simulation correlation\nCase study using the Wild River CMP-50 IEEE P370 compliant test fixture with lab measurements from DC to 50GHz\nExplanation of material property identification\, correlation challenges\, influence of connector models\, manufacturing tolerance/variation\, and more
URL:https://marketingeda.com/event/validating-clarity-3d-solver-accuracy-through-measurement-correlation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240124T090000
DTEND;TZID=America/Los_Angeles:20240124T100000
DTSTAMP:20240117T174723Z
CREATED:20240117T174723Z
LAST-MODIFIED:20240117T174723Z
UID:7523-1706086800-1706090400@marketingeda.com
SUMMARY:Introducing OrCAD X\, Our Next-Generation PCB Layout Solution
DESCRIPTION:Whether you’re a beginner or a seasoned engineer\, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. \n\nLearn how you can: \n\nDesign with an intuitive UI\nCollaborate using design review and markup\nUse the new and improved 3D engine\nVisualize and set up of 3D DRCs\nSet up and navigate to flex regions\nUse dynamic shapes\nSave time generating manufacturing documentation with LiveDOC\n\n\nSpeaker: John Carney\, Product Engineering Architect\, Cadence \nHost: Supreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/introducing-orcad-x-our-next-generation-pcb-layout-solution/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Cadence-January-24-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240124T080000
DTEND;TZID=Asia/Tokyo:20240126T170000
DTSTAMP:20231227T195553Z
CREATED:20231227T195553Z
LAST-MODIFIED:20231227T195553Z
UID:7462-1706083200-1706288400@marketingeda.com
SUMMARY:Automotive World 2024
DESCRIPTION:Combination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics\, connected car\, autonomous driving\, EV/HV/FCV\, lightweight\, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. \n\n1\,650 Exhibitors\n85\,000 Visitors\n170 Speakers
URL:https://marketingeda.com/event/automotive-world-2024/
LOCATION:Tokyo Big Sight\, 3 Choe-11-1 Ariake\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Automotive-World-2024.jpg
END:VEVENT
END:VCALENDAR