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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240220T150000
DTEND;TZID=Asia/Kolkata:20240220T170000
DTSTAMP:20240122T182008Z
CREATED:20240122T181727Z
LAST-MODIFIED:20240122T182008Z
UID:7542-1708441200-1708448400@marketingeda.com
SUMMARY:DVClub India - Using AI/ML in Design Verification
DESCRIPTION:This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. \nVenue – Cadence Design System\, Bengaluru & Online\n\n\n\nTime\nSession\n\n\n15:00 GMT\nWelcome and introduction – Mike Bartley\, Tessolve\n\n\n15:00 GMT\nCadence\n\n\n16:00 GMT\nTessolve\n\n\n16:30 GMT\nTBD\n\n\n17:00 GMT\nClose\n\n\n\nAbout DVClub\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/dvclub-india-using-ai-ml-in-design-verification/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-February-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240220T080000
DTEND;TZID=America/Los_Angeles:20240220T090000
DTSTAMP:20240216T185704Z
CREATED:20240216T185704Z
LAST-MODIFIED:20240216T185704Z
UID:7621-1708416000-1708419600@marketingeda.com
SUMMARY:SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
DESCRIPTION:The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power\, performance\, area\, and yield\, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process\, voltage\, and temperature corners\, as well as local variation. \nWhere traditional brute-force Monte Carlo solutions are insufficient to scale to meet these escalating design requirements\, an effective SPICE-level verification methodology can provide a robust solution to meet these growing demands in shorter design and verification cycles. \nI invite you to join me in this webinar\, where we’ll delve into the evolving challenges of variation-aware verification in IC design\, uncover the most effective best practices\, and explore how a methodology leveraging Solido Design Environment’s AI technologies can enhance SPICE-level variation-aware verification\, accelerating verification runtime while enhancing coverage and accuracy. \nWhat you will learn:\nIn this masterclass you’ll gain a comprehensive understanding of design variations and effective techniques to manage them. Explore Solido Design Environment’s AI-powered tools\, and discover how they streamline design verification\, ensuring improved speed and accuracy. \nFeatured Products: Solido Design Environment \nSpeaker:\n\nMohamed Atoua\nProduct Manager\, Siemens EDA \nMohamed Atoua is a Product Manager for Solido Design Environment at Siemens EDA with more than 7 years of experience in the EDA industry. With a track record of blending technical solutions with business acumen\, his current mission is to help circuit designers address the challenges of meeting higher design complexity faster with less effort through Siemens’ Solido Design Environment software. \nHis journey began at Cairo University\, where he earned a bachelor’s degree in electrical engineering\, specializing in electronics with a minor in computer engineering. Atoua is currently pursuing his master’s degree in business administration at the University of Illinois Urbana-Champaign\, he thrives at the intersection of technology and management.
URL:https://marketingeda.com/event/spice-accurate-variation-aware-verification-best-practices-with-solido-ai-powered-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240218T080000
DTEND;TZID=America/Los_Angeles:20240222T170000
DTSTAMP:20231230T004304Z
CREATED:20231230T004304Z
LAST-MODIFIED:20231230T004304Z
UID:7483-1708243200-1708621200@marketingeda.com
SUMMARY:ISSCC 2024
DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts.
URL:https://marketingeda.com/event/isscc-2024/
LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240215T110000
DTEND;TZID=America/Los_Angeles:20240215T120000
DTSTAMP:20240202T185233Z
CREATED:20240202T185233Z
LAST-MODIFIED:20240202T185233Z
UID:7574-1707994800-1707998400@marketingeda.com
SUMMARY:Essential Steps to Simplify VHDL Testbenches Using OSVVM
DESCRIPTION:This “Getting Started” webinar focuses on the first\, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing\, self-checking tests\, messaging\, reports\, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. \n  \nThe “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development\, increase reuse\, and reduce maintenance costs. \n  \nSelf-checking is essential in test cases as checking waveform output manually is time consuming\, error prone\, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection\, some of which might be in a different entity) we will need to sum them up and generate an error report. However\, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. \n  \nMessaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities\, we need controls that have a wide scope. Furthermore\, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. \n  \nTest reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run\, and the OSVVM test case report provides details on the self-checking\, functional coverage\, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing)\, these reports help us quickly find which test cases failed and why. \n  \nThe OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation\, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. \n  \nAbout OSVVM \nOSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex\, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.\nGetting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. \n  \nWebinar Duration: \n\n45 min presentation/live demo\n10 min Q&A\n\n  \nPresenter BIO \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and spacecraft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/essential-steps-to-simplify-vhdl-testbenches-using-osvvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Oslo:20240214T080000
DTEND;TZID=Europe/Oslo:20240215T170000
DTSTAMP:20240209T180613Z
CREATED:20240209T180613Z
LAST-MODIFIED:20240209T180613Z
UID:7599-1707897600-1708016400@marketingeda.com
SUMMARY:FPGA Forum 2024 - Norway
DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication.
URL:https://marketingeda.com/event/fpga-forum-2024-norway/
LOCATION:Royal Garden\, Trondheim\, Norway
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240213T110000
DTEND;TZID=America/New_York:20240213T120000
DTSTAMP:20240206T191819Z
CREATED:20240206T191819Z
LAST-MODIFIED:20240206T191819Z
UID:7581-1707822000-1707825600@marketingeda.com
SUMMARY:Introducing Ansys AI: A New Chapter in Engineering Simulation
DESCRIPTION:Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We’re revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI\, AnsysGPT\, and Ansys AI+. \nOverview\nAt Ansys\, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer\, bringing unprecedented speed\, innovation\, and accessibility to the engineering world. With Ansys AI\, we enable product engineers to leverage their previous simulation and measurement data to reliably assess the performance of new designs in minutes instead of hours. We are not just accelerating simulations but transforming how engineers work\, making simulation simple\, natural\, and accessible. \nWhat you will learn\n\nFirst\, we’ll introduce Ansys SimAI\, a machine learning platform for engineers who must rapidly explore and predict the performance of new concepts across design phases. SimAI provides reliable and fast results\, accessible through user-friendly cloud-native application\, targeting a broad engineering audience that includes all simulation engineers and designers.\nSecond\, we’ll showcase the AnsysGPT chatbot\, which re-imagines the user and support experience through simple\, natural language interaction.\nFinally\, we’ll demonstrate how Ansys AI+ add-ons augment the product capabilities across the Ansys collection\, starting with optiSLang AI+ and Granta MI AI+.\n\nWho should attend\nCAE/CAD Engineers / Designers / Simulation Analyst / Engineers\, Computation Engineers \nSpeaker\nIlya Tolchinsky
URL:https://marketingeda.com/event/introducing-ansys-ai-a-new-chapter-in-engineering-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240213T100000
DTEND;TZID=Europe/Paris:20240213T110000
DTSTAMP:20240205T215030Z
CREATED:20240205T215030Z
LAST-MODIFIED:20240205T215030Z
UID:7578-1707818400-1707822000@marketingeda.com
SUMMARY:Power Innovations in Consumer Electronics Using LF EM Solutions
DESCRIPTION:This webinar will cover how the Ansys simulation tools are now widely used in many low-frequency (LF) EM applications\, such as wireless charging\, power supplies\, transformers\, magnetic latches and actuators\, PCB/ECAD\, and more. Discover how Ansys Maxwell enables rapid and accurate simulation of EM fields in electronic and consumer devices to reduce design iterations\, component footprint\, size\, and time to market. \n\n\n\n\nWhat You Will Learn\n\nComponent design considerations for consumer electronics devices (i.e.\,smartphones\, tablets\, watches\, earbuds\, and digital cameras)\nAnsys Maxwell solution for EM component design\nNew Maxwell capabilities for PCB and ECAD\nMultiphysics workflows for coupling EM with structural/kinematic\, NVH\, and thermal for comprehensive product design\n\nWho should attend?\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeakers\nIrene Woyna
URL:https://marketingeda.com/event/power-innovations-in-consumer-electronics-using-lf-em-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T110000
DTSTAMP:20240122T184006Z
CREATED:20240122T183940Z
LAST-MODIFIED:20240122T184006Z
UID:7546-1707386400-1707390000@marketingeda.com
SUMMARY:Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
DESCRIPTION:Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed\, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process\, leading to faster signoff of designs. With analysis shifting left in the design cycle\, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks\, gigabit-speed serializer/deserializer (SerDes)\, and the latest double-data rate (DDR) memory interfaces. \nLearn about three key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes)\, power analysis\, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology\, including Sigrity Aurora\, Sigrity SystemSI\, and Allegro technologies\, empowers EEs to create successful products on time and on budget.\nAttendees will learn to address: \n\nSerDes compliance\nPower analysis\nDDR memory interface compliance
URL:https://marketingeda.com/event/seamless-si-pi-signoff-of-allegro-pcb-designs-driven-by-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T103000
DTSTAMP:20240118T213134Z
CREATED:20240118T213134Z
LAST-MODIFIED:20240118T213134Z
UID:7526-1707386400-1707388200@marketingeda.com
SUMMARY:Power Devices SPICE Modeling for Si\, GaN and SiC Technologies
DESCRIPTION:We start by examining the different technologies used in the manufacturing of power devices\, including Si\, GaN\, and SiC\, considering their respective particularities and advantages.\nWe will then analyze various approaches to the SPICE modeling of power devices\, including compact models and macromodels.\nA significant portion of our presentation will be dedicated to the topic of power FET modeling. In particular we will illustrate how to properly address its specific bias-dependent capacitances and how to deal with model tuning based on dynamic characteristics.\nFinally\, we will share some of our expertise in dealing with the unique challenges of power devices\, including parasitic elements and model accuracy. \nWhat You Will Learn\n\nSPICE models for GaN and SiC FET\nModeling power FET-specific capacitances\nGeneral power FET model extraction methodology\nAdvantages of TCAD-based SPICE modeling\nSPICE modeling examples of Si\, GaN\, and SiC devices\n\n\n\n\n\n\nPresenter\n\n\n\n\nBogdan Tudor\, Senior Manager\, Device Characterization \nBogdan Tudor is Head of Device Characterization for Silvaco\, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/power-devices-spice-modeling-for-si-gan-and-sic-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240207T090000
DTEND;TZID=America/New_York:20240207T100000
DTSTAMP:20240202T014858Z
CREATED:20240202T014858Z
LAST-MODIFIED:20240202T014858Z
UID:7571-1707296400-1707300000@marketingeda.com
SUMMARY:Design Exploration of RF GaN Amplifier\, 3D Packaging\, and Thermal Analysis
DESCRIPTION:Join us for this webinar on RF GaN amplifier design using electromagnetic/thermal 3D solvers. We will discuss the step-by-step process of building a GaN amplifier\, beginning with the transistor model in the circuit simulator. The webinar will outline the steps required to convert this to a physical layout for electromagnetic simulation and verification while integrating packaging and thermal effects co-simulation to analyze a complete packaged system. Discover how this comprehensive approach yields innovative solutions\, important design insights\, and their potential impact on packaged performance. \nTime:\nFebruary 7\, 2024\n9 AM EST / 3 PM CET / 7:30 PM IST \nVenue:\nDigital
URL:https://marketingeda.com/event/design-exploration-of-rf-gan-amplifier-3d-packaging-and-thermal-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Feb-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240206T100000
DTEND;TZID=America/Los_Angeles:20240206T110000
DTSTAMP:20240116T175320Z
CREATED:20240116T175320Z
LAST-MODIFIED:20240116T175320Z
UID:7520-1707213600-1707217200@marketingeda.com
SUMMARY:Functional Verification workflow for Trusted and Assured Microelectronics
DESCRIPTION:In a world of increasing trust and assurance challenges for microelectronic devices\, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies\, built upon a foundation of world-class simulation and formal engines\, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs. In this presentation\, we will introduce apps that provide advanced automated functional checking\, secure data path verification\, trustworthiness assessment\, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today. \n  \nWhat You Will Learn: \n\nHow to identify security threats and vulnerabilities in your ASIC/FPGA microelectronic designs\nHow to identify and mitigate Common Weakness Enumeration (CWE) threats in your ASIC/FPGA designs\nHow to meet reporting requirements for your Trust and Assurance verification\n\nWho Should Attend: \n\nHardware Assurance & Security Experts\nSystems Engineers\nASIC\, FPGA & Program Manager\nDesign & Verification Engineers\n\n  \nWhat/Which Products are Covered:  \n\nQuesta Inspect\nQuesta Verify Secure\nQuesta Verify Trust\nQuesta Equivalent FPGA\n\n\n\nSpeaker:\n\n\n\n\n\n\nJohn Hallman\nAerospace and Defense Solutions Manager\, Siemens EDA\n\n\n\n\nMr. John Hallman is the Aerospace and Defense Solutions Manager with Siemens EDA focusing on verification workflows for A&D customers. His experience spans multiple defense industrial base organizations and EDA companies and includes ASIC/FPGA design\, verification\, application of formal technologies\, and microelectronics trustworthiness research. Today his responsibilities include enabling the development of automated tools for Trust and Assurance\, as well as enhancing productivity for the defense workforce. John is active in several organizations\, such as SAE\, IEEE\, and NDIA\, and has interests in numerous standards activities that raise the bar for microelectronic trust\, assurance and security.
URL:https://marketingeda.com/event/functional-verification-workflow-for-trusted-and-assured-microelectronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240206T090000
DTEND;TZID=America/New_York:20240206T180000
DTSTAMP:20240129T191342Z
CREATED:20240129T191342Z
LAST-MODIFIED:20240129T191342Z
UID:7559-1707210000-1707242400@marketingeda.com
SUMMARY:Canada's Semiconductor Summit
DESCRIPTION:Help build Canada’s role in North America’s integrated semiconductor supply chain.\n\n\nFeaturing key industry and government decision-makers from Canada\, the United States\, and international jurisdictions\, your insights at this by-invitation-only event will help us build an effective action plan. The summit will establish priorities and define opportunities to accelerate the growth\, development\, and competitiveness of Canada’s semiconductor sector. \n\nProgram\n\n\n9-9:10 AM Welcome & Introductory Remarks \nMC:  Ruth Rayman\, former Director General\, Advanced Electronics and Photonics Research Centre\, NRC \n\n\n\n\n\n9:10-9:30 AM An Unprecedented Global Recalibration \nSemiconductors are the backbone of the digital economy. As an integrated North American semiconductor supply chain takes shape\, Canada has the opportunity to transform existing\, discrete areas of expertise into a coherent offering\, forge new collaborations and maximize new markets. \nKey topics: \n\nLay of the land\, threats and opportunities etc.\n\nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n9:30-10:45 AM Automotive\, EVs\, and Batteries: Amplifying Our Strengths \nCanada is creating a world class EV supply chain with OEMs and electrification sub-systems. Semiconductors lie at the heart of the 21st century automobile. How can Canada play a larger role in the semiconductor supply chain for EVs? What are the short and long-term opportunities? \nKey topics: \n\nWhat is the size of the automotive semiconductor market in Canada? What is its impact on the automotive manufacturing ecosystem in Canada?\nEV sub-systems: which is the best sub-system to target for Canada to grow the auto semiconductor ecosystem?\nHow can semiconductors complement the increasing investment in EV manufacturing in Canada in the future?\n\nModerator: Kirk Ouellette\,  Vice President\, Strategy Development and Strategic Marketing\, STMicroelectronics \nPanelists: \n\nAndrea Tranchida\, Vice President\, Global Automotive Solutions\, NXP Semiconductors\nBenoit Rousseau\, Vice President – GaN Automotive\, Infineon Technologies\nDaniel Boisvert\, Director of Business Development\, C-MAC Electronics Solutions\nMona Eghanian\, Assistant Vice President\, OVIN\n\n\n\n\n\n\n10:45-11 AM Break \nNetworking and refreshments. \n\n\n\n\n\n11 AM-12:15 PM Advanced Technologies: Leveraging Canadian Capabilities \nCanada needs to strategically leverage existing areas of strength and promising new advanced technologies to integrate with critical capabilities into the global semiconductor supply chain. What future-looking technologies are worth pursuing? What is the market telling us—and what criteria should guide our investments?  \nKey topics: \n\nPhotonics/RF\nAI\nSensors\nCompound semiconductors\nQuantum computing\n\nModerator: Duncan Stewart\, Partner\, Deep Tech Venture Fund\, BDC \nPanelists: \n\nJon Rogers\, Co-founder and SVP Engineering\, Alphawave Semi\nI-Cheng Chen\, Fellow\, Platform Architecture\, AMD Canada\nIgor Arsovski\, Head of Silicon\, Fellow\, Groq\nJim Hjartarson\, President and COO\, Inpho\n\n\n\n\n\n\n12:15-1:15 PM Catered buffet lunch with guest speaker \nSilicon Valley legend\, John East\, former CEO of Actel\, and veteran of AMD and Fairchild Semiconductor\, remembers those formative\, chaotic years in Silicon Valley—and the analogies in Canada today. \nSpeaker: John East\, Chairman of the Board\, SPARK Microsystems \n\n\n\n\n\n1:15-2:30 PM Building a Competitive Semiconductor Ecosystem: Harnessing an Economic Juggernaut \nSilicon Valley\, Taiwan\, South Korea\, Saxony\, IMEC\, Albany etc. Not every successful tech ecosystem has to adhere to the same model. What can Canada learn from successful semiconductor ecosystems? What relationships need to be established with key US hubs? How should the private sector\, academia and government collaborate? \nKey topics: \n\nEcosystem overview\nWhat gave the stimulus to get it off the ground?\nWhat’s the private/government split?\n\nModerator: Normand Bourbonnais\, Président Directeur Général\, Technum Québec \nPanelists: \n\nLode Lauwers\, SVP\, Business Development & Sales\, IMEC\nMarie-Josée Turgeon\, Présidente – Directrice générale\, C2MI\nLaMar Hill\, Director\, NY Creates\nCharles Sturman\, CEO\, TechWorks\n\n\n\n\n\n\n2:30-2:45 PM Break \nNetworking and refreshments. \n\n\n\n\n\n2:45-4PM The Talent Question: Building the Pipeline \nThe semiconductor workforce must double to an estimated half a million people to meet the demands of North American semiconductor reshoring. What mix of training\, apprenticeship programs\, immigration\, financial incentives\, and creative retention strategies will build the pipeline for Canada? \nKey topics: \n\nTraining programs\nImmigration\nFinancial incentives\nApprenticeship programs\nFunding university Chairs\nRetention\nBrain drain\n\nModerator: Dr. Tony Chan Carusone\, CTO\, Alphawave Semi \nPanelists: \n\nDino Toffolon\, SVP of Engineering-Interface IP\, Synopsys\nKate Alcott\, Director of Workforce Programs\, NY Creates\nSylvain Charbonneau\, Vice-President\, Research and Innovation\, University of Ottawa\nArvind Gupta\, Professor at Department of Computer Science\, University of Toronto\n\n\n\n\n\n\n4-5 PM Strategic Initiatives and Next Steps for 2024: Making It Happen \nCanada has a powerful opportunity to establish itself as new niches emerge across the North American corridor. But we need to act fast.  Regional hubs have formed this year and are actively forging new partnerships and market plays.  How can we  ensure Canadian technology and expertise accesses these burgeoning markets?   \nKey topics: \n\nCSC 2024 Federal Budget Proposal\nAnnounced proposals ie. CSC\, FABrIC\, SECTR etc.\nFinancing growth\nPrivate-public partnerships\n\nModerator: Chris Ouslis\, Industrial Technology Advisor\, NRC \nPanelists: \n\nGord Harling\, President & CEO\, CMC Microsystems\nClaude Jean\, Executive Vice President\, Strategy & Partnership\, Teledyne Digital\nVelko Tzolov\, Director General\, Canadian Photonics Fabrication Centre (CPFC)\nDr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council\n\n\n\n\n\n\n5-5:30 PM Wrap Up & Closing Remarks \nSpeaker: Dr. C. Paul Slaby\, Managing Director\, Canada’s Semiconductor Council \n\n\n\n\n\n5:30-6:30 PM Networking Reception \nNetworking and refreshments.
URL:https://marketingeda.com/event/canadas-semiconductor-summit/
LOCATION:Brookstreet Hotel\, 525 Leggett Drive\, Ottawa\, Canada
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Canada-Semi-Summit-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240131T183000
DTEND;TZID=America/Los_Angeles:20240131T210000
DTSTAMP:20231212T174026Z
CREATED:20231212T173907Z
LAST-MODIFIED:20231212T174026Z
UID:7163-1706725800-1706734800@marketingeda.com
SUMMARY:Signal & Power Integrity Special Interest Group
DESCRIPTION:Dear SIPI Engineer\, \nAs a member of the engineering community\, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. \nThis event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will provide the opportunity for networking and interactive discussion with other SIPI engineers to exchange ideas and strategies on signal and power integrity challenges and solutions. \nWe will offer Synopsys and partner product demonstrations during our cocktail hour\, followed by a sit-down dinner with invited guest speakers and conclude with a panel discussion. Stay to the end for a chance to win a raffle prize! \nWe are excited to see you in-person once again. Please be sure to reserve your spot today as seating is limited.
URL:https://marketingeda.com/event/signal-power-integrity-special-interest-group/
LOCATION:Hilton Santa Clara\, 4949 Great America Parkway\, Santa Clara\, CA\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-January-31-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240130T080000
DTEND;TZID=America/Los_Angeles:20240201T170000
DTSTAMP:20231212T172849Z
CREATED:20231212T172135Z
LAST-MODIFIED:20231212T172849Z
UID:7160-1706601600-1706806800@marketingeda.com
SUMMARY:DesignCon 2024
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers\n\n\n\n\nDesignCon is the premier high-speed communications and system design conference and exposition\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. \n\n\n40 Under 40\n\n\n\n\nCalling all Emerging Engineers and Leaders! \nDesignCon’s 40 Under 40 program launches in 2024 and provides an opportunity for up-and-coming engineers to further their careers through access to DesignCon’s full conference education\, including 14 tracks plus DesignCon’s automotive-focused Drive World conference. \n\nNominate yourself or a fellow engineer. Those accepted receive a complimentary Education Pass plus access to an exclusive networking breakfast with leading engineers and mentors.  Deadline: 12/14/23.   \n» Click here to learn more. \n\n\nThe Conference – A Systematic Approach to Learning & Discovery\n\n\n\n\nAttend the expertly curated 14-track conference created by engineers for engineers featuring technical paper sessions\, tutorials\, and industry panels covering all aspects of chip\, board\, and systems design. \n\n\nThe Expo – Take Your Electronic Design Expertise to the Next Level at DesignCon\n\n\n\n\nBrowse exhibits with hundreds of new products and technologies in the expo hall\, attend educational sessions in the Chiphead Theater\, see interactive demos\, and network with high-caliber industry professionals at multiple social functions. \n\n\nExpanded Drive World Conference Track and Exhibits\n\n\n\n\nDrive World expands in 2024 to support electric vehicle technology in addition to sessions in the areas of automotive electronics and intelligence\, as engineers prepare for unprecedented growth in an automotive electronics market forecast to see revenue surge more 37% 2023-2027. Accelerate the path to autonomous and electric vehicles by attending the Drive World conference track with education on advancing automotive tech. \nNew in 2024 — the Advanced Automotive section of the expo floor highlighting advanced automotive electronics suppliers focused on the autonomous\, EV and energy-storage markets. \n\n\nEngineer of the Year\n\n\n\n\nDesignCon’s “Engineer of the Year” Award is given out each year during the DesignCon event. The award seeks to recognize the best of the best in engineering and new product advancements at the chip\, board\, or system level. \nThe award winner is selected based on his or her leadership\, creativity\, and out-of-the-box thinking brought to design/test of chips\, boards\, or systems\, with particular attention paid to areas of signal and power integrity. \nVoting to choose the 2024 Engineer of the Year is now open. \nCast your vote for the finalist who you feel should be the DesignCon 2024 Engineer of the Year. Voting ends December 19 at noon Pacific. \n» Click to the ballot \nRead about all 5 finalists on Design News
URL:https://marketingeda.com/event/designcon-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T110000
DTEND;TZID=America/Los_Angeles:20240125T120000
DTSTAMP:20240122T173407Z
CREATED:20240122T173407Z
LAST-MODIFIED:20240122T173407Z
UID:7533-1706180400-1706184000@marketingeda.com
SUMMARY:Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
DESCRIPTION:AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract\, review and statically verify AXI bus interfaces. In addition\, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects\, Aldec provides FPGA vendor-agnostic AXI Bus Functional Models (BFM) as well as Riviera-PRO functional verification platform. \nIn this webinar\, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then\, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally\, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification. \nAgenda: \n\nBus interfaces extraction\nBus interfaces static verification \nTest harness development (script-based) \nAldec AXI BFM overview\nDynamic verification of AXI interconnect design using Aldec AXI BFM and Riviera-PRO\nLive demo\nConclusion\nQ&A\n\nWebinar Duration \n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n\nBio: \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/verifying-axi-interconnects-with-alint-pro-and-riviera-pro/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-January-252024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T100000
DTEND;TZID=America/Los_Angeles:20240125T110000
DTSTAMP:20240111T184907Z
CREATED:20240111T184907Z
LAST-MODIFIED:20240111T184907Z
UID:7512-1706176800-1706180400@marketingeda.com
SUMMARY:Validating Clarity 3D Solver Accuracy Through Measurement Correlation
DESCRIPTION:Cadence’s Clarity 3D Solver is an industry-leading EM simulation platform used by hundreds of design teams to address signal and power integrity (SI/PI) challenges. By solving bigger problems on more efficient compute resources\, Clarity 3D Solver users have reimagined what can be done with 3D finite element method (FEM) solver technology. However\, EM extraction results to 50GHz and beyond require correlation to lab measurement. \n\nThis webinar presents a case study that shares the experience and best practices for achieving measurement-to-simulation correlation with Clarity based on the Wild River CMP-50 IEEE P370 compliant test fixture\, where lab measurements have been taken from DC to 50GHz. Topics covered include material property identification\, correlation challenges\, the influence of connector models\, manufacturing tolerance/variation\, and more. \n\nThe audience will learn: \n\nBest practices for using Clarity to achieve measurement-to-simulation correlation\nCase study using the Wild River CMP-50 IEEE P370 compliant test fixture with lab measurements from DC to 50GHz\nExplanation of material property identification\, correlation challenges\, influence of connector models\, manufacturing tolerance/variation\, and more
URL:https://marketingeda.com/event/validating-clarity-3d-solver-accuracy-through-measurement-correlation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240124T090000
DTEND;TZID=America/Los_Angeles:20240124T100000
DTSTAMP:20240117T174723Z
CREATED:20240117T174723Z
LAST-MODIFIED:20240117T174723Z
UID:7523-1706086800-1706090400@marketingeda.com
SUMMARY:Introducing OrCAD X\, Our Next-Generation PCB Layout Solution
DESCRIPTION:Whether you’re a beginner or a seasoned engineer\, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. \n\nLearn how you can: \n\nDesign with an intuitive UI\nCollaborate using design review and markup\nUse the new and improved 3D engine\nVisualize and set up of 3D DRCs\nSet up and navigate to flex regions\nUse dynamic shapes\nSave time generating manufacturing documentation with LiveDOC\n\n\nSpeaker: John Carney\, Product Engineering Architect\, Cadence \nHost: Supreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/introducing-orcad-x-our-next-generation-pcb-layout-solution/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Cadence-January-24-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240124T080000
DTEND;TZID=Asia/Tokyo:20240126T170000
DTSTAMP:20231227T195553Z
CREATED:20231227T195553Z
LAST-MODIFIED:20231227T195553Z
UID:7462-1706083200-1706288400@marketingeda.com
SUMMARY:Automotive World 2024
DESCRIPTION:Combination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics\, connected car\, autonomous driving\, EV/HV/FCV\, lightweight\, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. \n\n1\,650 Exhibitors\n85\,000 Visitors\n170 Speakers
URL:https://marketingeda.com/event/automotive-world-2024/
LOCATION:Tokyo Big Sight\, 3 Choe-11-1 Ariake\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Automotive-World-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240123T100000
DTEND;TZID=Europe/London:20240123T110000
DTSTAMP:20240104T173400Z
CREATED:20240104T173400Z
LAST-MODIFIED:20240104T173400Z
UID:7503-1706004000-1706007600@marketingeda.com
SUMMARY:Verisium SimAI: Coverage Gaps Meet Their Match
DESCRIPTION:Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps\, including technical complexity\, lack of resources\, and shifting requirements. In constrained random environments\, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity\, persistence\, and technical expertise. A much greater effort is needed to create tests that significantly increase “last mile” coverage\, and the “knee of the curve” that defines the last mile may occur anywhere from 70% to 95% for code and functional coverage. \nThis webinar will discuss addressing coverage gaps using new Verisium SimAI technology with the Cadence Xcelium Logic Simulator\, the ultimate breakthrough in accelerating verification closure. Verisium SimAI uses Machine learning to build a model to identify and eliminate redundancies in regressions\, generate optimized stimulus\, and automatically close coverage gaps. Users can also leverage the Jasper Coverage Unreachability (UNR) App in their flow to identify structural aspects that limit certain bins from getting hit\, further reducing the last-mile coverage gap. \nJoin us on January 23 to learn how a combination of Verisium\, Xcelium\, and Jasper Apps can quickly\, efficiently\, and automatically eliminate coverage holes and minimize the coverage closure gap.
URL:https://marketingeda.com/event/verisium-simai-coverage-gaps-meet-their-match/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Seoul:20240122T080000
DTEND;TZID=Asia/Seoul:20240125T170000
DTSTAMP:20231229T165332Z
CREATED:20231229T165332Z
LAST-MODIFIED:20231229T165332Z
UID:7479-1705910400-1706202000@marketingeda.com
SUMMARY:ASP-DAC 2024
DESCRIPTION:ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions\, one of the most active regions of design\, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists\, engineers\, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.
URL:https://marketingeda.com/event/asp-dac-2024/
LOCATION:Incheon Songdo Convensia\, 123 Central Street\, Yeonsu-gu\, Incheon\, Korea\, Democratic People's Republic of
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240118T100000
DTEND;TZID=America/Los_Angeles:20240118T110000
DTSTAMP:20240103T221805Z
CREATED:20240103T221805Z
LAST-MODIFIED:20240103T221805Z
UID:7499-1705572000-1705575600@marketingeda.com
SUMMARY:Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
DESCRIPTION:The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process\, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. \n\nOne way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in the design cycle. Instead of simply passing a completed design to SI/PI experts for inspection\, design teams can now run in-design analysis (IDA) using intuitive graphical feedback to improve design quality. This change in process saves multiple design re-spins and produces high-performance\, high-quality IC packages for even the most challenging schedules. \n\nThis webinar will educate IC package designers and their managers about Cadence in-design analysis software\, part of the market-leading Cadence IC package design technology. It will showcase the latest updates to the guided\, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges\, reduces design iterations\, and saves significant non-recurring engineering budget.
URL:https://marketingeda.com/event/meet-advanced-ic-package-design-schedule-challenges-with-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/cadence-January-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240116T100000
DTEND;TZID=America/Chicago:20240116T110000
DTSTAMP:20240110T172405Z
CREATED:20240110T172405Z
LAST-MODIFIED:20240110T172405Z
UID:7509-1705399200-1705402800@marketingeda.com
SUMMARY:PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
DESCRIPTION:“Right first time” is a goal we all aspire to\, but how often does it really happen? Even when we follow layout rules as closely as possible\, problems creep into the layout that cause issues during lab testing and result in costly\, time-consuming respins. \n‌ \nJoin our expert presenter Todd Westerhoff in this LinkedIn Live session where he will dive into why this happens and how to address it through a multifaceted approach that involves meticulous consideration of board fabrication nuances such as layer thickness and conductivity\, and ensuring simulations actually model the board as implemented (instead of the board as intended) by using automated post-layout verification that extracts\, models and analyzes all the design’s serial channels instead of only a select few. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on January 16\, 2023. 
URL:https://marketingeda.com/event/pcb-design-best-practices-how-to-fully-verify-your-serdes-based-designs-before-prototype-manufacture/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240116T080000
DTEND;TZID=America/Los_Angeles:20240116T090000
DTSTAMP:20231220T172444Z
CREATED:20231220T172444Z
LAST-MODIFIED:20231220T172444Z
UID:7201-1705392000-1705395600@marketingeda.com
SUMMARY:Speed Up Your Electronic Component Design with HPC ​
DESCRIPTION:About this Webinar\nElectronic components design and their integration on PCBs involve complex simulations to predict EM fields and forces accurately. These simulations can be computationally intensive and time-consuming. High-Performance Computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process\, enabling quick iteration\, optimization\, and validation. The ECAD capability of Maxwell allows modeling and simulation of the PCB along with its components and interdependencies. This system-level simulation enables faster identification and resolution of design challenges.​ \nWhat You Will Learn\n\nHigh-Performance Computing (HPC): provides knowledge to tackle efficiently complex EM computational problems\nParallel Computing: HPC breaks down complex tasks into smaller subtasks that can be executed concurrently\nScalability: Efficiently scale computational resources as the size of the problem increases is crucial in HPC\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\n\nMarius Rosu\nRyan Magargle
URL:https://marketingeda.com/event/speed-up-your-electronic-component-design-with-hpc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240106T080000
DTEND;TZID=Asia/Kolkata:20240110T170000
DTSTAMP:20231228T190611Z
CREATED:20231227T173925Z
LAST-MODIFIED:20231228T190611Z
UID:7458-1704528000-1704906000@marketingeda.com
SUMMARY:VLSID 2024
DESCRIPTION:The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata\, India\, during January 6-10\, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders\, Indian and international industry bodies\, and academic researchers in a common platform. \nIn the present era of automation and connected things\, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift\, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”. \nBrilliant minds across the VLSI domain will brainstorm during the conference to redefine the future course of VLSI Design and Embedded research and application in India. Kolkata (Known as Calcutta during the British Imperial rule) is surrounded by several premier technical and scientific institutes like IIEST Shibpur (B. E. College\, Shibpur)\, IIT Kharagpur\, ISI Calcutta\, Calcutta University\, Jadavpur University etc. \nEast and north-eastern region of our country is a hub of innovation with a focus on emerging technologies. Over the years the region has generated huge number of ESDM professionals and academicians who are right now fueling the growth of ESDM industry. It is high time to operationalize state level high technology clusters in the field of VLSI design\, embedded systems\, cognitive system design and silicon/display/compound fab. VLSID 2024 provides the unique stage where MNCs\, start-ups\, industry bodies and academicians come together and get synergized with what the states of this region have to offer. \nOver a span of five-days of VLSID2024\, the summit will feed brains and nurture minds with state-of-the-art exhibitors\, presentations\, panel discussions\, innovation forums\, and tutorials by established technologists.
URL:https://marketingeda.com/event/vlsid-2024/
LOCATION:ITC Royal Bengal\, Kolkata\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231215T100000
DTEND;TZID=America/Los_Angeles:20231215T110000
DTSTAMP:20231211T212819Z
CREATED:20231211T212623Z
LAST-MODIFIED:20231211T212819Z
UID:7155-1702634400-1702638000@marketingeda.com
SUMMARY:Debugging SystemC with GDB
DESCRIPTION:Webinar Overview:\nThis webinar explores debugging SystemC code with basic tools\, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and accelerate development. \nThe webinar is suitable for SystemC programmers of any level. It will cover: \n\nSystemC debug challenges\nTools\nDemo:\n\nConfiguring the code\n.gdbinit\n\n\nStrategies & Wrap-up\n\nThe webinar also features the Virtualizer Studio IDE from Synopsys for browsing\, editing and debug of SystemC source code. \nThe webinar is presented by David C Black\, Doulos Senior Member of Technical Staff and co-author of “SystemC: From the Ground Up”. \nAttendance is FREE! \n\n \nDavid C Black \, Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/debugging-systemc-with-gdb/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-December-15-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231214T100000
DTEND;TZID=America/Los_Angeles:20231214T110000
DTSTAMP:20231120T175241Z
CREATED:20231120T175241Z
LAST-MODIFIED:20231120T175241Z
UID:7114-1702548000-1702551600@marketingeda.com
SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs
DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO
URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T100000
DTEND;TZID=America/Los_Angeles:20231213T110000
DTSTAMP:20231211T211948Z
CREATED:20231211T211948Z
LAST-MODIFIED:20231211T211948Z
UID:7152-1702461600-1702465200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III
DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T090000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231204T224640Z
CREATED:20231204T224336Z
LAST-MODIFIED:20231204T224640Z
UID:7139-1702458000-1702461600@marketingeda.com
SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics
DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA.
URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T070000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231110T200548Z
CREATED:20231110T200548Z
LAST-MODIFIED:20231110T200548Z
UID:7073-1702450800-1702461600@marketingeda.com
SUMMARY:RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
DESCRIPTION:Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? \nIn this free technical Training Webinar with Application Engineer Sai Srinivas Pamula\, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator\, Modus DFT Software Solution\, Genus Synthesis Solution\, Conformal technologies\, Innovus Implementation System\, and Tempus Timing Solution—that provide great power\, performance\, and area (PPA). \nWe’ll explore topics like: \n\nWriting RTL code using Verilog or VHDL\nSynthesizing the RTL design into a gate-level netlist\nInserting scan chains into the netlist for testing and debugging\nPerforming logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design\nImplementing the netlist by performing floorplanning\, placement\, clock tree synthesis\, and routing\nPerforming timing signoff to verify that the design meets all of its timing requirements\nExtracting the GDSII file from the physical layout to manufacture the chip\n\nWebinar\nRTL-to-GDSII Flow for ASIC Design Using Cadence Tools \nDate and Time\nWednesday\, December 13\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n\nTo register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration and complete the requested information.
URL:https://marketingeda.com/event/rtl-to-gdsii-flow-for-asic-design-using-cadence-tools/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-13-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231212T110000
DTEND;TZID=America/Los_Angeles:20231212T120000
DTSTAMP:20231120T173808Z
CREATED:20231120T173808Z
LAST-MODIFIED:20231120T173808Z
UID:7111-1702378800-1702382400@marketingeda.com
SUMMARY:Solve EM Fields and Forces in PCBs for Consumer Electronics ​
DESCRIPTION:This webinar will demonstrate how Ansys tools can improve PCB designs for higher performance and reliability. Ansys Maxwell simulates low-frequency (LF) EM fields to identify potential EMI/EMC issues for shielding and grounding purposes. Engineers can also predict electric currents distributed throughout the PCB power traces and study the EM forces generated by the magnetic field of the permanent magnets. Computed broadband forces are mapped to Ansys Mechanical for NVH analysis to reduce undesired mechanical vibrations.​ \nWhat You Will Learn\n\nDesign and development of electronic circuits and PCBs\nModel detailed printed circuit boards\nPerform electromagnetic analysis to import EM sources\nConduct mechanical analysis to identify noise sources\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\nTianze Kan and Marius Rosu
URL:https://marketingeda.com/event/solve-em-fields-and-forces-in-pcbs-for-consumer-electronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-December-12-2023.jpg
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END:VCALENDAR