BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.19//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20250309T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20251102T070000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241210T183000 DTEND;TZID=America/Los_Angeles:20241210T203000 DTSTAMP:20260408T025412 CREATED:20241121T224138Z LAST-MODIFIED:20241121T224138Z UID:8520-1733855400-1733862600@marketingeda.com SUMMARY:Synopsys TCAD Winter Reception DESCRIPTION:Join us in person at the Synopsys TCAD Winter Reception on December 10\, 2024. You have a chance to meet with our executives and product experts to learn about the latest insights on how Synopsys TCAD products can unleash the power of smart technology modeling – from atoms to circuits. Sign up and learn about the application of Synopsys TCAD solutions to accelerate the research\, development\, and optimization of semiconductor technologies. \nVenue: Hotel Nikko\, 222 Mason St\, San Francisco\, CA 94102 (across the IEDM Conference @ Hilton SF Union Square)\nRoom: Peninsula\, 25th floor\nRSVP: By Dec 6\, 2024 \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/synopsys-tcad-winter-reception/ LOCATION:Hotel Nikko\, 222 Mason Street\, San Francisco\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241207T080000 DTEND;TZID=America/Los_Angeles:20241211T170000 DTSTAMP:20260408T025412 CREATED:20241008T155901Z LAST-MODIFIED:20241018T161813Z UID:8386-1733558400-1733936400@marketingeda.com SUMMARY:70th Annual IEEE International Electron Devices Meeting - IEDM 2024 DESCRIPTION:IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology\, design\, manufacturing\, physics\, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology\, advanced memory\, displays\, sensors\, MEMS devices\, novel quantum and nano-scale devices and phenomenology\, optoelectronics\, devices for power and energy harvesting\, high-speed devices\, as well as process technology and device modeling and simulation. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/70th-annual-ieee-international-electron-devices-meeting/ LOCATION:Hilton San Francisco Union Square\, 333 O'Farrell Street\, San Francisco\, 94102\, United States CATEGORIES:Conference,EDA,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/70thiedmcolor.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241205T090000 DTEND;TZID=America/Los_Angeles:20241205T100000 DTSTAMP:20260408T025412 CREATED:20241203T172119Z LAST-MODIFIED:20241203T172119Z UID:8544-1733389200-1733392800@marketingeda.com SUMMARY:Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips DESCRIPTION:Efficient management of registers and memory maps is critical for the success of modern System-on-Chip (SoC) designs. System Register Description Language (SystemRDL)\, combined with Agnisys’s IDesignSpec Suite\, provides an advanced solution to automate and simplify these complex processes. In this webinar\, “Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips\,” we will demonstrate how the IDesignSpec Suite leverages SystemRDL to accelerate register design\, improve design quality\, and streamline SoC development. You’ll gain insights into best practices\, learn how to automate crucial tasks\, and see how our tools ensure compliance with industry standards. \nYou’ll learn:\n• Best Practices for register design and memory map management using SystemRDL.\n• How the IDesignSpec Suite accelerates SoC development with automation\, reducing manual errors and ensuring compliance with industry standards.\n• Practical use cases\, including generating design files\, firmware headers\, and comprehensive documentation for seamless hardware-software integration. \nExclusive Features and Highlights:\n• Explore how Agnisys’s SystemRDL VS Code Extension enhances your design workflow.\n• Discover the Agnisys PSS Compiler and its ability to simplify Portable Stimulus generation.\n• See real-world examples\, such as the Power Controller use case\, demonstrating the suite’s capabilities in addressing industrial challenges. \nWhat’s on the Agenda? \nThe webinar will guide you through every facet of SystemRDL and its integration with IDesignSpec:\n• Core Concepts: Registers\, Memory\, Address Maps\, and Parameters.\n• Advanced Techniques: Constraint Management\, Verification Constructs\, and Structural Testing.\n• Comprehensive Outputs: From HDL Path generation to SoC assembly and IP packaging.\n• Bonus: Insights into SoC Hardware-Software Interface (HSI) and device driver generation. \nReserve your spot today and join us for this hands-on\, practical session! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimizing-hardware-design-with-systemrdl-tools-techniques-and-tips/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241203T100000 DTEND;TZID=America/Los_Angeles:20241203T170000 DTSTAMP:20260408T025412 CREATED:20241106T234135Z LAST-MODIFIED:20241106T234135Z UID:8481-1733220000-1733245200@marketingeda.com SUMMARY:Keysight EDA 2025 Launch event DESCRIPTION:New EDA Tools for 5G and AI Infrastructure Design\n\n\n\n\n\nWe are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain insights and workflows enhanced by artificial intelligence (AI). \nGet the Roadmap\nThe webinar will kick off with an overview of the Keysight EDA 2025 roadmap from Richard Duvall\, senior EDA marketing manager. Then\, you can choose the discussion topic that interests you most. Explore product release highlights\, watch demo videos\, and participate in question-and-answer sessions. After the live webinar\, use the same registration link to watch other topics on demand. \nTrack 1: What’s New in Advanced System Design (ADS) for RF Circuit Design \n\n\n\nLearn how RF circuit design tools with Python APIs enable open workflows that help you address the complex design challenges of sub-terahertz chipsets.\nWatch advanced RF simulation enable a multi-domain co-design cockpit\, essential for troubleshooting designs with nonlinear\, power\, electromagnetic\, thermal\, and wideband 5G digital modulation.\nHarness the latest AI and machine learning (ML) technology to create reliable power amplifier simulation models with minimal effort using artificial neural networks.\n\nTrack 2: What’s New in ADS for High-Speed Digital Circuit Design \n\n\n\nDiscover how to use the Keysight Chiplet PHY Designer to predict the true end-to-end link margin and verify compliance with cross talk analysis and quarter-rate clock support.\nLearn how the Keysight PCIe® Designer can help you perform complete PCIe system analysis and simulation-driven virtual compliance tests with a streamlined workflow.\nWatch the Keysight Power Integrity Designer enable simulations that deliver thousands of amps to the next generation of custom multi-die packages\, AI chips\, and cloud server applications.\n\nTrack 3: What’s New in Device Modeling and Characterization \n\nLearn how new AI / ML-based algorithms in IC-CAP can help fully automate the model recentering process and increase productivity by 10 times\, from days to hours.\nSee how the Keysight Model Builder Pro leverages Python to automate the modeling process\, helping standardize the modeling flow and reducing turnaround time.\nLearn how the Keysight Model Generator framework enables a turnkey workflow that is 30% faster with less programming and more automation.\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/keysight-eda-2025-launch-event/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-December-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241127T150000 DTEND;TZID=Europe/London:20241127T153000 DTSTAMP:20260408T025412 CREATED:20241105T181903Z LAST-MODIFIED:20241105T181903Z UID:8475-1732719600-1732721400@marketingeda.com SUMMARY:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases DESCRIPTION:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases \nWith the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI assisted advanced DV Flow and Use cases\n\nAI Training Bots\nAI Assistance\, CoPilot\nAI Code CoPilot\nRAG\nRAG Assessment\nAI Agents\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-3-tessolve-ai-assisted-advanced-dv-flow-and-use-cases/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-27-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241126T120000 DTEND;TZID=Europe/London:20241126T130000 DTSTAMP:20260408T025412 CREATED:20241022T165229Z LAST-MODIFIED:20241107T165901Z UID:8444-1732622400-1732626000@marketingeda.com SUMMARY:DVClub Europe - AI/ML in Verification DESCRIPTION:This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. \n\n\nAgenda (GMT):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction – Mike Bartley\, Tessolve \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nHardik Raina\, Agnisys\, Inc – Genetic Algorithms for Automated Verification from VCD Data.\n\n\n\n\n12.20 GMT\nPaula Mathias\, Cadence Design System – AI-based SVA Generation\n\n\n\n\n12.40 GMT\nDavid Kelf\, Breker Verification Systems – VerifyGPT! Is it possible and what do we need in place?\n\n\n\n\n13.00 GMT\n  \nClose\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/dvclub-europe-ai-ml-in-verification-2/ CATEGORIES:EDA,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241121T093000 DTEND;TZID=Europe/London:20241121T140000 DTSTAMP:20260408T025412 CREATED:20241113T173601Z LAST-MODIFIED:20241113T173601Z UID:8506-1732181400-1732197600@marketingeda.com SUMMARY:FPGA Front Runner: FPGA Safety and Security DESCRIPTION:This event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains\, FPGA hardware and the IP used on the FPGA\n \nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.30\nArrival and registration\n\n\n10.00\nTobias Adryan\, Synopsys\nSecuring FPGAs Beyond the Bitstream\n\n\n10.30\nEspen Tallaksen\, EmLogic\nFPGA Requirements Tracking and the Requirements Traceability Matrix\n\n\n11.00\nAndrew Swirski\, Beetlebox\nSecuring FPGA Development Pipelines with DevSecOps\n\n\n11.30\nRefreshment break\n\n\n12.00\nIan Pearson\, Microchip Technology Inc.\nEU Cyber Resilience Act – Impacts on Business and Product Design\n\n\n12.30\nFlemming Christensen\, Sundance Multiprocessor Technology Ltd\nHow to secure supply of ‘COTS’ FPGA Modules\n\n\n13.00\nPeter Davies\, Thales\n\n\n\n13.30\nLunch and networking\n\n\n14.00\nEnd\n\n\n\n\n\n\n\n FPGA Front Runner event Partner: TechWorks & Tessolve \nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fpga-front-runner-fpga-safety-and-security/ LOCATION:The Cass Centre\, Shaftesbury Road\, Cambridge\, CB2 8BS\, United Kingdom CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-21-November-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260408T025412 CREATED:20241107T182710Z LAST-MODIFIED:20241107T182710Z UID:8486-1732176000-1732179600@marketingeda.com SUMMARY:Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus DESCRIPTION:This webinar to delve into the integrated design flow for power modules for electric vehicles (EVs) for enhanced functional safety and reliability. The power modules are distinguished by their high voltage and current requirements\, substantial power dissipation\, and the resulting temperature rise. Ensuring their safety and reliability is paramount. We will explore how Cadence’s cutting-edge solutions – Allegro X\, PSpice\, Clarity 3D Solver\, and Celsius Thermal Solver—designed to support a thermally aware design process\, come together in an end-to-end integrated design solution \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-electric-vehicle-development-integrated-design-flow-for-power-modules-with-functional-safety-and-reliability-focus/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260408T025412 CREATED:20241031T164508Z LAST-MODIFIED:20241031T164508Z UID:8466-1732176000-1732179600@marketingeda.com SUMMARY:Boost your verification productivity with Questa Verification IQ DESCRIPTION:This session will explore Questa Verification IQ (VIQ)\, Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics\, enhanced collaboration\, and comprehensive traceability. By leveraging machine learning\, VIQ significantly enhances verification efficiency to boost your productivity. \nWhat you will learn: \n\n‌How to implement a collaborative\, plan-driven verification process\, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results\nSetting up a collaborative regression environment with live visibility and control to drive debug and optimize verification flows\nEnabling team-based collaborative analysis to accelerate coverage closure by applying analytics\nConfiguring dashboards with visualizations and insights into what happened and why\, utilizing trending data\, gauges\, and cross-analytics\n‌\n\nWho should attend: \nVerification Engineers & Managers \n\n\nProducts Covered:   \n\nQuesta Verification IQ:\n\nTestplan Author\nRegression Navigator\nCoverage Analyzer\nVerification Insight\n\n\n\n\n\nSpeaker:\n\n\n\n\n\n\nMark Carey\nProduct Engineer\, Siemens EDA\n\n\n\n\nMark Carey is a Product Engineer in the Digital Verification Technologies division at Siemens EDA. With over two decades of experience in EDA\, he started his career as a software developer before moving into technical marketing and product management roles across design\, virtual prototyping\, requirement traceability\, and now works as part of the verification management team. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/boost-your-verification-productivity-with-questa-verification-iq/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241120T150000 DTEND;TZID=Europe/London:20241120T153000 DTSTAMP:20260408T025412 CREATED:20241105T181405Z LAST-MODIFIED:20241105T181405Z UID:8472-1732114800-1732116600@marketingeda.com SUMMARY:Webinar 2: Tessolve AI assisted DV Flow DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information Tessolve AI assisted DV Flow\n  \n\nSpec Analysis\nRegister Extraction\nTest Flow\nAssertion Generation\nCoverpoints\nTestcases\nScripts for UVM etc.\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-2-tessolve-ai-assisted-dv-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20241120T090000 DTEND;TZID=Asia/Kolkata:20241120T170000 DTSTAMP:20260408T025412 CREATED:20241114T182226Z LAST-MODIFIED:20241114T182631Z UID:8514-1732093200-1732122000@marketingeda.com SUMMARY:Ansys IDEAS User Conference India 2024 DESCRIPTION:Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies. \nOverview\nAt this premier conference\, you will: \n\nDiscover Key Insights: Learn from industry experts and simulation specialists about cutting-edge techniques and strategies in on-chip power integrity and reliability\nExplore Multi-Scale Multiphysics Challenges: Dive into complex topics\, including multi-scale\, multiphysics simulations essential for 3DICs and heterogeneous integration\nAccelerate Innovation: Gain valuable knowledge on how advanced simulation technologies like Sigma-DVD can streamline design processes and drive innovation\nNetwork with Experts: Connect with peers and Ansys experts\, sharing experiences and exploring new opportunities for collaboration\n\nIDEAS India is your opportunity to deepen your understanding of power-noise-reliability sign-off for Chip-Package systems\, enhance your skills\, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology. \nKey Discussion Topics\n\nSoC Power-Integrity and Reliability Sign-off\nAdvanced Power Integrity Flows: Sigma-DVD\, ROM\, IR-ECO\, etc\n3DIC / Interposer – Power\, Signal\, Thermal Integrity\nAnalog & Mixed-Signal Designs Power and Reliability\nRTL Power Analysis and Optimization\nReliability Analysis: Electromigration\, ESD\, and Thermal\nShift-left /In-design Analysis and Optimization\nChip-Package-System Co-Simulation\n\n\n\n\nAgenda\n\n\n\nTime\nSession\nSpeakers\n\n\n9:00 am – 10:00 am\nRegistration + Hi-Tea\n\n\n10:00 am – 10:15 am\nWelcome & Inauguration\nJai Pollayil\nSenior Director & Global Semiconductor AE Head\nAnsys\n\n\n10:15 am – 10:45 am\nIndustry Keynote\nBalajee Sowrirajan\nCorporate EVP & MD\nSamsung Semiconductor India Research\n\n\n10:45 am – 11:15 am\nAnsys Keynote\nJohn Lee\nGeneral Manager and Vice President\nAnsys\n\n\n11:15 am – 11:30 am\nTea/Coffee Break\n\n\n\nTrack 1: Advanced SOC Power Integrity & Reliability\n(Convention Hall)\nTrack 2: Power-Signal-Thermal-ESD Integrity across RTL / Custom IP / IC / 3DIC\n(Tactic 5)\n\n\n\nSession\nSpeakers\nSession\nSpeakers\n\n\n11:30 am – 12:00 pm\nConquering IR ECO complexity with PrimeClosure\nSynopsys\nRaghavendra Swami Sadhu\nBackside power delivery and advanced technology EM/IR analysis in Totem\nIntel\nAnil Dsouza\n\n\n12:00 pm – 12:30 pm\nMaximizing IR signoff coverage using Sigma-AV and its benefit on PPA\nGoogle\n Sandeep Gajbhare\nComprehensive Electrical & Thermal integrity of Power Management IC using a new Integrated solution\nTexas Instruments\nGirish Bijjal\n\n\n12:30 pm – 1:00 pm\nAccelerating Full Flat EMIR Sign-off of Multi-billion Instance Design using RedHawk-SC ROM (Reduced Order Model)\nSamsung Semiconductor India Research\nRaja Ramachandra Rao & Satyaki Mandal\nOptimizing Standard cell library development flow using “ParagonX” – EDA tool for IC layout parasitics analysis\nNXP Semiconductors\nRavi JN & Santhosh Kamatam\n\n\n1:00 om – 2:00 pm\nLunch Break\n\n\n2:00 pm – 2:30 pm\nAn efficient methodology for Multi-PVT EMIR analysis of Large SOCs\nNVIDIA\nRamesh Aggarwal\nSignal and Power Integrity analysis of Silicon Interposer for multi-chiplet integration\nAlphawave Semi\nGangaraju M & Yadavalli Jagadeeswari\n\n\n2:30 pm – 3:00 pm\nAccounting for IR Drop in Static Timing Analysis: A Path to Accurate Delay Estimation\nIntel\nPurushotham Reddy N & Manoj Varama S\nComprehensive Thermal Analysis of 3DIC design using Redhawk_SC-ElectroThermal (RHSC-ET\nSamsung\nRishikanth Mekala & Abhishek Chinchani\n\n\n3:00 pm – 3:30 pm\nNovel method of Vectorless IR Analysis for DFT\nMediaTek\nArun CS\nAccelerated ESD Sign-off with Pathfinder-SC: An Efficient and Scalable Approach\nGoogle\nSmaritha Kasukurthi\n\n\n3:30 pm – 4:00 pm\nOptimizing Power Integrity with RHSC in Smart PDN Framework Qualcomm\nGaurav Jain & Rajender Nune\nAn Integrated Approach to Power Analysis & Optimization: Synergizing Emulation\, RTL Design\, and Physical Design\nAMD\nNeeraj Dwivedi\n\n\n4:00 pm – 4:30 pm\nRobust techniques for IR prediction\nAMD\nSayani Das\nA Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape’s DataLake and Micro-Resiliency\nARM\nChandrakumar A\n\n\n4:30 pm – 4:35 pm\nConcluding Remarks\n\nConcluding Remarks\n\n\n\n4:35 pm – 5:00 pm\nTea & Networking\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ansys-ideas-user-conference-india-2024/ CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-20-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241120T070000 DTEND;TZID=America/Los_Angeles:20241120T090000 DTSTAMP:20260408T025412 CREATED:20241025T162958Z LAST-MODIFIED:20241025T162958Z UID:8453-1732086000-1732093200@marketingeda.com SUMMARY:Fast Track RTL Debug with the Verisium Debug Python App Store DESCRIPTION:Working with debugging scripts locally and manually can be challenging\, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? \nThe answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. \nJoin us for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps\, learn about them\, install\, or uninstall them\, and even customize existing apps. \nDate and Time\nWednesday\, November 20\, 2024\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n  \nTo register for this webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register. Once registered\, you’ll receive a confirmation email containing all login details. \nA quick reminder: \n\nIf you haven’t received a registration confirmation within one hour of registering\, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled.\nFor issues with registration or other inquiries\, reach out to eur_training_webinars@cadence.com\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fast-track-rtl-debug-with-the-verisium-debug-python-app-store/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241119T090000 DTEND;TZID=America/Los_Angeles:20241119T100000 DTSTAMP:20260408T025412 CREATED:20241019T030235Z LAST-MODIFIED:20241019T030235Z UID:8436-1732006800-1732010400@marketingeda.com SUMMARY:Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design DESCRIPTION:The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC\, GPU\, mobile\, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. \nFor the past years\, Synopsys and Ansys have been creating design flows that carry designers through early exploration\, implementation\, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market. \nRegister now to learn about:\n– Multi-die design best practices for thermal\, signal\, and power integrity\n– Insights from practical multi-die design case studies\n– More advanced packaging technologies for thermal management\, backside power\, and co-packaged optics \nSPEAKERS \nMarc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose\, CA. Before joining Ansys\, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys\, Azuro\, and Sequence Design\, where he gained experience with a wide array of digital and analog design tools. \nKeith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design\, analog/mixed signal (AMS) and RF/mmWave product experience\, including 8 years designing high speed data converters and amplifiers at Analog Devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ansys-synopsys-technology-update-the-latest-advances-in-multi-die-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Synopsys-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241118T080000 DTEND;TZID=America/Los_Angeles:20241118T170000 DTSTAMP:20260408T025412 CREATED:20240524T205337Z LAST-MODIFIED:20240524T205337Z UID:8049-1731916800-1731949200@marketingeda.com SUMMARY:Workshop on Open Source EDA Technologies (WOSET) DESCRIPTION:Virtual! No registration fee! \nThe WOSET workshop aims to galvanize the open-source EDA movement. The\nworkshop will bring together EDA researchers who are committed to\nopen-source principles to share their experiences and coordinate\nefforts towards developing a reliable\, fully open-source EDA flow. The\nworkshop will feature presentations and posters that overview existing\nor under-development open-source tools\, designs and technology\nlibraries. A live demo session for tools in advanced state will be\nplanned. The workshop will feature a panel on the present status and\nfuture challenges in open-source EDA\, and how to coordinate efforts\nand ensure quality and interoperability across open-source tools. \nTopics of interest include\, but are not limited to:\n* Overview of an existing or under-development open-source EDA tool.\n* Overview of support infrastructure (e.g. EDA databases and design benchmarks).\n* Open-source cloud-based EDA tools\n* Open-source hardware designs\n* Position statements (e.g. critical gaps\, blockers/obstacles) \nSubmission Information\n* All submissions must include links to open-source repositories with\nall source code and an open-source license (BSD\, GPL\, Apache\, etc.)\n* Please reference your open-source repository!\n* Review is single blind (anonymous reviewers).\n* Videos will be put on WOSET site if accepted.\n* Virtual presentation for regular papers (in addition to archival video)\n* Regular Paper Submissions (3-4 pages + 1 page references + 15 min video + virtual presentation)\n* Work in Progress Submissions (1-2 page abstract + 1 page references + 10 min video + virtual zoom room)\n* Submission site: https://lnkd.in/gEtDztEY \nImportant dates:\n* Sept 23 2024 (end of day\, anywhere in world): submission due date.\n* Oct 18 2024: notification date.\n* Nov 8 2024: video due (if accepted)\n* Nov 18 2024: workshop \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/workshop-on-open-source-eda-technologies-woset/ CATEGORIES:EDA,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WOSET-2024.jpg ORGANIZER;CN="UC Santa Cruz":MAILTO:mrg@ucsc.edu END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260408T025412 CREATED:20241030T170948Z LAST-MODIFIED:20241030T170948Z UID:8460-1731578400-1731582000@marketingeda.com SUMMARY:Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling DESCRIPTION:In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges\, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and power efficiency of deep learning algorithms\, including Deep and Convolutional Neural Networks (DNNs and CNNs). \nThrough system-level modeling\, design teams can analyze and optimize critical factors such as response time\, power consumption\, component selection\, and cost-effectiveness before finalizing their designs. This session is particularly beneficial for SoC architects\, embedded systems designers\, and other professionals working to balance performance\, power\, and cost for AI deployments in demanding environments. \nWhat You’ll Learn \nWith AI systems like CNNs now integral to technologies in real-time tracking\, object detection\, and autonomous navigation\, the need for architecture trade-offs has intensified. Our approach to system-level modeling allows teams to: \n\nEvaluate Hardware Combinations: Assess combinations of CPUs\, GPUs\, AI-specific processing units\, and standalone FPGAs to select the best configuration for your needs.\nOptimize Task Partitioning: Partition tasks across chips to achieve targeted performance without compromising power efficiency or exceeding budget constraints.\nRealistic Workload Simulation: Use cycle-accurate models to depict AI/ML algorithm performance under real-world conditions\, creating accurate simulations of hardware components in action.\n\nThrough detailed case studies across industries like automotive\, avionics\, data centers\, and radar systems\, you’ll see how this methodology applies to diverse scenarios\, helping to trade off key performance indicators (e.g.\, vehicle mileage vs. processing power). \n\n\n\n\nKey Takeaways\n\n\n\n\n\nTrade-Off Latency\, Power\, and Cost Using Early Simulation\n\nBy modeling early\, teams can visualize trade-offs and make informed decisions on processor and component selection to hit project goals effectively.\n\n\nIntegrate Shift-Left and Shift-Right Strategies in System-Level Modeling\n\nBring software testing and design validation forward to avoid issues in later stages\, enhancing the quality of final designs.\n\n\nMap Applications to Diverse Processing Units\n\nLearn to deploy applications seamlessly across CPUs\, GPUs\, TPUs\, and AI engines to maximize AI’s impact while optimizing for cost and power.\n\n\nFoster Collaboration Between OEMs\, Tier 1 Suppliers\, and Semiconductor Manufacturers\n\nUse our methodology to facilitate better communication and integration across all stakeholders involved in the AI hardware design process.\n\n\n\nWhether you’re involved in automotive\, avionics\, or advanced SoC architectures\, this session offers an invaluable opportunity to master the nuances of system-level modeling for AI architecture and streamline your deep learning deployment. \nDon’t Miss Out on Transforming Your AI Deployment Strategy!\nJoin us for this exclusive session and gain the insights you need to optimize your systems and semiconductor architecture for cutting-edge deep learning applications. \n\n\n\n\nDate: November 14th\, 2024\nSession 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China \nSign up: https://bit.ly/4eZqnjP \nSession 2: 10:00 AM USA PDT / 1:00 PM USA EDT \nRegister: https://bit.ly/3YFM82o \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimize-systems-and-semiconductor-architecture-for-deep-learning-algorithms-using-system-level-modeling/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260408T025412 CREATED:20241025T163841Z LAST-MODIFIED:20241025T163841Z UID:8456-1731578400-1731582000@marketingeda.com SUMMARY:AI-Driven Constraint Generation for PCB and IC Package Design DESCRIPTION:Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. \nKey Takeaways:\n \n\nLearn how the Sigrity Topology Workbench\, a robust system-level SI/PI environment for what-if and pre-route analysis\, is linked to the Allegro X PCB and IC package implementation tools.\nExperience the power of AI optimization in simulating parameterized structures to quickly reach target objectives\, and see how the physical attributes that meet these target objectives are automatically fed into the implementation tool as constraints.\nEnvision the efficiency of reusing or updating AI-generated constraints in future designs to consistently reduce design cycle time\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ai-driven-constraint-generation-for-pcb-and-ic-package-design/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241113T150000 DTEND;TZID=Europe/London:20241113T153000 DTSTAMP:20260408T025412 CREATED:20241105T180842Z LAST-MODIFIED:20241105T180842Z UID:8469-1731510000-1731511800@marketingeda.com SUMMARY:Tessolve AI Strategy & Eco System for DV DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI Strategy & Eco System for DV\n\nAI Strategies at Tessolve\nAI Tool range for DV-\n\nDV RAG Tool\,\nAssertify\,\nUnit TB Generation\,\nUVM AI\,\nISO26262 AI etc.\n\n\n\n  \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/tessolve-ai-strategy-eco-system-for-dv/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tesolve-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T110000 DTEND;TZID=America/Los_Angeles:20241112T120000 DTSTAMP:20260408T025412 CREATED:20241021T181622Z LAST-MODIFIED:20241021T181734Z UID:8440-1731409200-1731412800@marketingeda.com SUMMARY:Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification DESCRIPTION:High-level design techniques and automation tools to address the limitations of traditional RTL\, reduce verification times\, improve performance\, and manage growing design complexity—integrating seamlessly.\n\n\nWhat You’ll Learn:\n\n\n\n\nThis Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary\, but familiarity with hardware design and RTL synthesis is recommended. \nSome key takeaways you can expect: \n** Rise Design Automation Overview – Introduction to the tools\, use cases\, methodologies\, and project value of raising the abstraction beyond RTL with Rise. \n** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog. \n** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity. \n** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling\, pipelining\, and scheduling to optimize power\, performance\, and area—while gaining early insights into trade-offs. \n** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework. \n** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning\, DSP\, and video/image processing. \n** Learn how collaboration between system architects\, RTL designers\, and verification engineers speeds up development and delivers more reliable hardware. \n\n\n\n\nWho should attend:\n\n\n\n\n** Design Engineers looking to improve control paths\, data flow\, and performance\, while adopting new methods gradually and with minimal risk. \n** Verification Engineers looking to implement earlier\, more efficient verification processes to minimize risk and accelerate timelines\, without overhauling their current flows. \n** Project Leads managing trade-offs in timelines\, power\, performance\, and area\, while ensuring smooth integration of new techniques into existing processes. \n** System Architects looking to model\, explore\, and validate architectural decisions early\, focusing on performance\, power\, and area trade-offs without late-stage surprises. \n\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/rise-together-beyond-rtl-practical-techniques-for-improving-asic-design-efficiency-and-early-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-DA-November-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T080000 DTEND;TZID=America/Los_Angeles:20241114T170000 DTSTAMP:20260408T025412 CREATED:20241030T174154Z LAST-MODIFIED:20241030T174154Z UID:8463-1731398400-1731603600@marketingeda.com SUMMARY:IEEE World Technology Summit - AI INFRASTRUCTURE DESCRIPTION:This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems\, focusing on these core areas: \n\nAI applications and their required infrastructure\nSilicon to support AI applications\nSystems to support AI applications\nSecurity and Standards\n\nAI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit\, where companies\, governments\, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions. \nThe main focus of this conference is AI Infrastructure. \nTo deliver value we need the infrastructure for AI to work!!! This infrastructure includes software\, data storage\, computing\, communications\, power and energy\, standards\, and security. \nTo form an event to address the above issues\, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns\, challenges\, solutions\, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI\, which is critical to make AI work. \nCompanies are invited to sponsor\, engage\, and have employees attend this event. \nIf interested\, contact us at: wtscontact@ieee.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ieee-world-technology-summit-ai-infrastructure/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WTS-November-12-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241107T080000 DTEND;TZID=Asia/Taipei:20241109T170000 DTSTAMP:20260408T025412 CREATED:20240522T185455Z LAST-MODIFIED:20240522T185455Z UID:8022-1730966400-1731171600@marketingeda.com SUMMARY:APCCAS 2024 DESCRIPTION:The APCCAS is a major international forum for researchers\, scientists\, educators\, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including\, but not limited to the following： \n\nArtificial Intelligence Circuits\, Systems\, and Applications\nDigital Integrated Circuits and Systems\nAnalog and Mixed Signal Circuits and Systems\nPower and Energy Circuits and Systems\nBiomedical Circuits and Systems\nSensory Circuits and Systems\nRF/Communications Circuits and Systems\nBeyond CMOS: Nanoelectronics and Hybrid Systems Integration\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/apccas-2024/ LOCATION:Chang Yung-Fa Foundation\, No. 11\, Zhongshan S. Rd.\, Taipei City\, Taiwan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/APCCAS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20260408T025412 CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T183000 DTEND;TZID=America/Los_Angeles:20241106T210000 DTSTAMP:20260408T025412 CREATED:20240927T160600Z LAST-MODIFIED:20240927T160600Z UID:8357-1730917800-1730926800@marketingeda.com SUMMARY:Phil Kaufman Award & Banquet DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \nElectronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor \nDR. JASON CONG\nDistinguished Professor and Volgenau Chair for Engineering Excellence at the University of California\, Los Angeles (UCLA) with the \n2024 Phil Kaufman Award\n2024 Award Recipient\nDr. Jason Cong will be honored for sustained fundamental contributions to Field-Programmable Gate Array (FPGA) design automation technology\, from circuit to system levels\, with widespread industrial impact. His contributions cover four key areas of EDA: \nAlgorithmic Foundations for FPGA Synthesis \nInterconnect Optimization \nDomain Specific FPGA Computing \nNeural Nets in FPGA \nIn addition to being an excellent educator\, Dr. Cong has an outstanding track record of transforming his research results to EDA tools to benefit the EDA industry. \nDr. Jason Cong will be honored at the 2024 Phil Kaufman Award Ceremony and Banquet on November 6\, 2024 in San Jose\, CA. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/phil-kaufman-award-banquet-3/ LOCATION:Hayes Mansion\, 200 Edenvale Avenue\, San Jose\, CA\, United States CATEGORIES:Award,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Kaufman-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T100000 DTEND;TZID=America/Los_Angeles:20241106T110000 DTSTAMP:20260408T025412 CREATED:20241018T165537Z LAST-MODIFIED:20241018T165537Z UID:8433-1730887200-1730890800@marketingeda.com SUMMARY:Navigating Trends and Tools in Automotive Design with Cadence DESCRIPTION:Join us for our first webinar in this insightful series\, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles\, highlighting key trends such as ADAS\, software-defined vehicles\, and zonal architectures. \nLearn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety. \nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together! \nWhat will be covered: \n\nEmerging trends in ADAS\, software-defined vehicles\, zonal architectures\, connectivity\, and electrification\nHow high-performance centralized computing\, cloud-native software development\, power management\, safety design support\, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.\n\nWho Should Attend: \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers\, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-trends-and-tools-in-automotive-design-with-cadence/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-Nnovember-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20241106T093000 DTEND;TZID=America/Chicago:20241106T170000 DTSTAMP:20260408T025412 CREATED:20241017T160613Z LAST-MODIFIED:20241017T160903Z UID:8425-1730885400-1730912400@marketingeda.com SUMMARY:Verification Academy Live: Austin DESCRIPTION:Overview \nThis seminar will update you on technologies and techniques you can adopt to\nincrease your verification productivity today. Specifically\, we will cover: \n\nHow the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains.\nProtocol and memory verification solutions you need for your next silicon verification project.\nData-driven verification with automated analytics\, collaboration\, and traceability capabilities.\nTechnologies and techniques you can adopt to increase your DFT productivity.\n\n‌\n‌ \nAgenda \n9:30 am – 10:00 am\nRegistration and check-in\nCoffee and networking with your peers\n‌\n10:00 am – 10:05 am\nWelcome/Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n‌\n10:05 am – 11:00 am\nKeyNote: Smart Verification – Faster is not Enough\nAbhi Kolpekwar | VP & GM\, Digital Verification Technologies Division \nThe electronics industry is on the brink of an unprecedented paradigm shift. The AI/ML-focused chips account for 20% of the semiconductor market\, a figure set to skyrocket to 73% by 2030\, fueled by the ongoing digital transformation. This seismic shift will significantly impact the architecture\, design\, and manufacturing of computing\, networking\, and communication solutions\, necessitating careful consideration of power\, performance\, security\, and safety concerns. Conventional verification flows\, reliant on disparate point tools\, will struggle to meet the demands of emerging systems. This keynote explores the prevailing macro-trends shaping today’s digital transformation before outlining a visionary approach to functional verification. By leveraging collective wisdom across tools\, technologies\, workflows\, and methodologies\, this new paradigm promises productivity gains beyond the reach of traditional methods.\n‌\n11:00 am – Noon\nQuesta Verification IQ:\nBoost verification predictability and efficiency with Big Data\nAhmed ElKady | Product Engineer \nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost.\n‌\nNoon – 12:45 pm\nLunch and networking\n‌\n12:45 pm – 1:15 pm\nQuesta Verification IQ: Sneak Peek of Debug IQ and Regression IQ\n‌\nContinuation of the Questa Verification IQ session.\n‌\n1:15 pm – 2:00 pm\nThe New Leader in Verification IP: Questa + Avery Solutions\nLuis Rodriguez | Senior Technical Product Manager & VIP Architect \nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n‌\n2:00 pm – 2:30 pm\nCapturing additional DFT coverage thru Functional Fault Grading\nByron Brinson | Product Engineer \nIdeally\, for manufacturing test coverage the goal is to achieve 100%. This becomes even more important for chips used in safety critical applications. However\, there are usually limitations regarding the amount of coverage that the DFT infrastructure can provide within a chip. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.\n‌\nb\nAccelerating Verification Closure with Siemens DFT Tailored Verification Solutions\nRick Koster | Product Engineer \nAs semiconductor designs evolve to more complex architectures\, 3DICs\, and heterogeneous integration\, verification engineers face increasing pressure to accelerate DFT verification closure. Siemens offers a comprehensive technology suite tailored to industry leading Tessent solutions\, designed to address the growing complexity and increasing challenges in Design for Test (DFT). This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows\, delivering industry leading performance and enhanced user experience\, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.\n‌\n3:00 pm- 5:00 pm\nTopGolf happy hour & networking\n‌ \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verification-academy-live-austin/ LOCATION:Top Golf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, United States CATEGORIES:EDA,Seminar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241103T080000 DTEND;TZID=America/Los_Angeles:20241108T170000 DTSTAMP:20260408T025412 CREATED:20241004T174855Z LAST-MODIFIED:20241004T174855Z UID:8376-1730620800-1731085200@marketingeda.com SUMMARY:ITC 2024 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWe are holding the conference in beautiful San Diego\, CA.  We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! \nITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum\, where the wide range of its offerings allows ITC participants to learn\, network and conduct business. This year’s program includes a top-notch technical program\, vibrant exhibitors\, information-packed tutorials\, interactive technical panels\, three workshops\, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions\, a large number will focus on AI\, automotive\, memory\, and hardware security. In complement to the paper presentations\, there will be special sessions on hardware security certification\, chiplet integration\, silicon lifecycle management\, computing in memory\, as well as design and test of high-power compound devices and quantum electronics. \nWe are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances. \nITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology. \nThis year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening. \nLast\, but not least\, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time\, expertise\, and enthusiasm. Without their hard work and dedication\, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future. \nITC is the premier event for networking\, where professionals from all over the world converge to sharpen skills\, exchange ideas and do business. Join us\, throughout the conference\, for networking activities and to unwind. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/itc-2024/ LOCATION:Hilton San Diego Bayfront\, 1 Park Blvd\, San Diego\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241030T090000 DTEND;TZID=America/Los_Angeles:20241030T100000 DTSTAMP:20260408T025412 CREATED:20241016T180601Z LAST-MODIFIED:20241016T180601Z UID:8419-1730278800-1730282400@marketingeda.com SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241027T080000 DTEND;TZID=America/New_York:20241031T170000 DTSTAMP:20260408T025412 CREATED:20240925T172254Z LAST-MODIFIED:20240925T172254Z UID:8353-1730016000-1730394000@marketingeda.com SUMMARY:ICCAD 2024 DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/iccad-2024/ LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241023T090000 DTEND;TZID=America/Los_Angeles:20241023T100000 DTSTAMP:20260408T025412 CREATED:20241009T193236Z LAST-MODIFIED:20241009T193236Z UID:8402-1729674000-1729677600@marketingeda.com SUMMARY:Hardware Verification using VirtuaLAB DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/hardware-verification-using-virtualab/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20260408T025412 CREATED:20240725T182742Z LAST-MODIFIED:20240725T182818Z UID:8184-1729584000-1729702800@marketingeda.com SUMMARY:Jasper User Group San Jose 2024 DESCRIPTION:The CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 – 23 at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. \nShare Your Story\nWe’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted\, you can: \n\nIncrease industry visibility for you and your team’s field of expertise\nImprove and fine-tune your methods with insights from colleagues across the industry\nEarn wide acclaim with a Best Presentation Award nomination\n\n  \nPlease visit the website for further information. Accepted authors are expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm PDT on Monday\, August 26\, 2024. \nConference registration will open at the end of August. We look forward to meeting you at Jasper User Group San Jose 2024! \nQuestions? Please email us. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/jasper-user-group-san-jose/ LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Jasper-October-22-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20260408T025412 CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT END:VCALENDAR