BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.20//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20250309T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20251102T070000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241119T090000 DTEND;TZID=America/Los_Angeles:20241119T100000 DTSTAMP:20260410T064234 CREATED:20241019T030235Z LAST-MODIFIED:20241019T030235Z UID:8436-1732006800-1732010400@marketingeda.com SUMMARY:Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design DESCRIPTION:The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC\, GPU\, mobile\, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. \nFor the past years\, Synopsys and Ansys have been creating design flows that carry designers through early exploration\, implementation\, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market. \nRegister now to learn about:\n– Multi-die design best practices for thermal\, signal\, and power integrity\n– Insights from practical multi-die design case studies\n– More advanced packaging technologies for thermal management\, backside power\, and co-packaged optics \nSPEAKERS \nMarc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose\, CA. Before joining Ansys\, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys\, Azuro\, and Sequence Design\, where he gained experience with a wide array of digital and analog design tools. \nKeith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design\, analog/mixed signal (AMS) and RF/mmWave product experience\, including 8 years designing high speed data converters and amplifiers at Analog Devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ansys-synopsys-technology-update-the-latest-advances-in-multi-die-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Synopsys-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241118T080000 DTEND;TZID=America/Los_Angeles:20241118T170000 DTSTAMP:20260410T064234 CREATED:20240524T205337Z LAST-MODIFIED:20240524T205337Z UID:8049-1731916800-1731949200@marketingeda.com SUMMARY:Workshop on Open Source EDA Technologies (WOSET) DESCRIPTION:Virtual! No registration fee! \nThe WOSET workshop aims to galvanize the open-source EDA movement. The\nworkshop will bring together EDA researchers who are committed to\nopen-source principles to share their experiences and coordinate\nefforts towards developing a reliable\, fully open-source EDA flow. The\nworkshop will feature presentations and posters that overview existing\nor under-development open-source tools\, designs and technology\nlibraries. A live demo session for tools in advanced state will be\nplanned. The workshop will feature a panel on the present status and\nfuture challenges in open-source EDA\, and how to coordinate efforts\nand ensure quality and interoperability across open-source tools. \nTopics of interest include\, but are not limited to:\n* Overview of an existing or under-development open-source EDA tool.\n* Overview of support infrastructure (e.g. EDA databases and design benchmarks).\n* Open-source cloud-based EDA tools\n* Open-source hardware designs\n* Position statements (e.g. critical gaps\, blockers/obstacles) \nSubmission Information\n* All submissions must include links to open-source repositories with\nall source code and an open-source license (BSD\, GPL\, Apache\, etc.)\n* Please reference your open-source repository!\n* Review is single blind (anonymous reviewers).\n* Videos will be put on WOSET site if accepted.\n* Virtual presentation for regular papers (in addition to archival video)\n* Regular Paper Submissions (3-4 pages + 1 page references + 15 min video + virtual presentation)\n* Work in Progress Submissions (1-2 page abstract + 1 page references + 10 min video + virtual zoom room)\n* Submission site: https://lnkd.in/gEtDztEY \nImportant dates:\n* Sept 23 2024 (end of day\, anywhere in world): submission due date.\n* Oct 18 2024: notification date.\n* Nov 8 2024: video due (if accepted)\n* Nov 18 2024: workshop \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/workshop-on-open-source-eda-technologies-woset/ CATEGORIES:EDA,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WOSET-2024.jpg ORGANIZER;CN="UC Santa Cruz":MAILTO:mrg@ucsc.edu END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260410T064234 CREATED:20241030T170948Z LAST-MODIFIED:20241030T170948Z UID:8460-1731578400-1731582000@marketingeda.com SUMMARY:Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling DESCRIPTION:In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges\, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and power efficiency of deep learning algorithms\, including Deep and Convolutional Neural Networks (DNNs and CNNs). \nThrough system-level modeling\, design teams can analyze and optimize critical factors such as response time\, power consumption\, component selection\, and cost-effectiveness before finalizing their designs. This session is particularly beneficial for SoC architects\, embedded systems designers\, and other professionals working to balance performance\, power\, and cost for AI deployments in demanding environments. \nWhat You’ll Learn \nWith AI systems like CNNs now integral to technologies in real-time tracking\, object detection\, and autonomous navigation\, the need for architecture trade-offs has intensified. Our approach to system-level modeling allows teams to: \n\nEvaluate Hardware Combinations: Assess combinations of CPUs\, GPUs\, AI-specific processing units\, and standalone FPGAs to select the best configuration for your needs.\nOptimize Task Partitioning: Partition tasks across chips to achieve targeted performance without compromising power efficiency or exceeding budget constraints.\nRealistic Workload Simulation: Use cycle-accurate models to depict AI/ML algorithm performance under real-world conditions\, creating accurate simulations of hardware components in action.\n\nThrough detailed case studies across industries like automotive\, avionics\, data centers\, and radar systems\, you’ll see how this methodology applies to diverse scenarios\, helping to trade off key performance indicators (e.g.\, vehicle mileage vs. processing power). \n\n\n\n\nKey Takeaways\n\n\n\n\n\nTrade-Off Latency\, Power\, and Cost Using Early Simulation\n\nBy modeling early\, teams can visualize trade-offs and make informed decisions on processor and component selection to hit project goals effectively.\n\n\nIntegrate Shift-Left and Shift-Right Strategies in System-Level Modeling\n\nBring software testing and design validation forward to avoid issues in later stages\, enhancing the quality of final designs.\n\n\nMap Applications to Diverse Processing Units\n\nLearn to deploy applications seamlessly across CPUs\, GPUs\, TPUs\, and AI engines to maximize AI’s impact while optimizing for cost and power.\n\n\nFoster Collaboration Between OEMs\, Tier 1 Suppliers\, and Semiconductor Manufacturers\n\nUse our methodology to facilitate better communication and integration across all stakeholders involved in the AI hardware design process.\n\n\n\nWhether you’re involved in automotive\, avionics\, or advanced SoC architectures\, this session offers an invaluable opportunity to master the nuances of system-level modeling for AI architecture and streamline your deep learning deployment. \nDon’t Miss Out on Transforming Your AI Deployment Strategy!\nJoin us for this exclusive session and gain the insights you need to optimize your systems and semiconductor architecture for cutting-edge deep learning applications. \n\n\n\n\nDate: November 14th\, 2024\nSession 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China \nSign up: https://bit.ly/4eZqnjP \nSession 2: 10:00 AM USA PDT / 1:00 PM USA EDT \nRegister: https://bit.ly/3YFM82o \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimize-systems-and-semiconductor-architecture-for-deep-learning-algorithms-using-system-level-modeling/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260410T064234 CREATED:20241025T163841Z LAST-MODIFIED:20241025T163841Z UID:8456-1731578400-1731582000@marketingeda.com SUMMARY:AI-Driven Constraint Generation for PCB and IC Package Design DESCRIPTION:Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. \nKey Takeaways:\n \n\nLearn how the Sigrity Topology Workbench\, a robust system-level SI/PI environment for what-if and pre-route analysis\, is linked to the Allegro X PCB and IC package implementation tools.\nExperience the power of AI optimization in simulating parameterized structures to quickly reach target objectives\, and see how the physical attributes that meet these target objectives are automatically fed into the implementation tool as constraints.\nEnvision the efficiency of reusing or updating AI-generated constraints in future designs to consistently reduce design cycle time\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ai-driven-constraint-generation-for-pcb-and-ic-package-design/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241113T150000 DTEND;TZID=Europe/London:20241113T153000 DTSTAMP:20260410T064234 CREATED:20241105T180842Z LAST-MODIFIED:20241105T180842Z UID:8469-1731510000-1731511800@marketingeda.com SUMMARY:Tessolve AI Strategy & Eco System for DV DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI Strategy & Eco System for DV\n\nAI Strategies at Tessolve\nAI Tool range for DV-\n\nDV RAG Tool\,\nAssertify\,\nUnit TB Generation\,\nUVM AI\,\nISO26262 AI etc.\n\n\n\n  \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/tessolve-ai-strategy-eco-system-for-dv/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tesolve-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T110000 DTEND;TZID=America/Los_Angeles:20241112T120000 DTSTAMP:20260410T064234 CREATED:20241021T181622Z LAST-MODIFIED:20241021T181734Z UID:8440-1731409200-1731412800@marketingeda.com SUMMARY:Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification DESCRIPTION:High-level design techniques and automation tools to address the limitations of traditional RTL\, reduce verification times\, improve performance\, and manage growing design complexity—integrating seamlessly.\n\n\nWhat You’ll Learn:\n\n\n\n\nThis Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary\, but familiarity with hardware design and RTL synthesis is recommended. \nSome key takeaways you can expect: \n** Rise Design Automation Overview – Introduction to the tools\, use cases\, methodologies\, and project value of raising the abstraction beyond RTL with Rise. \n** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog. \n** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity. \n** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling\, pipelining\, and scheduling to optimize power\, performance\, and area—while gaining early insights into trade-offs. \n** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework. \n** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning\, DSP\, and video/image processing. \n** Learn how collaboration between system architects\, RTL designers\, and verification engineers speeds up development and delivers more reliable hardware. \n\n\n\n\nWho should attend:\n\n\n\n\n** Design Engineers looking to improve control paths\, data flow\, and performance\, while adopting new methods gradually and with minimal risk. \n** Verification Engineers looking to implement earlier\, more efficient verification processes to minimize risk and accelerate timelines\, without overhauling their current flows. \n** Project Leads managing trade-offs in timelines\, power\, performance\, and area\, while ensuring smooth integration of new techniques into existing processes. \n** System Architects looking to model\, explore\, and validate architectural decisions early\, focusing on performance\, power\, and area trade-offs without late-stage surprises. \n\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/rise-together-beyond-rtl-practical-techniques-for-improving-asic-design-efficiency-and-early-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-DA-November-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T080000 DTEND;TZID=America/Los_Angeles:20241114T170000 DTSTAMP:20260410T064234 CREATED:20241030T174154Z LAST-MODIFIED:20241030T174154Z UID:8463-1731398400-1731603600@marketingeda.com SUMMARY:IEEE World Technology Summit - AI INFRASTRUCTURE DESCRIPTION:This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems\, focusing on these core areas: \n\nAI applications and their required infrastructure\nSilicon to support AI applications\nSystems to support AI applications\nSecurity and Standards\n\nAI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit\, where companies\, governments\, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions. \nThe main focus of this conference is AI Infrastructure. \nTo deliver value we need the infrastructure for AI to work!!! This infrastructure includes software\, data storage\, computing\, communications\, power and energy\, standards\, and security. \nTo form an event to address the above issues\, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns\, challenges\, solutions\, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI\, which is critical to make AI work. \nCompanies are invited to sponsor\, engage\, and have employees attend this event. \nIf interested\, contact us at: wtscontact@ieee.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ieee-world-technology-summit-ai-infrastructure/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WTS-November-12-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241107T080000 DTEND;TZID=Asia/Taipei:20241109T170000 DTSTAMP:20260410T064234 CREATED:20240522T185455Z LAST-MODIFIED:20240522T185455Z UID:8022-1730966400-1731171600@marketingeda.com SUMMARY:APCCAS 2024 DESCRIPTION:The APCCAS is a major international forum for researchers\, scientists\, educators\, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including\, but not limited to the following： \n\nArtificial Intelligence Circuits\, Systems\, and Applications\nDigital Integrated Circuits and Systems\nAnalog and Mixed Signal Circuits and Systems\nPower and Energy Circuits and Systems\nBiomedical Circuits and Systems\nSensory Circuits and Systems\nRF/Communications Circuits and Systems\nBeyond CMOS: Nanoelectronics and Hybrid Systems Integration\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/apccas-2024/ LOCATION:Chang Yung-Fa Foundation\, No. 11\, Zhongshan S. Rd.\, Taipei City\, Taiwan CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/APCCAS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20260410T064234 CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T183000 DTEND;TZID=America/Los_Angeles:20241106T210000 DTSTAMP:20260410T064234 CREATED:20240927T160600Z LAST-MODIFIED:20240927T160600Z UID:8357-1730917800-1730926800@marketingeda.com SUMMARY:Phil Kaufman Award & Banquet DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \nElectronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor \nDR. JASON CONG\nDistinguished Professor and Volgenau Chair for Engineering Excellence at the University of California\, Los Angeles (UCLA) with the \n2024 Phil Kaufman Award\n2024 Award Recipient\nDr. Jason Cong will be honored for sustained fundamental contributions to Field-Programmable Gate Array (FPGA) design automation technology\, from circuit to system levels\, with widespread industrial impact. His contributions cover four key areas of EDA: \nAlgorithmic Foundations for FPGA Synthesis \nInterconnect Optimization \nDomain Specific FPGA Computing \nNeural Nets in FPGA \nIn addition to being an excellent educator\, Dr. Cong has an outstanding track record of transforming his research results to EDA tools to benefit the EDA industry. \nDr. Jason Cong will be honored at the 2024 Phil Kaufman Award Ceremony and Banquet on November 6\, 2024 in San Jose\, CA. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/phil-kaufman-award-banquet-3/ LOCATION:Hayes Mansion\, 200 Edenvale Avenue\, San Jose\, CA\, United States CATEGORIES:Award,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Kaufman-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T100000 DTEND;TZID=America/Los_Angeles:20241106T110000 DTSTAMP:20260410T064234 CREATED:20241018T165537Z LAST-MODIFIED:20241018T165537Z UID:8433-1730887200-1730890800@marketingeda.com SUMMARY:Navigating Trends and Tools in Automotive Design with Cadence DESCRIPTION:Join us for our first webinar in this insightful series\, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles\, highlighting key trends such as ADAS\, software-defined vehicles\, and zonal architectures. \nLearn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety. \nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together! \nWhat will be covered: \n\nEmerging trends in ADAS\, software-defined vehicles\, zonal architectures\, connectivity\, and electrification\nHow high-performance centralized computing\, cloud-native software development\, power management\, safety design support\, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.\n\nWho Should Attend: \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers\, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-trends-and-tools-in-automotive-design-with-cadence/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-Nnovember-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20241106T093000 DTEND;TZID=America/Chicago:20241106T170000 DTSTAMP:20260410T064234 CREATED:20241017T160613Z LAST-MODIFIED:20241017T160903Z UID:8425-1730885400-1730912400@marketingeda.com SUMMARY:Verification Academy Live: Austin DESCRIPTION:Overview \nThis seminar will update you on technologies and techniques you can adopt to\nincrease your verification productivity today. Specifically\, we will cover: \n\nHow the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains.\nProtocol and memory verification solutions you need for your next silicon verification project.\nData-driven verification with automated analytics\, collaboration\, and traceability capabilities.\nTechnologies and techniques you can adopt to increase your DFT productivity.\n\n‌\n‌ \nAgenda \n9:30 am – 10:00 am\nRegistration and check-in\nCoffee and networking with your peers\n‌\n10:00 am – 10:05 am\nWelcome/Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n‌\n10:05 am – 11:00 am\nKeyNote: Smart Verification – Faster is not Enough\nAbhi Kolpekwar | VP & GM\, Digital Verification Technologies Division \nThe electronics industry is on the brink of an unprecedented paradigm shift. The AI/ML-focused chips account for 20% of the semiconductor market\, a figure set to skyrocket to 73% by 2030\, fueled by the ongoing digital transformation. This seismic shift will significantly impact the architecture\, design\, and manufacturing of computing\, networking\, and communication solutions\, necessitating careful consideration of power\, performance\, security\, and safety concerns. Conventional verification flows\, reliant on disparate point tools\, will struggle to meet the demands of emerging systems. This keynote explores the prevailing macro-trends shaping today’s digital transformation before outlining a visionary approach to functional verification. By leveraging collective wisdom across tools\, technologies\, workflows\, and methodologies\, this new paradigm promises productivity gains beyond the reach of traditional methods.\n‌\n11:00 am – Noon\nQuesta Verification IQ:\nBoost verification predictability and efficiency with Big Data\nAhmed ElKady | Product Engineer \nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost.\n‌\nNoon – 12:45 pm\nLunch and networking\n‌\n12:45 pm – 1:15 pm\nQuesta Verification IQ: Sneak Peek of Debug IQ and Regression IQ\n‌\nContinuation of the Questa Verification IQ session.\n‌\n1:15 pm – 2:00 pm\nThe New Leader in Verification IP: Questa + Avery Solutions\nLuis Rodriguez | Senior Technical Product Manager & VIP Architect \nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n‌\n2:00 pm – 2:30 pm\nCapturing additional DFT coverage thru Functional Fault Grading\nByron Brinson | Product Engineer \nIdeally\, for manufacturing test coverage the goal is to achieve 100%. This becomes even more important for chips used in safety critical applications. However\, there are usually limitations regarding the amount of coverage that the DFT infrastructure can provide within a chip. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.\n‌\nb\nAccelerating Verification Closure with Siemens DFT Tailored Verification Solutions\nRick Koster | Product Engineer \nAs semiconductor designs evolve to more complex architectures\, 3DICs\, and heterogeneous integration\, verification engineers face increasing pressure to accelerate DFT verification closure. Siemens offers a comprehensive technology suite tailored to industry leading Tessent solutions\, designed to address the growing complexity and increasing challenges in Design for Test (DFT). This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows\, delivering industry leading performance and enhanced user experience\, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.\n‌\n3:00 pm- 5:00 pm\nTopGolf happy hour & networking\n‌ \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verification-academy-live-austin/ LOCATION:Top Golf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, United States CATEGORIES:EDA,Seminar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241103T080000 DTEND;TZID=America/Los_Angeles:20241108T170000 DTSTAMP:20260410T064234 CREATED:20241004T174855Z LAST-MODIFIED:20241004T174855Z UID:8376-1730620800-1731085200@marketingeda.com SUMMARY:ITC 2024 DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWe are holding the conference in beautiful San Diego\, CA.  We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! \nITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum\, where the wide range of its offerings allows ITC participants to learn\, network and conduct business. This year’s program includes a top-notch technical program\, vibrant exhibitors\, information-packed tutorials\, interactive technical panels\, three workshops\, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions\, a large number will focus on AI\, automotive\, memory\, and hardware security. In complement to the paper presentations\, there will be special sessions on hardware security certification\, chiplet integration\, silicon lifecycle management\, computing in memory\, as well as design and test of high-power compound devices and quantum electronics. \nWe are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances. \nITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology. \nThis year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening. \nLast\, but not least\, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time\, expertise\, and enthusiasm. Without their hard work and dedication\, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future. \nITC is the premier event for networking\, where professionals from all over the world converge to sharpen skills\, exchange ideas and do business. Join us\, throughout the conference\, for networking activities and to unwind. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/itc-2024/ LOCATION:Hilton San Diego Bayfront\, 1 Park Blvd\, San Diego\, CA\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241030T090000 DTEND;TZID=America/Los_Angeles:20241030T100000 DTSTAMP:20260410T064234 CREATED:20241016T180601Z LAST-MODIFIED:20241016T180601Z UID:8419-1730278800-1730282400@marketingeda.com SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241027T080000 DTEND;TZID=America/New_York:20241031T170000 DTSTAMP:20260410T064234 CREATED:20240925T172254Z LAST-MODIFIED:20240925T172254Z UID:8353-1730016000-1730394000@marketingeda.com SUMMARY:ICCAD 2024 DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/iccad-2024/ LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241023T090000 DTEND;TZID=America/Los_Angeles:20241023T100000 DTSTAMP:20260410T064234 CREATED:20241009T193236Z LAST-MODIFIED:20241009T193236Z UID:8402-1729674000-1729677600@marketingeda.com SUMMARY:Hardware Verification using VirtuaLAB DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/hardware-verification-using-virtualab/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20260410T064234 CREATED:20240725T182742Z LAST-MODIFIED:20240725T182818Z UID:8184-1729584000-1729702800@marketingeda.com SUMMARY:Jasper User Group San Jose 2024 DESCRIPTION:The CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 – 23 at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. \nShare Your Story\nWe’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted\, you can: \n\nIncrease industry visibility for you and your team’s field of expertise\nImprove and fine-tune your methods with insights from colleagues across the industry\nEarn wide acclaim with a Best Presentation Award nomination\n\n  \nPlease visit the website for further information. Accepted authors are expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm PDT on Monday\, August 26\, 2024. \nConference registration will open at the end of August. We look forward to meeting you at Jasper User Group San Jose 2024! \nQuestions? Please email us. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/jasper-user-group-san-jose/ LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Jasper-October-22-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20260410T064234 CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20260410T064234 CREATED:20240806T194900Z LAST-MODIFIED:20240806T194900Z UID:8209-1729152000-1729184400@marketingeda.com SUMMARY:OSMOSIS 2024 DESCRIPTION:Elevate your success with osmosis 2024\nThe annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative\, we invite you to unveil it at osmosis. \nYou will benefit from increased industry visibility as a subject matter expert\, and the conversations that follow may help you and others improve formal-based verification solutions. \n\n\nAbstract guidelines\nCraft a concise narrative outlining the essential bits of your success story\, encompassing: \n\nthe intricate problem you addressed\nrationale for employing formal technology-based solutions\ntangible outcomes\, ideally quantifiable\nkey learnings and findings\n\nFor utmost impact\, please limit your abstract to a single page\, front and back. \nInclude diagrams and code examples if desired. \nIf you have questions or need guidance in refining your narrative\, please reach out to us at osmosis.sisw@siemens.com \n\n\nSchedules and processes\nThe deadline for abstract submissions is 6 p.m. Central EU time on Mon.\, Sept. 23\, 2024. \nSubmissions will be evaluated as they are received. As we select abstracts\, we will begin working with the authors on their presentations. If we fill the agenda early\, we’ll close submissions. \n\n\nWe look forward to receiving your abstracts and seeing you in Munich! \n\n\nOn-demand presentations\nCheck out past\, on-demand presentations. \n\nOsmosis Aerospace and Defense – April 2024\nOsmosis Aerospace and Defense – 2023\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/osmosis-2024/ LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSMOSIS-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20260410T064234 CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20241015T080000 DTEND;TZID=Europe/Berlin:20241016T170000 DTSTAMP:20260410T064234 CREATED:20240130T165521Z LAST-MODIFIED:20240130T165521Z UID:7564-1728979200-1729098000@marketingeda.com SUMMARY:DVCon Europe 2024 DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools\, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications\, and demonstrations for the practical use of EDA solutions for electronic design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/dvcon-europe-2024/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241010T110000 DTEND;TZID=America/Los_Angeles:20241010T120000 DTSTAMP:20260410T064234 CREATED:20241007T181311Z LAST-MODIFIED:20241007T181311Z UID:8383-1728558000-1728561600@marketingeda.com SUMMARY:The Development and Evolution of Verilog & SystemVerilog DESCRIPTION:Abstract: \nSystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities\, constrained random testing (CRT)\, and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today. \nCliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog\, why the features were added\, and the origins of many of those features.\n\nAgenda:\n\nVerilog HDL and Its Ancestors and Descendants (reference paper)\nBrief History of Verilog & SystemVerilog\nHILO\, Verilog\, C\, PLI\nSDF\, Synthesis\, VHDL\, VPI\nSuperlog\, IHDL (Intel)\, SystemC\, Vera\nOOP\, e-Specman\, SystemVerilog\, C++\nOVL\, PSL\, SVA\nOVM / UVM history\nSimulation & Functional Coverage\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nClifford E. Cummings\, \nVice President of Training at Paradigm Works and Founder of Sunburst Design \nCliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog\, UVM\, CDC and synthesis training classes. Cliff has 42 years of ASIC\, FPGA and system design experience and 32 years of combined Verilog\, SystemVerilog\, UVM verification\, synthesis\, and methodology training experience.  Cliff has taught expert Verilog\, SystemVerilog\, Design Synthesis\, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics.  Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/the-development-and-evolution-of-verilog-systemverilog/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241008T120000 DTEND;TZID=Europe/London:20241008T130000 DTSTAMP:20260410T064234 CREATED:20240911T161307Z LAST-MODIFIED:20240911T161307Z UID:8325-1728388800-1728392400@marketingeda.com SUMMARY:Cocotb 2.0: Modernize your testbenches for even more productivity DESCRIPTION:Cocotb 2.0 is the latest major version of cocotb\, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches\, you can benefit from improved typing and less surprising corner cases. In this talk\, we’ll show what’s new in cocotb 2.0\, and how you can modernize your code bases to make best use of it.  We also have a presentation from a cocotb user performing HDL simulation with python cocotb\, with a Transaction Level Modelling (TLM) approach with a completely free and open source chain (GHDL simulator and WSL Linux). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAgenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 BST\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 BST\nSimple yet powerful: Open-source HDL simulation with Cocotb \nHayder Al-Hakeem ( Wärtsilä Finland)\n\n\n\n\n12.30 BST\nCocotb 2.0: Modernize your testbenches for even more productivity \nPhilipp Wagner ( FOSSi Foundation)\n\n\n\n\n13.00 BST\n  \nClose\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community. \n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cocotb-2-0-modernize-your-testbenches-for-even-more-productivity/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-October-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241008T100000 DTEND;TZID=America/Los_Angeles:20241008T150000 DTSTAMP:20260410T064234 CREATED:20240917T161235Z LAST-MODIFIED:20240917T161235Z UID:8340-1728381600-1728399600@marketingeda.com SUMMARY:Accelerating DFT verification sign-off with the Questa DFT Verification Platform DESCRIPTION:Accelerating DFT verification sign-off with the Questa DFT Verification Platform \nThis seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically\, we will cover:\n‌\nNavigating the Growing Complexity of Design-for-Test and Evolving Verification Challenges\nRevolutionizing Test Strategies to deliver reliable products into HPC\, Automotive\, Aerospace\, Medical\, and beyond\n‌ \nAgenda: \n10:00 am – 10:25 am\nRegistration and check-in\nCoffee and networking with your peers.\n‌\n10:25 am – 10:30 am\nWelcome/Intro\nHarsh Patel | Sr. AE Manager\, Functional Verification\n‌\n10:30 am -11:15 am\nUnderstanding and navigating the new challenges in Design-for-Test\nLee Harrison | Director of Product Marketing -Tessent\n‌\n11:15 am – 12:00 noon\nAccelerating verification closure with Siemens DFT tailored verification solutions\nJake Wiltgen | Director\, IC Verification Solutions\n‌\n12:00 noon – 12:30 pm\nLunch and networking\n‌\n12:30 pm – 1:15 pm\nEmbracing a New Era in DFT: Addressing High Defect Coverage\, Silent Data Errors\, and Emerging Challenges\nLee Harrison | Director of Product Marketing -Tessent\n‌\n1:15 pm – 2:00 pm\nIncreasing fault coverage with Siemens Functional Fault Grading solutions\nAnn Keffer | Product Manager\n‌\n2:00 pm – 3:00 pm\nWrap-up and networking \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-dft-verification-sign-off-with-the-questa-dft-verification-platform/ LOCATION:Siemens EDA\, 46871 Bayside Parkway\, Building B\, Fremont\, CA\, United States CATEGORIES:EDA,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-8-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241008T080000 DTEND;TZID=America/Los_Angeles:20241011T170000 DTSTAMP:20260410T064234 CREATED:20240906T174011Z LAST-MODIFIED:20240926T000653Z UID:8301-1728374400-1728666000@marketingeda.com SUMMARY:PCB West 2024 DESCRIPTION:For more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/pcb-west-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241003T113000 DTEND;TZID=America/Los_Angeles:20241003T170000 DTSTAMP:20260410T064234 CREATED:20240827T163546Z LAST-MODIFIED:20240827T163546Z UID:8283-1727955000-1727974800@marketingeda.com SUMMARY:Signoff Special Interest Group DESCRIPTION:Join us at this year’s Synopsys Signoff SIG (Special Interest Group) event. \nSignoff is a critical quality control checkpoint in the chip development process\, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year’s Synopsys Signoff SIG event\, we’ll explore how signoff can help meet these scalability challenges. We’ll here from several industry-leading companies how they are using the latest technology advances in timing\, power\, extraction\, and eco to realize the full PPA potential of their designs with the fastest path to design closure. \n\n\n\n\n\n\n\n\nAgenda\n\n\nMore details coming soon. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n11:30 – 12:30 PM PDT\n\n\nRegistration Check in & Lunch\n\n\nBadge pick-up begins at 11:30. Lunch will be served\, come early for a chance to eat and network before sessions begin. \nRead Less \n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n12:30 – 01:15 PM PDT\n\n\nKeynote\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n01:15 – 04:05 PM PDT\n\n\nTechnical Sessions\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n04:05 – 05:00 PM PDT\n\n\nNetworking Reception\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/signoff-special-interest-group/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,Seminar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241003T090000 DTEND;TZID=America/Los_Angeles:20241003T170000 DTSTAMP:20260410T064234 CREATED:20240911T225059Z LAST-MODIFIED:20240911T225246Z UID:8328-1727946000-1727974800@marketingeda.com SUMMARY:VC Formal Special Interest Group DESCRIPTION:Register for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users\, managers\, and enthusiasts to stay connected with the latest formal verification innovations\, techniques and methodologies. \nIndustry leaders such as Amazon\, Black Sesame\, Microsoft\, NVIDIA\, Samsung\, and Untether AI will share their experiences with the latest formal verification technologies. Topics that will be covered include strategies for achieving formal convergence\, exploring formal methodologies used for RISC-V verification\, and the integration of VC Formal with generative AI functionalities – which offer the potential to automate the creation of formal verification testbenches. \nKeynote Session \n\nThe Impact of LLMs on Formal Verification \nExplore how LLMs can transform formal verification\, reducing manual effort and improving results. We’ll discuss current benchmarks and future goals for deploying LLMs to enhance formal verification processes. \nPresented by Syed Suhaib\, NVIDIA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/vc-formal-special-interest-group/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VC-Formal-SIG-October-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241003T080000 DTEND;TZID=America/Los_Angeles:20241004T170000 DTSTAMP:20260410T064234 CREATED:20241002T224220Z LAST-MODIFIED:20241004T174051Z UID:8372-1727942400-1728061200@marketingeda.com SUMMARY:Electronic Design Process Symposium (EDPS) - 2024 DESCRIPTION:EDPS 2024 is now taking shape. The place to be is once again SEMI\, in Milpitas\, and the dates are Thursday and Friday\, Oct 3rd and 4th\, 2024. \nRegistration is now open: https://2024-ieee-edps.eventbrite.com. Who needs to register? Please see the Registration page. \nTalks from EDPS 2023 and the last 24 years of EDPS\, are are available and searchable\, on the Prior Years page. \nDay 1\, Thursday 9:00am; Session 1\n9:05am\n\nEnergy and Thermal Management of Chips\, Systems and Datacenters Necessitates a Return to Fundamentals\nChandrakant Patel\nHP\n\n  \nThe latter part of 20th century witnessed the rise of the compute utility made up of large-scale data centers housing densely packed compute\, storage and networking equipment. The cyber age data centers became modern day factories requiring megawatts of power for the information technology (IT) equipment much like the process equipment in a factory of the machine age. Electrical energy supplied to the chips and systems in the data centers turned into multi-megawatts of heat energy which in turn required heat removal means. The active heat removal means also required power. While many innovative measures have been used for heat removal and energy management in data centers\, there is a substantial gap in application of fundamentals of engineering when compared to the approaches taken by the contributors of the 19th and early 20th century machine age. As an example\, machine age contributors performed exergy (2nd law of thermodynamics) analysis and deemed it necessary to build a hydro-electric plant as part of the design of an Aluminum factory. Indeed\, majority of data centers today rely on the power infrastructure built by our predecessors. Given the inexorable trajectory of data centers strongly driven by AI\, and associated demands on available energy\, it is time we returned to such fundamentals particularly given the environmental challenges. \nIn my talk\, I will present a holistic approach that traces the energy flow from a power plant to a chip\, and from the chip core to the cooling tower. \n10:00am\n\nEnabling Effortless Machine Learning for Embedded Edge Applications\nGopal Hegde\nSiMa.ai\n\n  \nMachine Learning is a game changing technology of our generation and similar Internet in the 1990s\, will impact every aspect of our life. While Machine Learning use cases and applications are well established in the cloud & IoT devices\, in the embedded edge market\, its usage is in its infancy. We at SiMa.ai are focused on disrupting this market by turbo charging embedded compute with the addition of machine learning. Embedded edge has space and power constraints and has a huge expertise gap relative to cloud computing when it comes to machine learning. The presentation covers market requirements\, key challenges and our unique software first approach to machine learning at embedded edge. We will discuss key market segments\, their unique requirements and how our silicon and software solutions provide a way for our customers to easily develop and deploy machine learning solutions that address their use cases and applications. \n10:35am\n\nAI: Trailblazing the Next Generation of Semiconductor Innovation\nVishal Khandewal\nSynopsys\n\n  \nWith AI-based applications coming pervasively mainstream through ChatGPT\, digital healthcare\, and almost everything else we do with our devices daily\, digital chip design is seeing an exponential push towards complexity\, performance\, power\, and time-to market. EDA tool flows are becoming mission critical to meet the demands of a hardware-led 4th industrial revolution that is driving everything towards being intelligent\, connected\, monitored and data-driven. In this talk we go into the details of how hardware design and EDA tools are evolving to deliver the next generation of performance\, power\, and productivity (PP&P) boost. Even with exponential growth in design productivity in the past decade\, overall design cycle is not meeting its intended targets. The technical complexity of advanced node design with new dominant effects like thermal and IR\, are leading to highly complex tool/methodology flows. This is where at Synopsys\, we have taken a full tool-stack approach to build pervasive AI into our tools to deliver unprecedented PP&P boost. We will share examples of applications ranging from design implementation\, verification\, test\, and analog/manufacturing to showcase the potential of this technology and how it is reshaping chip design workflows. Many of these technologies are taking us closer to the no-human-in-the-loop goal for chip design. With serious talent shortage and increase in solution complexity beyond human expertise\, AI-augmented solutions for chip design are the way forward. \n11:10am\n\nHarnessing LLMs for Advanced EDA Platforms: Code Generation and Beyond\nAkhilesh Kumar\nAnsys\n\n  \nLarge Language Models (LLMs) such as GPT-4\, Gemini\, Llama etc.\, have demonstrated astounding capabilities in a range of tasks such as knowledge extraction\, Q&A\, summarization\, code generation\, contextual problem solving etc. The LLMs can also be adapted to specific applications through a variety of methods such as fine tuning\, in-context learning\, RAG\, agent-based systems etc.\, making them quite versatile. \nModern EDA platforms\, such as Ansys SeaScape\, have sophisticated workflows\, hundreds of user APIs\, complex input data requirements\, and require deep domain knowledge and expertise for efficiently using the platform. This talk will discuss how LLMs can greatly improve the productivity and user experiences for such EDA platforms. The talk presents an overview of code generation techniques using LLMs and will discuss our experience in developing an LLM-based code generation solution for the Ansys SeaScape platform. Going beyond the code generation\, this presentation will discuss creating an LLM agent-based copilot for providing intuitive assistance to the users of the Ansys SeaScape platform for a variety of operational modalities. \n12:45pm\n\nThe Application of AI to Chip Design\nMark Ren\nNVidia\n\n  \nThe applications of AI in chip design undergo an evolutionary path. \nInspired by the success of AlphaGO\, Reinforcement Learning techniques were deployed to a number of design problems\, achieving results showing the potential of AI. \nThe advancement of Large Language Models further enabled the application of AI in a much broader set of design activities. \nLLM-based copilots can improve design productivity by providing knowledge and coding assistance; agents can provide further assistance in key design tasks such as analysis\, debugging\, and optimization. \nThe evolution of AI will continue\, and we will discuss critical challenges to realizing its revolutionary potential in the chip design process \n1:35pm\n\nHow AI is changing every aspect of EDA\, starting from transistor-level simulation\nSathishkumar Balasubramanian\nSiemens\n\n  \nThere is a lot of hype in the industry around AI\, but behind the hype there is the reality. That reality is that AI really is impacting virtually every aspect of semiconductor design. However\, its not as simple as taking general purpose AI solutions and hoping they work for EDA\, the risks are too high and when dealing with parts per billion (or trillion) in acceptable errors\, hallucinations are not acceptable. What is needed are Verifiable AI solutions that deliver results that users can trust and that reduce the overall resources needed to complete a task. At Siemens EDA we have been able to leverage Verifiable AI to accelerate virtually every aspect of the design and verification process. \nIn this presentation we will explore the requirements for\, and state of the art of\, AI in EDA application. We will explore AI’s impact on every aspect of design starting from transistor-level simulation. \n2:10pm\n\nTest\, Repair and Reliability Challenges of Chip-let Interconnects\nSreejit Chakravarty\nAmpere Computing\n\n  \nChip-let based design\, fueled by various advanced packaging technologies\, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement\, during high volume manufacturing\, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. RAS solutions required to address such reliability issues are highlighted. \n2:45pm\n\nArtificial Intelligence and Machine Learning for RF and Microwave Design\nJianjun Xu\nKeysight\n\n  \nThis talk reviews some powerful and practical Artificial Intelligence and Machine Learning (AI/ML) technologies for applications in traditional RF and Microwave design and beyond. After a very brief overview of the AI/ML landscape\, we focus on Artificial Neural Networks (ANNs) and provide several key examples of modern ANN applications to electronic\, electro-thermal\, and electro-chemical device modeling\, and behavioral modeling to illustrate the substantial benefits and generality of present techniques. \nThe talk concludes with a discussion of the potential of AI/ML technologies to address and solve future challenging and important RF and Microwave design problems\, e.g.\, for 6G. \n3:30pm\n\nPromises and Challenges of Digital Twin for Semiconductor Manufacturing\nAla Moradian\nApplied Materials\n\n  \nThe advancement of cutting-edge technologies like Artificial Intelligence (AI)\, Large Language Models (LLM)\, and Electric Vehicles (EV) demands sophisticated semiconductor devices with precise specifications. \nConcurrently\, the emergence of digital twins and AI stands as pivotal in facilitating the development and enablement of such technologies. \nThis talk delves into the vision and significance of AppliedTwin(tm)\, a proposed digital twin framework tailored for semiconductor manufacturing. \nAppliedTwin delineates various levels of abstractions ranging from digital fabrication facility down to digital twin of individual devices\, each characterized by distinct attributes governing their interaction with physical assets\, fidelity\, etc. \nApplied Materials has spearheaded the application of digital twins in semiconductor manufacturing with the introduction of EcoTwin(tm)\, a platform designed to promote sustainability. \nIn this talk the critical role of digital twins in propelling innovation and efficiency in semiconductor equipment manufacturing. \n4:05pm\n\nMaking Data Center Digital Twins a Reality\nPaul Harrison\nCadence\n\n  \nThis talk will discuss the application of Digital Twins to Data Centers. \nHistorically decisions for data center operations were made based on rules of thumb or the person who would most confidently put across their point of view. \nCabinet power densities continue to rise\, accelerated by AI\, increasing the need complex technologies like liquid cooling to be more widely implemented. This means data center operations have become more difficult to manage\, while the impact of their downtime can be catastrophic for companies. Fortunately\, data center operators are starting to adopt CFD-based Digital Twins to help inform their operational decisions\, improve their understanding\, and reduce the risks. This talk will explain how to create a Data Center Digital Twin\, some of the challenges with creating them\, how they integrate with data sources and existing processes\, and the benefits to operators this technology brings. \n4:40pm\n\nInnovating Semiconductor Manufacturing with ML-augmented Digital Twins\nNorman Chang\nElectronics\, Semiconductor\, and Optics BU\, Ansys\n\n  \nDeveloping each processing step in semiconductor manufacturing has heavily relied on in-situ sensors in the equipment and numerous try-outs in recipe generation. However\, with advancements in multiphysics simulation technologies\, an innovative ML-augmented hybrid simulation methodology has been developed. This methodology combines the strengths of multiphysics simulation and in-situ measurement in building semiconductor processing digital twins. In this talk\, we will review the current state-of-the-art digital twin technologies and identify the gaps that need to be addressed to fully utilize digital twins in developing new process recipes in semiconductor manufacturing. \n6:45pm\n\nSemiconductors and Artificial Intelligence:The Virtuous Cycle\nPushkar Apte\nSEMI\n\n  \nArtificial Intelligence (AI) has taken the world by storm\, and has become a strategic imperative for most industries. While the concept of AI is over half a century old\, it has accelerated rapidly just over the past decade\, in large part due to amazing advances in semiconductor chips. In turn\, AI is driving growth in semiconductor revenues and improvements in operational efficiency\, creating a virtuous cycle. \nHowever\, there are formidable roadblocks ahead. AI models and datasets are growing at an exponential rate\, far outpacing hardware advances – creating both performance and sustainability challenges. System-level innovation is required for continued progress in AI\, which requires meaningful collaboration and data-sharing – often difficult in an industry where IP is critical. \nThis presentation will focus on this virtuous cycle between semiconductors and AI\, highlighting the benefits\, challenges and solution paths for continued progress. \nDay 2\, Friday 9:00am; Session 1\n9:05am\n\nIs AI intelligent?\nRonjon Nag\nStanford Medicine\n\n  \nArtificial intelligence is in the news daily\, and people ask whether they are truly intelligent. \nMaybe it still lacks the depth of human intelligence today\, but where is already cleverer\, and what stops it from reaching the ultimate pinnacle of ”general intelligence” – could that ever be possible? We will consider the implications of creating truly intelligent machines and the potential consequences for human society. \n10:00am\n\nTrust Based Modeling for Improved Security\nNaresh Sehgal\nDeeply Human AI\n\n  \nThe present state of Edge Computing is an environment of different computing capabilities connected via various communication paths. Actors on the Edge may interact with each other and a central datacenter. An important part of information security is the evaluation of trust between actors\, whether those actors are people or machines. Although many distributed trust models exist\, our proposed model introduces three key concepts. The first concept is that trust is not bidirectional between two parties. The second concept is that trust is different between different actors\, based upon the nature of their relationships. The third concept is that trust depends on the content of a transaction. We will present some real-life examples to illustrate these concepts. \n10:35am\n\nAdvancing Hardware Security in the Post-Quantum Cryptography Landscape: Challenges and Solutions\nQian Wang\nU. Cal. Merced\n\n  \nHardware security in the era of post-quantum cryptography has become increasingly crucial due to the potential threat quantum computers pose to traditional cryptographic algorithms. Post-quantum cryptography aims to develop cryptographic algorithms that are resistant to attacks from quantum computers. However\, ensuring the security of these algorithms requires not only advancements in software but also robust hardware security measures. In this talk\, we will first discuss the implementation of quantum-resistant cryptographic modules on hardware platforms\, necessitating upgrades in both hardware and firmware to accommodate new algorithms efficiently. Moreover\, hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks\, where an attacker exploits information leaked through physical characteristics such as power consumption or electromagnetic radiation. Post-quantum cryptographic hardware must incorporate countermeasures to mitigate these risks. \n11:20am\n\nScaling to Meet the Needs of AI\nPradeep Dubey\nIntel\n\n  \nArtificial intelligence (AI) is impacting not just what computing can do for us\, rather how computing gets done. Fast-evolving AI algorithms are driving demand for growing performance at an unprecedented rate and scale. This talk is about some of our research aimed at exploring technological and system-level opportunities for cost-effective scaling of emerging AI datacenters. \n1:00pm\n\nThe Future of Generative AI: Key Technology Trends and Innovations\nShiva Kintali\nR3AI\n\n  \nLLMs have emerged as powerful tools\, revolutionizing various domains from natural language processing to content generation\, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention. \nWhile they offer convenience and productivity\, we dissect how they can also be manipulated and weaponized by malicious actors\, raising concerns about inherent biases\, jailbreaking potential\, security concerns\, privacy issues\, misinformation\, deepfakes\, cyber threats and their unsettling societal consequences. We explore how biases present in training data\, historical injustices\, and societal prejudices can be perpetuated and even amplified by these models\, posing a significant threat to fairness\, equity\, and inclusivity. \nThis talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges\, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences. \n1:35pm\n\nEmerging Technologies for Computing Paradigm Shift\nBrandon Wang\nSynopsys\n\n  \nThe explosive growth of AI has triggered a rapid increase in semiconductor demand\, leading to soaring power consumption and unsustainable water usage. This presentation will explore emerging technologies essential for driving a paradigm shift towards energy-efficient computing. Topics will include the “Shift Left” design methodology\, the impact of SLMs (Small Language Models) on computational efficiency in AI\, and the potential of neuromorphic and quantum computing as next-generation architectures. These advancements are poised to enable significant digital transformation and drive pervasive intelligence across various industries. The speaker will also provide insights into how organizations can stay at the cutting edge of these innovations\, offering a forward-looking perspective on the future of computational systems and the strategic steps needed to lead in this rapidly evolving landscape. \n2:10pm\n\nTBD\nChris Cheng\nHewlett-Packard Enterprise\n  \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/electronic-design-process-symposium-edps-2024/ LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States CATEGORIES:EDA,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/edps-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T110000 DTEND;TZID=America/Los_Angeles:20241001T113000 DTSTAMP:20260410T064234 CREATED:20240930T220024Z LAST-MODIFIED:20240930T220024Z UID:8361-1727780400-1727782200@marketingeda.com SUMMARY:Interactive SPICE Model Verification Platform ME-Pro DESCRIPTION:ME-Pro™ is a unified tool for designers\, process developers\, modeling engineers\, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation. \nThis comprehensive platform supports evaluation across device\, circuit\, and process domains enabling interactive development and offering critical feedback for process improvements. With decades of Primarius’ expertise\, ME-Pro™ features pre-configured templates\, hundreds of verification data entries\, and the built-in NanoSpice parallel simulator that is all designed to streamline setup and reduce learning curves. \nPresenter\nErik Supnet is a Senior Application Engineer at Primarius for two years supporting pre-sales and post-sales activities for modeling and simulation products. He earned his B.S. in Computer Engineering and M.A in Education at the University of the Pacific. Prior to his current role\, he held design engineering positions as D.E.C\, SiByte\, Broadcom\, and Intel\, and has a background in custom circuit design\, automation\, methodologies\, and education. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/interactive-spice-model-verification-platform-me-pro/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/primarius-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240926T100000 DTEND;TZID=America/Los_Angeles:20240926T110000 DTSTAMP:20260410T064234 CREATED:20240911T233717Z LAST-MODIFIED:20240911T233717Z UID:8333-1727344800-1727348400@marketingeda.com SUMMARY:Learn How to Simulate 2D-TMD-Channel FETs with Atomistic Precision DESCRIPTION:Are 2D-TMD-channel transistors suitable candidates for the replacement of silicon ? Considering the extreme scaling down to a few atomic layers of the FET channel\, only an atomistic solution looks viable. In this context\, we show how the Victory Atomistic tool can answer this essential question thanks to quantum mechanics\, offering valuable support for the prototyping effort of a 2D transistor in a professional TCAD environment. \nWhat You Will Learn\n\nAn understanding of the physics and engineering of 2D TMD NR architectures at the atomic scale\nWhy to use Atomistic TCAD\nHow to simulate and prototype at the atomic level\nExample of a 2D-TMD TFET\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Philippe Blaise\, Senior Application Engineer\, Silvaco\, Inc. \nDr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco\, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops\, plus 5 patents and one book chapter.\nDr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes\, France. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, device engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/learn-how-to-simulate-2d-tmd-channel-fets-with-atomistic-precision/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-September-26-2024.jpg END:VEVENT END:VCALENDAR