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DTSTART;TZID=America/Los_Angeles:20241103T080000
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LAST-MODIFIED:20241004T174855Z
UID:8376-1730620800-1731085200@marketingeda.com
SUMMARY:ITC 2024
DESCRIPTION:International Test Conference\, the cornerstone of TestWeek™ events\, is the world’s premier conference dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, test\, diagnosis\, failure analysis and back to process and design improvement. At ITC\, test and design professionals can confront the challenges the industry faces\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWe are holding the conference in beautiful San Diego\, CA.  We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! \nITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum\, where the wide range of its offerings allows ITC participants to learn\, network and conduct business. This year’s program includes a top-notch technical program\, vibrant exhibitors\, information-packed tutorials\, interactive technical panels\, three workshops\, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions\, a large number will focus on AI\, automotive\, memory\, and hardware security. In complement to the paper presentations\, there will be special sessions on hardware security certification\, chiplet integration\, silicon lifecycle management\, computing in memory\, as well as design and test of high-power compound devices and quantum electronics. \nWe are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances. \nITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology. \nThis year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening. \nLast\, but not least\, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time\, expertise\, and enthusiasm. Without their hard work and dedication\, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future. \nITC is the premier event for networking\, where professionals from all over the world converge to sharpen skills\, exchange ideas and do business. Join us\, throughout the conference\, for networking activities and to unwind.
URL:https://marketingeda.com/event/itc-2024/
LOCATION:Hilton San Diego Bayfront\, 1 Park Blvd\, San Diego\, CA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241030T090000
DTEND;TZID=America/Los_Angeles:20241030T100000
DTSTAMP:20241016T180601Z
CREATED:20241016T180601Z
LAST-MODIFIED:20241016T180601Z
UID:8419-1730278800-1730282400@marketingeda.com
SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC.
URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20241027T080000
DTEND;TZID=America/New_York:20241031T170000
DTSTAMP:20240925T172254Z
CREATED:20240925T172254Z
LAST-MODIFIED:20240925T172254Z
UID:8353-1730016000-1730394000@marketingeda.com
SUMMARY:ICCAD 2024
DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees.
URL:https://marketingeda.com/event/iccad-2024/
LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241023T090000
DTEND;TZID=America/Los_Angeles:20241023T100000
DTSTAMP:20241009T193236Z
CREATED:20241009T193236Z
LAST-MODIFIED:20241009T193236Z
UID:8402-1729674000-1729677600@marketingeda.com
SUMMARY:Hardware Verification using VirtuaLAB
DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA
URL:https://marketingeda.com/event/hardware-verification-using-virtualab/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241022T080000
DTEND;TZID=America/Los_Angeles:20241023T170000
DTSTAMP:20240725T182818Z
CREATED:20240725T182742Z
LAST-MODIFIED:20240725T182818Z
UID:8184-1729584000-1729702800@marketingeda.com
SUMMARY:Jasper User Group San Jose 2024
DESCRIPTION:The CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 – 23 at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. \nShare Your Story\nWe’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted\, you can: \n\nIncrease industry visibility for you and your team’s field of expertise\nImprove and fine-tune your methods with insights from colleagues across the industry\nEarn wide acclaim with a Best Presentation Award nomination\n\n  \nPlease visit the website for further information. Accepted authors are expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm PDT on Monday\, August 26\, 2024. \nConference registration will open at the end of August. We look forward to meeting you at Jasper User Group San Jose 2024! \nQuestions? Please email us.
URL:https://marketingeda.com/event/jasper-user-group-san-jose/
LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Jasper-October-22-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241017T110000
DTEND;TZID=America/Los_Angeles:20241017T120000
DTSTAMP:20241014T214312Z
CREATED:20241014T214312Z
LAST-MODIFIED:20241014T214312Z
UID:8416-1729162800-1729166400@marketingeda.com
SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs
DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241017T080000
DTEND;TZID=America/Los_Angeles:20241017T170000
DTSTAMP:20240806T194900Z
CREATED:20240806T194900Z
LAST-MODIFIED:20240806T194900Z
UID:8209-1729152000-1729184400@marketingeda.com
SUMMARY:OSMOSIS 2024
DESCRIPTION:Elevate your success with osmosis 2024\nThe annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative\, we invite you to unveil it at osmosis. \nYou will benefit from increased industry visibility as a subject matter expert\, and the conversations that follow may help you and others improve formal-based verification solutions. \n\n\nAbstract guidelines\nCraft a concise narrative outlining the essential bits of your success story\, encompassing: \n\nthe intricate problem you addressed\nrationale for employing formal technology-based solutions\ntangible outcomes\, ideally quantifiable\nkey learnings and findings\n\nFor utmost impact\, please limit your abstract to a single page\, front and back. \nInclude diagrams and code examples if desired. \nIf you have questions or need guidance in refining your narrative\, please reach out to us at osmosis.sisw@siemens.com \n\n\nSchedules and processes\nThe deadline for abstract submissions is 6 p.m. Central EU time on Mon.\, Sept. 23\, 2024. \nSubmissions will be evaluated as they are received. As we select abstracts\, we will begin working with the authors on their presentations. If we fill the agenda early\, we’ll close submissions. \n\n\nWe look forward to receiving your abstracts and seeing you in Munich! \n\n\nOn-demand presentations\nCheck out past\, on-demand presentations. \n\nOsmosis Aerospace and Defense – April 2024\nOsmosis Aerospace and Defense – 2023
URL:https://marketingeda.com/event/osmosis-2024/
LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSMOSIS-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241015T100000
DTEND;TZID=America/Los_Angeles:20241015T110000
DTSTAMP:20241008T164139Z
CREATED:20241008T164139Z
LAST-MODIFIED:20241008T164139Z
UID:8399-1728986400-1728990000@marketingeda.com
SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted
DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service.
URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20241015T080000
DTEND;TZID=Europe/Berlin:20241016T170000
DTSTAMP:20240130T165521Z
CREATED:20240130T165521Z
LAST-MODIFIED:20240130T165521Z
UID:7564-1728979200-1729098000@marketingeda.com
SUMMARY:DVCon Europe 2024
DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools\, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications\, and demonstrations for the practical use of EDA solutions for electronic design.
URL:https://marketingeda.com/event/dvcon-europe-2024/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241010T110000
DTEND;TZID=America/Los_Angeles:20241010T120000
DTSTAMP:20241007T181311Z
CREATED:20241007T181311Z
LAST-MODIFIED:20241007T181311Z
UID:8383-1728558000-1728561600@marketingeda.com
SUMMARY:The Development and Evolution of Verilog & SystemVerilog
DESCRIPTION:Abstract: \nSystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities\, constrained random testing (CRT)\, and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today. \nCliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog\, why the features were added\, and the origins of many of those features.\n\nAgenda:\n\nVerilog HDL and Its Ancestors and Descendants (reference paper)\nBrief History of Verilog & SystemVerilog\nHILO\, Verilog\, C\, PLI\nSDF\, Synthesis\, VHDL\, VPI\nSuperlog\, IHDL (Intel)\, SystemC\, Vera\nOOP\, e-Specman\, SystemVerilog\, C++\nOVL\, PSL\, SVA\nOVM / UVM history\nSimulation & Functional Coverage\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nClifford E. Cummings\, \nVice President of Training at Paradigm Works and Founder of Sunburst Design \nCliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog\, UVM\, CDC and synthesis training classes. Cliff has 42 years of ASIC\, FPGA and system design experience and 32 years of combined Verilog\, SystemVerilog\, UVM verification\, synthesis\, and methodology training experience.  Cliff has taught expert Verilog\, SystemVerilog\, Design Synthesis\, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics.  Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.
URL:https://marketingeda.com/event/the-development-and-evolution-of-verilog-systemverilog/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-10-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20241008T120000
DTEND;TZID=Europe/London:20241008T130000
DTSTAMP:20240911T161307Z
CREATED:20240911T161307Z
LAST-MODIFIED:20240911T161307Z
UID:8325-1728388800-1728392400@marketingeda.com
SUMMARY:Cocotb 2.0: Modernize your testbenches for even more productivity
DESCRIPTION:Cocotb 2.0 is the latest major version of cocotb\, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches\, you can benefit from improved typing and less surprising corner cases. In this talk\, we’ll show what’s new in cocotb 2.0\, and how you can modernize your code bases to make best use of it.  We also have a presentation from a cocotb user performing HDL simulation with python cocotb\, with a Transaction Level Modelling (TLM) approach with a completely free and open source chain (GHDL simulator and WSL Linux). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAgenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 BST\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 BST\nSimple yet powerful: Open-source HDL simulation with Cocotb \nHayder Al-Hakeem ( Wärtsilä Finland)\n\n\n\n\n12.30 BST\nCocotb 2.0: Modernize your testbenches for even more productivity \nPhilipp Wagner ( FOSSi Foundation)\n\n\n\n\n13.00 BST\n  \nClose\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/cocotb-2-0-modernize-your-testbenches-for-even-more-productivity/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-October-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241008T100000
DTEND;TZID=America/Los_Angeles:20241008T150000
DTSTAMP:20240917T161235Z
CREATED:20240917T161235Z
LAST-MODIFIED:20240917T161235Z
UID:8340-1728381600-1728399600@marketingeda.com
SUMMARY:Accelerating DFT verification sign-off with the Questa DFT Verification Platform
DESCRIPTION:Accelerating DFT verification sign-off with the Questa DFT Verification Platform \nThis seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically\, we will cover:\n‌\nNavigating the Growing Complexity of Design-for-Test and Evolving Verification Challenges\nRevolutionizing Test Strategies to deliver reliable products into HPC\, Automotive\, Aerospace\, Medical\, and beyond\n‌ \nAgenda: \n10:00 am – 10:25 am\nRegistration and check-in\nCoffee and networking with your peers.\n‌\n10:25 am – 10:30 am\nWelcome/Intro\nHarsh Patel | Sr. AE Manager\, Functional Verification\n‌\n10:30 am -11:15 am\nUnderstanding and navigating the new challenges in Design-for-Test\nLee Harrison | Director of Product Marketing -Tessent\n‌\n11:15 am – 12:00 noon\nAccelerating verification closure with Siemens DFT tailored verification solutions\nJake Wiltgen | Director\, IC Verification Solutions\n‌\n12:00 noon – 12:30 pm\nLunch and networking\n‌\n12:30 pm – 1:15 pm\nEmbracing a New Era in DFT: Addressing High Defect Coverage\, Silent Data Errors\, and Emerging Challenges\nLee Harrison | Director of Product Marketing -Tessent\n‌\n1:15 pm – 2:00 pm\nIncreasing fault coverage with Siemens Functional Fault Grading solutions\nAnn Keffer | Product Manager\n‌\n2:00 pm – 3:00 pm\nWrap-up and networking \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team
URL:https://marketingeda.com/event/accelerating-dft-verification-sign-off-with-the-questa-dft-verification-platform/
LOCATION:Siemens EDA\, 46871 Bayside Parkway\, Building B\, Fremont\, CA\, United States
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241008T080000
DTEND;TZID=America/Los_Angeles:20241011T170000
DTSTAMP:20240926T000653Z
CREATED:20240906T174011Z
LAST-MODIFIED:20240926T000653Z
UID:8301-1728374400-1728666000@marketingeda.com
SUMMARY:PCB West 2024
DESCRIPTION:For more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics!
URL:https://marketingeda.com/event/pcb-west-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241003T113000
DTEND;TZID=America/Los_Angeles:20241003T170000
DTSTAMP:20240827T163546Z
CREATED:20240827T163546Z
LAST-MODIFIED:20240827T163546Z
UID:8283-1727955000-1727974800@marketingeda.com
SUMMARY:Signoff Special Interest Group
DESCRIPTION:Join us at this year’s Synopsys Signoff SIG (Special Interest Group) event. \nSignoff is a critical quality control checkpoint in the chip development process\, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year’s Synopsys Signoff SIG event\, we’ll explore how signoff can help meet these scalability challenges. We’ll here from several industry-leading companies how they are using the latest technology advances in timing\, power\, extraction\, and eco to realize the full PPA potential of their designs with the fastest path to design closure. \n\n\n\n\n\n\n\n\nAgenda\n\n\nMore details coming soon. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n11:30 – 12:30 PM PDT\n\n\nRegistration Check in & Lunch\n\n\nBadge pick-up begins at 11:30. Lunch will be served\, come early for a chance to eat and network before sessions begin. \nRead Less \n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n12:30 – 01:15 PM PDT\n\n\nKeynote\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n01:15 – 04:05 PM PDT\n\n\nTechnical Sessions\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n04:05 – 05:00 PM PDT\n\n\nNetworking Reception
URL:https://marketingeda.com/event/signoff-special-interest-group/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-3-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241003T090000
DTEND;TZID=America/Los_Angeles:20241003T170000
DTSTAMP:20240911T225246Z
CREATED:20240911T225059Z
LAST-MODIFIED:20240911T225246Z
UID:8328-1727946000-1727974800@marketingeda.com
SUMMARY:VC Formal Special Interest Group
DESCRIPTION:Register for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users\, managers\, and enthusiasts to stay connected with the latest formal verification innovations\, techniques and methodologies. \nIndustry leaders such as Amazon\, Black Sesame\, Microsoft\, NVIDIA\, Samsung\, and Untether AI will share their experiences with the latest formal verification technologies. Topics that will be covered include strategies for achieving formal convergence\, exploring formal methodologies used for RISC-V verification\, and the integration of VC Formal with generative AI functionalities – which offer the potential to automate the creation of formal verification testbenches. \nKeynote Session \n\nThe Impact of LLMs on Formal Verification \nExplore how LLMs can transform formal verification\, reducing manual effort and improving results. We’ll discuss current benchmarks and future goals for deploying LLMs to enhance formal verification processes. \nPresented by Syed Suhaib\, NVIDIA
URL:https://marketingeda.com/event/vc-formal-special-interest-group/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VC-Formal-SIG-October-3-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241003T080000
DTEND;TZID=America/Los_Angeles:20241004T170000
DTSTAMP:20241004T174051Z
CREATED:20241002T224220Z
LAST-MODIFIED:20241004T174051Z
UID:8372-1727942400-1728061200@marketingeda.com
SUMMARY:Electronic Design Process Symposium (EDPS) - 2024
DESCRIPTION:EDPS 2024 is now taking shape. The place to be is once again SEMI\, in Milpitas\, and the dates are Thursday and Friday\, Oct 3rd and 4th\, 2024. \nRegistration is now open: https://2024-ieee-edps.eventbrite.com. Who needs to register? Please see the Registration page. \nTalks from EDPS 2023 and the last 24 years of EDPS\, are are available and searchable\, on the Prior Years page. \nDay 1\, Thursday 9:00am; Session 1\n9:05am\n\nEnergy and Thermal Management of Chips\, Systems and Datacenters Necessitates a Return to Fundamentals\nChandrakant Patel\nHP\n\n  \nThe latter part of 20th century witnessed the rise of the compute utility made up of large-scale data centers housing densely packed compute\, storage and networking equipment. The cyber age data centers became modern day factories requiring megawatts of power for the information technology (IT) equipment much like the process equipment in a factory of the machine age. Electrical energy supplied to the chips and systems in the data centers turned into multi-megawatts of heat energy which in turn required heat removal means. The active heat removal means also required power. While many innovative measures have been used for heat removal and energy management in data centers\, there is a substantial gap in application of fundamentals of engineering when compared to the approaches taken by the contributors of the 19th and early 20th century machine age. As an example\, machine age contributors performed exergy (2nd law of thermodynamics) analysis and deemed it necessary to build a hydro-electric plant as part of the design of an Aluminum factory. Indeed\, majority of data centers today rely on the power infrastructure built by our predecessors. Given the inexorable trajectory of data centers strongly driven by AI\, and associated demands on available energy\, it is time we returned to such fundamentals particularly given the environmental challenges. \nIn my talk\, I will present a holistic approach that traces the energy flow from a power plant to a chip\, and from the chip core to the cooling tower. \n10:00am\n\nEnabling Effortless Machine Learning for Embedded Edge Applications\nGopal Hegde\nSiMa.ai\n\n  \nMachine Learning is a game changing technology of our generation and similar Internet in the 1990s\, will impact every aspect of our life. While Machine Learning use cases and applications are well established in the cloud & IoT devices\, in the embedded edge market\, its usage is in its infancy. We at SiMa.ai are focused on disrupting this market by turbo charging embedded compute with the addition of machine learning. Embedded edge has space and power constraints and has a huge expertise gap relative to cloud computing when it comes to machine learning. The presentation covers market requirements\, key challenges and our unique software first approach to machine learning at embedded edge. We will discuss key market segments\, their unique requirements and how our silicon and software solutions provide a way for our customers to easily develop and deploy machine learning solutions that address their use cases and applications. \n10:35am\n\nAI: Trailblazing the Next Generation of Semiconductor Innovation\nVishal Khandewal\nSynopsys\n\n  \nWith AI-based applications coming pervasively mainstream through ChatGPT\, digital healthcare\, and almost everything else we do with our devices daily\, digital chip design is seeing an exponential push towards complexity\, performance\, power\, and time-to market. EDA tool flows are becoming mission critical to meet the demands of a hardware-led 4th industrial revolution that is driving everything towards being intelligent\, connected\, monitored and data-driven. In this talk we go into the details of how hardware design and EDA tools are evolving to deliver the next generation of performance\, power\, and productivity (PP&P) boost. Even with exponential growth in design productivity in the past decade\, overall design cycle is not meeting its intended targets. The technical complexity of advanced node design with new dominant effects like thermal and IR\, are leading to highly complex tool/methodology flows. This is where at Synopsys\, we have taken a full tool-stack approach to build pervasive AI into our tools to deliver unprecedented PP&P boost. We will share examples of applications ranging from design implementation\, verification\, test\, and analog/manufacturing to showcase the potential of this technology and how it is reshaping chip design workflows. Many of these technologies are taking us closer to the no-human-in-the-loop goal for chip design. With serious talent shortage and increase in solution complexity beyond human expertise\, AI-augmented solutions for chip design are the way forward. \n11:10am\n\nHarnessing LLMs for Advanced EDA Platforms: Code Generation and Beyond\nAkhilesh Kumar\nAnsys\n\n  \nLarge Language Models (LLMs) such as GPT-4\, Gemini\, Llama etc.\, have demonstrated astounding capabilities in a range of tasks such as knowledge extraction\, Q&A\, summarization\, code generation\, contextual problem solving etc. The LLMs can also be adapted to specific applications through a variety of methods such as fine tuning\, in-context learning\, RAG\, agent-based systems etc.\, making them quite versatile. \nModern EDA platforms\, such as Ansys SeaScape\, have sophisticated workflows\, hundreds of user APIs\, complex input data requirements\, and require deep domain knowledge and expertise for efficiently using the platform. This talk will discuss how LLMs can greatly improve the productivity and user experiences for such EDA platforms. The talk presents an overview of code generation techniques using LLMs and will discuss our experience in developing an LLM-based code generation solution for the Ansys SeaScape platform. Going beyond the code generation\, this presentation will discuss creating an LLM agent-based copilot for providing intuitive assistance to the users of the Ansys SeaScape platform for a variety of operational modalities. \n12:45pm\n\nThe Application of AI to Chip Design\nMark Ren\nNVidia\n\n  \nThe applications of AI in chip design undergo an evolutionary path. \nInspired by the success of AlphaGO\, Reinforcement Learning techniques were deployed to a number of design problems\, achieving results showing the potential of AI. \nThe advancement of Large Language Models further enabled the application of AI in a much broader set of design activities. \nLLM-based copilots can improve design productivity by providing knowledge and coding assistance; agents can provide further assistance in key design tasks such as analysis\, debugging\, and optimization. \nThe evolution of AI will continue\, and we will discuss critical challenges to realizing its revolutionary potential in the chip design process \n1:35pm\n\nHow AI is changing every aspect of EDA\, starting from transistor-level simulation\nSathishkumar Balasubramanian\nSiemens\n\n  \nThere is a lot of hype in the industry around AI\, but behind the hype there is the reality. That reality is that AI really is impacting virtually every aspect of semiconductor design. However\, its not as simple as taking general purpose AI solutions and hoping they work for EDA\, the risks are too high and when dealing with parts per billion (or trillion) in acceptable errors\, hallucinations are not acceptable. What is needed are Verifiable AI solutions that deliver results that users can trust and that reduce the overall resources needed to complete a task. At Siemens EDA we have been able to leverage Verifiable AI to accelerate virtually every aspect of the design and verification process. \nIn this presentation we will explore the requirements for\, and state of the art of\, AI in EDA application. We will explore AI’s impact on every aspect of design starting from transistor-level simulation. \n2:10pm\n\nTest\, Repair and Reliability Challenges of Chip-let Interconnects\nSreejit Chakravarty\nAmpere Computing\n\n  \nChip-let based design\, fueled by various advanced packaging technologies\, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement\, during high volume manufacturing\, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. RAS solutions required to address such reliability issues are highlighted. \n2:45pm\n\nArtificial Intelligence and Machine Learning for RF and Microwave Design\nJianjun Xu\nKeysight\n\n  \nThis talk reviews some powerful and practical Artificial Intelligence and Machine Learning (AI/ML) technologies for applications in traditional RF and Microwave design and beyond. After a very brief overview of the AI/ML landscape\, we focus on Artificial Neural Networks (ANNs) and provide several key examples of modern ANN applications to electronic\, electro-thermal\, and electro-chemical device modeling\, and behavioral modeling to illustrate the substantial benefits and generality of present techniques. \nThe talk concludes with a discussion of the potential of AI/ML technologies to address and solve future challenging and important RF and Microwave design problems\, e.g.\, for 6G. \n3:30pm\n\nPromises and Challenges of Digital Twin for Semiconductor Manufacturing\nAla Moradian\nApplied Materials\n\n  \nThe advancement of cutting-edge technologies like Artificial Intelligence (AI)\, Large Language Models (LLM)\, and Electric Vehicles (EV) demands sophisticated semiconductor devices with precise specifications. \nConcurrently\, the emergence of digital twins and AI stands as pivotal in facilitating the development and enablement of such technologies. \nThis talk delves into the vision and significance of AppliedTwin(tm)\, a proposed digital twin framework tailored for semiconductor manufacturing. \nAppliedTwin delineates various levels of abstractions ranging from digital fabrication facility down to digital twin of individual devices\, each characterized by distinct attributes governing their interaction with physical assets\, fidelity\, etc. \nApplied Materials has spearheaded the application of digital twins in semiconductor manufacturing with the introduction of EcoTwin(tm)\, a platform designed to promote sustainability. \nIn this talk the critical role of digital twins in propelling innovation and efficiency in semiconductor equipment manufacturing. \n4:05pm\n\nMaking Data Center Digital Twins a Reality\nPaul Harrison\nCadence\n\n  \nThis talk will discuss the application of Digital Twins to Data Centers. \nHistorically decisions for data center operations were made based on rules of thumb or the person who would most confidently put across their point of view. \nCabinet power densities continue to rise\, accelerated by AI\, increasing the need complex technologies like liquid cooling to be more widely implemented. This means data center operations have become more difficult to manage\, while the impact of their downtime can be catastrophic for companies. Fortunately\, data center operators are starting to adopt CFD-based Digital Twins to help inform their operational decisions\, improve their understanding\, and reduce the risks. This talk will explain how to create a Data Center Digital Twin\, some of the challenges with creating them\, how they integrate with data sources and existing processes\, and the benefits to operators this technology brings. \n4:40pm\n\nInnovating Semiconductor Manufacturing with ML-augmented Digital Twins\nNorman Chang\nElectronics\, Semiconductor\, and Optics BU\, Ansys\n\n  \nDeveloping each processing step in semiconductor manufacturing has heavily relied on in-situ sensors in the equipment and numerous try-outs in recipe generation. However\, with advancements in multiphysics simulation technologies\, an innovative ML-augmented hybrid simulation methodology has been developed. This methodology combines the strengths of multiphysics simulation and in-situ measurement in building semiconductor processing digital twins. In this talk\, we will review the current state-of-the-art digital twin technologies and identify the gaps that need to be addressed to fully utilize digital twins in developing new process recipes in semiconductor manufacturing. \n6:45pm\n\nSemiconductors and Artificial Intelligence:The Virtuous Cycle\nPushkar Apte\nSEMI\n\n  \nArtificial Intelligence (AI) has taken the world by storm\, and has become a strategic imperative for most industries. While the concept of AI is over half a century old\, it has accelerated rapidly just over the past decade\, in large part due to amazing advances in semiconductor chips. In turn\, AI is driving growth in semiconductor revenues and improvements in operational efficiency\, creating a virtuous cycle. \nHowever\, there are formidable roadblocks ahead. AI models and datasets are growing at an exponential rate\, far outpacing hardware advances – creating both performance and sustainability challenges. System-level innovation is required for continued progress in AI\, which requires meaningful collaboration and data-sharing – often difficult in an industry where IP is critical. \nThis presentation will focus on this virtuous cycle between semiconductors and AI\, highlighting the benefits\, challenges and solution paths for continued progress. \nDay 2\, Friday 9:00am; Session 1\n9:05am\n\nIs AI intelligent?\nRonjon Nag\nStanford Medicine\n\n  \nArtificial intelligence is in the news daily\, and people ask whether they are truly intelligent. \nMaybe it still lacks the depth of human intelligence today\, but where is already cleverer\, and what stops it from reaching the ultimate pinnacle of ”general intelligence” – could that ever be possible? We will consider the implications of creating truly intelligent machines and the potential consequences for human society. \n10:00am\n\nTrust Based Modeling for Improved Security\nNaresh Sehgal\nDeeply Human AI\n\n  \nThe present state of Edge Computing is an environment of different computing capabilities connected via various communication paths. Actors on the Edge may interact with each other and a central datacenter. An important part of information security is the evaluation of trust between actors\, whether those actors are people or machines. Although many distributed trust models exist\, our proposed model introduces three key concepts. The first concept is that trust is not bidirectional between two parties. The second concept is that trust is different between different actors\, based upon the nature of their relationships. The third concept is that trust depends on the content of a transaction. We will present some real-life examples to illustrate these concepts. \n10:35am\n\nAdvancing Hardware Security in the Post-Quantum Cryptography Landscape: Challenges and Solutions\nQian Wang\nU. Cal. Merced\n\n  \nHardware security in the era of post-quantum cryptography has become increasingly crucial due to the potential threat quantum computers pose to traditional cryptographic algorithms. Post-quantum cryptography aims to develop cryptographic algorithms that are resistant to attacks from quantum computers. However\, ensuring the security of these algorithms requires not only advancements in software but also robust hardware security measures. In this talk\, we will first discuss the implementation of quantum-resistant cryptographic modules on hardware platforms\, necessitating upgrades in both hardware and firmware to accommodate new algorithms efficiently. Moreover\, hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks\, where an attacker exploits information leaked through physical characteristics such as power consumption or electromagnetic radiation. Post-quantum cryptographic hardware must incorporate countermeasures to mitigate these risks. \n11:20am\n\nScaling to Meet the Needs of AI\nPradeep Dubey\nIntel\n\n  \nArtificial intelligence (AI) is impacting not just what computing can do for us\, rather how computing gets done. Fast-evolving AI algorithms are driving demand for growing performance at an unprecedented rate and scale. This talk is about some of our research aimed at exploring technological and system-level opportunities for cost-effective scaling of emerging AI datacenters. \n1:00pm\n\nThe Future of Generative AI: Key Technology Trends and Innovations\nShiva Kintali\nR3AI\n\n  \nLLMs have emerged as powerful tools\, revolutionizing various domains from natural language processing to content generation\, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention. \nWhile they offer convenience and productivity\, we dissect how they can also be manipulated and weaponized by malicious actors\, raising concerns about inherent biases\, jailbreaking potential\, security concerns\, privacy issues\, misinformation\, deepfakes\, cyber threats and their unsettling societal consequences. We explore how biases present in training data\, historical injustices\, and societal prejudices can be perpetuated and even amplified by these models\, posing a significant threat to fairness\, equity\, and inclusivity. \nThis talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges\, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences. \n1:35pm\n\nEmerging Technologies for Computing Paradigm Shift\nBrandon Wang\nSynopsys\n\n  \nThe explosive growth of AI has triggered a rapid increase in semiconductor demand\, leading to soaring power consumption and unsustainable water usage. This presentation will explore emerging technologies essential for driving a paradigm shift towards energy-efficient computing. Topics will include the “Shift Left” design methodology\, the impact of SLMs (Small Language Models) on computational efficiency in AI\, and the potential of neuromorphic and quantum computing as next-generation architectures. These advancements are poised to enable significant digital transformation and drive pervasive intelligence across various industries. The speaker will also provide insights into how organizations can stay at the cutting edge of these innovations\, offering a forward-looking perspective on the future of computational systems and the strategic steps needed to lead in this rapidly evolving landscape. \n2:10pm\n\nTBD\nChris Cheng\nHewlett-Packard Enterprise\n 
URL:https://marketingeda.com/event/electronic-design-process-symposium-edps-2024/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/edps-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241001T110000
DTEND;TZID=America/Los_Angeles:20241001T113000
DTSTAMP:20240930T220024Z
CREATED:20240930T220024Z
LAST-MODIFIED:20240930T220024Z
UID:8361-1727780400-1727782200@marketingeda.com
SUMMARY:Interactive SPICE Model Verification Platform ME-Pro
DESCRIPTION:ME-Pro™ is a unified tool for designers\, process developers\, modeling engineers\, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation. \nThis comprehensive platform supports evaluation across device\, circuit\, and process domains enabling interactive development and offering critical feedback for process improvements. With decades of Primarius’ expertise\, ME-Pro™ features pre-configured templates\, hundreds of verification data entries\, and the built-in NanoSpice parallel simulator that is all designed to streamline setup and reduce learning curves. \nPresenter\nErik Supnet is a Senior Application Engineer at Primarius for two years supporting pre-sales and post-sales activities for modeling and simulation products. He earned his B.S. in Computer Engineering and M.A in Education at the University of the Pacific. Prior to his current role\, he held design engineering positions as D.E.C\, SiByte\, Broadcom\, and Intel\, and has a background in custom circuit design\, automation\, methodologies\, and education.
URL:https://marketingeda.com/event/interactive-spice-model-verification-platform-me-pro/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/primarius-October-1-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240926T100000
DTEND;TZID=America/Los_Angeles:20240926T110000
DTSTAMP:20240911T233717Z
CREATED:20240911T233717Z
LAST-MODIFIED:20240911T233717Z
UID:8333-1727344800-1727348400@marketingeda.com
SUMMARY:Learn How to Simulate 2D-TMD-Channel FETs with Atomistic Precision
DESCRIPTION:Are 2D-TMD-channel transistors suitable candidates for the replacement of silicon ? Considering the extreme scaling down to a few atomic layers of the FET channel\, only an atomistic solution looks viable. In this context\, we show how the Victory Atomistic tool can answer this essential question thanks to quantum mechanics\, offering valuable support for the prototyping effort of a 2D transistor in a professional TCAD environment. \nWhat You Will Learn\n\nAn understanding of the physics and engineering of 2D TMD NR architectures at the atomic scale\nWhy to use Atomistic TCAD\nHow to simulate and prototype at the atomic level\nExample of a 2D-TMD TFET\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Philippe Blaise\, Senior Application Engineer\, Silvaco\, Inc. \nDr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco\, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops\, plus 5 patents and one book chapter.\nDr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes\, France. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, device engineers\, process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/learn-how-to-simulate-2d-tmd-channel-fets-with-atomistic-precision/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-September-26-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240925T093000
DTEND;TZID=America/Los_Angeles:20240925T180000
DTSTAMP:20240917T003907Z
CREATED:20240917T003541Z
LAST-MODIFIED:20240917T003907Z
UID:8337-1727256600-1727287200@marketingeda.com
SUMMARY:TSMC North America OIP Ecosystem Forum 2024
DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for A16\, N2 and N3 processes\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC OIP Ecosystem Forum!
URL:https://marketingeda.com/event/tsmc-north-america-oip-ecosystem-forum-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240925T080000
DTEND;TZID=America/Los_Angeles:20240927T170000
DTSTAMP:20240612T170503Z
CREATED:20240612T170425Z
LAST-MODIFIED:20240612T170503Z
UID:8093-1727251200-1727456400@marketingeda.com
SUMMARY:SISPAD 2024
DESCRIPTION:The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of leading-edge research and development in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. \nSISPAD2024 will be held in person in San José\, USA from September 25-27\, 2024. A technical workshop will be offered on September 24\, 2024. Details on the invited speakers\, technical program and workshop will be posted here as soon as they are available. There are slots still available for tutorials or workshop sessions for September 24\, please reach out to us if you are interested in organizing one. \nLooking forward to seeing you all in San José!
URL:https://marketingeda.com/event/sispad-2024/
LOCATION:The Westin San Jose\, 302 S Market Street\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SISPAD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240924T094500
DTEND;TZID=Europe/London:20240924T143000
DTSTAMP:20240906T170817Z
CREATED:20240906T170817Z
LAST-MODIFIED:20240906T170817Z
UID:8297-1727171100-1727188200@marketingeda.com
SUMMARY:FPGA Front Runner: FPGA Verification Strategies
DESCRIPTION:Time\nSpeaker\nDetails\n\n\n09.30\nArrival and Registration\n\n\n10.00\nDave Sanders\, Rolls-Royce\nOverview of Rolls Royce @ Solihull \nPresentation Title – Rolls-Royce… the past\, the present and the future \nAbstract – Rolls-Royce has come a long way since its inception as a car manufacturer at the start of the twentieth century\, for starters it doesn’t make cars anymore! This talk will provide an insight into Rolls-Royce’s past present and future with a focus on the pivotal role that electronics now plays in a company traditionally known for its mechanical engineering solutions.\n\n\n10.30\nEspen Tallaksen\, EmLogic\nPresentation Title – Modern VHDL testbenches – An AXI-stream example\, first dead simple\, then advanced \nAbstract – Do you want to see how easily you can verify your FPGA or ASIC? Join in to see this exemplified with a testbench for an AXI-stream based data flow design – using UVVM\, which is currently used by more than one third of all European FPGA designers. \nMost testbenches verifying a complex DUT are relatively unstructured and difficult to understand\, modify\, extend\, maintain and reuse. You can often easily reduce the verification time by at least a factor of two by having a well structured and easy to understand test harness\, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high-level commands. \nThis presentation will first show how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components\, models\, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way.\n\n\n11.00\nJim Lewis\, SynthWorks Design Inc\nPresentation Title – Why Should Our Team be Using VHDL + OSVVM for Verification? \nAbstract – Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems. \nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports. \nThis presentation examines how these capabilities will benefit your projects. \nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities. \nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers. \nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\n11.30\nRefreshment break\n\n\n12.00\nPhilipp Wagner\, FOSSi Foundation\nPresentation Title – cocotb is making verification fun! \nAbstract – cocotb lets you verify chips like software: productive\, simulator-agnostic\, in Python. In this talk\, you’ll learn what cocotb is and how using Python for verification can make your next verification job more productive. There’s even something in there for those of you who already know cocotb: a look at cocotb 2.0 and tips and tricks how to update your testbenches to make best use of the new features.\n\n\n12.30\nChristian Tchilikov\, semify GmbH\nPresentation Title – Utilizing the Cocotb Python Framework for Efficient Functional Verification \nAbstract – Cocotb is a framework that allows for verification test cases written in Python to interact with DUTs being simulated in common simulation tools. Compared to classical approaches for verification\, Cocotb has very low upfront engineering costs. With access to the full functionality of the Python programming language\, the complexity of testbenches can scale up as required. \nCocotb comes with built-in functionalities for many of the tasks required of a modern testbench\, like constrained random input generation\, coverage tracking\, and assertions. \nCocotb’s foundation being the Python language means that software models of the design can be written in a high-level Object-Oriented language. Additionally\, higher-level objects such as drivers or monitors can be designed for the bit-wiggling of DUT input signals\, providing a higher level of abstraction\, similar to UVM sequences. The software model can then be easily scoreboarded with the DUT through Cocotb. \nAdditionally\, Cocotb provides high-level abstractions for interfacing with the simulated design. This comes in the form of hierarchical signal reading and assignment\, event triggers\, and parallel execution of coroutines similar to SystemVerilog’s forks. Leveraging these tools\, it becomes simple to launch verification modules like drivers and monitors\, running and interfacing with the DUT in parallel. \nThird-party verification IP modules for many standard interfaces are available via the cocotb extensions packages hosted on PyPi\, so devices using SPI or AXI\, amongst others\, can be verified with minimal effort. In addition\, engineers can write and reuse their own verification IP\, such as bus monitors\, drivers\, etc\, similar to the UVM approach of verification. \nA special emphasis is on using cocotb alongside an open-source toolchain like Icarus Verilog\, acheiving a similar quality of results compared to commercial offerings. This combination of tools provides features that are otherwise hidden behind expensive licence paywalls\, and makes digital verification accessible to a wider audience. \nCocotb serves as a great alternative to traditional SystemVerilog Object-Oriented verification by working around the limitations of the simulators that do not support the full feature set of SystemVerilog by providing similar functionality in the Python language instead.\n\n\n13.00\nDave Amor\, Ultra Maritime\nPresentation Title – Integration of Atlassian Bamboo with MathWorks Tools for FPGA Development \nAbstract – In safety critical FPGA development\, the need for efficiency\, reliability\, and predictability while maintaining agility is vital. \nUltra Maritime has embraced these demands by integrating Continuous Integration (CI) practices with MathWorks tools and Agile methodologies\, creating a streamlined and robust development process that ensures high-quality outcomes in mission-critical applications. \nThis presentation will explore the strategies and technologies we use to achieve consistent\, and resilient FPGA development\, focusing on how these practices contribute to the success of our projects. \nAtlassian Bamboo allows us to automate testing\, code generation\, and the bitstream creation processes. \nThis integration ensures that every change in our FPGA designs can be automatically validated through rigorous testing\, significantly reducing the risk of errors and accelerating the development lifecycle. \nBy automating these processes\, a higher standard of code quality is possible while freeing up our engineers to focus on innovation and problem-solving. \nThis presentation will touch on the adoption of Agile Scrum practices within our FPGA development teams. \nAgile Scrum provides a flexible framework that allows us to adapt to changing requirements\, prioritise tasks effectively\, and deliver incremental improvements throughout the project lifecycle. Key ceremonies such as sprint planning\, daily stand-ups\, and retrospectives are essential to maintaining focus and ensuring continuous improvement. We will discuss how these practices have enhanced our ability to respond to challenges\, manage complexity\, and maintain alignment across our teams. \nA crucial aspect of our development process is the integration of Jira with Bamboo and Simulink. This connection enables seamless tracking of tasks\, test results\, and code changes. Automated reporting of test failures and direct linking to Jira tasks ensure that issues are identified\, prioritised and resolved. \nThe presentation will also address the advantages of CI in ensuring resilience against the turnover of key personnel. By standardising workflows and maintaining consistent environments\, we reduce the dependency on individual knowledge and ensure that our processes are sustainable. \nLooking to the future\, we will explore potential enhancements to our current setup\, by leveraging developments in Large Language Models. \nUltra Maritime’s approach to FPGA processes evolving over the last 25 years has created a environment that is effective\, adaptable and resilient\, ensuring the delivery of high-quality\, reliable products.\n\n\n13.30\nLunch\n\n\n14.00\nTour\n\n\n14.30\nFinish refreshments/networking
URL:https://marketingeda.com/event/fpga-front-runner-fpga-verification-strategies/
LOCATION:Rolls Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-September-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240918T100000
DTEND;TZID=America/New_York:20240918T110000
DTSTAMP:20240820T165235Z
CREATED:20240820T165149Z
LAST-MODIFIED:20240820T165235Z
UID:8255-1726653600-1726657200@marketingeda.com
SUMMARY:A Beginner's Guide to RTL-to-GDSII Front-End Flow
DESCRIPTION:In this Training Webinar\, explore the concepts of RTL design\, design verification\, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits\, the building blocks of modern electronics. \nThis webinar provides practical knowledge\, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow. \nWe’ll break down the process into manageable stages\, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore: \n\nKey concepts of specifying chip behavior and performance\nHow to translate ideas into a digital blueprint and transform that into a design\nHow to ensure your design is free of errors\n\nWebinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow\nDate: Wednesday\, September 18\, 2024\nTime: 07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing
URL:https://marketingeda.com/event/beginners-guide-rtl-gdsii-front-end-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240918T080000
DTEND;TZID=Asia/Kolkata:20240919T170000
DTSTAMP:20240807T162934Z
CREATED:20240807T162703Z
LAST-MODIFIED:20240807T162934Z
UID:8215-1726646400-1726765200@marketingeda.com
SUMMARY:DVCon India 2024
DESCRIPTION:On behalf of the DVCon India 2024 steering committee\, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore\, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. \nWe want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an Awards Night\, which saw an amazing response last year. \nOn behalf of the DVCon India 2024 steering committee\, it gives me immense pleasure to extend a warm welcome to each and every one of you to the 9th edition of the Design and Verification Conference in India. Set to unfold from the 18th to 19th of September 2024 in the vibrant city of Bangalore\, India\, this conference promises to be a pinnacle of innovation\, collaboration and insight. \nAs we embark on this journey\, we are fuelled by the electrifying momentum\, the techno-genius excitement and the enthusiasm that characterized last year’s edition of DVCon India. Our goal for DVCon India 2024 is clear: to build upon the successes of the past and propel the conference to even greater heights. \nThis year\, our focus is laser-sharp: we aim to demystify the essence of DVCon. While some may perceive it solely as a Digital Verification Conference\, DVCon embodies much more—it encapsulates the entire spectrum of Design and Verification\, spanning from Architecture and Design to Post Silicon Validation. \nTo ensure that this message resonates loud and clear across our community\, we have formed dedicated focus groups in pivotal areas: \n\nSystem and IP level modelling\, Virtual Prototyping & ESL\nArchitecture and Design\nRISC-V and its ecosystem\nAnalog and Mixed-Signal Design and Verification and\nPost Silicon Validation.\n\nThrough these specialized groups\, we seek to foster deeper understanding\, facilitate meaningful dialogue and foster inclusive participation. \nFurthermore\, in our relentless pursuit of excellence\, we are expanding our Technical Program Committee and implementing structural enhancements to optimize the participant experience. These changes underscore our commitment to delivering value-driven content and enriching interactions. \nWe extend an open invitation to the entire technical fraternity to actively engage\, collaborate and share insights at DVCon India 2024. Your collective expertise\, passion\, and dedication are instrumental in shaping the success of this conference\, and we eagerly anticipate your invaluable contributions. \nTogether\, let us ignite the spirit of Designnovation\, celebrate the power of collaboration and chart a path towards a future defined by excellence. \nWelcome to DVCon India 2024—a platform where ideas converge\, innovations thrive\, and possibilities abound. \nHere’s to a resounding success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2024
URL:https://marketingeda.com/event/dvcon-india-2024/
LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240918T080000
DTEND;TZID=America/Los_Angeles:20240918T090000
DTSTAMP:20240813T192856Z
CREATED:20240813T192856Z
LAST-MODIFIED:20240813T192856Z
UID:8231-1726646400-1726650000@marketingeda.com
SUMMARY:Managing Constraints Like a Pro in OrCAD X
DESCRIPTION:Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. \nWe’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints\, which are critical for HDI designs. \nThe webinar will feature a brief presentation\, a live demonstration using the NVIDIA Jetson Xavier Developer Kit Carrier Board\, and a Q&A session. \nTopics Covered:\n\nNavigating the constraint manager and reusing constraints\nCreating constraint sets\nSetting up physical and spacing constraints\nSetting up advanced constraints for HDI\nElectrical constraints (Propagation Delay\, Net Scheduling\, Differential Pairs)\nSetting up blind\, buried\, and microvias\nAnalysis setup\nPreview of the new constraints panel in OrCAD X Presto PCB Editor\n\n\nWe welcome PCB designers of all experience levels to join us. Enhance your expertise in managing basic and advanced constraints in your OrCAD X Presto designs! \n\nSPEAKERS: \nAdam Fuchs\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/managing-constraints-like-a-pro-in-orcad-x/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240914T080000
DTEND;TZID=America/Los_Angeles:20240919T170000
DTSTAMP:20240909T164418Z
CREATED:20240909T164418Z
LAST-MODIFIED:20240909T164418Z
UID:8313-1726300800-1726765200@marketingeda.com
SUMMARY:46th Annual EOS/ESD Symposium & Exhibits
DESCRIPTION:The EOS/ESD Symposium is dedicated to the understanding of issues related to electrostatic discharge and electrical transients/overstress\, and the application of this knowledge to the solution of problems in consumer\, industrial\, and automotive applications\, including electronic components\, as well as in systems\, subsystems\, and equipment.
URL:https://marketingeda.com/event/46th-annual-eos-esd-symposium-exhibits/
LOCATION:Peppermill Resort and Casino\, 2707 South Virginia Street\, Reno\, NV\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EOSESD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Stockholm:20240913T080000
DTEND;TZID=Europe/Stockholm:20240915T170000
DTSTAMP:20240717T214406Z
CREATED:20240717T214315Z
LAST-MODIFIED:20240717T214406Z
UID:8159-1726214400-1726419600@marketingeda.com
SUMMARY:ORConf 2024
DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org.
URL:https://marketingeda.com/event/orconf-2024/
LOCATION:Gothenburg\, Gothenburg\, Sweden
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T120000
DTEND;TZID=America/Los_Angeles:20240912T130000
DTSTAMP:20240823T181126Z
CREATED:20240823T181114Z
LAST-MODIFIED:20240823T181126Z
UID:8265-1726142400-1726146000@marketingeda.com
SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language
DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions
URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T100000
DTEND;TZID=America/Los_Angeles:20240912T110000
DTSTAMP:20240814T174526Z
CREATED:20240814T174526Z
LAST-MODIFIED:20240814T174526Z
UID:8237-1726135200-1726138800@marketingeda.com
SUMMARY:Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs
DESCRIPTION:Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar\, we will demonstrate using the Verisium Debug App to debug such DMS designs. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium and Spectre simulations\nHow Verisium Debug can be used to debug User-Defined Nets (UDNs)\nThe analog waveform debug features of Verisium Debug\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for design and verification engineers of all levels who need to debug Digital-Mixed-Signal designs when simulating using Xcelium Real Number Modeling (RNM) or mixed Xcelium/Spectre Digital-Mixed-Signal simulations. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nDoug Koslow\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence
URL:https://marketingeda.com/event/leveraging-verisium-debug-to-debug-digital-mixed-signal-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T100000
DTEND;TZID=America/Los_Angeles:20240912T110000
DTSTAMP:20240813T193558Z
CREATED:20240813T193538Z
LAST-MODIFIED:20240813T193558Z
UID:8234-1726135200-1726138800@marketingeda.com
SUMMARY:Addressing 3D-IC Power Integrity Design Challenges
DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff
URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240912T080000
DTEND;TZID=Asia/Shanghai:20240912T170000
DTSTAMP:20240605T173645Z
CREATED:20240605T173645Z
LAST-MODIFIED:20240605T173645Z
UID:8079-1726128000-1726160400@marketingeda.com
SUMMARY:D&R IP-SoC China 2024 Day
DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku.
URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/
LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg
END:VEVENT
END:VCALENDAR