BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST 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DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Denver BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20220313T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20221106T080000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20230312T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20231105T080000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20240310T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20241103T080000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Europe/London:20250221T090000 DTEND;TZID=Europe/London:20250221T140000 DTSTAMP:20250107T225935Z CREATED:20250107T225935Z LAST-MODIFIED:20250107T225935Z UID:8878-1740128400-1740146400@marketingeda.com SUMMARY:Using AI in development and product for FPGA DESCRIPTION:FPGA Front Runner – Using AI in development and product for FPGA \nHow are they used? What input language is used and how does it find it’s way into the FPGA? \nHow is the AI trained? \nAny use case example \nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.00\nArrival and registration\n\n\n09:30\nPete Leonard\, Renishaw\nIntroduction to Renishaw\n\n\n09:40\nGareth R\, TechWorks \nAI Manager\nTechWorks – https://www.techworks.org.uk/\n\n\n10:00\nAlexander Montgomerie \nCorcoran\, Heronic \nCEO\nHeronic – https://heronic.ai/\n\n\n10:30\nDavid Harold\, RED Semi \nChief Operating Officer\nREDSemi – https://redsemiconductor.com/\n\n\n11:00\nPedro Machado\, Nottingham Trent University\, Senior Lecturer in Computer Science\nNottingham Trent \nUniversity – https://www.ntu.ac.uk/\n\n\n11:30\nRefreshment break\n\n\n12:00\nJeremy Bennett\, Embecosm\, \nChief Executive\nEmbecosm – https://www.embecosm.com/\n\n\n12:30\nGiles Peckham\, Myrtle.ai\, \nHead Of Marketing\nMyrtle.ai – https://myrtle.ai/\n\n\n13:00\nSpeaker 8\n\n\n\n13:30\nLunch\n\n\n14:00\nEnd\n\n\n\nPartner \nFPGA Front Runner event Partner: TechWorks & Tessolve \nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance. \n\n\nLocation\nRenishaw plc\, New Mills\, Wotton-under-Edge \, Gloucestershire\, GL12 8JR \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/using-ai-in-development-and-product-for-fpga/ LOCATION:Renishaw plc\, New Mills\, Wotton-under-Edge\, Gloucestershire\, GL12 8JR\, United Kingdom CATEGORIES:Forum,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-Febuary-21-2025.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250220T080000 DTEND;TZID=America/Los_Angeles:20250220T190000 DTSTAMP:20241212T171517Z CREATED:20241212T171448Z LAST-MODIFIED:20241212T171517Z UID:8572-1740038400-1740078000@marketingeda.com SUMMARY:GSA Mena Executive Summit DESCRIPTION:On February 20\, 2025 in Cairo\, Egypt\, we are hosting the GSA MENA Executive Summit to look beyond the current divisions and rather recognize the Middle East North Africa regional potential as a source of capital and destination for innovative tech developments. \nThis semiconductor and tech-focused exec forum will take place in a stunning brand-new venue: the Grand Egyptian Museum (GEM)\, an outstanding new destination for history and archeology lovers on par with the world’s very best museums\, near the Giza pyramid complex. \nBeside ample opportunities for networking\, including with government officials from the entire region\, we will cover topics including: \n\nthe state of the global semiconductor industry\nthe regional potential as a source of capital and destination for innovative tech development centers\nthe state of Entrepreneurship in the region\, with a moderated panel discussion of Venture Capital firms.\nProgress in Automotive\, as a crucial industry for the whole EMEA region\nkey technological updates\, on AI (GenAI\, Edge AI\, Cloud AI)\, New Chip Design Paradigms (Chiplets\, 3D packaging\, EDA advancements)\, Cybersecurity\, Quantum\, and more.\n\nThis event is hosted in cooperation with the Egyptian Information Technology Industry Development Agency (ITIDA) and the Egyptian Information & Communication Technology Association (EiTESAL). \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/gsa-mena-executive-summit/ LOCATION:Grand Egypian Museum\, Alexandria Desert Rd\, Kafr Nassar\, Al Haram\, Giza Governorate\, Cairo\, Egypt CATEGORIES:EDA,Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-February-20-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250129T130000 DTEND;TZID=Europe/London:20250129T173000 DTSTAMP:20241220T033019Z CREATED:20241220T033019Z LAST-MODIFIED:20241220T033019Z UID:8642-1738155600-1738171800@marketingeda.com SUMMARY:DVClub Europe - Mixed Signal Verification DESCRIPTION:Analog mixed signal chips continue to grow in both demand and complexity\, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the University of Edinburgh and the university students will be attending. The first half of the DVClub will focus concepts of digital and analog verification\, as well as an overview of the work the university is doing on AI in semiconductors through the APRIL hub\, focusing on the verification activities. \nIn the second half of this DVClub\, local companies will focus on challenges and solutions for mixed signal verification at SoC\, system and in safety-related applications. \nAgenda (GMT) \n13.00: Arrival and Registration with Coffee and Snacks \n\nmainly for students but local companies also welcome\n\n13:25: Mike: Welcome \n13.30: Introduction from the University \n14.00: Mike – Introduction to Digital Verification \n14:30: Peter/Graeme – Mixed Signal Verification Part I \n15.00: Break – Coffee and Snacks \n\n Delegates can also attend for 2nd half only if preferred\n\n15:30: Peter/Graeme – Mixed Signal Verification II \n16:00: Michael O’Sullivan & Marcel Ahmedzai\, Cadence Design Systems – SoC Verification \n16:30: System and Safety Verification: (TBC) \n17:00: Mike: wrap up and next steps for students/local companies to collaborate \n17:10: Drinks and Pizza\n \nAdditional Information\nFor additional information please visit the Tessolve DVClub webpage for this event. \nSponsors\nDVClub Europe\, Edinburgh is made possible through the generous support of our sponsors:  Cadence\, Partner: TechWorks \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvclub-europe-mixed-signal-verification/ LOCATION:Edinburgh City Centre\, Edinburgh\, United Kingdom CATEGORIES:EDA,Forum,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-29-January-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20241119T080000 DTEND;TZID=Europe/Amsterdam:20241119T170000 DTSTAMP:20241106T193115Z CREATED:20241106T192658Z LAST-MODIFIED:20241106T193115Z UID:8478-1732003200-1732035600@marketingeda.com SUMMARY:2024 TSMC Europe OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for A16\, N2 and N3 processes\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-tsmc-europe-oip-ecosystem-forum/ LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240926T080000 DTEND;TZID=America/Los_Angeles:20240926T170000 DTSTAMP:20240710T165347Z CREATED:20240710T165347Z LAST-MODIFIED:20240710T165347Z UID:8121-1727337600-1727370000@marketingeda.com SUMMARY:GSA U.S. Executive Forum 2024 DESCRIPTION:THE JOURNEY TO A $1T GLOBAL INDUSTRY\n\n\n\n\n\n\n\nThe GSA US Executive Forum will delve into the semiconductor industry’s journey toward achieving the trillion-dollar milestone. The industry operates in a complex environment where global forces intersect with regional dynamics. Industry executives will explore the delicate balance between globalization and regionalization\, considering both opportunities and challenges while emphasizing sustainable growth\, innovation\, and strategic business practices. \nIndustry leaders will also provide thought leadership into the market forces and advancements that shape the industry’s growth trajectory and explore the key drivers propelling the industry for sustainable growth. \n\n\n\n\nThe US Executive Forum is GSA’s premier exclusive\, invitation-only event that brings together influential executives\, thought leaders\, and subject matter experts for thought exchange and collaborative dialogue on the dynamic landscape of the global semiconductor value chain. With technological advancements driving rapid change\, the US Executive Forum fosters a deep understanding of the industry’s future direction and identifies strategies for success in an era of innovation and collaboration.\n\n\n\n1:00 PM\n\nWelcome Remarks\n\nJodi Shelton // CEO // GSA\n \n\n\n\n\n\n\n1:10 PMPANEL\n\nFireside Chat\n\nJensen Huang // Co-founder\, President and CEO // Nvidia \n\n\n\n\n\n\n1:50 PMPRESENTATION\n\nGlobal Landscape Impacting the Industry\n\n\n\n\n\n2:10 PMKEYNOTE\n\nKeynote – Industry Outlook\n\nDave Mosley / CEO / Seagate\n\n\n\n\n\n\n2:40 PM\n\nNetworking Break\n\n\n\n\n\n3:10 PMPANEL\n\nDisruptors in AI\n\nJitendra Mohan / Co-founder and CEO / Astera Labs\nRodrigo Liang / Co-founder and CEO / SambaNova\n\n\n\n\n\n\n3:50 PMPRESENTATION\n\nAutomotive Supply Chain\n\n\n\n\n\n4:05 PMPANEL\n\nAutomotive Electrification Panel Discussion\n\nKarn Budhiraj / Vice President\, Supply Chain / Tesla\nSiva Sivaram / CEO / QuantumScape\n\n\n\n\n\n\n4:45 PM\n\nNetworking Break\n\n\n\n\n\n5:15 PMPANEL\n\nExecutive Panel Discussion\n\nTien Wu / CEO / ASE Group & USI\nSandra Rivera / CEO / Altera\, an Intel company\nRene Hass / CEO / Arm\n\n\n\n\n\n\n6:00 PMKEYNOTE\n\nClosing Keynote\n\n\n\n\n\n6:40 PM\n\nVIP Reception\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/gsa-u-s-executive-forum-2024/ LOCATION:Rosewood Sand Hill\, 2825 Sand Hill Road\, Menlo Park\, CA\, United States CATEGORIES:Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-US-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240925T093000 DTEND;TZID=America/Los_Angeles:20240925T180000 DTSTAMP:20240917T003907Z CREATED:20240917T003541Z LAST-MODIFIED:20240917T003907Z UID:8337-1727256600-1727287200@marketingeda.com SUMMARY:TSMC North America OIP Ecosystem Forum 2024 DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for A16\, N2 and N3 processes\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-north-america-oip-ecosystem-forum-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,Forum,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240924T094500 DTEND;TZID=Europe/London:20240924T143000 DTSTAMP:20240906T170817Z CREATED:20240906T170817Z LAST-MODIFIED:20240906T170817Z UID:8297-1727171100-1727188200@marketingeda.com SUMMARY:FPGA Front Runner: FPGA Verification Strategies DESCRIPTION:Time\nSpeaker\nDetails\n\n\n09.30\nArrival and Registration\n\n\n10.00\nDave Sanders\, Rolls-Royce\nOverview of Rolls Royce @ Solihull \nPresentation Title – Rolls-Royce… the past\, the present and the future \nAbstract – Rolls-Royce has come a long way since its inception as a car manufacturer at the start of the twentieth century\, for starters it doesn’t make cars anymore! This talk will provide an insight into Rolls-Royce’s past present and future with a focus on the pivotal role that electronics now plays in a company traditionally known for its mechanical engineering solutions.\n\n\n10.30\nEspen Tallaksen\, EmLogic\nPresentation Title – Modern VHDL testbenches – An AXI-stream example\, first dead simple\, then advanced \nAbstract – Do you want to see how easily you can verify your FPGA or ASIC? Join in to see this exemplified with a testbench for an AXI-stream based data flow design – using UVVM\, which is currently used by more than one third of all European FPGA designers. \nMost testbenches verifying a complex DUT are relatively unstructured and difficult to understand\, modify\, extend\, maintain and reuse. You can often easily reduce the verification time by at least a factor of two by having a well structured and easy to understand test harness\, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high-level commands. \nThis presentation will first show how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components\, models\, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way.\n\n\n11.00\nJim Lewis\, SynthWorks Design Inc\nPresentation Title – Why Should Our Team be Using VHDL + OSVVM for Verification? \nAbstract – Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems. \nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports. \nThis presentation examines how these capabilities will benefit your projects. \nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities. \nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers. \nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\n11.30\nRefreshment break\n\n\n12.00\nPhilipp Wagner\, FOSSi Foundation\nPresentation Title – cocotb is making verification fun! \nAbstract – cocotb lets you verify chips like software: productive\, simulator-agnostic\, in Python. In this talk\, you’ll learn what cocotb is and how using Python for verification can make your next verification job more productive. There’s even something in there for those of you who already know cocotb: a look at cocotb 2.0 and tips and tricks how to update your testbenches to make best use of the new features.\n\n\n12.30\nChristian Tchilikov\, semify GmbH\nPresentation Title – Utilizing the Cocotb Python Framework for Efficient Functional Verification \nAbstract – Cocotb is a framework that allows for verification test cases written in Python to interact with DUTs being simulated in common simulation tools. Compared to classical approaches for verification\, Cocotb has very low upfront engineering costs. With access to the full functionality of the Python programming language\, the complexity of testbenches can scale up as required. \nCocotb comes with built-in functionalities for many of the tasks required of a modern testbench\, like constrained random input generation\, coverage tracking\, and assertions. \nCocotb’s foundation being the Python language means that software models of the design can be written in a high-level Object-Oriented language. Additionally\, higher-level objects such as drivers or monitors can be designed for the bit-wiggling of DUT input signals\, providing a higher level of abstraction\, similar to UVM sequences. The software model can then be easily scoreboarded with the DUT through Cocotb. \nAdditionally\, Cocotb provides high-level abstractions for interfacing with the simulated design. This comes in the form of hierarchical signal reading and assignment\, event triggers\, and parallel execution of coroutines similar to SystemVerilog’s forks. Leveraging these tools\, it becomes simple to launch verification modules like drivers and monitors\, running and interfacing with the DUT in parallel. \nThird-party verification IP modules for many standard interfaces are available via the cocotb extensions packages hosted on PyPi\, so devices using SPI or AXI\, amongst others\, can be verified with minimal effort. In addition\, engineers can write and reuse their own verification IP\, such as bus monitors\, drivers\, etc\, similar to the UVM approach of verification. \nA special emphasis is on using cocotb alongside an open-source toolchain like Icarus Verilog\, acheiving a similar quality of results compared to commercial offerings. This combination of tools provides features that are otherwise hidden behind expensive licence paywalls\, and makes digital verification accessible to a wider audience. \nCocotb serves as a great alternative to traditional SystemVerilog Object-Oriented verification by working around the limitations of the simulators that do not support the full feature set of SystemVerilog by providing similar functionality in the Python language instead.\n\n\n13.00\nDave Amor\, Ultra Maritime\nPresentation Title – Integration of Atlassian Bamboo with MathWorks Tools for FPGA Development \nAbstract – In safety critical FPGA development\, the need for efficiency\, reliability\, and predictability while maintaining agility is vital. \nUltra Maritime has embraced these demands by integrating Continuous Integration (CI) practices with MathWorks tools and Agile methodologies\, creating a streamlined and robust development process that ensures high-quality outcomes in mission-critical applications. \nThis presentation will explore the strategies and technologies we use to achieve consistent\, and resilient FPGA development\, focusing on how these practices contribute to the success of our projects. \nAtlassian Bamboo allows us to automate testing\, code generation\, and the bitstream creation processes. \nThis integration ensures that every change in our FPGA designs can be automatically validated through rigorous testing\, significantly reducing the risk of errors and accelerating the development lifecycle. \nBy automating these processes\, a higher standard of code quality is possible while freeing up our engineers to focus on innovation and problem-solving. \nThis presentation will touch on the adoption of Agile Scrum practices within our FPGA development teams. \nAgile Scrum provides a flexible framework that allows us to adapt to changing requirements\, prioritise tasks effectively\, and deliver incremental improvements throughout the project lifecycle. Key ceremonies such as sprint planning\, daily stand-ups\, and retrospectives are essential to maintaining focus and ensuring continuous improvement. We will discuss how these practices have enhanced our ability to respond to challenges\, manage complexity\, and maintain alignment across our teams. \nA crucial aspect of our development process is the integration of Jira with Bamboo and Simulink. This connection enables seamless tracking of tasks\, test results\, and code changes. Automated reporting of test failures and direct linking to Jira tasks ensure that issues are identified\, prioritised and resolved. \nThe presentation will also address the advantages of CI in ensuring resilience against the turnover of key personnel. By standardising workflows and maintaining consistent environments\, we reduce the dependency on individual knowledge and ensure that our processes are sustainable. \nLooking to the future\, we will explore potential enhancements to our current setup\, by leveraging developments in Large Language Models. \nUltra Maritime’s approach to FPGA processes evolving over the last 25 years has created a environment that is effective\, adaptable and resilient\, ensuring the delivery of high-quality\, reliable products.\n\n\n13.30\nLunch\n\n\n14.00\nTour\n\n\n14.30\nFinish refreshments/networking\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-front-runner-fpga-verification-strategies/ LOCATION:Rolls Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37\, United Kingdom CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-September-24-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240905T090000 DTEND;TZID=America/Los_Angeles:20240905T183000 DTSTAMP:20240711T225247Z CREATED:20240711T225247Z LAST-MODIFIED:20240711T225247Z UID:8138-1725526800-1725561000@marketingeda.com SUMMARY:Synopsys Processor IP Summit 2024: RISC-V\, DSP and NPU IP for Your Diverse SoC Processing Needs DESCRIPTION:As electronic systems continue to become more complex and integrate greater functionality\, SoC developers are faced with the challenge of developing more powerful\, yet more energy-efficient devices. The processors used in these applications must be efficient to deliver high levels of performance within limited power and silicon area budgets. \n  \nWhy Attend?\nJoin us for the Processor IP Summit to get in-depth information from industry leaders on the latest in ARC-V™ RISC-V processor IP\, ARC® VPX DSP IP and ARC NPX NPU IP along with related hardware/software technologies that enable you to achieve PPA differentiation in your chip or system design. Synopsys experts\, partners\, and our processor IP user community will discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, software development and more. Sessions will be followed by a networking reception where you can see live demos. \n  \nWho Should Attend?\nWhether you are a developer of chips\, systems or software\, the Synopsys Processor IP Summit will give you practical information to help you create more differentiated products in the shortest amount of time. \n  \nAgenda\nAgenda is coming soon \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-processor-ip-summit-2024-risc-v-dsp-and-npu-ip-for-your-diverse-soc-processing-needs/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240827T090000 DTEND;TZID=America/Los_Angeles:20240827T170000 DTSTAMP:20240827T162200Z CREATED:20240827T162200Z LAST-MODIFIED:20240827T162200Z UID:8279-1724749200-1724778000@marketingeda.com SUMMARY:Q3 Memory Fabric Forum DESCRIPTION:Memory fabrics unlock the power to pool\, tier\, and share memory in a data center fabric. The results will be vastly more memory capacity and lower cost due to higher utilization—the things needed to support memory-hungry generative AI apps. \n  \nAttend this webinar for a comprehensive update on CXL® market adoption\, technology\, products\, and use cases. \n\nRegister to attend and/or watch on YouTube after the event. \n  \nPart 1 – Industry Landscape. Highlighted by the presentation at 9:10 PT by Samsung of a “Moonshot” project to leapfrog from 10\,000 AI cluster nodes to 1\,000\,000 nodes. \nPart 2 – Technologies and products for the Enterprise. Highlighted by an overview from NVIDIA at 12:09 PT of their portfolio of high-bandwidth\, low-latency networking products for AI. \nPart 3 – Technologies and products for developers. Highlighted by new CXL forecast data presented by Montage at 1:26 PT. \n  \nBest\, Frank Berry\, VP of Marketing at MemVerge.\n\n\n \n\n\n\n\n\n \n\n\nQ3 Memory Fabric Forum Agenda \nRegister to attend\n\n\n \n\n\n\n\n\n\nIndustry Landscape\n\n\n1\n9:00 PT\nFrank Berry\nMemVerge\nThe AI Big Bang\n\n\n2\n9:10 PT\nSiamak Tavallaei\nSamsung\nAt-scale Systems: Interconnecting Massively Parallel xPUs\n\n\n3\n9:41 PT\nKurtis Bowman\nCXL Consortium\nCXL® Advancing Coherent Connectivity\n\n\n4\n9:53 PT\nJim Handy\nObjective Analysis\nCXL Is Exciting\, But Where is It Headed?\n\n\n5\n10:16 PT\nMark Nossokoff\nHyperion Research\nHPC/AI Market Update and Industry Composability Snapshot\n\n\n6\n10:32 PT\nJack Gidding\nSTAC Research\nSTAC Overview\n\n\n7\n10:46 PT\nSeth Friedman\nLiquid Markets\nLiquid-Markets-Solutions: Introduction to UberNIC\n\n\nTechnology and Products for the Enterprise\n\n\n8\n11:10 PT\nAnil Godbole\nIntel\nIntel Compute Express Link™ Enablement\n\n\n9\n11:25 PT\nMichael Abraham\nMicron\nCXL-Compatible Memory Modules\n\n\n10\n11:45 PT\nTorry Steed\nSMART Modular\nCXL Memory Expansion Advantages\n\n\n11\n12:09 PT\nReggie Reynolds\nNVIDIA\nNVIDIA Networking for HPC\, AI\, and Accelerated IO\n\n\n12\n12:41 PT\nSteve Scargall\nMemVerge\nMemory Machine™ for CXL\n\n\n13\n1:00 PT\nPhilip Maher\nMSI\nS2301 CXL Memory Expansion Server\n\n\nTechnology and Products for the Enterprise\n\n\n14\n1:08 PT\nMichael Ocampo\nAstera Labs\nAccelerating AI & ML with CXL-Attached Memory\n\n\n15\n1:26 PT\nGeof Findley\nMontage\nCXL 2.0 Use Case: Using Both DDR4 & DDR5 on the Same Server\n\n\n16\n1:43 PT\nJP Jiang\nXConn\nCXL Switch for Scalable & Composable Memory Pooling/Sharing\n\n\n17\n2:05 PT\nGary Ruggles\nSynopsys\nEnabling New Memory Applications Using CXL IP\n\n\n18\n2:37 PT\nNilesh Shah\nZeroPoint\nHyperscale Composable Memory Systems with Dynamically Adjusting Compressed Tier\n\n\n19\n3:00 PT\nGrant Mackey\nJackrabbit Labs\nYou Don’t Know Jack: CXL Fabric Orchestration and Management\n\n\n20\n3:19 PT\nBill Gervasi\nWolley\nNVMe Over CXL: How CXL Lets Us Do Controller Memory Buffers the Right Way\n\n\n21\n3:39 PT\nBill Gervasi\nWolley\nFleX: Bringing CXL to the Motherboard\n\n\n22\n3:59 PT\nBill Gervasi\nWolley\nCXL Native Memory: Do We Really Need DDR?\n\n\n23\n4:20 PT\nArvind Jagannath\nVMware\nVMware Memory Tiering: Customer-Ready Today\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/q3-memory-fabric-forum/ CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Q3-Memory-Fabric-Forum.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240820T100000 DTEND;TZID=America/Los_Angeles:20240820T150000 DTSTAMP:20240723T174531Z CREATED:20240723T174531Z LAST-MODIFIED:20240723T174531Z UID:8171-1724148000-1724166000@marketingeda.com SUMMARY:Cloud Tech Day DESCRIPTION:Join your fellow engineers and the Cadence Cloud team for an educational and networking event focused on developing a secure and scalable electronic design flow in the cloud. \nDate: August 20\, 2024\nTime: 10:00am – 3:00pm PDT\nLocation: Cadence HQ | 2655 Seely Avenue San Jose\, CA\, 95134 | Building 5 \n  \nWhat You Will Learn \n\nExciting new features and a roadmap view of Cadence Cloud\nStrategies and solutions for all-cloud or hybrid-cloud environment for your next design\nHands-on workshop: Experience running a design flow in Cadence Cloud\nMeet the R&D team behind the Cadence Cloud portfolio\n\nWho Should Attend \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers and business leaders seeking to optimize their design flow and technology infrastructure.\n\nLimited seating available\, register now to reserve your spot! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cloud-tech-day/ LOCATION:Cadence Design Systems\, Building 5\, 2655 Seely Avenue\, San Jose\, CA\, 95131\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240711T091500 DTEND;TZID=America/Los_Angeles:20240711T120000 DTSTAMP:20240710T195826Z CREATED:20240710T195715Z LAST-MODIFIED:20240710T195826Z UID:8131-1720689300-1720699200@marketingeda.com SUMMARY:Synopsys Virtual Prototyping Day 2024 DESCRIPTION:Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology\, covering applications from automotive\, AI\, and data center domains.​ \n​Industry leaders will share their experiences with the latest techniques and methodologies using virtual prototypes for early software development and architecture exploration. Presentations will highlight how virtual prototypes help to address the increased architectural challenges of highly complex SoC and multi-die architecture designs\, as well as enabling early embedded software development\, debug\, and testing. \nWelcome\n9:15 AM-9:30 AM\nGeneral Session\nJoin Marc Serughetti as he welcomes you to Virtual Prototyping Day. \nM S\nMarc Serughetti\nVP Product Management\nSynopsys \nLeveraging Virtual Platforms to Shift-left HW/SW Verification\nJuly 11\, 2024 \n9:30 AM-9:55 AMPT\nSoftware Development & Test\nAs SoC(System-On-Chip) complexity continues to increase due to the hardware-dependent software functionality\, hardware/software co-verification should be done in the early design stage. This presentation shows how the virtual platform technology enables early software development as well as the concurrent hardware/software co-verification for SSD(Solid State Drive) development as an industrial case study \nKyungsu Kang\nSamsung \nPre-Design Verification and Optimization for On-chip Interconnects\nJuly 11\, 2024 \n9:30 AM-10:00 AMPT\nSystem Architecture Design & Exploration\nData movement plays a big role in overall SoC performance. It is essential to qualify the on-chip interconnect architecture as early as possible – to verify algorithms applied on the on-chip interconnect\, determine the best performance tuning settings in the design\, and assist in power and performance projections – all before RTL is available. \nThis presentation discusses the collaboration between Microsoft and Synopsys on the on-chip interconnect model development and exploration using Platform Architect\, the many learnings that were made along the way\, and the achievements made by the team. \nCharlie Zhou\nMicrosoft \nMonica Tang\nMicrosoft \nApplication-level Hybrid Emulation for Software-Defined-Systems\nJuly 11\, 2024 \n9:55 AM-10:25 AMPT\nSoftware Development & Test\nOver the last 10 years\, Hybrid Emulation has been widely deployed for Early SW bring-up and HW/SW validation. Combining a fast virtual prototype of the CPU sub-system with the RTL of the remaining SoC running on an emulator typically produces a 10x speed-up over full emulation setups and saves precious emulator resources. ​ \nRecent advances in both virtual prototyping and emulation now yield another leap in hybrid performance\, which enables pre-silicon execution of full Software stacks\, including end-user applications. In an emerging world of Software-defined Systems\, this provides invaluable insight for the validation and optimization of HW resources and their deployment by Software applications under realistic use-case scenarios\, like AI-enabled functions\, autonomous drive stacks\, end-to-end networking applications\, etc.​ \nIn this tutorial\, we will first review the latest state-of-the-art of hybrid emulation technologies and use-cases. We will then illustrate the application of hybrid emulation for the pre-silicon validation and optimization of Software-defined Systems. \nTim Kogel\nSr. Director for Technical Product Management\nSynopsys \nNetwork-on-Chip Design for Automotive Processor and Platform Integration for Front-end Benchmarking\nJuly 11\, 2024 \n10:00 AM-10:30 AMPT\nSystem Architecture Design & Exploration\nIn this presentation we would like to address our flow of architectural exploration of StellarApp SoC using Synopsys Platform Architect tool and Designware LPDDR5 model. Validation of automotive SoCs using valid benchmark is must to guarantee all performance and design parameters are met and this could not be possible without usage of Synopsys Platform Architect tool: 1) to assemble models with different level of abstraction and from 3rd parities (ARM and Arteris )\, 2) easy configuration and sweeping their parameters in different round of fast simulation\, 3) effective analysis from both HW and SW point of view and 4) finally accurate model of Synopsys DW_LPDDR5 which helped us extremely fast and effective to validate our SoC with different benchmark. \nFilippo Colaninno\nST \nVirtual Prototypes Drive RISC-V Software Development\, Optimization and Test\nJuly 11\, 2024 \n10:25 AM-10:55 PMPT\nSoftware Development & Test\nAs RISC-V processors gain momentum in the semiconductor market\, attention is shifting from a complete focus on the processor design to a shared focus on processor and software. Just as with other processor architectures\, software development is most often the critical path to SoC projects. Challenges for software development include how to shift left software development\, how to optimize architecture\, effective debug\, software optimization\, and continuous integration and DevOps flow integration. \nVirtual prototypes provide a productive answer to these challenges. Virtual prototypes\, with ImperasFPM RISC-V fast processor models and the Virtualizer tools\, enable pre-silicon software development. The virtual prototypes also enable architecture optimization (RISC-V custom instructions) and software optimization with Virtualizer analysis tools. Virtualizer also supports hardware-software debug\, and is used every day in DevOps flows. \nWith the ImperasFPMs supporting RISC-V processor IP from both vendors and custom processors\, users have full flexibility to design in a RISC-V domain-specific processor\, and build the software to execute on their SoC platform. \nLarry Lapides\nExec. Director\, Business Development\nSynopsys \nEarly Performance Exploration of Kalray ManyCore IC Using App Dataflows w/Arm Performance Models\nJuly 11\, 2024 \n10:30 AM-11:00 AMPT\nSystem Architecture Design & Exploration\nEarly validation of system architecture decisions is crucial to avoid delays and meet product requirements. Kalray’s ManyCore chips\, designed for storage\, compute and AI applications\, need high compute efficiency and optimized dataflows between the chip’s interfaces\, main memory\, and local memory. The efficiency of these dataflows depends on various hardware and software parameters\, such as workload patterns\, the number of concurrent workloads\, DRAM transaction distribution\, DRAM scheduling policies\, and interconnect configurations. \nUsing Synopsys Platform Architect\, with generic IP and Arm performance models\, we created a performance SystemC simulation platform that helps validate architectural assumptions early on\, guiding data-driven decisions during chip design. Our simulation platform\, which can be quickly developed without needing RTL availability\, supports continuous integration to detect potential architecture regressions. We plan to enhance the model’s accuracy by integrating IP models as the design progresses. \nPierre-Yves Taloud\nKalray \nEnflame Virtual Prototyping for AI Chip Early SW Development\nJuly 11\, 2024 \n10:55 AM-11:25 AMPT\nSoftware Development & Test\nEnflame is an AI chip start-up company. It also develops runtime/framework SW to run AI models on its chip. Synopsys Virtualizer helps to shift-left SW development by 6 months. On virtual prototyping of the whole AI chip\, HW designer got early feedback for new architecture; Performance optimization started before chip tap-out; Hybrid virtual prototyping even help to verify RTL design. HW and its SW’s time-to-market was reduced. This session will present: \nWhy Virtual Prototyping\nVirtual Prototyping Development\nUsage Model\nAchievements and Next Steps \nGang Jia\nEnflame \nUse of Platform Architect for Architecting the Next Generation AURIX Microcontroller\nJuly 11\, 2024 \n11:00 AM-11:30 PMPT\nSystem Architecture Design & Exploration\nVirtual prototyping is key for early design space exploration and proper architecture definition for any given SoC platform. This talk focuses on how the Synopsys Platform Architect tool is used to help architect the next generation AURIX microcontroller:​ \nPrimarily\, the tool is used to execute system performance simulations for different architectural domains such as compute\, interconnect and memory. ​\nOur simulation platform comprises of several components with different modelling abstraction levels\, such as Synopsys library models\, custom developed models and even RTL models.​\nSimulations are executed using both standard code benchmarks and synthetic traffic as stimuli.​\nThe simulation results are analysed using standard metrics such as latency\, bandwidth\, etc.\, with deeper analysis using automated custom post-processing scripts​ \nSandeep Vangipuram\nInfineon Technologies \nOrchestrating SoC Design Space Exploration to Optimize Performance for Multi-Agent Core-IO Workloads\nJuly 11\, 2024 \n11:30 AM-12:00 PMPT\nSystem Architecture Design & Exploration\nOptimizing the performance of System-on-Chip (SoC) designs requires a comprehensive understanding of the workload characteristics and complex interactions between fabric interconnects\, system caches\, and DRAM controllers. In this presentation we will share a robust methodology to model different workloads and orchestrate design space exploration (DSE) for performance optimization of these critical SoC components using Synopsys Platform Architect.​ \nOur approach utilizes the advanced capabilities of Synopsys Platform Architect to create detailed and accurate workload models and use performance models of the fabric\, system cache\, and DRAM controller. By integrating these models with heuristic optimization techniques\, we conduct an efficient and exhaustive exploration of the design space\, identifying configurations that offer the best trade-offs between performance\, power\, and area (PPA). We specifically address the challenges posed by multi-agent Core-IO traffic\, focusing on the intricate interactions between compute and memory subsystems.​ \nThe results demonstrate marked improvements in design efficiency\, with optimized configurations achieving orders of improvement in Performance compared to baseline designs. This methodology equips industry practitioners with a powerful toolset for early-stage SoC DSE\, enabling more informed design decisions and enhancing the overall performance of computing systems. \nMelwyn Scudder\nIntel NEX \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-virtual-prototyping-2024/ CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240618T080000 DTEND;TZID=Europe/Berlin:20240619T170000 DTSTAMP:20240417T180940Z CREATED:20240417T180940Z LAST-MODIFIED:20240417T180940Z UID:7870-1718697600-1718816400@marketingeda.com SUMMARY:GSA European Executive Forum 2024 DESCRIPTION:The GSA European Executive Forum\, our flagship event in Europe\, is BACK! Join us June 18th and 19th in Munich for the event of the summer! \nThis year\, in honor of GSA’s 30th anniversary\, we want to celebrate by bringing you the very best EEF ever: amazing speakers\, most thought provoking topics and the very best attendees. \nExpect a captivating combination of high-level discussions with forward looking technology trends: a masterful CEO fireside chat\, sessions ranging from genAI impact on the semiconductor industry\, to the future of networks\, to the emergence of a chiplet ecosystem\, to automotive\, sustainability\, and even on how tantalizing close we are to unlocking the world-changing promises of nuclear fusion and clean energy for all! \n  \nVIP Dinner capacity is strictly limited. \nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region. \nHotels in Munich are already very hard to find around the event date: PLEASE BOOK YOUR HOTEL ROOM NOW. \n  \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/gsa-european-executive-forum-2024/ LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany CATEGORIES:Forum,Foundry,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-18-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240612T080000 DTEND;TZID=America/Los_Angeles:20240613T170000 DTSTAMP:20240610T171842Z CREATED:20240610T171842Z LAST-MODIFIED:20240610T171842Z UID:8085-1718179200-1718298000@marketingeda.com SUMMARY:Samsung Foundry Forum & SAFE Forum 2024 U.S. DESCRIPTION:June 12th\, 2024\n12:30 – 5:30 PM PDT \n\n\n01:35 – 01:50 PM\nSamsung Keynote\nSiyoung Choi\nPresident and GM\, Foundry Business Samsung Electronics\n\n\n\n\n01:50 – 02:05 PM\nThe Accelerated Compute Platform for the Age of AI\nRene Haas\nCEO\nARM\n\n\n\n\n02:05 – 02:20 PM\nGroq’s Transformation of Generative AI ComputeJonathan RossCEO and Founder\n\n\n\n02:20 – 02:55 PM\nSamsung AI Solutions\nTaeJoong Song\nVP\, Head of Business Development\nIndong Kim\nVP\, Head of DRAM Product Planning\nHee Joung Joun\nVP\, AVP Marketing & Strategy Group\nSamsung Electronics\n\n\n\n\n03:25 – 04:00 PM\nProcess Technology\nJa-Hum Ku\nEVP\, Head of Technology Development\nSamsung Electronics\n\n\n\n04:00 – 04:15 PM\nManufacturing Excellence\nSang Sup Jeong\nEVP\, Head of Foundry Manufacturing Technology Center\nSamsung Electronics\n\n\n\n\n04:15 – 04:30 PM\nDesign Platform\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n04:30 – 04:40 PM\nBusiness & Customers\nSang-Pil Sim\nEVP\, Head of Worldwide Sales and Marketing\nSamsung Electronics\n\nJune 13th\, 2024\n9:00AM-5:30 PM PDT \n\n\n10:00 – 10:15 AM\nWelcome Remarks\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n10:15 – 10:35 AM\nEnabling a New Era of Design\nMike EllowCEO\nSiemens EDA Silicon Systems\n\n\n\n10:35 – 10:55 AM\nDemand for Power Efficiency in the Age of AI\nBill EnCorporate Vice President\nAMD\n\n\n\n\n10:55 – 11:15 AM\nThe Photonic FabricTM\, Optical Compute Interconnect for Accelerated Computing\nDavid Lazovsky\nCEO and Founder\nCelestial AI\n\n\n\n11:15 – 11:35 AM\nTechnology & Business Update\nTaeJoong Song\nVP\, Head of Business Development\nSamsung Electronics\n\n\n\n\n1:00 – 4:30 PM\nTech Session Ⅰ:\nAdvanced Technology and Design Enablement\nSei Seung Yoon\nEVP\, Head of Library Development\nSungwook Moon\nMaster(VP of Technology)\,\nFoundry Design Service\nSamsung Electronics\n\n1:00 – 4:30 PMTech Session Ⅱ:\nDesign Solutions of AI\, for AI\, and by AI\nJongshin Shin\nEVP\, Head of Foundry IP Ecosystem\nSamsung Electronics \n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/samsung-foundry-forum-safe-forum-2024-u-s/ LOCATION:Samsung Semiconductor US Campus\, 3655 N. First Street\, San Jose\, CA\, United States CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-SAFE-2024-US.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240509T173000 DTEND;TZID=America/Los_Angeles:20240509T203000 DTSTAMP:20240328T160417Z CREATED:20240328T160417Z LAST-MODIFIED:20240328T160417Z UID:7787-1715275800-1715286600@marketingeda.com SUMMARY:ESD Alliance CEO/Executive Outlook DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/ LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240502T093000 DTEND;TZID=America/Los_Angeles:20240502T160000 DTSTAMP:20240424T162043Z CREATED:20240424T162005Z LAST-MODIFIED:20240424T162043Z UID:7901-1714642200-1714665600@marketingeda.com SUMMARY:Keysight EDA Connect Tour - Austin DESCRIPTION:Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin\, TX and Burlington\, MA. \nSave the dates for our upcoming events in Austin\, TX on May 2 or Burlington\, MA on May 16\, where we’ll explore the future of AI in 6G to 3D Module integration. \nThese technical sessions promise to recharge your design productivity\, refresh your knowledge base\, and renew contacts with fellow design professionals. \nDon’t miss out on this opportunity to be at the forefront of innovation with Keysight. \nAs AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nLight breakfast and lunch will be provided. \nAgenda\n\n\n\n09:30\nCheck-in & Breakfast\n\n\n10:00\nWelcome – Keynote\n\n\n10:10\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs\n\n\n11:00\nRF System Design / New System Verification Tools in ADS for Circuit Designers\n\n\n12:00\nSolving 3D Module Integration Challenges for High-Performance Microwave Design (Integration is our differentiator)\n\n\n12:45\nRF Switch Design with Keysight ADS\n\n\n1:30-4:00\nLunch Break / Golf\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/keysight-eda-connect-tour-austin/ LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240429T100000 DTEND;TZID=Europe/London:20240429T143000 DTSTAMP:20240322T163227Z CREATED:20240322T163227Z LAST-MODIFIED:20240322T163227Z UID:7746-1714384800-1714401000@marketingeda.com SUMMARY:TechNES FPGA Front Runner Event DESCRIPTION:The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. \nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/technes-fpga-front-runner-event/ LOCATION:New Mills\, Wotton-under-Edge\, GL12 8JR\, United Kingdom CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-29-April-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T111500 DTEND;TZID=America/Los_Angeles:20240425T170000 DTSTAMP:20240411T001153Z CREATED:20240411T001153Z LAST-MODIFIED:20240411T001153Z UID:7836-1714043700-1714064400@marketingeda.com SUMMARY:Tech Summit: ASC Sunstone & Screaming Circuits DESCRIPTION:Calling all PCB designers and engineers to join us for an exclusive Technical Summit and Casino Excursion for Designers & Engineers! \nThis summit is crafted to bring together PCB engineers and technical professionals for a day of immersive learning\, cutting-edge insights\, and many networking opportunities. \nJoin us to expand your knowledge\, establish invaluable connections\, and stay at the forefront of PCB innovation! Dive into the latest advancements\, share knowledge\, and forge meaningful connections within the PCB design and engineering community. \nOnce we have all had a chance to share and digest\, we will board a bus to Ilani Casino for some fun and entertainment! We’ll even have you back at a decent hour so you can be fresh for work on Friday. \n11:15 AM – 11:45 AM \nIntroduction/Box Lunch \nAnaya Vardya \nMatt Stevenson \n\nAnaya – CEO American Standar Circuits/Sunstone Circuits -CEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. Matt Stevenson – VP and General Mgr ASC Sunstone Circuits – has extensive experience in the PCB industry and has proven his skill and dedication to Sunstone by continuing to grow the company’s revenue and enhance the customer experience. \n11:45 AM – 12:30 PM \nBest Practices – PCB Design \nStephen Chavez \n\nSenior Product Marketing Manager – SME PCB Design\, MIT\, CID+\, CPCD – Chairman – Printed Circuit Engineering Association (PCEA) – Steph is a senior printed circuit engineer with three decades’ experience. He spent the past 12 years as a Principal Engineer and global subject matter expert of PCB design for Collins Aerospace (Raytheon Technologies). He is an IPC Certified Master Instructor Trainer (MIT) for PCB design\, an IPC Certified Advanced PCB Designer (CID+)\, and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA) where his focus is on the continuous improvement\, professional development\, and the evolution of the printed circuit engineer throughout the industry. An active IPC member since 2003\, he is currently involved in several subcommittees including specifications IPC-6012\, IPC-2221/2222. Chavez is recognized as an industry subject matter expert in PCB design by PCEA\, IPC\, and several leading industry publications. \n12:35 PM – 1:15 PM \nDFM/DFA\nMike Galloway \nMike Galloway has extensive experience in the electronics manufacturing industry\, specializing in prototype process development with a focus on Surface Mount Technology (SMT). With over 15 years at Screaming Circuits as a Senior Manufacturing Engineer\, he plays a crucial role in prototyping and providing short-run production support. Before joining Screaming Circuits\, Mike built his experience at various Contract Manufacturers (CMs) and Original Equipment Manufacturers (OEMs) as well as working with tooling firms serving the electronics industry. Mike’s expertise lies in optimizing manufacturing processes for prototypes\, particularly in the realm of SMT and scaling into production volumes. \n1:30 PM – 2:10 PM \nThermal Management\nAnaya Vardya \nCEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. He has over a decade of executive management experience in public companies manufacturing PWBs. In addition\, he writes about a variety of subjects but he us particularly focused on partnerships\, technology and manufacturing techniques. \n2:15 PM – 3:00 PM \nUltra HDI\nJohn Johnson \nDirector of Quality at American Standard Circuits – John has a long tenure in Material and Printed Circuit manufacturing. After obtaining an Masters of Science in Organic Chemistry from The Ohio State University\, he has held positions as an R&D Chemist\, Quality Engineer\, Sr. Process Engineer\, Quality Manager\, Sales Rep\, Director of Sales\, General Manager\, President/CEO. Prior to joining ASC as a Director of Business Development\, he was VP of Sales and Customer Support at Averatek Corp and focused on Ultra Fine Line technology. John currently serves as ASC’s Director of Quality and is ASC’s Technology Expert on Ultra High Density Interconnects. \n3:05 PM – 3:45 PM\nFlex/Rigid-Flex PCBs \nJoe Fjelstad \nFounder/President Verdant Electronics – is an international authority and innovator in the field of electronic interconnection and packaging technologies with more than 185 U.S. patents issued or pending. He is the author of Flexible Circuit Technology and author\, co-author or editor of several other books including Chip Scale Packaging for Modern Electronics. He has also authored numerous technical papers and articles. He frequently presents seminars on PCB\, flex circuit and chip scale packaging technologies at industry conferences. \n4:00 PM – 5:00 PM\nPanel Discussion \nOpen floor for Q & A with all speakers. Any questions not able to fit in can be emailed to marketing@sunstone.com. \n5:00 PM – 10:00 PM \nOptional Bus to Ilani Casino with Casino Bucks – Ridgefield Wa \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tech-summit-asc-sunstone-screaming-circuits/ LOCATION:Holiday Inn Portland – Columbia Riverfront\, 909 North Hayden Island Drive\, Portland\, OR\, 97217\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tech-Summit-April-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T080000 DTEND;TZID=America/Los_Angeles:20240425T114500 DTSTAMP:20240329T165734Z CREATED:20240329T165734Z LAST-MODIFIED:20240329T165734Z UID:7790-1714032000-1714045500@marketingeda.com SUMMARY:AI Driving Fabs of the Future… People\, Technology\, Infrastructure DESCRIPTION:This is an incredibly exciting time for semiconductor manufacturing. After the supply chain disruption in the early 2020s\, companies are rapidly expanding and enhancing operations to meet market demands. Over the next few years\, many new fully automated 300mm fabs will bring major advancements to the industry. Get first-hand information—Join us in person or online. REGISTER TODAY. \nAttend the Pacific Northwest Breakfast Forum hosted at Analog Devices in Beaverton\, Oregon to hear experts discuss— \n\nKEYNOTE: The 5th Industrial Revolution: The Adjacent Possible of AI in Semiconductor Manufacturing—Analog Devices\nMacro Trends and Value Creation in the Semiconductor Industry—McKinsey & Company\nWhat Does It Mean for the Existing 200mm Legacy Fabs?—Microchip Technology\nSEMI Smart Manufacturing Initiative—Microchip Technology\nAI Use Cases in the Fab—Applied Materials\nEXECUTIVE PANEL: Discussion for Talent Acquisition\, Workforce Development\, Labor Shortage\n\nEXPERT SPEAKERS\nKEYNOTE\nDANIEL BURLINGAME\nANALOG DEVICES\n\n\nDAVID HANNY\nAPPLIED MATERIALS\n\n\n\nHENRY MARCIL\nMCKINSEY & COMPANY\n\n\n\nGARY STINSON\nMICROCHIP TECHNOLOGY\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-driving-fabs-of-the-future-people-technology-infrastructure/ LOCATION:Analog Devices\, 14320 SW Jenkins Road\, Beaverton\, OR\, 97005\, United States CATEGORIES:Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-April-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240423T100000 DTEND;TZID=America/Los_Angeles:20240424T123000 DTSTAMP:20240409T163519Z CREATED:20240409T163519Z LAST-MODIFIED:20240409T163519Z UID:7820-1713866400-1713961800@marketingeda.com SUMMARY:osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event DESCRIPTION:osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant and other high-consequence systems. \n‌ \nWe have put together the following program covering a wide range of formal verification topics.\n Day 1 – Tuesday\, April 23 \n\n10:00am Pacific | 1:00pm Eastern\n\nKeynote: Importance of Microelectronics Assurance \nCody Wagner | US Navy CRANE \n\n10:30am Pacific | 1:30pm Eastern\n\nTrusted and Assured Microelectronics Begin Long Before Silicon\nJohn Hallman | Siemens \n\n11:00am Pacific | 2:00pm Eastern\n\nEnverite PV-Bit: Bitstream Verification for FPGA Design Assurance\nDr. Jonathan Graf | Graf Research \n\n11:30am Pacific | 2:30pm Eastern\n\nOptimizing FPGA Equivalence Checking for A&D Designs \nKevin Urish | Siemens \n\nNoon Pacific | 3:00pm Eastern\n\nSupply Chain Traceability and Assurance \nBrett Attaway | Siemens Government Technologies \n‌\n Day 2 – Wednesday\, April 24 \n‌ \n\n10:00am Pacific | 1:00pm Eastern\n\nDecoding Design Mysteries: Revolutionize Your Architectural Insights with \nQuesta Analyze Architecture \nChristopher Diltz | Edaptive \n\n10:30am Pacific | 1:30pm Eastern\n\nEnhanced Assurance for FPGA EDA Tools \nChristopher Clark | GTRI \n\n11:00am Pacific | 2:00pm Eastern\n\nDriving efficient execution with Continuous Integration \nKevin Campbell | Siemens \n\n11:30am Pacific | 2:30pm Eastern\n\nNew AI Horizons in Static & Formal Verification A&D \nDan Yu | Siemens \nIf you have any questions (including whether you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis A&D 2024” keyword in the subject header. \n‌ \nWe look forward to seeing you online! \n‌ \nThe Siemens Formal Verification Team \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/osmosis-aerospace-and-defense-2024-a-formal-verification-virtual-event/ CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240306T100000 DTEND;TZID=Europe/London:20240306T190000 DTSTAMP:20240219T174522Z CREATED:20240219T174522Z LAST-MODIFIED:20240219T174522Z UID:7641-1709719200-1709751600@marketingeda.com SUMMARY:Agile Analog Technology Showcase Event DESCRIPTION:Learn how innovative analog IP can help analog design engineers. \nAgile Analog is transforming the analog IP industry\, with Composa\, our configurable\, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion\, Power Management\, IC Monitoring\, Security and Always-On IPs. Applications include High Performance Computing (HPC)\, IoT\, AI\, automotive and aerospace. \nAnalog IP the way you want it\nWorking with customers across the world on a broad range of technologies\, we partner with all the major foundries. Our customizable\, digitally wrapped and verified solutions can be seamlessly integrated into any SoC\, helping chip designers by significantly reducing complexity\, time and costs. \nTechnology Deep Dive Day\nWe are coming to Scotland to showcase our cutting-edge analog IP technology and expanding product portfolio to electronics engineers in the region\, and to explain how we can simplify analog design and accelerate the integration process.\n‍\nThis event will be an informal and relaxed environment for you to discover how we are revolutionizing the world of analog IP. It’s the ideal opportunity to: \nSee a demo of our Composa technology\nDelve deeper into the finer technical details\nChat with some of our team face-to-face\nEvent Time:\nMorning Session:\n10.00-12.00: Demo & Discussions\n12.00-14.00: Networking Lunch \nAfternoon Session:\n15.00-17.00: Demo & Discussions\n17.00-19.00: Networking Drinks \nEvent Venue:\nThe Royal Society of Edinburgh\nScott Room\,\n22-26 George St\,\nEdinburgh. EH2 2PQ. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/agile-analog-technology-showcase-event/ LOCATION:The Royal Society of Edinburgh\, 22-26 George Street\, Edinburgh\, EH2 2PQ\, United Kingdom CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agile-Analog-6-March-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240226T123000 DTEND;TZID=America/Los_Angeles:20240226T164500 DTSTAMP:20240125T175450Z CREATED:20240125T175450Z LAST-MODIFIED:20240125T175450Z UID:7556-1708950600-1708965900@marketingeda.com SUMMARY:Synopsys Technical Forum 2024 DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-technical-forum-2024/ LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Oslo:20240214T080000 DTEND;TZID=Europe/Oslo:20240215T170000 DTSTAMP:20240209T180613Z CREATED:20240209T180613Z LAST-MODIFIED:20240209T180613Z UID:7599-1707897600-1708016400@marketingeda.com SUMMARY:FPGA Forum 2024 - Norway DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-forum-2024-norway/ LOCATION:Royal Garden\, Trondheim\, Norway CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20231127T100000 DTEND;TZID=Europe/London:20231127T143000 DTSTAMP:20231108T173556Z CREATED:20231108T173556Z LAST-MODIFIED:20231108T173556Z UID:7054-1701079200-1701095400@marketingeda.com SUMMARY:FPGA Frontrunner Meet & Greet DESCRIPTION:The FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda: \n\n\n\n10:00\nArrival and Registration\n\n\n10.30\nPeter Davies\, Thales – Security in FPGA-based Systems\n\n\n11:15\nMark Frost\, Intel – Security in FPGA\n\n\n11:35\nIan Pearson\, Microchip – System and Device Level Security Considerations\n\n\n11:55\nMaximilian Werner\, Efinix Inc – Efinix FPGA Encryption solution\n\n\n12:15\nAnkith Srinivasan & Guests – How and why we use FPGAs in our systems\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet-2/ LOCATION:Thales\, 350 Longwater Avenue\, Reading\, RG2 6GF\, United Kingdom CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-FPGA-November-23-1200x600-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20231115T080000 DTEND;TZID=Asia/Shanghai:20231115T170000 DTSTAMP:20231108T013000Z CREATED:20231108T013000Z LAST-MODIFIED:20231108T013000Z UID:7050-1700035200-1700067600@marketingeda.com SUMMARY:TSMC 2023 Open Innovation Platform Ecosystem Forum - China DESCRIPTION:Join us at the TSMC 2023 China OIP Ecosystem Forum!\nChina OIP Ecosystem Forum (In-Person Event)\nDate: November 15\, 2023 (Wednesday) \nTime: 9:30a.m. – 5:45p.m. \nVenue: Shangri-La Nanjing Hotel \n329 Zhongyang Road\, Gulou District\, Nanjing\, Jiangsu Province\, 210037 China \n  \nChina OIP Ecosystem Forum (Online VOD Event)\nDate: November 22\, 2023 (Wednesday) \nWebsite link to be provided in November. \nLearn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: events@pl-marketing.biz. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-open-innovation-platform-ecosystem-forum-china/ LOCATION:Shangri-La Nanjing Hotel\, 29 Zhongyang Road\, Gulou District\, Nanjing\, China CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-OIP-China.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231113T083000 DTEND;TZID=America/Los_Angeles:20231113T160000 DTSTAMP:20231026T171213Z CREATED:20231026T171213Z LAST-MODIFIED:20231026T171213Z UID:6998-1699864200-1699891200@marketingeda.com SUMMARY:CadenceCONNECT: The Race Is On! DESCRIPTION:Event Overview \n\n\n\n\n\n\n\n\n\n\n\n\nDate: Monday\, November 13\, 2023 \nTime: 8:30am – 4:00pm\, followed by an exclusive networking event \nLocation: Cadence Headquarters\, San Jose\, CA \n\n\n\n\n\n\n\n\n\n\n\n\nThere is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power\, security\, reliability\, and other multifaceted requirements have surpassed the basic performance\, power consumption\, and area constraints of traditional chip design. The race is on to enable traditional automotive companies to enter the new field of automotive electronic chips quickly\, and to improve the performance of established automotive chips to deliver higher and higher computing capabilities while meeting safety and reliability requirements. \n\nJoin Cadence on November 13\, at Cadence headquarters in San Jose\, as we present a new generation of automotive electronics chip design full-flow solutions. Learn about the most recent advancements in the field of automotive chips\, including upcoming technology trends and innovations\, such as autonomous driving to electric vehicles\, functional safety\, reliability of automotive semiconductors\, and more. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nCAE professionals with a background in electrical engineering\, fluid dynamics\, engineering directors and managers\, and engineering team members who work in automotive electronics (SoC) design\, as well as academics and researchers from relevant fields are welcome. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nDesign IP for Automotive SoC Design\n3D-IC Design and Interconnect IP Solution for Chiplet-Based Design\nConfigurable Multi-Core DSP and AI Platform for Automotive Applications\nFMEDA-Driven Safety Analysis and Verification\nSafety-Aware Implementation\nAnalog/Mixed-Signal Safety Verification\nSystem Design and Analysis (EMI\, EMC\, Electrothermal)\nAutomotive CFD Solutions (Aerodynamics\, Aeroacoustics\, HVAC\, Turbo/Pumps\, ​\nThermal Management)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRev Up Your Networks! \n\n\n\n\n\n\n\n\n\n\n\n\n“The race is on!” not just on the circuits\, but also here in the center of our event. Accelerate your knowledge at our seminar and shift your networking into high gear. \nWe’re thrilled to announce that a special guest will be joining us. Be ready to mingle with an elite McLaren Formula 1 driver at our exclusive networking event. Don’t miss this unique opportunity to meet and interact with one of racing’s finest up close and personal. Whether you’re a die-hard F1 fan or simply looking to network with experts in the industry\, this is a pit stop you won’t want to miss! \n\nStay tuned for more information! \n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cadenceconnect-the-race-is-on/ LOCATION:Cadence\, San Jose\, CA\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-13-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231109T090000 DTEND;TZID=America/Los_Angeles:20231109T133000 DTSTAMP:20231027T171914Z CREATED:20231027T171914Z LAST-MODIFIED:20231027T171914Z UID:7001-1699520400-1699536600@marketingeda.com SUMMARY:CHIPS Alliance - FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development DESCRIPTION:IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side\, the concept of package managers is widely used to build a product from many different sources\, but chip designers often rely on ad-hoc solutions which tends to build up a maintenance cost and burden. Fortunately FuseSoC and Edalize exists to help. Being the most popular package manager for IP cores\, there are already hundreds of FuseSoC-compatible IP cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so\, and it is being increasingly used inside small and large companies for development of proprietary systems as well. With support for almost 40 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification. Sounds great\, doesn’t it? It sure does\, and this presentation will take you through the basics of FuseSoC to help you get started\, using VeeRwolf\, the CHIPS Alliance-governed reference platform for the VeeR family of CPU cores as an example\, and looks beyond this to how FuseSoC can help you focus on your core business instead of your cores. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chips-alliance-fusesoc-package-manager-and-build-abstraction-tool-for-fpga-asic-development/ LOCATION:Google\, 237 Moffett Park Drive\, Sunnyvale\, CA\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chips-Alliance-November-9-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20231108T080000 DTEND;TZID=Asia/Taipei:20231108T170000 DTSTAMP:20230913T234027Z CREATED:20230913T234027Z LAST-MODIFIED:20230913T234027Z UID:6800-1699430400-1699462800@marketingeda.com SUMMARY:TSMC 2023 Taiwan OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: events@pl-marketing.biz. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-taiwan-oip-ecosystem-forum/ LOCATION:Ambassador Hotel Hsinchu\, 0F\, No.188\, Sec. 2\, Zhonghua Rd.\, Hsinchu City\, Taiwan CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Denver:20231102T093000 DTEND;TZID=America/Denver:20231102T170000 DTSTAMP:20231019T045430Z CREATED:20231019T045430Z LAST-MODIFIED:20231019T045430Z UID:6972-1698917400-1698944400@marketingeda.com SUMMARY:RISC-V in Space DESCRIPTION:Join us for “RISC-V in… Space” on November 2\, 2023\, as we explore the exciting intersection of RISC-V\, electronics design\, and space! \n\n\n\nAgenda\n\n\n\n\n\n9:30 AM – 10:00 AM \nRegistration & Welcome \n\n\n\n\n10:00 AM – 12:00 PM \nCase Study Presentations: Tenstorrent\, Synopsys\, RISC AI\, Arteris IP \n\n\n\n\n12:00 PM – 1:00 PM \nLunch Buffet \n\n\n\n\n1:00 PM – 3:00 PM \nCase Study Presentations: Breker Systems\, Imperas\, Cycuity\, Codasip \n\n\n\n\n3:00 PM – 5:00 PM \nNetworking Reception with appetizers and refreshments \n\n\n\n\n\n\nAbout this event\n\n\n7 hours\nMobile eTicket\n\n\n\n\nTenstorrent is hosting a meet up in Denver aimed at practitioners and entrepreneurs developing electronic systems and components for space applications. Alongside partners Codasip\, Cycuity\, Breker Systems\, Imperas\, RISC AI\, Synopsys\, and Arteris IP we are excited to invite you to explore with us at the Omni Interlocken Hotel in Broomfield\, CO. \nThrough user-group discussions\, case studies\, and application notes (and steering clear of sales pitches) we’ll explore the exciting sector of space electronics with crucial emphasis on: \n\nArtificial Intelligence & Machine Learning\nEmbedded Processing\nSecurity\nDesign Verification\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-in-space/ LOCATION:Omni Interlocken Hotel\, 5000 Interlocken boulevard\, Broomfield\, CO\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Temstorrent-November-2-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231019T080000 DTEND;TZID=Europe/Berlin:20231019T170000 DTSTAMP:20231017T164930Z CREATED:20231017T164930Z LAST-MODIFIED:20231017T164930Z UID:6963-1697702400-1697734800@marketingeda.com SUMMARY:Samsung Foundry Forum 2023 EMEA DESCRIPTION:We’re inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF & SAFE™ Forum 2023 will be held in several different countries around the world. Check the map below to see where our other forums will be held this year. \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/samsung-foundry-forum-2023-emea/ LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-Foundry-Forum-2023-EMEA.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20231004T080000 DTEND;TZID=Europe/Amsterdam:20231004T170000 DTSTAMP:20230913T233730Z CREATED:20230913T233730Z LAST-MODIFIED:20230913T233730Z UID:6798-1696406400-1696438800@marketingeda.com SUMMARY:TSMC 2023 Europe OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-europe-oip-ecosystem-forum/ LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023.jpg END:VEVENT END:VCALENDAR