BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20210314T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20211107T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20220313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20221106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT 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BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Amsterdam BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20210328T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20211031T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240612T080000 DTEND;TZID=America/Los_Angeles:20240613T170000 DTSTAMP:20240610T171842Z CREATED:20240610T171842Z LAST-MODIFIED:20240610T171842Z UID:8085-1718179200-1718298000@marketingeda.com SUMMARY:Samsung Foundry Forum & SAFE Forum 2024 U.S. DESCRIPTION:June 12th\, 2024\n12:30 – 5:30 PM PDT \n\n\n01:35 – 01:50 PM\nSamsung Keynote\nSiyoung Choi\nPresident and GM\, Foundry Business Samsung Electronics\n\n\n\n\n01:50 – 02:05 PM\nThe Accelerated Compute Platform for the Age of AI\nRene Haas\nCEO\nARM\n\n\n\n\n02:05 – 02:20 PM\nGroq’s Transformation of Generative AI ComputeJonathan RossCEO and Founder\n\n\n\n02:20 – 02:55 PM\nSamsung AI Solutions\nTaeJoong Song\nVP\, Head of Business Development\nIndong Kim\nVP\, Head of DRAM Product Planning\nHee Joung Joun\nVP\, AVP Marketing & Strategy Group\nSamsung Electronics\n\n\n\n\n03:25 – 04:00 PM\nProcess Technology\nJa-Hum Ku\nEVP\, Head of Technology Development\nSamsung Electronics\n\n\n\n04:00 – 04:15 PM\nManufacturing Excellence\nSang Sup Jeong\nEVP\, Head of Foundry Manufacturing Technology Center\nSamsung Electronics\n\n\n\n\n04:15 – 04:30 PM\nDesign Platform\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n04:30 – 04:40 PM\nBusiness & Customers\nSang-Pil Sim\nEVP\, Head of Worldwide Sales and Marketing\nSamsung Electronics\n\nJune 13th\, 2024\n9:00AM-5:30 PM PDT \n\n\n10:00 – 10:15 AM\nWelcome Remarks\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n10:15 – 10:35 AM\nEnabling a New Era of Design\nMike EllowCEO\nSiemens EDA Silicon Systems\n\n\n\n10:35 – 10:55 AM\nDemand for Power Efficiency in the Age of AI\nBill EnCorporate Vice President\nAMD\n\n\n\n\n10:55 – 11:15 AM\nThe Photonic FabricTM\, Optical Compute Interconnect for Accelerated Computing\nDavid Lazovsky\nCEO and Founder\nCelestial AI\n\n\n\n11:15 – 11:35 AM\nTechnology & Business Update\nTaeJoong Song\nVP\, Head of Business Development\nSamsung Electronics\n\n\n\n\n1:00 – 4:30 PM\nTech Session Ⅰ:\nAdvanced Technology and Design Enablement\nSei Seung Yoon\nEVP\, Head of Library Development\nSungwook Moon\nMaster(VP of Technology)\,\nFoundry Design Service\nSamsung Electronics\n\n1:00 – 4:30 PMTech Session Ⅱ:\nDesign Solutions of AI\, for AI\, and by AI\nJongshin Shin\nEVP\, Head of Foundry IP Ecosystem\nSamsung Electronics \n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/samsung-foundry-forum-safe-forum-2024-u-s/ LOCATION:Samsung Semiconductor US Campus\, 3655 N. First Street\, San Jose\, CA\, United States CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-SAFE-2024-US.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240509T173000 DTEND;TZID=America/Los_Angeles:20240509T203000 DTSTAMP:20240328T160417Z CREATED:20240328T160417Z LAST-MODIFIED:20240328T160417Z UID:7787-1715275800-1715286600@marketingeda.com SUMMARY:ESD Alliance CEO/Executive Outlook DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/ LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240502T093000 DTEND;TZID=America/Los_Angeles:20240502T160000 DTSTAMP:20240424T162043Z CREATED:20240424T162005Z LAST-MODIFIED:20240424T162043Z UID:7901-1714642200-1714665600@marketingeda.com SUMMARY:Keysight EDA Connect Tour - Austin DESCRIPTION:Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin\, TX and Burlington\, MA. \nSave the dates for our upcoming events in Austin\, TX on May 2 or Burlington\, MA on May 16\, where we’ll explore the future of AI in 6G to 3D Module integration. \nThese technical sessions promise to recharge your design productivity\, refresh your knowledge base\, and renew contacts with fellow design professionals. \nDon’t miss out on this opportunity to be at the forefront of innovation with Keysight. \nAs AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nLight breakfast and lunch will be provided. \nAgenda\n\n\n\n09:30\nCheck-in & Breakfast\n\n\n10:00\nWelcome – Keynote\n\n\n10:10\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs\n\n\n11:00\nRF System Design / New System Verification Tools in ADS for Circuit Designers\n\n\n12:00\nSolving 3D Module Integration Challenges for High-Performance Microwave Design (Integration is our differentiator)\n\n\n12:45\nRF Switch Design with Keysight ADS\n\n\n1:30-4:00\nLunch Break / Golf\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/keysight-eda-connect-tour-austin/ LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240429T100000 DTEND;TZID=Europe/London:20240429T143000 DTSTAMP:20240322T163227Z CREATED:20240322T163227Z LAST-MODIFIED:20240322T163227Z UID:7746-1714384800-1714401000@marketingeda.com SUMMARY:TechNES FPGA Front Runner Event DESCRIPTION:The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. \nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/technes-fpga-front-runner-event/ LOCATION:New Mills\, Wotton-under-Edge\, GL12 8JR\, United Kingdom CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-29-April-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T111500 DTEND;TZID=America/Los_Angeles:20240425T170000 DTSTAMP:20240411T001153Z CREATED:20240411T001153Z LAST-MODIFIED:20240411T001153Z UID:7836-1714043700-1714064400@marketingeda.com SUMMARY:Tech Summit: ASC Sunstone & Screaming Circuits DESCRIPTION:Calling all PCB designers and engineers to join us for an exclusive Technical Summit and Casino Excursion for Designers & Engineers! \nThis summit is crafted to bring together PCB engineers and technical professionals for a day of immersive learning\, cutting-edge insights\, and many networking opportunities. \nJoin us to expand your knowledge\, establish invaluable connections\, and stay at the forefront of PCB innovation! Dive into the latest advancements\, share knowledge\, and forge meaningful connections within the PCB design and engineering community. \nOnce we have all had a chance to share and digest\, we will board a bus to Ilani Casino for some fun and entertainment! We’ll even have you back at a decent hour so you can be fresh for work on Friday. \n11:15 AM – 11:45 AM \nIntroduction/Box Lunch \nAnaya Vardya \nMatt Stevenson \n\nAnaya – CEO American Standar Circuits/Sunstone Circuits -CEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. Matt Stevenson – VP and General Mgr ASC Sunstone Circuits – has extensive experience in the PCB industry and has proven his skill and dedication to Sunstone by continuing to grow the company’s revenue and enhance the customer experience. \n11:45 AM – 12:30 PM \nBest Practices – PCB Design \nStephen Chavez \n\nSenior Product Marketing Manager – SME PCB Design\, MIT\, CID+\, CPCD – Chairman – Printed Circuit Engineering Association (PCEA) – Steph is a senior printed circuit engineer with three decades’ experience. He spent the past 12 years as a Principal Engineer and global subject matter expert of PCB design for Collins Aerospace (Raytheon Technologies). He is an IPC Certified Master Instructor Trainer (MIT) for PCB design\, an IPC Certified Advanced PCB Designer (CID+)\, and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA) where his focus is on the continuous improvement\, professional development\, and the evolution of the printed circuit engineer throughout the industry. An active IPC member since 2003\, he is currently involved in several subcommittees including specifications IPC-6012\, IPC-2221/2222. Chavez is recognized as an industry subject matter expert in PCB design by PCEA\, IPC\, and several leading industry publications. \n12:35 PM – 1:15 PM \nDFM/DFA\nMike Galloway \nMike Galloway has extensive experience in the electronics manufacturing industry\, specializing in prototype process development with a focus on Surface Mount Technology (SMT). With over 15 years at Screaming Circuits as a Senior Manufacturing Engineer\, he plays a crucial role in prototyping and providing short-run production support. Before joining Screaming Circuits\, Mike built his experience at various Contract Manufacturers (CMs) and Original Equipment Manufacturers (OEMs) as well as working with tooling firms serving the electronics industry. Mike’s expertise lies in optimizing manufacturing processes for prototypes\, particularly in the realm of SMT and scaling into production volumes. \n1:30 PM – 2:10 PM \nThermal Management\nAnaya Vardya \nCEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. He has over a decade of executive management experience in public companies manufacturing PWBs. In addition\, he writes about a variety of subjects but he us particularly focused on partnerships\, technology and manufacturing techniques. \n2:15 PM – 3:00 PM \nUltra HDI\nJohn Johnson \nDirector of Quality at American Standard Circuits – John has a long tenure in Material and Printed Circuit manufacturing. After obtaining an Masters of Science in Organic Chemistry from The Ohio State University\, he has held positions as an R&D Chemist\, Quality Engineer\, Sr. Process Engineer\, Quality Manager\, Sales Rep\, Director of Sales\, General Manager\, President/CEO. Prior to joining ASC as a Director of Business Development\, he was VP of Sales and Customer Support at Averatek Corp and focused on Ultra Fine Line technology. John currently serves as ASC’s Director of Quality and is ASC’s Technology Expert on Ultra High Density Interconnects. \n3:05 PM – 3:45 PM\nFlex/Rigid-Flex PCBs \nJoe Fjelstad \nFounder/President Verdant Electronics – is an international authority and innovator in the field of electronic interconnection and packaging technologies with more than 185 U.S. patents issued or pending. He is the author of Flexible Circuit Technology and author\, co-author or editor of several other books including Chip Scale Packaging for Modern Electronics. He has also authored numerous technical papers and articles. He frequently presents seminars on PCB\, flex circuit and chip scale packaging technologies at industry conferences. \n4:00 PM – 5:00 PM\nPanel Discussion \nOpen floor for Q & A with all speakers. Any questions not able to fit in can be emailed to marketing@sunstone.com. \n5:00 PM – 10:00 PM \nOptional Bus to Ilani Casino with Casino Bucks – Ridgefield Wa \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tech-summit-asc-sunstone-screaming-circuits/ LOCATION:Holiday Inn Portland – Columbia Riverfront\, 909 North Hayden Island Drive\, Portland\, OR\, 97217\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tech-Summit-April-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T080000 DTEND;TZID=America/Los_Angeles:20240425T114500 DTSTAMP:20240329T165734Z CREATED:20240329T165734Z LAST-MODIFIED:20240329T165734Z UID:7790-1714032000-1714045500@marketingeda.com SUMMARY:AI Driving Fabs of the Future… People\, Technology\, Infrastructure DESCRIPTION:This is an incredibly exciting time for semiconductor manufacturing. After the supply chain disruption in the early 2020s\, companies are rapidly expanding and enhancing operations to meet market demands. Over the next few years\, many new fully automated 300mm fabs will bring major advancements to the industry. Get first-hand information—Join us in person or online. REGISTER TODAY. \nAttend the Pacific Northwest Breakfast Forum hosted at Analog Devices in Beaverton\, Oregon to hear experts discuss— \n\nKEYNOTE: The 5th Industrial Revolution: The Adjacent Possible of AI in Semiconductor Manufacturing—Analog Devices\nMacro Trends and Value Creation in the Semiconductor Industry—McKinsey & Company\nWhat Does It Mean for the Existing 200mm Legacy Fabs?—Microchip Technology\nSEMI Smart Manufacturing Initiative—Microchip Technology\nAI Use Cases in the Fab—Applied Materials\nEXECUTIVE PANEL: Discussion for Talent Acquisition\, Workforce Development\, Labor Shortage\n\nEXPERT SPEAKERS\nKEYNOTE\nDANIEL BURLINGAME\nANALOG DEVICES\n\n\nDAVID HANNY\nAPPLIED MATERIALS\n\n\n\nHENRY MARCIL\nMCKINSEY & COMPANY\n\n\n\nGARY STINSON\nMICROCHIP TECHNOLOGY\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-driving-fabs-of-the-future-people-technology-infrastructure/ LOCATION:Analog Devices\, 14320 SW Jenkins Road\, Beaverton\, OR\, 97005\, United States CATEGORIES:Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-April-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240423T100000 DTEND;TZID=America/Los_Angeles:20240424T123000 DTSTAMP:20240409T163519Z CREATED:20240409T163519Z LAST-MODIFIED:20240409T163519Z UID:7820-1713866400-1713961800@marketingeda.com SUMMARY:osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event DESCRIPTION:osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant and other high-consequence systems. \n‌ \nWe have put together the following program covering a wide range of formal verification topics.\n Day 1 – Tuesday\, April 23 \n\n10:00am Pacific | 1:00pm Eastern\n\nKeynote: Importance of Microelectronics Assurance \nCody Wagner | US Navy CRANE \n\n10:30am Pacific | 1:30pm Eastern\n\nTrusted and Assured Microelectronics Begin Long Before Silicon\nJohn Hallman | Siemens \n\n11:00am Pacific | 2:00pm Eastern\n\nEnverite PV-Bit: Bitstream Verification for FPGA Design Assurance\nDr. Jonathan Graf | Graf Research \n\n11:30am Pacific | 2:30pm Eastern\n\nOptimizing FPGA Equivalence Checking for A&D Designs \nKevin Urish | Siemens \n\nNoon Pacific | 3:00pm Eastern\n\nSupply Chain Traceability and Assurance \nBrett Attaway | Siemens Government Technologies \n‌\n Day 2 – Wednesday\, April 24 \n‌ \n\n10:00am Pacific | 1:00pm Eastern\n\nDecoding Design Mysteries: Revolutionize Your Architectural Insights with \nQuesta Analyze Architecture \nChristopher Diltz | Edaptive \n\n10:30am Pacific | 1:30pm Eastern\n\nEnhanced Assurance for FPGA EDA Tools \nChristopher Clark | GTRI \n\n11:00am Pacific | 2:00pm Eastern\n\nDriving efficient execution with Continuous Integration \nKevin Campbell | Siemens \n\n11:30am Pacific | 2:30pm Eastern\n\nNew AI Horizons in Static & Formal Verification A&D \nDan Yu | Siemens \nIf you have any questions (including whether you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis A&D 2024” keyword in the subject header. \n‌ \nWe look forward to seeing you online! \n‌ \nThe Siemens Formal Verification Team \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/osmosis-aerospace-and-defense-2024-a-formal-verification-virtual-event/ LOCATION:TX CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240306T100000 DTEND;TZID=Europe/London:20240306T190000 DTSTAMP:20240219T174522Z CREATED:20240219T174522Z LAST-MODIFIED:20240219T174522Z UID:7641-1709719200-1709751600@marketingeda.com SUMMARY:Agile Analog Technology Showcase Event DESCRIPTION:Learn how innovative analog IP can help analog design engineers. \nAgile Analog is transforming the analog IP industry\, with Composa\, our configurable\, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion\, Power Management\, IC Monitoring\, Security and Always-On IPs. Applications include High Performance Computing (HPC)\, IoT\, AI\, automotive and aerospace. \nAnalog IP the way you want it\nWorking with customers across the world on a broad range of technologies\, we partner with all the major foundries. Our customizable\, digitally wrapped and verified solutions can be seamlessly integrated into any SoC\, helping chip designers by significantly reducing complexity\, time and costs. \nTechnology Deep Dive Day\nWe are coming to Scotland to showcase our cutting-edge analog IP technology and expanding product portfolio to electronics engineers in the region\, and to explain how we can simplify analog design and accelerate the integration process.\n‍\nThis event will be an informal and relaxed environment for you to discover how we are revolutionizing the world of analog IP. It’s the ideal opportunity to: \nSee a demo of our Composa technology\nDelve deeper into the finer technical details\nChat with some of our team face-to-face\nEvent Time:\nMorning Session:\n10.00-12.00: Demo & Discussions\n12.00-14.00: Networking Lunch \nAfternoon Session:\n15.00-17.00: Demo & Discussions\n17.00-19.00: Networking Drinks \nEvent Venue:\nThe Royal Society of Edinburgh\nScott Room\,\n22-26 George St\,\nEdinburgh. EH2 2PQ. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/agile-analog-technology-showcase-event/ LOCATION:The Royal Society of Edinburgh\, 22-26 George Street\, Edinburgh\, EH2 2PQ\, United Kingdom CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agile-Analog-6-March-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240226T123000 DTEND;TZID=America/Los_Angeles:20240226T164500 DTSTAMP:20240125T175450Z CREATED:20240125T175450Z LAST-MODIFIED:20240125T175450Z UID:7556-1708950600-1708965900@marketingeda.com SUMMARY:Synopsys Technical Forum 2024 DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-technical-forum-2024/ LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Oslo:20240214T080000 DTEND;TZID=Europe/Oslo:20240215T170000 DTSTAMP:20240209T180613Z CREATED:20240209T180613Z LAST-MODIFIED:20240209T180613Z UID:7599-1707897600-1708016400@marketingeda.com SUMMARY:FPGA Forum 2024 - Norway DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-forum-2024-norway/ LOCATION:Royal Garden\, Trondheim\, Norway CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20231127T100000 DTEND;TZID=Europe/London:20231127T143000 DTSTAMP:20231108T173556Z CREATED:20231108T173556Z LAST-MODIFIED:20231108T173556Z UID:7054-1701079200-1701095400@marketingeda.com SUMMARY:FPGA Frontrunner Meet & Greet DESCRIPTION:The FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda: \n\n\n\n10:00\nArrival and Registration\n\n\n10.30\nPeter Davies\, Thales – Security in FPGA-based Systems\n\n\n11:15\nMark Frost\, Intel – Security in FPGA\n\n\n11:35\nIan Pearson\, Microchip – System and Device Level Security Considerations\n\n\n11:55\nMaximilian Werner\, Efinix Inc – Efinix FPGA Encryption solution\n\n\n12:15\nAnkith Srinivasan & Guests – How and why we use FPGAs in our systems\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet-2/ LOCATION:Thales\, 350 Longwater Avenue\, Reading\, RG2 6GF\, United Kingdom CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-FPGA-November-23-1200x600-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20231115T080000 DTEND;TZID=Asia/Shanghai:20231115T170000 DTSTAMP:20231108T013000Z CREATED:20231108T013000Z LAST-MODIFIED:20231108T013000Z UID:7050-1700035200-1700067600@marketingeda.com SUMMARY:TSMC 2023 Open Innovation Platform Ecosystem Forum - China DESCRIPTION:Join us at the TSMC 2023 China OIP Ecosystem Forum!\nChina OIP Ecosystem Forum (In-Person Event)\nDate: November 15\, 2023 (Wednesday) \nTime: 9:30a.m. – 5:45p.m. \nVenue: Shangri-La Nanjing Hotel \n329 Zhongyang Road\, Gulou District\, Nanjing\, Jiangsu Province\, 210037 China \n  \nChina OIP Ecosystem Forum (Online VOD Event)\nDate: November 22\, 2023 (Wednesday) \nWebsite link to be provided in November. \nLearn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: events@pl-marketing.biz. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-open-innovation-platform-ecosystem-forum-china/ LOCATION:Shangri-La Nanjing Hotel\, 29 Zhongyang Road\, Gulou District\, Nanjing\, China CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-OIP-China.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231113T083000 DTEND;TZID=America/Los_Angeles:20231113T160000 DTSTAMP:20231026T171213Z CREATED:20231026T171213Z LAST-MODIFIED:20231026T171213Z UID:6998-1699864200-1699891200@marketingeda.com SUMMARY:CadenceCONNECT: The Race Is On! DESCRIPTION:Event Overview \n\n\n\n\n\n\n\n\n\n\n\n\nDate: Monday\, November 13\, 2023 \nTime: 8:30am – 4:00pm\, followed by an exclusive networking event \nLocation: Cadence Headquarters\, San Jose\, CA \n\n\n\n\n\n\n\n\n\n\n\n\nThere is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power\, security\, reliability\, and other multifaceted requirements have surpassed the basic performance\, power consumption\, and area constraints of traditional chip design. The race is on to enable traditional automotive companies to enter the new field of automotive electronic chips quickly\, and to improve the performance of established automotive chips to deliver higher and higher computing capabilities while meeting safety and reliability requirements. \n\nJoin Cadence on November 13\, at Cadence headquarters in San Jose\, as we present a new generation of automotive electronics chip design full-flow solutions. Learn about the most recent advancements in the field of automotive chips\, including upcoming technology trends and innovations\, such as autonomous driving to electric vehicles\, functional safety\, reliability of automotive semiconductors\, and more. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nCAE professionals with a background in electrical engineering\, fluid dynamics\, engineering directors and managers\, and engineering team members who work in automotive electronics (SoC) design\, as well as academics and researchers from relevant fields are welcome. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nDesign IP for Automotive SoC Design\n3D-IC Design and Interconnect IP Solution for Chiplet-Based Design\nConfigurable Multi-Core DSP and AI Platform for Automotive Applications\nFMEDA-Driven Safety Analysis and Verification\nSafety-Aware Implementation\nAnalog/Mixed-Signal Safety Verification\nSystem Design and Analysis (EMI\, EMC\, Electrothermal)\nAutomotive CFD Solutions (Aerodynamics\, Aeroacoustics\, HVAC\, Turbo/Pumps\, ​\nThermal Management)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRev Up Your Networks! \n\n\n\n\n\n\n\n\n\n\n\n\n“The race is on!” not just on the circuits\, but also here in the center of our event. Accelerate your knowledge at our seminar and shift your networking into high gear. \nWe’re thrilled to announce that a special guest will be joining us. Be ready to mingle with an elite McLaren Formula 1 driver at our exclusive networking event. Don’t miss this unique opportunity to meet and interact with one of racing’s finest up close and personal. Whether you’re a die-hard F1 fan or simply looking to network with experts in the industry\, this is a pit stop you won’t want to miss! \n\nStay tuned for more information! \n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cadenceconnect-the-race-is-on/ LOCATION:Cadence\, San Jose\, CA\, United States CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-13-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231109T090000 DTEND;TZID=America/Los_Angeles:20231109T133000 DTSTAMP:20231027T171914Z CREATED:20231027T171914Z LAST-MODIFIED:20231027T171914Z UID:7001-1699520400-1699536600@marketingeda.com SUMMARY:CHIPS Alliance - FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development DESCRIPTION:IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side\, the concept of package managers is widely used to build a product from many different sources\, but chip designers often rely on ad-hoc solutions which tends to build up a maintenance cost and burden. Fortunately FuseSoC and Edalize exists to help. Being the most popular package manager for IP cores\, there are already hundreds of FuseSoC-compatible IP cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so\, and it is being increasingly used inside small and large companies for development of proprietary systems as well. With support for almost 40 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification. Sounds great\, doesn’t it? It sure does\, and this presentation will take you through the basics of FuseSoC to help you get started\, using VeeRwolf\, the CHIPS Alliance-governed reference platform for the VeeR family of CPU cores as an example\, and looks beyond this to how FuseSoC can help you focus on your core business instead of your cores. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chips-alliance-fusesoc-package-manager-and-build-abstraction-tool-for-fpga-asic-development/ LOCATION:Google\, 237 Moffett Park Drive\, Sunnyvale\, CA\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chips-Alliance-November-9-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20231108T080000 DTEND;TZID=Asia/Taipei:20231108T170000 DTSTAMP:20230913T234027Z CREATED:20230913T234027Z LAST-MODIFIED:20230913T234027Z UID:6800-1699430400-1699462800@marketingeda.com SUMMARY:TSMC 2023 Taiwan OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: events@pl-marketing.biz. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-taiwan-oip-ecosystem-forum/ LOCATION:Ambassador Hotel Hsinchu\, 0F\, No.188\, Sec. 2\, Zhonghua Rd.\, Hsinchu City\, Taiwan CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Denver:20231102T093000 DTEND;TZID=America/Denver:20231102T170000 DTSTAMP:20231019T045430Z CREATED:20231019T045430Z LAST-MODIFIED:20231019T045430Z UID:6972-1698917400-1698944400@marketingeda.com SUMMARY:RISC-V in Space DESCRIPTION:Join us for “RISC-V in… Space” on November 2\, 2023\, as we explore the exciting intersection of RISC-V\, electronics design\, and space! \n\n\n\nAgenda\n\n\n\n\n\n9:30 AM – 10:00 AM \nRegistration & Welcome \n\n\n\n\n10:00 AM – 12:00 PM \nCase Study Presentations: Tenstorrent\, Synopsys\, RISC AI\, Arteris IP \n\n\n\n\n12:00 PM – 1:00 PM \nLunch Buffet \n\n\n\n\n1:00 PM – 3:00 PM \nCase Study Presentations: Breker Systems\, Imperas\, Cycuity\, Codasip \n\n\n\n\n3:00 PM – 5:00 PM \nNetworking Reception with appetizers and refreshments \n\n\n\n\n\n\nAbout this event\n\n\n7 hours\nMobile eTicket\n\n\n\n\nTenstorrent is hosting a meet up in Denver aimed at practitioners and entrepreneurs developing electronic systems and components for space applications. Alongside partners Codasip\, Cycuity\, Breker Systems\, Imperas\, RISC AI\, Synopsys\, and Arteris IP we are excited to invite you to explore with us at the Omni Interlocken Hotel in Broomfield\, CO. \nThrough user-group discussions\, case studies\, and application notes (and steering clear of sales pitches) we’ll explore the exciting sector of space electronics with crucial emphasis on: \n\nArtificial Intelligence & Machine Learning\nEmbedded Processing\nSecurity\nDesign Verification\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-in-space/ LOCATION:Omni Interlocken Hotel\, 5000 Interlocken boulevard\, Broomfield\, CO\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Temstorrent-November-2-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231019T080000 DTEND;TZID=Europe/Berlin:20231019T170000 DTSTAMP:20231017T164930Z CREATED:20231017T164930Z LAST-MODIFIED:20231017T164930Z UID:6963-1697702400-1697734800@marketingeda.com SUMMARY:Samsung Foundry Forum 2023 EMEA DESCRIPTION:We’re inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF & SAFE™ Forum 2023 will be held in several different countries around the world. Check the map below to see where our other forums will be held this year. \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/samsung-foundry-forum-2023-emea/ LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-Foundry-Forum-2023-EMEA.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20231004T080000 DTEND;TZID=Europe/Amsterdam:20231004T170000 DTSTAMP:20230913T233730Z CREATED:20230913T233730Z LAST-MODIFIED:20230913T233730Z UID:6798-1696406400-1696438800@marketingeda.com SUMMARY:TSMC 2023 Europe OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-europe-oip-ecosystem-forum/ LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230927T090000 DTEND;TZID=America/Los_Angeles:20230927T170000 DTSTAMP:20230920T165423Z CREATED:20230913T232432Z LAST-MODIFIED:20230920T165423Z UID:6795-1695805200-1695834000@marketingeda.com SUMMARY:TSMC 2023 North America OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N2\, N3/N3E/N3P/N3AE\, N4/N4P\, N5/N5A\, N6/N6e/N6RF/N7\, N12e\, and N22\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem specific TSMC reference flow implementations\, P&R optimization\, machine learn-ing to improve design quality and productivity\, and cloud-based design solutions\nSuccessful \, real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2023-north-america-oip-ecosystem-forum/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230627T080000 DTEND;TZID=America/Los_Angeles:20230628T170000 DTSTAMP:20230620T180630Z CREATED:20230620T180400Z LAST-MODIFIED:20230620T180630Z UID:6541-1687852800-1687971600@marketingeda.com SUMMARY:SFF & SAFE™ Forum 2023 San Jose\, CA DESCRIPTION:Day 1 June 27th\, 2023\n\n\n\n\n12:00 – 1:00pm PDT\nNetworking Lunch & Registration\n\n\n\n\n1:00 – 1:05pm PDT\nOpening\nJinman Han\nEVP\, Head of DSA Office\,\nSamsung Electronics\n\n\n\n\n1:05 – 1:20pm PDT\nSamsung Keynote\nSiyoung Choi\nPresident and GM\, Foundry Business\,\nSamsung Electronics\n\n\n\n\n1:20 – 1:35pm PDT\nAn Energy Efficient Future of AI\nJoe Macri\nSVP\, CTO of Computing & Graphics\,\nAMD\n\n\n\n\n1:35 – 1:50pm PDT\nMeeting System User Demands in a Slowing Moore’s Law Era\nChidi Chidambaram\nFellow\, Technology and Foundry Engineering\, Qualcomm\n\n\n\n\n1:50 – 2:05pm PDT\nBreak\n\n\n\n\n2:05 – 2:35pm PDT\nProcess Technology\nGitae Jeong\nEVP\, Head of Technology Development\,\nSamsung Electronics\nOhkyum Kwon\nVP\, Head of 8-inch Manufacturing Technology Team\,\nSamsung Electronics\n\n\n\n\n2:35 – 2:50pm PDT\nManufacturing Excellence\nSang Sup Jeong\nEVP\, Head of Foundry Manufacturing Technology Center\,\nSamsung Electronics\n\n\n\n\n2:50 – 3:10pm PDT\nDesign Platform\nJongwook Kye\nEVP\, Head of Foundry Design Platform Development\,\nSamsung Electronics\n\n\n\n\n3:10 – 3:25pm PDT\nSustainability\nClaire Hyun\nJung Seo\nVP\, DS Corporate Sustainability Management Office\,\nSamsung Electronics\n\n\n\n\n3:25 – 3:40pm PDT\nBreak\n\n\n\n\n3:40 – 3:55pm PDT\nRiscV\, AI and the Next Generation of Compute\nJim Keller\nPresident and CEO\,\nTenstorrent\n\n\n\n\n3:55 – 4:15pm PDT\nAdvanced Heterogeneous Integration\nMoonSoo Kang\nEVP\, Head of AVP Business Team\,\nSamsung Electronics\n\n\n\n\n4:15 – 4:35pm PDT\nBusiness & Customers\nSang-Pil Sim\nEVP\, Head of Foundry Worldwide Sales and Marketing\,\nSamsung Electronics\n\n\n\n\n4:35 – 4:40pm PDT\nClosing\nMarco Chisari\nEVP\, Head of U.S. Foundry and SSIC\,\nSamsung Electronics\n\n\n\n\n4:40 – 5:30pm PDT\nPartner Pavilion & Networking\n\nDay 2 June 28th\, 2023\n\n\n\n\n9:00 – 10:00am PDT\nRegistration\n\n\n\n\n10:00 – 10:05am PDT\nOpening\nJinman Han\nEVP\, Head of DSA Office\,\nSamsung Electronics\n\n\n\n\n10:05 – 10:15am PDT\nWelcoming Remarks\nJongwook Kye\nEVP\, Head of Foundry Design Platform Development\,\nSamsung Electronics\n\n\n\n\n10:15 – 10:35am PDT\nThe 3Ps of 3D-ICs\nAjei Gopal\nPresident and CEO\,\nAnsys\n\n\n\n\n10:35 – 10:55am PDT\nUnleashing a New Era of Compute with Chiplet-Powered Silicon\nTony E. Pialis\nPresident and CEO\,\nAlphawave Semi\n\n\n\n\n10:55 – 11:15am PDT\nHigh-Performance Design in Samsung Foundry\nLeon Stok\nVP\, EDA\, IBM Infrastructure\,\nIBM\n\n\n\n\n11:15 – 11:35am PDT\nSamsung Foundry Process & Business Update\nGibong Jeong\nEVP\, Head of Foundry Business Development Team\,\nSamsung Electronics\n\n\n\n\n11:35 – 12:45pm PDT\nLunch\n\n\n\n\n12:45 – 1:00pm PDT\nBreak\n\n\n\n\n1:00 – 4:15pm PDT\nTech Session I: Advanced Technology and Design Infrastructure\nSangyun Kim\n(Tech Talk) VP\, Head of Foundry Design Technology Team\,\nSamsung Electronics\nSynopsys\, ARM\, ADTechnology\, Cadence\, Ansys\n\n\n\n\n1:00 – 4:15pm PDT\nTech Session II: Advanced Design Solutions for HPC and Automotive\nJongshin Shin\n(Tech Talk) EVP\, Head of Foundry IP Ecosystem\,\nSamsung Electronics\nCadence\, Alphawave\, Samsung AVP\, CoAsia\, Siemens\, Synopsys\, SemiFive\n\n\n\n\n4:15 – 4:30pm PDT\nClosing\nMarco Chisari\nEVP\, Head of U.S. Foundry and SSIC\,\nSamsung Electronics\n\n\n\n\n4:30 – 5:30pm PDT\nPartner Pavilion & Networking\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/sff-safe-forum-2023-san-jose-ca/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:EDA,Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAFE-San-Jose-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20230614T080000 DTEND;TZID=Europe/Berlin:20230615T170000 DTSTAMP:20230612T171200Z CREATED:20230313T202424Z LAST-MODIFIED:20230612T171200Z UID:6114-1686729600-1686848400@marketingeda.com SUMMARY:GSA 2023 European Executive Forum DESCRIPTION:Dealing with Uncertainty\nThe global economy is sending mixed messages\, and with every new data release comes a new batch of upbeat or defeatist headlines. \nUncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in years\, on the other all major tech companies have announced significant layoffs.  The chip shortage is not over yet in some segments\, but in some others there is excess supply. Our new multipolar world order will enforce structural changes to the economy\, such as the need to rebuild reliable supply chains closer to home\, which often comes at higher prices. \nDespite these uncertainties\, innovation in our industry remains as strong as ever\, with relentless growth driven by automotive\, 5G and next generation connectivity\, new silicon design paradigms including RISC-V and chiplets\, big trends towards decarbonization and new materials like SiC\, the positive effects of increased diversity and inclusion. And large amounts of government money is made available globally to support this growth\, through “chips acts” and “green deals”. \nThere is therefore a strong belief that tech innovation and growth will continue to prevail and\, with a little more positive international cooperation\, deal with the apparent challenges altogether. \n\n\n\n\n\n\n\n\n\n\nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: close to 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region. \n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/gsa-2023-european-executive-forum/ LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany CATEGORIES:EDA,Forum,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-14-15-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20230329T084500 DTEND;TZID=Asia/Kolkata:20230329T164500 DTSTAMP:20230317T205939Z CREATED:20230317T205939Z LAST-MODIFIED:20230317T205939Z UID:6189-1680079500-1680108300@marketingeda.com SUMMARY:Siemens Tessent DFT Forum 2023 India DESCRIPTION:About Siemens Tessent DFT Forum 2023 India\nPresenting silicon lifecycle solutions from Siemens EDA:  Engineering a smarter future faster \nJoin us for the Siemens Tessent Design-for-Test (DFT) India Tech Forum\, being held in Hotel Radisson Blu\, Marathalli ORR\, Bengalur India\, on 29th March\, 2023 learn from Industry leaders\, fellow designers and experts from Siemens about how to leverage the Tessent Platform to address your Design-for-Test challenges while solving more complex challenges. \nThe in-person forum will focus on EDA silicon lifecycle solutions\, allowing you to Engineer a Smarter Future Faster with Siemens EDA. \nWith multi-billion transistor instances\, design complexity is increasing ever so rapidly\, and Industry has to mitigate with smart solutions that are highly efficient\, automatable & future proof. Siemens EDA is actively delivering new solutions and use models that enable our customers to deliver innovations to market smartly and efficiently. \nThis event is your opportunity to hear Siemens EDA Tessent experts discuss how to get the most from the Tessent design-for-test platform. Hear about the latest tool features to improve DFT efficiency\, save test time\, and deploy IP for in-life monitoring. \nSlots are limited to maximize your learning experience\, submit your registration immediately to request your spot today. \nA place to connect\nExclusive event for our executive and global community to share strategies on how they are transforming their organization’s business process\, products\, and industry through digitalization.​ \nWhat will you learn\nHow is Industry solving chiplet\, 2.5D & 3D challenge with Tessent Multi-die. \nHow Tessent solutions are catering to stringent needs of Automotive\, safety & security.   \nHow to turbo charge your network access throughput with Fast IJTAG. \nHow Tessent DFT for tiling designs saving weeks of engineering effort & benefiting backend flows. \nHow Streaming Scan Network is transforming scan delivery & how the industry is leveraging packetized test in their next designs. \nAccess to a wealth of content on Tessent DFT\nThe opportunity to meet peers and Siemens Tessent & Design for Test(DFT) experts to address and resolve strategic opportunities and tactical barriers.​ \nDesign Engineers and Experts from around the Globe come together to learn how to improve the DFT experiences and capabilities.​ \nWhat to expect?\nAn exclusive\, unique experience to understand about the latest Design for Test techniques besides listening to leading experts who are leading the change in the Industry. \n  \n\nExecutive-level concentrated agenda on the digital future\nIndustry leaders presenting Design for Test use cases\nInnovation leaders sharing business challenges and roadblocks\nContent demonstrating business results\nProven strategies for successful business transformation\n\n… and more than 6 hours of networking with like-minded peers! \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/siemens-tessent-dft-forum-2023-india/ LOCATION:Hotel Radisson Blu\, Marathalli ORR\, Bengaluru\, India CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessent-March-29-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20230316T083000 DTEND;TZID=America/Los_Angeles:20230316T113000 DTSTAMP:20230217T231519Z CREATED:20230217T231519Z LAST-MODIFIED:20230217T231519Z UID:6002-1678955400-1678966200@marketingeda.com SUMMARY:Semiconductor Outlook: Navigating Through Turbulent Times and the Impact of the Recession DESCRIPTION:Businesses across the globe faced a host of new challenges during the recent pandemic. As the pandemic wanes\, we are now faced with recession as high inventories and low demand could mean trouble for semiconductor chip manufacturers. \nJoin us to hear industry leaders and market experts discuss the outlook and the impact on semiconductor design and manufacturing supply chain in the near and long term\, including regional and global economies\, and the Chips Act. \nSpeakers will discuss strategies for mitigating the impact and how to capture value. \nTopics include: \n\nMarket Trends & Forecast & Outlook\nAccessing Chips Act Funding and Roll out of Incentives\nGeopolitical Impact\nAdvanced Packaging & Chiplets\nEmerging and Expanding Markets\n\n  \nThis Virtual Forum is 8:30–11:00am Pacific Time\, 11:30am–2:00pm Eastern Time \nAGENDA\n\nVirtual Forum | Thursday\, March 16\, 2023 | Pacific Time\n\n\n8:30 am – 8:35 am\n\n\n\nEd Sperling\nEditor-in-Chief\nSemiconductor Engineering\n\n\n\nWelcome Remarks\n\nBiography \n\n\n\n\n\n8:35 am – 8:55 am\n\n\n\nJohn Cooney\nVice President\, Global Public Policy & Advocacy\nSEMI\n\n\n\nAn Update on the CHIPS Act and How to Apply for Funding\n\nBiography \n\n\n\n\n\n8:55 am – 9:20 am\n\n\n\nJay Vleeschhouwer\nSoftware Research\nGriffin Securities\n\n\n\nThe State of EDA: A View from Wall Street\n\nBiography \n\n\n\n\n\n9:20 am – 9:45 am\n\n\n\nDan Hutcheson\nVice Chair\nTechInsights\n\n\n\nNew Perspectives in Semiconductors: Cycles & Outlooks\n\nBiography \n\n\n\n\n\n9:45 am – 10:10 am\n\n\n\nJean-Christophe Eloy\nPresident and CEO\nYole Développement\n\n\n\nStatus of the Advanced Packaging Industry: How the Chiplet Revolution is Impacting the Industry?\n\nBiography \n\n\n\n\n\n10:10 am – 10:35 am\n\n\n\nPaul McLellan\nEditor of Breakfast Bytes\nCadence\n\n\n\nThree Things to Watch: 3DIC\, Supply Chain Disaggregation\, and Intel\n\nBiography \n\n\n\n\n\n10:35 am – 10:55 am\n\n\n\nLita Shon-Roy\nPresident/CEO\nTECHCET\n\n\n\nThe Impact on Supply-Chains – Materials & Equipment Consumables\n\nBiography \n\n\n\n\n\n10:55 am – 11:00 am\n\n\n\nEd Sperling\nEditor-in-Chief\nSemiconductor Engineering\n\n\n\nClosing Remarks\n\nBiography \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/semiconductor-outlook-navigating-through-turbulent-times-and-the-impact-of-the-recession/ LOCATION:TX CATEGORIES:EDA,Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-March-16-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20221129T120000 DTEND;TZID=Europe/London:20221129T133000 DTSTAMP:20221117T175858Z CREATED:20221117T175811Z LAST-MODIFIED:20221117T175858Z UID:5415-1669723200-1669728600@marketingeda.com SUMMARY:RISC-V Verification Strategies DESCRIPTION:With the popularity of the RISC-V open architecture\, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC. \n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction\nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve\n\n\n\n\n12.05 GMT\nRISC-V processor verification with new open standard RVVI based methodology\nSimon Davidmann\, Imperas Software\n\n\n\n\n12.25 GMT\nRISC-V Verif Generators : A Configurable ISA warrants a Configurable Verification Environment\nDr. Neel Gala\, InCore Semiconductors Pvt. Ltd.\n\n\n\n\n12.45 GMT\nRISC-V SoC integration verification including system coherency. Is your RISC-V SoC-ready?\nJohn Sotiropoulos\, Breker Verification Systems Inc\n\n\n\n\n13.05 GMT\nCORE-V-VERIF: an open-source SV/UVM environment for RISC-V cores\nMike Thompson\, OpenHW Group\n\n\n\n\n13.25 GMT\nClosing Remarks\n\n\n\n\n13.30 GMT\nClose\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-verification-strategies/ LOCATION:TX CATEGORIES:EDA,Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2022.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20221108T090000 DTEND;TZID=Europe/Amsterdam:20221108T180000 DTSTAMP:20221104T201045Z CREATED:20221104T201045Z LAST-MODIFIED:20221104T201045Z UID:5373-1667898000-1667930400@marketingeda.com SUMMARY:TSMC 2022 EU OIP Ecosystem Forum DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2022-eu-oip-ecosystem-forum/ LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands CATEGORIES:Forum,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2022-EU.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20221103T080000 DTEND;TZID=America/Los_Angeles:20221103T113000 DTSTAMP:20221013T202008Z CREATED:20221013T202008Z LAST-MODIFIED:20221013T202008Z UID:5306-1667462400-1667475000@marketingeda.com SUMMARY:THE FUTURE OF MORE THAN MOORE—Chiplets\, Advanced Packaging\, and More DESCRIPTION:Presented by the SEMI\nPacific Northwest and Silicon Valley Chapters \nHow can we extend Moore’s Law and drive new capabilities in the More than Moore era? The answer lies in the technology\, economics\, and new opportunities in the semiconductor supply chain. \nJoin us at the Forum on Thursday\, November 3\, 2022\, 8–11:30am Pacific Time to hear industry experts explore the Future of More Than Moore. The event is In-Person\, Virtual\, and On-Demand for your convenience. \nSpeakers\nASE\nMark Gerber\nSr. Director\, Engineering & Technical Marketing \nAdvanced Packaging: Enabling a New Generation of Silicon Systems\n\n\nFORMFACTOR\nAmy Leong\nSVP\, CMO\, GM Emerging Growth/M&A \nStrategy for Wafer Probe in a Chiplet World \nGARTNER\nBob Johnson\nVice President\,\nAnalyst \nSemiconductor Market Outlook: Change in the Midst of Uncertainty \n\nGOOGLE\nMartin Dixon\nDirector of\nEngineering \n[KEYNOTE] Open Chiplets to Enable a New Era of Silicon\n\n\nINTEL CORPORATION\nMartha Dudek\, PhD\nSr. Director\, Assembly Materials Global Supply Chain \n[KEYNOTE] Material Supply Chain Innovations for Advanced Packaging \n\n\n\nBIAMP SYSTEMS\nJoe Andrulis\nExecutive Vice President\,\nCorporate Development \n[HOST] Welcome &\nTour of Biamp \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/the-future-of-more-than-moore-chiplets-advanced-packaging-and-more/ LOCATION:Biamp Systems\, 9300 SW Gemini Dr.\, Beaverton\, OR\, United States CATEGORIES:Forum,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-November-3-2022.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20221026T090000 DTEND;TZID=America/Los_Angeles:20221026T183000 DTSTAMP:20221013T003013Z CREATED:20221013T003013Z LAST-MODIFIED:20221013T003013Z UID:5303-1666774800-1666809000@marketingeda.com SUMMARY:TSMC 2022 OIP - California DESCRIPTION:Join the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! \nRegister Now\n\n\n\n\nLearn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum! \nYour health and safety are important to us. TSMC continues to monitor guidelines for health safety measures from the Centers for Disease Control and Prevention\, California Department of Public Health\, and the Santa Clara County Department of Public Health. TSMC will follow applicable federal\, state and local laws\, then adapt TSMC plans accordingly and share updates with you. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2022-oip-california/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,Forum,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-OIP-2022-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20221003T080000 DTEND;TZID=America/Los_Angeles:20221004T170000 DTSTAMP:20220831T201004Z CREATED:20220831T201004Z LAST-MODIFIED:20220831T201004Z UID:5157-1664784000-1664902800@marketingeda.com SUMMARY:Samsung Foundry Forum & SAFE Forum 2022 - US DESCRIPTION:Through the various session programs\, clients\, partners\, and experts in each field will be able to meet again in person and prepare to go forth into the new future of the semiconductor market. \n  \nThe 2022 Samsung Foundry Forum and SAFE Forum are in-person events\, and will be held in San Jose in the U.S.\,Munich in Germany\, Tokyo in Japan\, and Seoul in South Korea. Check the locations for each event.※ Guests from China will be provided online access to the SFF & SAFE Forum 2022 starting October 21. \n  \nIntroducing the partners of Samsung Foundry’s reinforced SAFE ecosystem. Don’t miss the opportunity to expand your knowledge and gain innovative inspiration by networking with our various partners. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/samsung-foundry-forum-safe-forum-2022-us/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Forum,Foundry ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-October-03-04-2022.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20220927T080000 DTEND;TZID=America/Los_Angeles:20220927T170000 DTSTAMP:20220705T205605Z CREATED:20220705T205605Z LAST-MODIFIED:20220705T205605Z UID:4906-1664265600-1664298000@marketingeda.com SUMMARY:U.S. Executive Forum DESCRIPTION:The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park\, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it’s too late. \nIn this unique and exclusive gathering\, thought leaders\, visionaries and innovators will shed light on the leadership role that the semiconductor industry must embrace to lead the world to a brighter future. Our program features some of the biggest names in semis fostering discussions on the industry’s most pressing issues. We hope you’ll join us at USEF 2022 for a day of leadership\, networking and enrichment. \nTraditionally\, even as semiconductors have been at the core of technological innovation and have changed the world beyond any other technology\, they have often been seen as a commodity and rarely in the spotlight or getting noticed. \nThis has all changed with the acceleration of digital transformation across industries and digitalization of work and life styles. Semiconductors are enabling new technologies and applications\, such as AI and IoT\, that have sparked a new wave of innovation for the industry. \nIn addition\, the implementation of 5G networks coincides with the growing demand for faster high-performance computing devices in the cloud and at the edge. \nIt is time for the industry to step up and show leadership in not only the technology field but also as a responsible global industry in areas of social impact. Climate change\, digital inequality\, diversity\, are all areas that the industry impacts and can show leadership in change. \nIn this unique and exclusive gathering\, thought leaders\, visionaries\, and innovators will shed light on the leadership role that the semiconductor industry needs to embrace and lead the world for a brighter future. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/u-s-executive-forum/ LOCATION:TX CATEGORIES:EDA,Forum,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA.-September-27-2022.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20220914T080000 DTEND;TZID=America/Los_Angeles:20220916T170000 DTSTAMP:20220724T164508Z CREATED:20220724T164508Z LAST-MODIFIED:20220724T164508Z UID:4954-1663142400-1663347600@marketingeda.com SUMMARY:Forum on Specification and Design Languages DESCRIPTION:FDL is a well-established international forum to exchange experiences and promote new trends in the application of languages\, their associated design methods\, and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. \nThe program structure includes research working sessions\, embedded tutorials\, panels\, and technical discussions. The forum includes tutorials and fringe meetings\, such as user group or standardization meetings. “Wild and Crazy Ideas” and work in progress are also welcome. \nElectronic systems of interest to FDL include (but are not limited to) those that are used in internet-of-things (IoT)\, cyber-physical systems (CPS)\, mixed criticality embedded systems\, embedded systems for high-performance computing\, automatic driving and driver assistance\, real-time systems\, reconfigurable and secure computing. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/forum-on-specification-and-design-languages/ LOCATION:LIT Open Innovation Center\, Altenberger Str. 69\, Linz\, 4040\, Austria CATEGORIES:Forum ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/687BCA82-7F03-47F4-A206-8749F26F6C2B.jpeg END:VEVENT END:VCALENDAR