BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20260308T100000 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TZNAME:HKT DTSTART:20240101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Paris BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT 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TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Stockholm BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250319T080000 DTEND;TZID=America/Los_Angeles:20250320T170000 DTSTAMP:20241220T215313Z CREATED:20241220T215313Z LAST-MODIFIED:20241220T215313Z UID:8694-1742371200-1742490000@marketingeda.com SUMMARY:SNUG Silicon Valley 2025 DESCRIPTION:Connecting the Synopsys User Community\n\n\n\n\n\n\n\n\n\n\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2025 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nWe are thrilled to announce that SNUG Silicon Valley is celebrating its 35th year of innovation\, and we invite you to be a part of this milestone event. Have you used Synopsys technology to overcome difficult design issues or tackle one of those key challenges facing the industry? We’d like to hear from you! Showcase your work and share your experience with the community by submitting your proposal through the call for content process. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/snug-silicon-valley-2025/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Silicon-Valley-2025.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250129T130000 DTEND;TZID=Europe/London:20250129T173000 DTSTAMP:20241220T033019Z CREATED:20241220T033019Z LAST-MODIFIED:20241220T033019Z UID:8642-1738155600-1738171800@marketingeda.com SUMMARY:DVClub Europe - Mixed Signal Verification DESCRIPTION:Analog mixed signal chips continue to grow in both demand and complexity\, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the University of Edinburgh and the university students will be attending. The first half of the DVClub will focus concepts of digital and analog verification\, as well as an overview of the work the university is doing on AI in semiconductors through the APRIL hub\, focusing on the verification activities. \nIn the second half of this DVClub\, local companies will focus on challenges and solutions for mixed signal verification at SoC\, system and in safety-related applications. \nAgenda (GMT) \n13.00: Arrival and Registration with Coffee and Snacks \n\nmainly for students but local companies also welcome\n\n13:25: Mike: Welcome \n13.30: Introduction from the University \n14.00: Mike – Introduction to Digital Verification \n14:30: Peter/Graeme – Mixed Signal Verification Part I \n15.00: Break – Coffee and Snacks \n\n Delegates can also attend for 2nd half only if preferred\n\n15:30: Peter/Graeme – Mixed Signal Verification II \n16:00: Michael O’Sullivan & Marcel Ahmedzai\, Cadence Design Systems – SoC Verification \n16:30: System and Safety Verification: (TBC) \n17:00: Mike: wrap up and next steps for students/local companies to collaborate \n17:10: Drinks and Pizza\n \nAdditional Information\nFor additional information please visit the Tessolve DVClub webpage for this event. \nSponsors\nDVClub Europe\, Edinburgh is made possible through the generous support of our sponsors:  Cadence\, Partner: TechWorks \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvclub-europe-mixed-signal-verification/ LOCATION:Edinburgh City Centre\, Edinburgh\, United Kingdom CATEGORIES:EDA,Forum,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-29-January-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20250123T100000 DTEND;TZID=Asia/Tokyo:20250123T170000 DTSTAMP:20241217T174422Z CREATED:20241217T174422Z LAST-MODIFIED:20241217T174422Z UID:8611-1737626400-1737651600@marketingeda.com SUMMARY:Silvaco UseRs Global Event - Japan\, 2025 DESCRIPTION:SURGE (Silvaco UseRs Global Event) is a worldwide event held by Silvaco.\nSURGE is an event for discussing new technologies\, sharing user experiences\, and discovering innovative techniques for advanced semiconductor design in the fields of TCAD\, EDA\, and IP. The event will be held online. We look forward to your participation.\n\n\nWe will randomly select 8 lucky winners from those who participate on the day and fill out the questionnaire to receive a special prize.\n(Domestic shipping only.)\n\nPlease take this opportunity to register for SURGE Japan.\n\n\n\n\n\n\n\nDistribution : Online\ndistribution service : Zoom Meeting\nParticipation fee : Free\nLanguage : English \nAfter you register\, you will receive a notification email. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15 AM\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15 AM\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna\n\n\n11:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45 AM\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco\n\n\n12:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco\n\n\n12:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n1:00 PM\nLUNCH BREAK\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)\n\n\n2:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco\n\n\n2:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n2:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n3:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n3:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra\n\n\n3:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco\n\n\n4:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n4:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco\n\n\n4:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/silvaco-users-global-event-japan-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250121T100000 DTEND;TZID=Europe/London:20250121T170000 DTSTAMP:20241217T174512Z CREATED:20241217T174109Z LAST-MODIFIED:20241217T174512Z UID:8609-1737453600-1737478800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - EMEA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 21\, 2025. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45M\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n11:30\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n12:05\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n12:25\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n13:00\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n14:00\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n14:20\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n14:40\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n15:00\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n15:15\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n15:35\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n16:00\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n16:20\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n16:35\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/silvaco-users-global-event-emea-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250121T080000 DTEND;TZID=America/Los_Angeles:20250123T170000 DTSTAMP:20240723T220633Z CREATED:20240723T220210Z LAST-MODIFIED:20240723T220633Z UID:8174-1737446400-1737651600@marketingeda.com SUMMARY:Chiplet Summit 2025 DESCRIPTION:Position Your Company as a Leader in an Emerging Technology.  Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia).  Share Thoughts with Key Experts and Analysts.  Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. \n\nOnly event totally dedicated to the skyrocketing chiplet market\nTop experts\, major keynotes\, and critical topics will draw big-time customers\nPractical orientation will attract key designers and specifiers\nVendor-neutral show offers opportunities to everyone\n\nThe third annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. \nThey’ll get the scoop on ways to make their chiplets run faster\, scale better\, use less power\, and be more flexible. \nThis unique event gives attendees a place to network with peers\, ask questions of the experts\, and talk to vendors offering a wide variety of products and services. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplet-summit-2025/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chiplet-Summit-2025-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Hong_Kong:20250117T130000 DTEND;TZID=Asia/Hong_Kong:20250117T170000 DTSTAMP:20241217T174747Z CREATED:20241217T173838Z LAST-MODIFIED:20241217T174747Z UID:8606-1737118800-1737133200@marketingeda.com SUMMARY:Silvaco UseRs Global Event - China\, 2025 DESCRIPTION:We sincerely invite you to attend the annual Silvaco Global User Conference – SURGE. This year’s SURGE China will be held online from 13:00 to 17:00 Beijing time on Friday\, January 17\, 2025. \nSURGE aims to provide a sustainable learning and exchange platform for global customers to share the latest technologies and user experience in the fields of TCAD\, EDA and IP\, and explore innovative technologies for advanced semiconductor design. \nLucky Draw: \nThe event has a lucky draw session\, and we have carefully prepared prizes. All users participating online have the chance to win! \n\n\nEvent Schedule\n\n\n\n\n\n\n\ntime\nMain venue\n\n\n13:00\nCEO Speech – Babak Taheri\, Silvaco\, CEO and Board Member​\n\n\n13:15\nHow AI will take EDA to new heights – Wally Rhines\, President and CEO of Cornami\, Board Member of Silvaco\n\n\n13:30\nSpeech Topic – Sumeet Pandey\, Micron Technologies\n\n\n13:45\nLucky draw and rest\n\n\n\n\n\n\ntime\nSemiconductor Process and Devices Session\n\n\n14:15\nTCAD Update – Dr. Eric Guichard\, Silvaco Vice President and General Manager of TCAD Division\n\n\n14:30\nStudying Low-Temperature Properties of Nanowire Transistors with Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n14:45\nMachine Learning for Multiscale Plasma Process Integration and Optimization – Dr. Lado Filipovic\, Associate\n\n\n15:00\nSpeech topic – Dr. Gao Peixiong\, CanSemi\, TCAD Simulation Manager\n\n\n15:15\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Application Engineer\n\n\n15:35\nPhysics and AI-based digital twins to accelerate SiC power device design optimization and manufacturing – Dr. David Green\, Silvaco\n\n\n15:55\nPower Device SPICE Modeling – Study on SiC DMOS Parameter Extraction Method – Dr. Bogdan Tudor\, Silvaco\, Modeling Leader​\n\n\n16:15\nEDA Solutions for Power Device Physical Design – Stefano Pettazzi\, Silvaco\, Application Engineer\n\n\n16:30\nLucky Draw and Closing\n\n\n\n\n\n\ntime\nIC Design Session\n\n\n14:15\nEDA and IP Updates – Dan Fitzpatrick\, Silvaco\, Vice President and General Manager of the EDA Division – Ben Louie\, Silvaco\, Vice President and General Manager\n\n\n14:35\nJivaro Pro Advanced Parasitic Reduction – Silicon Creation​\n\n\n14:55\nUsing Viso to Explore\, Analyze\, and Solve Advanced Parasitic Problems – Carlos Berlitz\, Applications Engineer\, Silvaco\n\n\n15:10\nChallenges and Improvements in Characterization of Standard Cell Libraries – Siti Mariyam\, Senior IP Engineer\n\n\n15:30\nLow Voltage Standard Cell Library Design at 3nm – Fernando Carrion\, Silvaco\, R&D Engineer\n\n\n15:55\nAdvanced Node Cell Library Development Using Cello FinFET – Felipe Bortolon\, Silvaco\, Engineering Manager​\n\n\n16:15\nLDO and Bandgap Benchmarks for Low Voltage Design – Ahmad S. Mazumder\, Shaikh A Shams\, Silvaco\n\n\n16:30\nIntroduction to CAN-XL Automotive Bus IP – Mauricio Brochi\, Silvaco\, Director of Automotive IP\n\n\n16:45\nLucky Draw and Closing\n\n\n\n\n\n\n\n\n\n\n*Please refer to the schedule announced on the day of the event. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/silvaco-users-global-event-china-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250115T090000 DTEND;TZID=America/Los_Angeles:20250115T160000 DTSTAMP:20241217T173045Z CREATED:20241217T173045Z LAST-MODIFIED:20241217T173045Z UID:8603-1736931600-1736956800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - USA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 15\, 2025.  \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \nEveryone that registers will be entered into a drawing to win one of 2 pairs of Apple AirPods Pro 2. \nAll attendees will be entered into a drawing to win one Apple iPad Air 11″ M2. \n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n9:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n9:15 AM​\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n9:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n9:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n10:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n10:15 AM​\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n10:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n10:45 AM​\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n11:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n11:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n12:00 PM​\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n1:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n1:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n1:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n2:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n2:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n2:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n3:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n3:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n3:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/silvaco-users-global-event-usa-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250107T080000 DTEND;TZID=America/Los_Angeles:20250110T170000 DTSTAMP:20241209T181610Z CREATED:20241004T181728Z LAST-MODIFIED:20241209T181610Z UID:8380-1736236800-1736528400@marketingeda.com SUMMARY:CES 2025 DESCRIPTION:The world’s most powerful tech event is your place to experience the innovations transforming how we live. \n\n\n\n\nThis is where global brands get business done\, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Registration for CES 2025 is now open. \n\n\nCES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges. \n\n\n\n\n\nCES connects innovators\, decision makers\, media\, influencers\, visionaries\, and potential customers across the entire tech ecosystem. \nDon’t be left in the past as we shape the future.\n\nGlobally showcase your technology products\nStand side-by-side with the world’s most disruptive innovators\nPromote your brand through curated opportunities to connect with influencers and prospective partners\n\nCES is owned and produced by the Consumer Technology Association (CTA)®\, which provides the ultimate platform for technology leaders to connect\, collaborate\, and propel consumer technology forward. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ces-2025/ LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20241125T180804Z CREATED:20241125T180804Z LAST-MODIFIED:20241125T180804Z UID:8537-1733997600-1734001200@marketingeda.com SUMMARY:Accelerating SoC Automotive Design with Chiplets DESCRIPTION:Step into the forefront of innovation with our upcoming webinar\, which explores how chiplet technology is revolutionizing the automotive industry and setting new benchmarks. Discover how Cadence is empowering customers to achieve unparalleled success with chiplets. Here’s what you can look forward to: \n\nMastering Chiplet Architecture: Dive into the intricacies of mastering chiplet architecture\, where you’ll learn how to integrate multiple chiplets\, including processing\, memory\, I/O\, and accelerators\, into a single\, streamlined solution. Understand the critical importance of chiplet interoperability and how Cadence and Arm collaborate on standards like the Arm Chiplet System Architecture to ensure seamless integration.\nThe Impact of Chiplets on Automotive Designs: Explore the transformative impact of chiplets on automotive designs\, particularly in building scalable and extendable systems for key functions such as ADAS. Learn about Cadence’s ADAS chiplet reference design and how it can accelerate product development with fewer engineering resources\, driving innovation in the automotive sector.\nCadence Chiplet Designs: Discover Cadence’s cutting-edge chiplet designs\, including the recent successful tapeout of Cadence’s first system chiplet. Learn how Cadence tools like the Helium Virtual Platform and 3D-IC are key enablers for quickly designing chiplet solutions\, helping customers bring their products to market faster and with greater efficiency.\n\nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to embarking on this exciting journey together! \nWho Should Attend:\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers and business leaders seeking to optimize their design flow and technology infrastructure. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/accelerating-soc-automotive-design-with-chiplets/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20241211T080000 DTEND;TZID=Asia/Shanghai:20241212T170000 DTSTAMP:20241206T211410Z CREATED:20241206T210925Z LAST-MODIFIED:20241206T211410Z UID:8556-1733904000-1734022800@marketingeda.com SUMMARY:ICCAD-Expo 2024 DESCRIPTION:The China Integrated Circuit Design Industry Exhibition (ICCAD-Expo) has always played an important role in promoting industrial agglomeration\, connecting industrial resources\, and mastering industry trends. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/iccad-expo-2024/ LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-Expo-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20241210T090000 DTEND;TZID=Europe/Paris:20241211T190000 DTSTAMP:20241122T185502Z CREATED:20241122T185502Z LAST-MODIFIED:20241122T185502Z UID:8524-1733821200-1733943600@marketingeda.com SUMMARY:IP-SoC Conference 2024\, Europe DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2024 will be the 27th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, … \nAny question? Please contact us \n\n\n\n\n\n\nDay 1\n\n\n\n\n\n\n\n9.00 am\nWelcome Session\n \nChairperson: Gabrièle Saucier – Design And Reuse\n\n\n\n\nIP SoC Community: EU as a main player ? \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nThe network evolution and radio implications \nFredrik Tillman\nHead of Integrated Radio Systems\nEricsson \nAbout me\n\n\n\n\nIncreased competitiveness and sustainability in connectivity with advanced substrates solutions \nFrancois Brunier\nPartnership Program Manager\nSoitec \nAbout me\n\n\n\n\nChips Act and EU design Platform \nOlivier Thomas\nCEA \nAbout me\n\n\n\n\n10.20 am\nBreak\n\n\n\n11.00 am\nInterface IP\n \nChairperson: Olivier Thomas – CEA\n\n\n\n\nThe Critical Role of PCIe 7.0 & CXL 3.1 Solutions in Enabling AI applications \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\nIoT Solutions\n\n\n\nHow to select the best Audio codec architecture to enhance your wearables? \nEtienne Faucher\nProduct Marketing Manager\nDolphin Semiconductor \nAbout me\n\n\n\n\nWireless and Batteryless Interface for IoT \nPolina Proskurova\nProject Manager\nNTLab \nAbout me\n\n\n\n\n12.00 pm\nLunch Break\n\n\n\n1.00 pm\nAutomotive Solutions\n\n\n\nTowards a Sustainable Automobile: Reinventing the Industry for Green and Circular Mobility \nJerome Fohet\nMarketing and Communications Director\nSoitec \nAbout me\n\n\n\n\nSilicon Lifecycle Management (SLM) in context of Chiplets for Automotive \nGraham Woods\nPrincipal Product Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\nProtecting Automotive Networks with MACsec Security \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nCyber Resilience and Safety in Automotive: How Security IP Provides Essential Primitives for Compliance \nGordon Fairley\nKudelski IoT \nAbout me\n\n\n\n\n2.30 pm\nBreak\n\n\n\n2.45 pm\nSecurity IP\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nSecure-IC Differential Loop PUF : Overcoming some weaknesses of the traditional Loop PUF while enhancing its usability \nBrice GAIGNOUX\nPre-Sales Engineer EMEA\nSecure-IC \nAbout me\n\n\n\n\nThe CHERI Alliance – getting security embedded into electronic systems \nMike Eftimakis\nFounding Director\nCHERI Alliance \nAbout me\n\n\n\n\nIntegrated Security Solutions: How SRAM-based PUF Augments Embedded Hardware Secure Modules in a Post-Quantum World \nErik van der Sluis\nPrincipal R&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nSecurity Verification in SoCs \nAli Hmedat\nSenior Design vérification Engineer\nAEDVICES CONSULTING \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nWireless Solutions\n\n\n\nInCirT Pioneers High-Performance Data Converter Technologies for Next-Gen Wireless Communications \nDr.-Ing. Oner Hanay\nCEO\nInCirT GmbH \nAbout me\n\n\n\n\nBattle of the Bits: Evaluating Lossless Data Compression Algorithms and Cores \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\n5.00 pm\nBreak\n\n\n\n5.30 pm\nOpen Panel: Greener Electronics: a myth or a reality ?\n\n\n\n\n\n\n\n\n\n\n\n6R Greenness Profiling for IC and Boards \n\n\n\n\n\n\n\nGabrièle Saucier\nCEO\nDesign And Reuse\n\n\nwith \nDagmara Zielinska\nDesign And Reuse\n\n\nand \nArnaud Serra\nDesign And Reuse\n\n\n\n\n\nAbout me\n\n\n\n\n\n\n\n\nIC Life time modeling : a critical parameter for Greener Electronics \nHN Nguyen\nCTO\nMETASymbiose \nAbout me\n\n\n\n\nStrategic decision-making in the semiconductor sector: shifting from relative to absolute sustainability \nThibault Pirson\nPhD\, research assistant\nUCLouvain \nAbout me\n\n\n\n\n19.00 pm\nJoin the wine tasting party sponsored by Soitec \nDo not miss D&R banquet\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2\n\n\n\n\n\n\n\n9.00 am\nAnalog Design\n\n\n\nHow to Enhance Energy Efficiency and Reduce Costs with Advanced In-Situ Sensors? \nVincent Telandro\nProduct Marketing Manager\nDolphin Semiconductor \nAbout me\n\n\n\n\nStandardizing CDC and RDC abstract models \nJean-Christophe Brignone\nSMTS\nSTMicroelectronics \nAbout me\n\n\n\nDesign Platform and Design Flow\n \nChairperson: Erkan Isa – Fraunhofer-Gesellschaft\n\n\n\n\nMake Chip: the one and only turnkey 22FDX design environment \nPatrick Döll\nPhysical IC Design Engineer\nRacyics GmbH \nAbout me\n\n\n\n\nKeysom Studio – Design Space Exploration of processor architectures \nLuca TESTA\nCofounder & COO\nKeysom \nAbout me\n\n\n\n\nStandard EDA tools based asynchronous design flow \nGODARD Adrien\nPhD student\nSTMicroelectronics \nAbout me\n\n\n\n\nAutomated Abstractions: High-Level Model Generation from Design Specifications or RTL Descriptions \nANDRIAMISAINA Choukataly-Caaliph\nCEA \nAbout me\n\n\n\nMigration and Yield Consideration\n\n\n\nPorting ASIC IP Cores to FPGA: It’s Not a Cakewalk! \nPhilipp Jacobsohn\nPrincipal Application Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nNiche gets super niche in the SEMI conductor Equipment domain \nP SRINIVASA RAGHAVAN\nPractice Head\, Semiconductor BU\nHCL TECH \nAbout me\n\n\n\n\n12.00 pm\nLunch Break\n\n\nWhat’s new on FDSOI: the SOIL Project\n \nChairperson: Philippe Flatresse – Soitec\n\n\n\n\nSolidify the European FDSOI ecosystem and accelerating its industrial deployment; A Chips JU initiative \nMartin LABRUNE\nEuropean & France Public Affairs\nSTMicroelectronics \nAbout me\n\n\n\n\nDesigning Intelligence from our SOIL \nKrishna Pradee\nSoitec \nAbout me\n\n\n\n\nInnovating the Future with SOIL: Next-Gen IPs\, Transfer from Research to Silicon \nDamian Panter\nFraunhofer \nAbout me\n\n\n\n\nFrom silicon to the use cases\, SOIL as a test bench for automotive applications \nLeonardo Govoni\nAED Vantage GmbH \nAbout me\n\n\n\nFDSOI IP\n\n\n\nMarket Available FDSOI IP \nDagmara Zielinska\nPartnership Program Manager\nDesign And Reuse \nAbout me\n\n\n\n\nDesigning SOC with ABX® – Challenges and Solutions \nFlorian Bilstein\nDirector Design Service\nRacyics GmbH \nAbout me\n\n\n\n\nUltra-wide band digital-to-analogue converter for wireless communication \nDr.-Ing. Oner Hanay\nCEO\nInCirT GmbH \nAbout me\n\n\n\nPanel: Building a strong FDSOI Ecosystem: A Catalyst for Tomorrow’s market wide Applications \nOrganizer:  Philippe Flatresse – Soitec \nFDSOI Technology has been over for quite a long time. This panel will investigate whether or not the technology and Ecosystem supporting this technology worldwide have now reached its full maturity or are still in a growing phase. The panel groups FDSOI technology specialists\, FDSOI Business managers\, researchers and FDSOI IP providers. \nWith the participation of: \n\n\nOlivier Thomas\nCEA\n\n\nRainer Lutz\nSoitec\n\n\nAnton Klotz\nFraunhofer\n\n\n\n\nFlorian Bilstein\nRacyics GmbH\n\n\nMichel Vasmer\nCapgemini Engineering\n\n\n\n\n\n\n\n17.00 pm\nJoin the reception organized by the European SOIL FDSOI Ecosystem\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-conference-2024-europe/ LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-2024-Europe.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241119T090000 DTEND;TZID=America/Los_Angeles:20241119T100000 DTSTAMP:20241019T030235Z CREATED:20241019T030235Z LAST-MODIFIED:20241019T030235Z UID:8436-1732006800-1732010400@marketingeda.com SUMMARY:Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design DESCRIPTION:The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC\, GPU\, mobile\, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. \nFor the past years\, Synopsys and Ansys have been creating design flows that carry designers through early exploration\, implementation\, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market. \nRegister now to learn about:\n– Multi-die design best practices for thermal\, signal\, and power integrity\n– Insights from practical multi-die design case studies\n– More advanced packaging technologies for thermal management\, backside power\, and co-packaged optics \nSPEAKERS \nMarc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose\, CA. Before joining Ansys\, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys\, Azuro\, and Sequence Design\, where he gained experience with a wide array of digital and analog design tools. \nKeith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design\, analog/mixed signal (AMS) and RF/mmWave product experience\, including 8 years designing high speed data converters and amplifiers at Analog Devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ansys-synopsys-technology-update-the-latest-advances-in-multi-die-design/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Synopsys-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241113T090000 DTEND;TZID=America/New_York:20241113T100000 DTSTAMP:20241016T181319Z CREATED:20241016T181319Z LAST-MODIFIED:20241016T181319Z UID:8422-1731488400-1731492000@marketingeda.com SUMMARY:ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer DESCRIPTION:The AI revolution and other application domains\, like data centers\, advanced wireless communications\, image and video processing\, automated driving assistance\, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). \nASIPs have become a mainstream implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. This growth has driven many university projects and increased interest in initiatives like RISC-V\, which has significantly expanded beyond UC Berkeley. \n\nWhy Attend? \nYou will hear from leading university teams about their ASIP design project results across various application domains. Additionally\, Synopsys will provide a technical update on ASIP Designer with reference examples. \nThis event offers a great opportunity to exchange ideas\, build networks\, and gain valuable insights from university partners. \nDon’t miss out – register now to secure your spot! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/asip-university-day-2024-domain-specific-processor-design-using-asip-designer/ LOCATION:CA CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T080000 DTEND;TZID=America/Los_Angeles:20241114T170000 DTSTAMP:20241030T174154Z CREATED:20241030T174154Z LAST-MODIFIED:20241030T174154Z UID:8463-1731398400-1731603600@marketingeda.com SUMMARY:IEEE World Technology Summit - AI INFRASTRUCTURE DESCRIPTION:This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems\, focusing on these core areas: \n\nAI applications and their required infrastructure\nSilicon to support AI applications\nSystems to support AI applications\nSecurity and Standards\n\nAI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit\, where companies\, governments\, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions. \nThe main focus of this conference is AI Infrastructure. \nTo deliver value we need the infrastructure for AI to work!!! This infrastructure includes software\, data storage\, computing\, communications\, power and energy\, standards\, and security. \nTo form an event to address the above issues\, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns\, challenges\, solutions\, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI\, which is critical to make AI work. \nCompanies are invited to sponsor\, engage\, and have employees attend this event. \nIf interested\, contact us at: wtscontact@ieee.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-world-technology-summit-ai-infrastructure/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WTS-November-12-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20241023T171101Z CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20240805T221745Z CREATED:20240805T221455Z LAST-MODIFIED:20240805T221745Z UID:8202-1729584000-1729702800@marketingeda.com SUMMARY:RISC-V Summit - North America 2024 DESCRIPTION:RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped\, powering new innovations in AI/ML\, wireless\, automotive. data center\, space\, IoT\, embedded and more. Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy a new level of design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis October\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies\, as well as to network and build relationships. Come be part of the RISC-V movement. \n\n\n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo featuring dozens of community members showcasing their the latest solutions.\n\nIt’s community-curated content\, research and innovation driving the next wave of growth for RISC-V. \nLearn about software\, systems\, development tools\, security\, the latest use cases in key markets and more. It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-north-america-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-US-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20241014T214312Z CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20241008T164139Z CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20241014T202014Z CREATED:20241014T202014Z LAST-MODIFIED:20241014T202014Z UID:8413-1728979200-1729184400@marketingeda.com SUMMARY:2024 OCP Global Summit DESCRIPTION:The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights\, foster partnerships and showcase cutting-edge advancements in open hardware and software. \nThe 2024 OCP Global Summit theme is “From Ideas to Impact”. This encapsulates the transformative journey at the heart of the Open Compute Project. This year’s theme reflects OCP’s commitment to fostering innovation that transcends theoretical discussions and manifests into real-world solutions. As the pace of technological evolution accelerates and development cycles shorten\, our industry is forced to rapidly respond to emerging trends and needs. By harnessing the collective expertise of our global community\, we turn visionary ideas into groundbreaking technologies that drive openness\, efficiency\, sustainability\, scalability and growth in the data center industry. Our focus honors the relentless pursuit of progress and the profound impact that OCP’s community-driven innovation can achieve. OCP transforms concepts into impactful advancements. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ocp-global-summit/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-OCP-Global-Summit.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20241008T080000 DTEND;TZID=Europe/Madrid:20241010T170000 DTSTAMP:20240923T170650Z CREATED:20240923T170650Z LAST-MODIFIED:20240923T170650Z UID:8345-1728374400-1728579600@marketingeda.com SUMMARY:AutoSens Europe 2024 DESCRIPTION:Join us as we embark on an exciting new journey in the vibrant city of Barcelona!\n\n\n\n\nFrom 8-10 October 2024\, we will unite the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV. \nExpect over 60 expert speakers\, engaging panels\, technical case studies\, and exploration of 12 key themes. Dive into an exhibition with cutting-edge demos from sensor and computer vision leaders. \nDon’t miss AutoSens Europe 2024 in Barcelona – the future of sensing tech awaits! \n\n\nDiscover the latest technology\n\n\n\n\nFrom innovative start-ups to industry giants\, the AutoSens exhibition floor is where our community comes together to make key connections over coffee\, have critical conversations in our igloo meeting pods\, and negotiate new partnerships over drinks at our networking sessions. \nRegister now to make the most of:\n\n\n\nAccess to an expert community of over 500 experts and engineers \n\n\n\n\n\nExtensive exhibition with over 50 stands showcasing the latest technology\n\n\n\n\n\n\n\nVehicle demos from leading Tier 1 and systems companies\n\n\n\n\n\n\n\nHigh quality technical presentations from genuine experts\n\n\n\n\n\n\n\nThought-leader panel discussions that shape the industry’s future direction\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/autosens-europe-2024/ LOCATION:Palau de Congressos\, Av. de la Reina Maria Cristina\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241002T090000 DTEND;TZID=America/Los_Angeles:20241002T100000 DTSTAMP:20240906T215750Z CREATED:20240906T215750Z LAST-MODIFIED:20240906T215750Z UID:8307-1727859600-1727863200@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI - Session 2 DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nThe CPU Cluster on Wednesday\, Oct 2\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nAn overview of Arm’s most performant\, efficient\, and versatile CPU cluster based on the Armv9 architecture for maximum performance and power efficiency.\nFeatures\, benefits\, and performance enhancements of Arm Cortex-X925\, Cortex-A725 CPU\, Cortex-A520 CPU and Arm DSU-120.\nHow this CPU cluster can improve consumer experiences on mobile devices.\n\nSpeaker: Manish Pandey\, Senior Product Manager\, Arm \nFirst Session – September 18th \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai-session-2/ LOCATION:CA CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241002T080000 DTEND;TZID=Asia/Taipei:20241002T170000 DTSTAMP:20240826T192110Z CREATED:20240826T192110Z LAST-MODIFIED:20240826T192110Z UID:8276-1727856000-1727888400@marketingeda.com SUMMARY:Memory Users Conference 2024 - China\, Taiwan DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024-china-taiwan/ LOCATION:CA CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T080000 DTEND;TZID=America/Los_Angeles:20241001T120000 DTSTAMP:20240826T192125Z CREATED:20240826T191744Z LAST-MODIFIED:20240826T192125Z UID:8273-1727769600-1727784000@marketingeda.com SUMMARY:Memory Users Conference 2024 DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024/ LOCATION:CA CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240925T093000 DTEND;TZID=America/Los_Angeles:20240925T180000 DTSTAMP:20240917T003907Z CREATED:20240917T003541Z LAST-MODIFIED:20240917T003907Z UID:8337-1727256600-1727287200@marketingeda.com SUMMARY:TSMC North America OIP Ecosystem Forum 2024 DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for A16\, N2 and N3 processes\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-north-america-oip-ecosystem-forum-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,Forum,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T090000 DTEND;TZID=America/Los_Angeles:20240918T100000 DTSTAMP:20240906T215837Z CREATED:20240906T215234Z LAST-MODIFIED:20240906T215837Z UID:8304-1726650000-1726653600@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/ LOCATION:CA CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240917T080000 DTEND;TZID=Asia/Tokyo:20240917T170000 DTSTAMP:20240823T182503Z CREATED:20240823T182145Z LAST-MODIFIED:20240823T182503Z UID:8269-1726560000-1726592400@marketingeda.com SUMMARY:IP-SoC Japan 24 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-japan-24/ LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20240913T080000 DTEND;TZID=Europe/Stockholm:20240915T170000 DTSTAMP:20240717T214406Z CREATED:20240717T214315Z LAST-MODIFIED:20240717T214406Z UID:8159-1726214400-1726419600@marketingeda.com SUMMARY:ORConf 2024 DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2024/ LOCATION:Gothenburg\, Gothenburg\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DTSTAMP:20240823T181126Z CREATED:20240823T181114Z LAST-MODIFIED:20240823T181126Z UID:8265-1726142400-1726146000@marketingeda.com SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240813T193558Z CREATED:20240813T193538Z LAST-MODIFIED:20240813T193558Z UID:8234-1726135200-1726138800@marketingeda.com SUMMARY:Addressing 3D-IC Power Integrity Design Challenges DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/ LOCATION:CA CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240912T080000 DTEND;TZID=Asia/Shanghai:20240912T170000 DTSTAMP:20240605T173645Z CREATED:20240605T173645Z LAST-MODIFIED:20240605T173645Z UID:8079-1726128000-1726160400@marketingeda.com SUMMARY:D&R IP-SoC China 2024 Day DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/ LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg END:VEVENT END:VCALENDAR