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BEGIN:DAYLIGHT
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TZOFFSETTO:+0200
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231127T100000
DTEND;TZID=Europe/London:20231127T143000
DTSTAMP:20231108T173556Z
CREATED:20231108T173556Z
LAST-MODIFIED:20231108T173556Z
UID:7054-1701079200-1701095400@marketingeda.com
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:The FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda: \n\n\n\n10:00\nArrival and Registration\n\n\n10.30\nPeter Davies\, Thales – Security in FPGA-based Systems\n\n\n11:15\nMark Frost\, Intel – Security in FPGA\n\n\n11:35\nIan Pearson\, Microchip – System and Device Level Security Considerations\n\n\n11:55\nMaximilian Werner\, Efinix Inc – Efinix FPGA Encryption solution\n\n\n12:15\nAnkith Srinivasan & Guests – How and why we use FPGAs in our systems\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed
URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet-2/
LOCATION:Thales\, 350 Longwater Avenue\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-FPGA-November-23-1200x600-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20231123T080000
DTEND;TZID=Asia/Taipei:20231123T170000
DTSTAMP:20230925T223336Z
CREATED:20230925T223336Z
LAST-MODIFIED:20230925T223336Z
UID:6879-1700726400-1700758800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-taiwan-singapore/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231121T080000
DTEND;TZID=America/Los_Angeles:20231121T170000
DTSTAMP:20230925T223154Z
CREATED:20230925T223154Z
LAST-MODIFIED:20230925T223154Z
UID:6877-1700553600-1700586000@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – EMEA
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-emea/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T170000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231108T222010Z
CREATED:20231108T222010Z
LAST-MODIFIED:20231108T222010Z
UID:7064-1700154000-1700154000@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n– OpenFrame – a new version of Caravel that gives 50% more area \n– GPIO configuration questions \n– The new cocotb testing framework \n– IPM – The new IP manager tool \n– OpenLane design integration options \n– GFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T110000
DTEND;TZID=America/Los_Angeles:20231116T120000
DTSTAMP:20231009T172654Z
CREATED:20231009T172654Z
LAST-MODIFIED:20231009T172654Z
UID:6930-1700132400-1700136000@marketingeda.com
SUMMARY:System Simulation of Versal ACAP Designs
DESCRIPTION:AVersal ACAP\, developed by Xilinx/AMD\, is a groundbreaking adaptable platform composed of AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads\, including machine learning\, embedded computing\, and high-performance computing. \nIn this webinar\, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. We will also show how to run a system simulation of a Versal example design. \nRiviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL\, PS and AIE. The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application\, Riviera-PRO’s simulator for the PL kernels\, and  QEMU for the PS host application. SystemC models are also available for the AIE and NoC\, which can also be simulated in Riviera-PRO. \n  \nAgenda:\n\nVersal ACAP Overview\nVersal Simulation Flows and Simulation Models\nIntroduction to QEMU\nHardware Emulation (System Simulation)\nDemo\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/system-simulation-of-versal-acap-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231113T182451Z
CREATED:20231113T182330Z
LAST-MODIFIED:20231113T182451Z
UID:7079-1700128800-1700132400@marketingeda.com
SUMMARY:Webinar Series | RISC-V Ready for Prime Time?
DESCRIPTION:Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. \nWhether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation\, this webinar will provide invaluable insights\, practical strategies\, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration. \nSign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2 \n  \nAGENDA\n\nIntroduction to RISC-V: Understanding the modularity and appeal of RISC-V.\nCore Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs\, ASICs\, and FPGAs.\nVerification Strategies: Unveiling the tools and methodologies to address power\, performance\, concurrency\, inter-core communication\, synchronization\, security\, and safety concerns.\nReal-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.\nQ&A Session: An opportunity to get your questions answered by our experts.
URL:https://marketingeda.com/event/webinar-series-risc-v-ready-for-prime-time/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Impare-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T090000
DTEND;TZID=America/Los_Angeles:20231116T100000
DTSTAMP:20231115T180404Z
CREATED:20231115T180404Z
LAST-MODIFIED:20231115T180404Z
UID:7094-1700125200-1700128800@marketingeda.com
SUMMARY:Boost SoC debug and analytics with embedded software and smart monitors
DESCRIPTION:On-chip monitors and debug structures can dramatically simplify debug\, validation\, analytics\, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this webinar\, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative to extract even more insights out of your on-chip monitors and debug structures for analytics and optimization\, and to create a self-contained on-chip monitoring system. \nWe will explore how the Tessent Embedded SDK can be used to build embedded software applications to orchestrate Tessent Embedded Analytics on-chip smart monitors. With the combination of embedded software and a complete on-chip monitoring solution\, you can perform non-intrusive real-time logging\, cache more data for later analysis\, enable real-time performance analysis and anomaly detection. \n  \nWhat you will learn: \n\nDiscover the Tessent Embedded Software Development Kit (Embedded SDK)\, a suite of software utilities that allows SoCs to be equipped with self-contained monitoring and analytics capabilities\nExplore which debug\, optimization and monitoring tasks can be simplified using embedded software.\nLearn how to develop embedded applications using the Tessent Embedded SDK\n\n  \nWho Should Attend: \n\nEmbedded SW Engineers\nSilicon bring-up engineers\nSoC architects\n\n  \nSpeaker\n \nNaga Nagarajan \nSoftware Engineer \nSiemens EDA \n  \nNaga Nagarajan is a software engineer at Siemens EDA. Naga began his career with UltraSoC (acquired by Mentor Graphics which is now Siemens EDA) where he focused on improving the host-based analytics software product known as SystemInsight. Naga now focuses on the development of the Tessent Embedded SDK products\, including the entire implementation of critical features such as in-life\, real-time performance monitoring and analytics. Naga holds an MEng in Electrical and Electronic Engineering.
URL:https://marketingeda.com/event/boost-soc-debug-and-analytics-with-embedded-software-and-smart-monitors/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Seoul:20231116T080000
DTEND;TZID=Asia/Seoul:20231116T170000
DTSTAMP:20230925T223032Z
CREATED:20230925T223032Z
LAST-MODIFIED:20230925T223032Z
UID:6875-1700121600-1700154000@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Korea
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-korea/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231115T090000
DTEND;TZID=America/New_York:20231115T170000
DTSTAMP:20231018T180605Z
CREATED:20231018T180605Z
LAST-MODIFIED:20231018T180605Z
UID:6969-1700038800-1700067600@marketingeda.com
SUMMARY:ASIP University Day 2023
DESCRIPTION:ASIP University Day: Domain-Specific Processor Design using ASIP Designer\n\n\nApplication-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough.  Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as artificial intelligence\, image and video processing or automated driving assistance have fueled the development of such ASIPs\, and triggered many university projects.  Processor design projects such as the RISC-V initiative also initiated a lot of interest.  With all the commercial activity around RISC-V these days\, it has outgrown UC Berkeley. \nSynopsys ASIP Designer is the market leading tool for ASIP design\, verification\, and programming. It is used by leading companies around the globe with hundreds of successful projects to date. \nAt this informal event\, leading university teams will present results from their ongoing ASIP projects in a variety of application domains. Synopsys will share insight on market trends\, and provide a technical update on ASIP Designer along with reference examples.
URL:https://marketingeda.com/event/asip-university-day-2023/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T110000
DTEND;TZID=America/Los_Angeles:20231114T120000
DTSTAMP:20231103T204425Z
CREATED:20231103T204425Z
LAST-MODIFIED:20231103T204425Z
UID:7040-1699959600-1699963200@marketingeda.com
SUMMARY:Why Chiplets with UCIe are the Next Big Thing
DESCRIPTION:Artificial intelligence (AI) and virtual reality (VR) require fast\, efficient\, low-power technologies. Transistors are becoming harder and harder to shrink\, so chiplets are a promising alternative. Chiplets are small\, modular dies that use UCIe\, an open industry standard\, to communicate with each other. Combined in a Systems-on-Package (SoP)\, they provide superior performance\, reduced power consumption\, and increased design flexibility for customized applications such as cell phones\, autonomous vehicles\, etc. In this panel session\, signal and power integrity experts will discuss: \n  \n\nIndustry trends and why chiplets with UCIe are the next big thing.\nSignal and power integrity considerations when integrating chiplets and UCIe interfaces.\nEDA tools evolved\, and how to streamline chiplets integration into the design workflow.\n\nSpeakers:\n\n\n\nHeeSoo Lee\nSerDes/DDR Product Owner\, Keysight Technologies\n\n\nHeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division\, located in Santa Rosa\, Calif. He has held several positions in Keysight Technologies\, Agilent Technologies and Hewlett-Packard\, including consulting business manager\, technical marketing lead and field applications engineer since 1989. Prior to these positions\, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF\, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University\, South Korea. \n\nHeidi Barnes\nSenior Application Engineer and Power Integrity Product Owner\, Keysight Technologies\n\n\nHeidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight\, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation\, her recent activities include the application of electromagnetic\, transient\, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017. \n\nRandy White\nMemory Solutions Program Manager\, Keysight Technologies\n\n\nRandy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server\, mobile\, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques\, including de-embedding algorithms\, measurement/model correlation\, high-speed measurements for real-time & sampling oscilloscopes\, and BERTs & AWGs. He has participated on many standards committees\, including PCI-SIG\, USB-IF\, SATA-IO\, and JEDEC\, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
URL:https://marketingeda.com/event/why-chiplets-with-ucie-are-the-next-big-thing/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231110T193817Z
CREATED:20231110T193817Z
LAST-MODIFIED:20231110T193817Z
UID:7070-1699956000-1699959600@marketingeda.com
SUMMARY:Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
DESCRIPTION:As semiconductor industry leaders\, Bosch\, Infineon\, Nordic Semiconductor\, NXP\, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors\, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software\, this webinar will offer key insights into developing your own ISO 26262-grade\, Certified ASIL RISC-V automotive chip solution. Don’t miss this opportunity to stay ahead in the evolving semiconductor landscape. \nSpeakers: \nMarvin Chao\, Andes Technology Director of Solution Architecture\, will provide insights into the functionality and capabilities of the ISO 26262-certified AndesCore N25F-SE CPU IP. Learn how this new open-source CPU ISA is addressing the unique demands of automotive applications\, ensuring safety\, reliability\, and performance. \nChuck Brokish\, Green Hills Software Director of Automotive Business Development\, will demonstrate how Green Hills’ MULTI and TimeMachine Software Development Tools\, µ-velOSity Real-Time Operating System\, and Hardware Debugging and Trace Probes can be effectively used to write and debug ISO 26262-certified software that runs efficiently on the N25F-SE CPU IP. \n*This webinar is in partnership with SemiWiki\, Andes\, and Green Hills Software*
URL:https://marketingeda.com/event/leverage-certified-risc-v-ip-to-craft-asil-iso-26262-grade-automotive-chips/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T130000
DTEND;TZID=America/New_York:20231109T140000
DTSTAMP:20231030T181412Z
CREATED:20231030T181412Z
LAST-MODIFIED:20231030T181412Z
UID:7012-1699534800-1699538400@marketingeda.com
SUMMARY:Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace\, Government\, and Defense Systems
DESCRIPTION:Join industry experts from aerospace\, government\, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI)\, highlighting some of the technological\, manufacturing\, and economic complexities as well as security\, reliability\, and safety challenges.  The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research program plans to grow the 3DHI R&D ecosystem. Whether you are an engineer or a policymaker looking to deepen your 3DHI knowledge\, this panel offers insightful discussions to help anticipate and address future microelectronics design challenges for aerospace\, government\, and defense systems. \nSpeakers\nIan Land\nSynopsys\nSenior Director\, Security\, Government and Aerospace Solutions\nModerator \nDr. Carl McCants\nSpecial Assistant to the DARPA Director \nDr. Josh Fryman\nIntel Corporation\nFellow \nRob Aitken\nSynopsys\nDistinguished Architect
URL:https://marketingeda.com/event/tackling-challenges-in-3d-heterogenous-integrated-3dhi-microelectronics-for-aerospace-government-and-defense-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231109T090000
DTEND;TZID=America/Los_Angeles:20231109T133000
DTSTAMP:20231027T171914Z
CREATED:20231027T171914Z
LAST-MODIFIED:20231027T171914Z
UID:7001-1699520400-1699536600@marketingeda.com
SUMMARY:CHIPS Alliance - FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
DESCRIPTION:IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side\, the concept of package managers is widely used to build a product from many different sources\, but chip designers often rely on ad-hoc solutions which tends to build up a maintenance cost and burden. Fortunately FuseSoC and Edalize exists to help. Being the most popular package manager for IP cores\, there are already hundreds of FuseSoC-compatible IP cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so\, and it is being increasingly used inside small and large companies for development of proprietary systems as well. With support for almost 40 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification. Sounds great\, doesn’t it? It sure does\, and this presentation will take you through the basics of FuseSoC to help you get started\, using VeeRwolf\, the CHIPS Alliance-governed reference platform for the VeeR family of CPU cores as an example\, and looks beyond this to how FuseSoC can help you focus on your core business instead of your cores.
URL:https://marketingeda.com/event/chips-alliance-fusesoc-package-manager-and-build-abstraction-tool-for-fpga-asic-development/
LOCATION:Google\, 237 Moffett Park Drive\, Sunnyvale\, CA\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chips-Alliance-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231030T180110Z
CREATED:20231030T175759Z
LAST-MODIFIED:20231030T180110Z
UID:7009-1699437600-1699441200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part I
DESCRIPTION:Synopsys Webinar – Part I  \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-i/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20231107T090000
DTEND;TZID=Asia/Kolkata:20231108T180000
DTSTAMP:20231103T191339Z
CREATED:20231103T191339Z
LAST-MODIFIED:20231103T191339Z
UID:7036-1699347600-1699466400@marketingeda.com
SUMMARY:IESA AI Summit
DESCRIPTION:Experience the unprecedented growth opportunities in the semiconductor and electronics industry\, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions\, captivating emerging markets in the realm of AI.\nWitness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI\, igniting a renaissance in the electronics landscape. \nIn the dynamic realm of the Intelligent Electronics & Semiconductor ecosystem\, the India Electronics and Semiconductor Association (IESA) eagerly explores the immense potential of AI in the hardware sector. Unlock the limitless possibilities of AI and shape the future of the semiconductor industry. \nEmbrace cutting-edge technologies\, network with industry experts\, and drive innovation at the forefront of AI’s revolution in hardware.
URL:https://marketingeda.com/event/iesa-ai-summit/
LOCATION:Trident Hotel Hyderabad\, Hyderabad\, India
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IESA-AI-Summit-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231106T090000
DTEND;TZID=America/Los_Angeles:20231106T120000
DTSTAMP:20230926T165725Z
CREATED:20230926T165725Z
LAST-MODIFIED:20230926T165725Z
UID:6885-1699261200-1699272000@marketingeda.com
SUMMARY:RISC-V 101
DESCRIPTION:The RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard\, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. \nYou’ve seen the headlines and stories. Now\, here’s your chance to learn all about RISC-V and why it is being rapidly adopted by organizations of all size around the world. RISC-V 101 is your introduction to RISC-V and a primer on the ISA and ecosystem. \nThis free\, special event will cover the history of RISC-V and why organizations around the world are choosing it as the architecture for their computing needs. \nLearn more about RISC-V’s ecosystem\, including contributions from commercial companies\, research institutes\, consortia and government organizations. Discover how they are using RISC-V in their own applications and developing technologies that are powering solutions in a wide range of markets including data center\, automotive\, mobile\, embedded and more. \nRISC-V 101 will also feature breakout sessions to explore specific topics\, such as commercial solutions\, software development\, careers and getting started in technical committees. \nIf you have wanted to better understand what the hype is about\, here’s your chance to hear directly from and meet our community. On the eve of RISC-V Summit North America\, come to RISC-V 101 to learn how RISC-V could impact your future trajectory. \nThere is no cost to attend\, but you must register to guarantee your seat. Register now to unlock your understanding of RISC-V!
URL:https://marketingeda.com/event/risc-v-101/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-November-6-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231106T080000
DTEND;TZID=America/Los_Angeles:20231108T170000
DTSTAMP:20230905T182638Z
CREATED:20230905T182638Z
LAST-MODIFIED:20230905T182638Z
UID:6779-1699257600-1699462800@marketingeda.com
SUMMARY:RISC-V Summit US
DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V\, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis November\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies to network and build relationships and to experience much more. \n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo full of community members showcasing their the latest community innovations and offerings.\n\nIt’s community-curated content and innovation at the heart of the next wave of growth for RISC-V. \nFind out what’s happening in Automotive\, Data Centers\, Embedded\, Mobile\, AI/ML\, Security\, Software Stacks\, Development Tools\, Systems on a Chip\, Chiplets and more! It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. Meet your heroes. It’s all during RISC-V Week North America\, this November. Come join us! \nJoin us in Santa Clara\, CA for RISC-V Summit 2023! \nFor more information\, visit https://events.linuxfoundation.org/riscv-summit/.
URL:https://marketingeda.com/event/risc-v-summit-us/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-SUMMIT-US-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Denver:20231102T093000
DTEND;TZID=America/Denver:20231102T170000
DTSTAMP:20231019T045430Z
CREATED:20231019T045430Z
LAST-MODIFIED:20231019T045430Z
UID:6972-1698917400-1698944400@marketingeda.com
SUMMARY:RISC-V in Space
DESCRIPTION:Join us for “RISC-V in… Space” on November 2\, 2023\, as we explore the exciting intersection of RISC-V\, electronics design\, and space! \n\n\n\nAgenda\n\n\n\n\n\n9:30 AM – 10:00 AM \nRegistration & Welcome \n\n\n\n\n10:00 AM – 12:00 PM \nCase Study Presentations: Tenstorrent\, Synopsys\, RISC AI\, Arteris IP \n\n\n\n\n12:00 PM – 1:00 PM \nLunch Buffet \n\n\n\n\n1:00 PM – 3:00 PM \nCase Study Presentations: Breker Systems\, Imperas\, Cycuity\, Codasip \n\n\n\n\n3:00 PM – 5:00 PM \nNetworking Reception with appetizers and refreshments \n\n\n\n\n\n\nAbout this event\n\n\n7 hours\nMobile eTicket\n\n\n\n\nTenstorrent is hosting a meet up in Denver aimed at practitioners and entrepreneurs developing electronic systems and components for space applications. Alongside partners Codasip\, Cycuity\, Breker Systems\, Imperas\, RISC AI\, Synopsys\, and Arteris IP we are excited to invite you to explore with us at the Omni Interlocken Hotel in Broomfield\, CO. \nThrough user-group discussions\, case studies\, and application notes (and steering clear of sales pitches) we’ll explore the exciting sector of space electronics with crucial emphasis on: \n\nArtificial Intelligence & Machine Learning\nEmbedded Processing\nSecurity\nDesign Verification
URL:https://marketingeda.com/event/risc-v-in-space/
LOCATION:Omni Interlocken Hotel\, 5000 Interlocken boulevard\, Broomfield\, CO\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Temstorrent-November-2-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T100000
DTEND;TZID=America/Los_Angeles:20231101T103000
DTSTAMP:20231003T172423Z
CREATED:20231003T172423Z
LAST-MODIFIED:20231003T172423Z
UID:6910-1698832800-1698834600@marketingeda.com
SUMMARY:Mastering the Art of Managing IP\, Chiplets\, and Design Data
DESCRIPTION:Join us on Wednesday\, November 1st\, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity to revolutionize your approach to semiconductor chip design. \n  \nHere’s what you can learn:\n\nBest practices for efficient chip design data and IP handling.\nCutting-edge IP management strategies for reuse\, security\, and compliance.\nData integration and design flow techniques to enhance collaboration.\n\n  \nBONUS: Design Data and IP Management Best Practices eBook for All Participants! \n  \nWho should attend:\n\nSemiconductor Design and Verification Engineers\nIP Managers and Administrators\nData and tech enthusiasts\nInnovators seeking an edge\nAnyone passionate about chip design excellence\n\nDon’t miss out on this chance to gain a competitive edge in the dynamic world of semiconductor chip design. See you at the webinar!
URL:https://marketingeda.com/event/mastering-the-art-of-managing-ip-chiplets-and-design-data/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20231031T083000
DTEND;TZID=America/Chicago:20231031T170000
DTSTAMP:20231024T192426Z
CREATED:20231024T192233Z
LAST-MODIFIED:20231024T192426Z
UID:6991-1698741000-1698771600@marketingeda.com
SUMMARY:STAC Summit
DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment. \nWHEN\nTuesday\, October 31\, 2023\nSTAC Exchange (Exhibits) opens at 8:30am CDT\nConference starts at 9:00am CDT\nNetworking lunch at ~12:00pm CDT\nConference concludes at ~4:00pm CDT\nReception immediately following \nWHERE\nThe Metropolitan Club\nWillis Tower\n233 South Wacker Drive\n66th Floor\nChicago \n\n\n\n9:00am\nSTAC Update: Historical tick analytics\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present the latest results in STAC-M3 (tick analytics).\n\n\n\n\n\n\n9:15am\nInnovation Roundup\n\n\n\n“How to maximize your GPU investment”\nJeff Chu\, Financial Services Sales\, Penguin Solutions\n\n\n\n“Using a vector database to unlock the power of your data”\nJosh Kalina\, Pre-Sales Engineer\, KX\n\n\n\n“Data at Scale: Overcoming Challenges in Generative AI and LLM Development”\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\n\n\n\n\n\n9:35am\nEnforcing the foundation: Improving data lineage      ;\n\n\n\n\n\nMarc Gale\, Director of Data Engineering\, OncoHealth; former Manager of Data Engineering\, Chicago Trading Company\nJosh Kalina\, Pre-Sales Engineer\, KX\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\nIt’s no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets\, which come from many sources with varying quality. Even worse\, today’s data could be corrected tomorrow\, next week\, or next year. For models to stay stable during rapid innovation\, data engineers must properly track\, maintain\, and leverage the data’s lineage. How should they track change sets\, version data\, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix.\n\n\n\n\n\n\n10:05am\nThe unbearable heaviness of data: Can modern approaches help?\n\n\n\n\n\nVrashank Jain\, Sr. Director of Product Management for Data Management Solutions\, Dell Technologies\n\nIt’s common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users\, capture real-time streams\, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Vrashank has seen financial firms greatly reduce the burden of data maintenance\, allowing technologists to focus on developing data products. Using Dell’s experience with an international bank as a guide\, he’ll show how applying an open data platform\, from edge to core to cloud\, can reduce data movement\, consolidate data intelligently\, and allow access to diverse tools and uses\, all while keeping data secure. Be sure to bring your questions for Vrashank as he covers best practices in data modernization and the benefits they can bring.\n\n\n\n\n\n\n10:30am\nBreak\n\n\n\n\n\n\n11:00am\nSTAC Update: Big compute\n\n\n\n\n\nBishop Brock\, Head of Research\, Strategic Technology Analysis Center\n\nBishop and Peter will present the latest STAC Benchmark Council activities compute critical workloads\, including STAC-A2 (complex deriviatives risk computation) and an update from the STAC-ML Working Group.\n\n\n\n\n\n\n11:10am\nWaste not\, want not: Avoiding idle GPUs\n\n\n\n\n\nTroy Kaster\, VP of AI\, Penguin Solutions\n\nMany financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery\, portfolio management\, and quantitative research. But once they fill the compute gap\, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin’s experience bringing a 16k GPU cluster online for Meta\, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing\, building\, deploying\, and managing large-scale GPU clusters.\n\n\n\n\n\n\n11:35am\nInnovation Roundup\n\n\n\n“Build. Connect. Analyse. Beeks solves your colo and network visibility challenges.”\nMatthew Cretney\, Head of Product Management\, Beeks Group\n\n\n\n“Mechanics of Low Latency Capture”\nPramod Nayak\, Director of Product Management\, Low Latency\, Refinitiv\, an LSEG Business\n\n\n\n“The Smart Way to Configure a Tap Aggregator”\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\n\n\n\n\n\n\n11:50am\nEncrypting our markets: The impact of security on high-performance infrastructures\n\n\n\n\n\nVenkat Doddapuneni\, Senior Director of Software Engineering\, CME Group\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\nAdditional speakers to be announced\n\nSecurity has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections\, and at least one exchange has rolled them out. Encryption can provide a layer of protection\, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance\, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They’ll dive into important aspects\, including what concerns motivate a desire for higher security\, what should be in scope\, the impact on performance\, and how to maintain network-based risk\, compliance\, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.\n\n\n\n\n\n\n12:20pm\nNetworking Luncheon\n\n\n\n\n\n\n1:20pm\nSTAC Update: Network communications\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present on the latest STACT Benchmark Council activities in network communications\, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.\n\n\n\n\n\n\n1:35pm\nInnovation Roundup\n\n\n\n“Leveraging HATI for high resolution timing to FPGA’s.”\nCiaran Kennedy\, Sales\, Safran Timing & Navigation\n\n\n\n“Create a Better and Faster Consolidated View Across Markets Using FPGAs”\nCliff Maddox\, Director of Business Development\, NovaSparks\n\n\n\n“Cancel on Behalf is a Game Changer”\nJohn Hagerman\, VP Marketing and Business Development\, Algo-Logic\n\n\n\n“Using Equivalence Checking to Rapidly Evolve Your Design”\nMartin Rowe\, Sr. Application Engineer\, Siemens\n\n\n\n“Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions”\nJean-François Gagnon\, Ultra-Low Latency FPGA Solutions Architect\, Orthogone\n\n\n\n\n\n\n2:00pm\nTalent shortages in hardware verification: Can ML plug the gaps?\n\n\n\n\n\nAdam Sherer\, Verification Technology Executive\, Cadence\n\nAs discussed at recent STAC Summits\, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions\, but a shortage of experienced\, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that\, given the proper setup\, advances in ML can provide some relief by increasing the productivity of current staff. He’ll dive into tasks that grind on an engineer’s time—like regression optimization\, failure triage analysis\, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.\n\n\n\n\n\n\n2:20pm\nBreak\n\n\n\n\n\n\n2:50pm\nSTAC Update: Fast data\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will discuss the latest test results for STAC-N1 (full stack networking).\n\n\n\n\n\n\n2:55pm\nInnovation Roundup\n\n\n\n“ÜberNIC can do… Can Yours?”\nAlex Stein\, Global Head Business Development\, Liquid-Markets-Solutions\n\n\n\n“Trading at the speed of light – Beyond ultra-low latency with Salience Labs”\nChris Porthouse\, Chief Product Officer\, Salience Labs\n\n\n\n“nxFramework update: Added features and improved latency for the Exegy FPGA development framework”\n Laurent de Barry\, Sr. Director\, Global Head of Solutions Consulting\, Exegy\n\n\n\n\n\n\n3:15pm\nDesigning the right hardware stack for FPGA\n\n\n\n\n\nMichael Gorbovitski\, Executive Director\, Morgan Stanley\nRobert DeWitt\, Director Product Marketing\, AMD\nDarrin Machay\, Principal Engineer\, Arista\n\nFGPAs are a go-to component for firms looking to improve their latencies\, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know\, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack\, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute\, memory\, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities\, and what can we achieve with programmable switches? What’s the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.To kick off\, there will be some brief presentations:\n\n\n\n“Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading”\n Hamid Reza Salehi\, Director Product Marketing\, AMD\n\n\n\n“Arista 7130 Update: Ultra Low Latency 25G”\n Darrin Machay\, Principal Engineer\, Arista\n\n\n\n\n\n\n~4:00pm\nNetworking Reception
URL:https://marketingeda.com/event/stac-summit-2/
LOCATION:The Metropolitan Club\, 233 South Wacker Drive\, Chicago\, IL\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-October-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231026T080000
DTEND;TZID=America/Los_Angeles:20231026T170000
DTSTAMP:20230925T222750Z
CREATED:20230925T222750Z
LAST-MODIFIED:20230925T222750Z
UID:6872-1698307200-1698339600@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 - USA
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-usa/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20231024T080000
DTEND;TZID=Asia/Jerusalem:20231024T170000
DTSTAMP:20231003T164756Z
CREATED:20231003T164756Z
LAST-MODIFIED:20231003T164756Z
UID:6907-1698134400-1698166800@marketingeda.com
SUMMARY:SemIsrael Expo 2023
DESCRIPTION:SemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. \nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities.​   \nMeet Our Keynote Speakers\nVivek MishraCorporate Vice President – Product EngineeringCadence \nDr. Charlie SuCo-Founder\, President and CTOAndes Technology \nDr. Yervant ZorianChief Architect and FellowSynopsys \nKay EnjojiPresidentTEL Ventures \nLee HarrisonDirector Tessent Product MarketingSiemens EDA
URL:https://marketingeda.com/event/semisrael-expo-2023/
LOCATION:Avenue Convention Center\, Airport City\, Israel
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/semisrael-expo-2023-logo-blue-795-455.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231018T083000
DTEND;TZID=America/Los_Angeles:20231018T160000
DTSTAMP:20230927T172101Z
CREATED:20230927T172101Z
LAST-MODIFIED:20230927T172101Z
UID:6892-1697617800-1697644800@marketingeda.com
SUMMARY:The Race is On!
DESCRIPTION:Event Overview\n\n\n\n\n\n\n\n\n\n\n\n\nDate: Wednesday\, October 18\, 2023 \nTime: 8:30am – 4:00pm\, followed by an exclusive networking event \nLocation: Brazos Hall\, Austin\, TX \n\n\n\n\n\n\n\n\n\n\n\n\nThere is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power\, security\, reliability\, and other multifaceted requirements have surpassed the basic performance\, power consumption\, and area constraints of traditional chip design. The race is on to enable traditional automotive companies to enter the new field of automotive electronic chips quickly\, and to improve the performance of established automotive chips to deliver higher and higher computing capabilities while meeting safety and reliability requirements. \n\nJoin Cadence on October 18\, at Brazos Hall in Austin\, as we present a new generation of automotive electronics chip design full-flow solutions. Learn about the most recent advancements in the field of automotive chips\, including upcoming technology trends and innovations\, such as autonomous driving to electric vehicles\, functional safety\, reliability of automotive semiconductors\, and more. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend:\n\n\n\n\n\n\n\n\n\n\n\n\nCAE professionals with a background in electrical engineering\, fluid dynamics\, engineering directors and managers\, and engineering team members who work in automotive electronics (SoC) design. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn:\n\n\n\n\n\n\n\n\n\n\n\n\n\nDesign IP for Automotive SoC Design\n3D-IC Design and Interconnect IP Solution for Chiplet-Based Design\nConfigurable Multi-Core DSP and AI Platform for Automotive Applications\nFMEDA-Driven Safety Analysis and Verification\nSafety-Aware Implementation\nAnalog/Mixed-Signal Safety Verification\nSystem Design and Analysis (EMI\, EMC\, Electrothermal)\nAutomotive CFD Solutions (Aerodynamics\, Aeroacoustics\, HVAC\, Turbo/Pumps\, ​\nThermal Management)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n“The race is on!” not just on the circuits\, but also here in the center of our event. Accelerate your knowledge at our seminar and shift your networking into high gear. \nWe’re thrilled to announce that a special guest will be joining us. Be ready to mingle with an elite McLaren Formula 1 driver at our exclusive networking event. Don’t miss this unique opportunity to meet and interact with one of racing’s finest up close and personal. Whether you’re a die-hard F1 fan or simply looking to network with experts in the industry\, this is a pit stop you won’t want to miss! \n \nStay tuned for more information!
URL:https://marketingeda.com/event/the-race-is-on/
LOCATION:Brazos Hall\, East 4th Street\, Austin\, TX\, United States
CATEGORIES:EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20231017T120000
DTEND;TZID=Asia/Tokyo:20231017T173000
DTSTAMP:20231012T003544Z
CREATED:20231012T003512Z
LAST-MODIFIED:20231012T003544Z
UID:6941-1697544000-1697563800@marketingeda.com
SUMMARY:Samsung Foundry Forum 2023 Tokyo\, Japan
DESCRIPTION:Welcoming Remarks\n\nSeishu Arai \nVP\, Head of Japan Office\, Samsung Electronics \n\nSamsung Keynote\n\nSiyoung Choi \nPresident and GM\, Foundry Business\, Samsung Electronics \nGuest Speech I\n\nJunichiro Makino \nProfessor\, Kobe University \nGuest Speech II\n\nSumiko Kanamori \nAutomotive HPC\, Analog & Power Solutions Gr. Digital Head of H/W Unit\, VP\, Renesas Electronics Corporation \nGuest Speech III\n\nKazuoki Matsugatani \nSenior Director\, R&D Center\, Denso Corporation \nProcess Technology\n\nJa-Hum Ku \nEVP\, Head of Technology Development\,Samsung Electronics \nDesign Platform\n\nJongwook Kye \nEVP\, Head of Foundry Design Platform Development\, Samsung Electronics \nManufacturing Excellence\n\nSang Sup Jeong \nEVP\, Head of Foundry Manufacturing Technology Center\, Samsung Electronics \nBusiness & Customers\n\nSang-Pil Sim \nEVP\, Head of Worldwide Sales and Marketing\, Samsung Electronics \nAutomotive and HPC Solutions\n\nJongshin Shin \nEVP\, Head of Foundry IP Ecosystem\, Samsung Electronics \nClosing Remarks\n\nSang-Pil Sim \nEVP\, Head of Worldwide Sales and Marketing\, Samsung Electronics
URL:https://marketingeda.com/event/samsung-foundry-forum-2023-tokyo-japan/
LOCATION:Belle Salle Tokyo Nihonbashi\, 2-7-1 Nihombashi\, Chuo-ku\, Tokyo\, Japan
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-Foundry-Forum-2023-Tokyo.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230918T184234Z
CREATED:20230918T184234Z
LAST-MODIFIED:20230918T184234Z
UID:6811-1697104800-1697108400@marketingeda.com
SUMMARY:The UCIe™ 1.1 Specification: Future Applications of Chiplets
DESCRIPTION:Presenter: Dr. Debendra Das Sharma\, UCIe Consortium Chairman and Intel Senior Fellow\, Chief Architect of I/O Technology and Standards at Intel  \n\n\nThe UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023\, delivering valuable improvements to the chiplet ecosystem\, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide an overview on enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation. 
URL:https://marketingeda.com/event/the-ucie-1-1-specification-future-applications-of-chiplets/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-October-12-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230908T182145Z
CREATED:20230908T182145Z
LAST-MODIFIED:20230908T182145Z
UID:6786-1697104800-1697108400@marketingeda.com
SUMMARY:Proactively Address Thermal Concerns in Advanced IC Packages
DESCRIPTION:The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals\, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. \nThis webinar will show how design teams that implement thermal mitigation strategies early in the design cycle are facing fewer thermal concerns with their IC package prototypes.  We will walk through a reference design and discuss how Cadence Advanced Package Designer Plus combined with Celsius Thermal Solver address feasibility during the design planning stage to the full-system final signoff. \nJoin our webinar to learn how you can: \n\nEfficiently address thermal concerns throughout the design cycle\nReduce design iterations\nProactively drive predictability into your design schedules
URL:https://marketingeda.com/event/proactively-address-thermal-concerns-in-advanced-ic-packages/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-12-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231011T090000
DTEND;TZID=America/Los_Angeles:20231011T100000
DTSTAMP:20231006T190044Z
CREATED:20231006T190044Z
LAST-MODIFIED:20231006T190044Z
UID:6919-1697014800-1697018400@marketingeda.com
SUMMARY:Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
DESCRIPTION:In this Webinar\, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors\, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  \n\n Key Takeaways: \n\nDiscover the inner workings of FPGA components: Processor\, Logic Elements\, AIE/Tensor\, and more.\nUnderstand latency and throughput trade-offs when using NoC vs. direct interfaces.\nLearn how different data cache sizes impact AIE Tile network utilization.\nDive into various mapping decisions and their effect on application throughput and power consumption.\n\n  \nSo\, what are you waiting for? Don’t miss this opportunity
URL:https://marketingeda.com/event/mapping-signal-processing-algorithms-on-amd-xilinx-versal-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20231010T080000
DTEND;TZID=Europe/Berlin:20231011T170000
DTSTAMP:20231004T162118Z
CREATED:20231004T162118Z
LAST-MODIFIED:20231004T162118Z
UID:6913-1696924800-1697043600@marketingeda.com
SUMMARY:CadenceLIVE Europe 2023
DESCRIPTION:CadenceLIVE Europe 2023 – experience the power of intelligent system design – brings together users\, developers\, and industry experts to network\, share ideas\, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nAttendees will be able to attend captivating keynotes\, watch user presentations packed full of innovation\, see new product demos\, and learn new ways to solve design challenges from industry leaders and Cadence experts. \nCadence® products\, solutions\, flow\, and techniques will be featured at the conference in the following areas: \n\nMultiphysics In-Design Analysis\nHeterogeneous Integration\nCustom IC / Mixed-Signal / RF\nDigital Full Flow\nPCB / Advanced Packaging\nVerification Hardware and Software\nWorkforce Development\n\nCadence customers and partners can attend the event for FREE. \nCheck out the agenda to see what’s in store.
URL:https://marketingeda.com/event/cadencelive-europe-2023/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230927T080000
DTEND;TZID=Europe/Berlin:20230928T170000
DTSTAMP:20230923T041526Z
CREATED:20230923T041526Z
LAST-MODIFIED:20230923T041526Z
UID:6865-1695801600-1695920400@marketingeda.com
SUMMARY:GTS 2023 - Munich
DESCRIPTION:Register now and join us at GlobalFoundries Technology Summit 2023! \nGF Technology Summit (GTS) 2023 is our worldwide\, annual series of technology-focused events. GTS brings together leaders from the commercial\, business and research worlds to understand the latest technology challenges and opportunities\, and partner to create the most innovative applications and solutions. \nGTS 2023 Highlights \nThis year’s GTS will focus on GF’s industry and technology differentiation\, highlighted by three key areas of innovation: \n\nPower\, power\, power – Ultra-low power technology platforms and applications\, power management and power delivery solutions\nBest RF wins – RF and mmWave connectivity solutions for mobile and infrastructure applications\nIntelligence & security – Localized\, low-power intelligent applications with secure eNVM\n\nGF’s market-focused development includes partnerships across the broad electronics ecosystem – OEM\, fabless\, OSAT\, EDA and IP. The results of those collaborations will be seen and heard in the guest keynote addresses\, detailed technology roadmaps\, hardware and software demonstrations\, and leading applications for automotive\, IoT\, smart mobile\, datacenter and communications infrastructure markets. \nNew in 2023! GF Technology\, Business and Commercial teams will be at GTS to host 1:1 and small group meetings during the event. Please consider if there is someone you would like to meet with during your time in Munich – requests will be submitted during the registration process. \n  \nGTS Program Overview \nDay One Programming: 12:00 – 16:00 Networking Hour to follow \nCEO Dr. Thomas Caulfield\, joined by leaders in the fabless semiconductor and end-markets industries\, shares GF’s corporate vision and roadmap of manufacturing the essential chips we rely on for life\, work and connection. \nDay Two Programming: 9:00 – 14:00 with Networking Reception to follow \nGF’s technology and product management leaders share the company’s detailed technology and solutions roadmap\, joined by leaders in the semiconductor design and manufacturing ecosystem – working together to deliver a new era of more.
URL:https://marketingeda.com/event/gts-2023-munich/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GTS-2023-Munich.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230926T100000
DTEND;TZID=America/Los_Angeles:20230926T110000
DTSTAMP:20230921T161238Z
CREATED:20230921T161238Z
LAST-MODIFIED:20230921T161238Z
UID:6847-1695722400-1695726000@marketingeda.com
SUMMARY:Unleashing Innovation with UCIe​​​​​​​​​​​​​​
DESCRIPTION:Exploring the Next Frontier in Chip Integration\nWebinar Agenda : \n\nIntroduction to all UCIe layers\nDecrypting FLITs\, PHY Trainings\, Bring up flows FDI-RDI \, main band and side band FLIT transfers etc.\nImplementation of Stacks-Arbiter\, Retry mechanism & Retimer implementations\nShowcasing UCie FLIT transfer flow between multidies\nEnhancements done in UCIe 1.1\n\nWho Should Attend: \n\nProfessionals working on development of UCIe VIP.\nPeople keen to know how UCie VIP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/unleashing-innovation-with-ucie/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-September-26-2023.jpg
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END:VCALENDAR