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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230918T184234Z
CREATED:20230918T184234Z
LAST-MODIFIED:20230918T184234Z
UID:6811-1697104800-1697108400@marketingeda.com
SUMMARY:The UCIe™ 1.1 Specification: Future Applications of Chiplets
DESCRIPTION:Presenter: Dr. Debendra Das Sharma\, UCIe Consortium Chairman and Intel Senior Fellow\, Chief Architect of I/O Technology and Standards at Intel  \n\n\nThe UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023\, delivering valuable improvements to the chiplet ecosystem\, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide an overview on enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation. 
URL:https://marketingeda.com/event/the-ucie-1-1-specification-future-applications-of-chiplets/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230908T182145Z
CREATED:20230908T182145Z
LAST-MODIFIED:20230908T182145Z
UID:6786-1697104800-1697108400@marketingeda.com
SUMMARY:Proactively Address Thermal Concerns in Advanced IC Packages
DESCRIPTION:The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals\, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. \nThis webinar will show how design teams that implement thermal mitigation strategies early in the design cycle are facing fewer thermal concerns with their IC package prototypes.  We will walk through a reference design and discuss how Cadence Advanced Package Designer Plus combined with Celsius Thermal Solver address feasibility during the design planning stage to the full-system final signoff. \nJoin our webinar to learn how you can: \n\nEfficiently address thermal concerns throughout the design cycle\nReduce design iterations\nProactively drive predictability into your design schedules
URL:https://marketingeda.com/event/proactively-address-thermal-concerns-in-advanced-ic-packages/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231011T090000
DTEND;TZID=America/Los_Angeles:20231011T100000
DTSTAMP:20231006T190044Z
CREATED:20231006T190044Z
LAST-MODIFIED:20231006T190044Z
UID:6919-1697014800-1697018400@marketingeda.com
SUMMARY:Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
DESCRIPTION:In this Webinar\, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors\, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  \n\n Key Takeaways: \n\nDiscover the inner workings of FPGA components: Processor\, Logic Elements\, AIE/Tensor\, and more.\nUnderstand latency and throughput trade-offs when using NoC vs. direct interfaces.\nLearn how different data cache sizes impact AIE Tile network utilization.\nDive into various mapping decisions and their effect on application throughput and power consumption.\n\n  \nSo\, what are you waiting for? Don’t miss this opportunity
URL:https://marketingeda.com/event/mapping-signal-processing-algorithms-on-amd-xilinx-versal-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20231010T080000
DTEND;TZID=Europe/Berlin:20231011T170000
DTSTAMP:20231004T162118Z
CREATED:20231004T162118Z
LAST-MODIFIED:20231004T162118Z
UID:6913-1696924800-1697043600@marketingeda.com
SUMMARY:CadenceLIVE Europe 2023
DESCRIPTION:CadenceLIVE Europe 2023 – experience the power of intelligent system design – brings together users\, developers\, and industry experts to network\, share ideas\, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nAttendees will be able to attend captivating keynotes\, watch user presentations packed full of innovation\, see new product demos\, and learn new ways to solve design challenges from industry leaders and Cadence experts. \nCadence® products\, solutions\, flow\, and techniques will be featured at the conference in the following areas: \n\nMultiphysics In-Design Analysis\nHeterogeneous Integration\nCustom IC / Mixed-Signal / RF\nDigital Full Flow\nPCB / Advanced Packaging\nVerification Hardware and Software\nWorkforce Development\n\nCadence customers and partners can attend the event for FREE. \nCheck out the agenda to see what’s in store.
URL:https://marketingeda.com/event/cadencelive-europe-2023/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230927T080000
DTEND;TZID=Europe/Berlin:20230928T170000
DTSTAMP:20230923T041526Z
CREATED:20230923T041526Z
LAST-MODIFIED:20230923T041526Z
UID:6865-1695801600-1695920400@marketingeda.com
SUMMARY:GTS 2023 - Munich
DESCRIPTION:Register now and join us at GlobalFoundries Technology Summit 2023! \nGF Technology Summit (GTS) 2023 is our worldwide\, annual series of technology-focused events. GTS brings together leaders from the commercial\, business and research worlds to understand the latest technology challenges and opportunities\, and partner to create the most innovative applications and solutions. \nGTS 2023 Highlights \nThis year’s GTS will focus on GF’s industry and technology differentiation\, highlighted by three key areas of innovation: \n\nPower\, power\, power – Ultra-low power technology platforms and applications\, power management and power delivery solutions\nBest RF wins – RF and mmWave connectivity solutions for mobile and infrastructure applications\nIntelligence & security – Localized\, low-power intelligent applications with secure eNVM\n\nGF’s market-focused development includes partnerships across the broad electronics ecosystem – OEM\, fabless\, OSAT\, EDA and IP. The results of those collaborations will be seen and heard in the guest keynote addresses\, detailed technology roadmaps\, hardware and software demonstrations\, and leading applications for automotive\, IoT\, smart mobile\, datacenter and communications infrastructure markets. \nNew in 2023! GF Technology\, Business and Commercial teams will be at GTS to host 1:1 and small group meetings during the event. Please consider if there is someone you would like to meet with during your time in Munich – requests will be submitted during the registration process. \n  \nGTS Program Overview \nDay One Programming: 12:00 – 16:00 Networking Hour to follow \nCEO Dr. Thomas Caulfield\, joined by leaders in the fabless semiconductor and end-markets industries\, shares GF’s corporate vision and roadmap of manufacturing the essential chips we rely on for life\, work and connection. \nDay Two Programming: 9:00 – 14:00 with Networking Reception to follow \nGF’s technology and product management leaders share the company’s detailed technology and solutions roadmap\, joined by leaders in the semiconductor design and manufacturing ecosystem – working together to deliver a new era of more.
URL:https://marketingeda.com/event/gts-2023-munich/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GTS-2023-Munich.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230926T100000
DTEND;TZID=America/Los_Angeles:20230926T110000
DTSTAMP:20230921T161238Z
CREATED:20230921T161238Z
LAST-MODIFIED:20230921T161238Z
UID:6847-1695722400-1695726000@marketingeda.com
SUMMARY:Unleashing Innovation with UCIe​​​​​​​​​​​​​​
DESCRIPTION:Exploring the Next Frontier in Chip Integration\nWebinar Agenda : \n\nIntroduction to all UCIe layers\nDecrypting FLITs\, PHY Trainings\, Bring up flows FDI-RDI \, main band and side band FLIT transfers etc.\nImplementation of Stacks-Arbiter\, Retry mechanism & Retimer implementations\nShowcasing UCie FLIT transfer flow between multidies\nEnhancements done in UCIe 1.1\n\nWho Should Attend: \n\nProfessionals working on development of UCIe VIP.\nPeople keen to know how UCie VIP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/unleashing-innovation-with-ucie/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-September-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Singapore:20230922T080000
DTEND;TZID=Asia/Singapore:20230922T170000
DTSTAMP:20230918T203029Z
CREATED:20230918T203029Z
LAST-MODIFIED:20230918T203029Z
UID:6817-1695369600-1695402000@marketingeda.com
SUMMARY:SNUG Singapore 2023
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nPresent at SNUG Singapore\n\n\n\n\n\n\n\n\n\n\nHave you used Synopsys technology to overcome difficult design issues or tackle one of those key challenges facing the industry. We’d like to hear from you! Showcase your work and share your experience with the community by submitting your proposal through the call for content process:
URL:https://marketingeda.com/event/snug-singapore-2023/
LOCATION:ParkRoyal on Beach Road\, 7500 Beach Rd\, Singapore\, Singapore
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Singapore-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T110000
DTEND;TZID=America/Los_Angeles:20230921T120000
DTSTAMP:20230908T171723Z
CREATED:20230908T171723Z
LAST-MODIFIED:20230908T171723Z
UID:6783-1695294000-1695297600@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T100000
DTEND;TZID=America/Los_Angeles:20230921T110000
DTSTAMP:20230920T184452Z
CREATED:20230920T184452Z
LAST-MODIFIED:20230920T184452Z
UID:6841-1695290400-1695294000@marketingeda.com
SUMMARY:Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
DESCRIPTION:The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using Synopsys VCS® as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the Bluespec processor core simulated with Synopsys VCS and the results are compared with Spike instruction set simulation (ISS) results. \n  \nThis presentation will showcase: \n\nA reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV.\nHow designers can leverage Synopsys VCS simulation and Synopsys Verdi® for debug and relevant advanced coverage methodology\, to help speed verification signoff.\nThe combination of RISCV-DV and Synopsys tools provides a powerful and flexible solution for RISC-V verification and highest coverage.\nDemo on the RISC-V verification solution on the Synopsys Cloud platform.\n\nWhether you are a chip verification architect or a verification engineer or a system designer\, this Synopsys webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar\n\n\nSenior Director\, Applications Engineering\nBluespec \n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar is Senior Director of Applications Engineering for Bluespec Inc. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development\, formal property verification\, and hardware emulation. He leads Application Engineering and Support for Bluespec. Bipul has a strong background in formal verification of RISC-V based cores/subsystems\, arm based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive\, Cadence\, Mentor Graphics (Siemens) and SmartDV Technologies give him a broad perspective on the myriad challenges faced by design and verification teams\, allowing him to partner with customers for success throughout product evaluations and deployment. Bipul holds a Bachelor of Science in Engineering\, Electronics\, and Telecommunication from India’s National Institute of Technology\, Silchar. He is based in San Jose\, California. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami\n\n\nApplications Engineer\, Senior Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami is an Application Engineer at Synopsys\, focusing on VCS and Verdi products. She also collaborates with the global RISC-V customers to showcase the Synopsys RISC-V solution. She has a background in design and verification with expertise in SoCs and subsystems. Prabha likes music\, reading and enjoys long walks.
URL:https://marketingeda.com/event/efficient-bluespec-risc-v-processor-verification-for-highest-coverage-closure-a-comprehensive-case-study/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Brussels:20230919T080000
DTEND;TZID=Europe/Brussels:20230921T170000
DTSTAMP:20230801T171626Z
CREATED:20230801T171626Z
LAST-MODIFIED:20230801T171626Z
UID:6634-1695110400-1695315600@marketingeda.com
SUMMARY:AutoSens Brussels 2023
DESCRIPTION:We’re bringing AutoSens to Autoworld in Brussels once again to meet and shape the future of ADAS and AV. \nYou can look forward to the freshest agenda of over 60 speakers across expert panels\, technical case studies\, and sessions covering 12 key themes. You will experience an exhibition full of demos from technology companies at the forefront of sensors and computer vision to explore. \nJoin us on 19-21 September 2023 at the Autoworld Museum in Brussels. \n\n\nWindshield Technology\n\n\n\n\nEvery vehicle has one\, but are they optimised for ADAS/AD? A plenary session will consider the challenges of light\, heat\, tilt and yaw\, measurement\, and other important factors when pairing cameras with windshields. \n\n\nInfrastructure\n\n\n\n\nA keynote session will explore infrastructure from a perception and observation perspective\, as well as the communication between vehicles and the world around them (V2I and V2X). \n\n\nCyber Security & Data Privacy\n\n\n\n\nWith L4 and L5 drawing closer\, we must consider the ‘hackability’ of vehicles more than ever before\, not only for occupant safety\, but to prevent (or at least minimise) the weaponisation of autonomous vehicles. 
URL:https://marketingeda.com/event/autosens-brussels-2023/
LOCATION:Autoworld Museum\, 1000 Brussels\, Brussels\, Belgium
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Brussels-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230915T080000
DTEND;TZID=Europe/Berlin:20230917T170000
DTSTAMP:20230522T195247Z
CREATED:20230522T195211Z
LAST-MODIFIED:20230522T195247Z
UID:6422-1694764800-1694970000@marketingeda.com
SUMMARY:ORConf 2023
DESCRIPTION:FOSSi Foundation are pleased to announce ORConf 2023 will be taking place in beautiful Munich\, Germany on September\, 15th to 17th\, 2023. It will start Friday morning and Sunday is currently reserved for tutorials and workshops. \n\nORConf is an annual conference for open source digital\, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space. \nWe invite anyone with an interest in the field to join us and also consider a presentation\, big or small\, on your experience as a developer or a user of open source digital design projects. \nORConf remains to be free to attend thanks to each year’s sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf! \nORConf is organized by the Free and Open Source Silicon (FOSSi) Foundation. \nQuestions? Contact the organisers. \nSubmit a talk\n\nWe encourage anyone involved in the open source semiconductor engineering space to come along and give share your work or experience. \nThis year we’re offering lightning talk and 15-minute speaking slots\, with the choice of opting in to be considered for an extended slot of 30-40 minutes. We are intentionally reducing the standard speaking slot length this year to ensure we can accommodate all of the exceptional talk submissions we receive\, and to maximize face-to-face time throughout the event. We encourage speakers to skip the technical deep-dive presentations and instead provide high-level introductions and overviews of what makes their work great\, and prepare a poster or hardware demo for people to come and discuss details during the breaks. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience.
URL:https://marketingeda.com/event/orconf-2023/
LOCATION:Hochschule Munchen University of Applied Sciences\, Lothstr. 64\, Munich\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Copenhagen:20230914T080000
DTEND;TZID=Europe/Copenhagen:20230914T170000
DTSTAMP:20230901T173607Z
CREATED:20230901T173607Z
LAST-MODIFIED:20230901T173607Z
UID:6773-1694678400-1694710800@marketingeda.com
SUMMARY:FPGAworld Conference 2023 - Copenhagen
DESCRIPTION:The FPGAworld Conference is an international forum for researchers\, engineers\, teachers\, students\, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems\, FPGA/ASIC-based products\, educational & industrial cases\, and more. Registration for attendees is free and includes 2*coffee\, lunch and go-home drink.
URL:https://marketingeda.com/event/fpgaworld-conference-2023-copenhagen-2/
LOCATION:DTU Science Park\, 2800 Kongens\, Lyngby\, Denmark
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGAworld-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230913T080000
DTEND;TZID=Asia/Kolkata:20230914T170000
DTSTAMP:20230907T175227Z
CREATED:20230727T164506Z
LAST-MODIFIED:20230907T175227Z
UID:6617-1694592000-1694710800@marketingeda.com
SUMMARY:DVCon India 2023
DESCRIPTION:On behalf of the DVCon India 2023 steering committee\, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference.  We want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThis year’s edition will have a good blend of Vision and Keynote talks\, lively panel discussions tutorials and technical sessions spread across both the days. We are looking at some of the feedback and see how to set an agenda that provides key takeaways to everyone at the conference. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling and New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co- verification. We want to remind you that this isn’t just a Verification conference\, but a Design AND Verification conference and we want to ensure that the Design community has greater participation. \nThis year\, we will be expanding our Technical Program Committee and we want to make it even stronger than what it is now. The entire team is planning and putting in the extra hours to ensure we deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, engage\, share learnings with the rest of the community and take an enthusiastic part in DVCon India 2023 and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2023
URL:https://marketingeda.com/event/dvcon-india-2023/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T100000
DTEND;TZID=America/Los_Angeles:20230912T110000
DTSTAMP:20230829T220653Z
CREATED:20230829T220628Z
LAST-MODIFIED:20230829T220653Z
UID:6759-1694512800-1694516400@marketingeda.com
SUMMARY:NoC IP- Transforming Chip Communication
DESCRIPTION:Webinar Agenda : \n\nIntroduction to Mesh and Crossbar Architecture\nCache Introduction\nSupport for latest AMBA 5\nSafety and security features as ASIL Standard.\nPort configurabilities\n\nWho Should Attend: \n\nProfessionals working on development of NoC IP.\nPeople keen to know how NoC IP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/noc-ip-transforming-chip-communication/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Webinar-Series-NoC-IP-01_02.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T080000
DTEND;TZID=America/Los_Angeles:20230914T170000
DTSTAMP:20230424T172221Z
CREATED:20230424T172221Z
LAST-MODIFIED:20230424T172221Z
UID:6320-1694505600-1694710800@marketingeda.com
SUMMARY:AI Hardware & Edge AI Summit
DESCRIPTION:The combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. \nFor Enterprise ML Experts: Attend a unique AI systems event that will give you both hardware and software tools and techniques for training\, deploying\, and serving machine learning – the program contains a mixture of state-of-the-art topics and practical tutorials\, so you know what is out there\, and what you can use. 40% of our audience are enterprise ML practitioners just like you! \nFor Technology Vendors: Attend the premier event for the AI infrastructure ecosystem\, which blends systems\, software\, tooling and applications for a unique proposition that focuses on making ML faster\, more efficient and more affordable. If your product fits into this category\, your peers and customers are here! \n2023 LUMINARY KEYNOTE ANNOUNCEMENTS\nAndrew Ng\, Founder & CEO\, Landing AI \nJim Keller\, CEO\, Tenstorrent
URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Summit-2023.jpg
ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T080000
DTEND;TZID=America/Los_Angeles:20230912T170000
DTSTAMP:20230719T195215Z
CREATED:20230719T195215Z
LAST-MODIFIED:20230719T195215Z
UID:6605-1694505600-1694538000@marketingeda.com
SUMMARY:CadenceLIVE Boston 2023
DESCRIPTION:CadenceLIVE Boston 2023 – experience the power of intelligent system design – brings together users\, developers\, and industry experts to network\, share ideas\, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nAttendees will be able to attend captivating keynotes\, watch user presentations packed full of innovation\, see new product demos\, and learn new ways to solve design challenges from industry leaders and Cadence experts. \nCadence® products\, solutions\, flow\, and techniques will be featured at the conference in the following areas: \n\nMultiphysics In-Design Analysis\nHeterogeneous Integration\nCustom IC / Mixed-Signal / RF\nDigital Full Flow\nPCB / Advanced Packaging\nVerification Hardware and Software\nWorkforce Development\n\nCadence customers and partners can attend the event for FREE. \nCheck out the agenda to see what’s in store. \nKeynote Speakers\nTom Beckley\nCadence\n\nThomas Smelker\nMercury Microsystems
URL:https://marketingeda.com/event/cadencelive-boston-2023/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Boston-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Stockholm:20230912T080000
DTEND;TZID=Europe/Stockholm:20230912T170000
DTSTAMP:20230216T012619Z
CREATED:20230216T011624Z
LAST-MODIFIED:20230216T012619Z
UID:5985-1694505600-1694538000@marketingeda.com
SUMMARY:FPGAworld Conference 2023 - Stockholm
DESCRIPTION:The FPGAworld Conference is an international forum for researchers\, engineers\, teachers\, students\, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems\, FPGA/ASIC-based products\, educational & industrial cases\, and more. Registration for attendees is free and includes 2*coffee\, lunch and go-home drink. \n\nKeynote Speaker Copenhagen and Stockholm 2023\n\n\nKeynote speaker: Martin Kellermann \, Microchip Technology GmbH\, Munich\n\n\nTitle: RISC-V: Paving the Path Together to a Safe\, Secure and Reliable Future\n\n\nAbstract: RISC-V is an open-source instruction set that has created opportunities for companies of all sizes to innovate and make decisions independently. It is predicted to shape the future of computing for the next 50 years by providing a processor architecture that allows for more processing with a smaller carbon footprint\, more features with less development resources\, and new ways to combat threats with existing technologies. Companies are already utilizing RISC-V to develop applications such as High-Performance Spaceflight Computing (HPSC) processors. This keynote will explore how companies can benefit from this independence and how the ecosystems can enable easy adoption and scalability. It will also highlight companies that are already a part of this revolution and discuss how they can help create a safe and secure future. Through RISC-V\, companies can reach their goals and protect their future. Together\, we can move mountains. \nCV: Martin Kellermann is an experienced FPGA and SoC engineer with a diploma in Electrical Engineering from the Landshut University of Applied Sciences. He has expertise in high-speed serial data transmission\, signal integrity\, and hardware debugging\, successfully delivering projects in the industrial\, automotive\, and data-center domains. As Marketing Manager at Microchip Technology GmbH\, Munich\, he works with the European Sales and Field Application team to showcase the strengths of their FPGAs and SoCs. \n\nKeynote Speakers Stockholm 2023\n\n\nKeynote speaker: Mark Frost\, Intel’s Programmable Solutions Group (previously Altera)\, England\n\n\nTitle: Key Factors for Success in Today’s and Tomorrow’s Markets\n\n\nAbstract: This presentation will explore the key areas that FPGA suppliers must consider in order to succeed: industry-leading supply chain management\, product leadership\, and an up-to-date developer experience. We will examine the current supply chain landscape\, which is facing an unprecedented imbalance in demand and supply\, leading to long lead times and product allocations. We will also discuss the need for FPGA companies to make strategic investments to achieve product leadership and remain competitive. Furthermore\, we will look at the importance of having up-to-date knowledge and skills\, fast and appropriate EDA tools\, the right SoCs\, and the right RTL\, SW\, and hardware IP from generation to generation for FPGA developers to be productive. The presentation will then provide an overview of the different options available to FPGA vendors\, preferred standards\, and flows. Finally\, we will look at how FPGA technology is being used in different parts of the world and provide a prediction of its future. \nCV: Mark is the FPGA Security and 5G Technical Marketing Manager within Intel’s Programmable Solutions Group (previously Altera). Within this role Mark liaises between customers\, sales and engineering teams worldwide for security and 5G communication topics\, and works to create market awareness of Intel’s portfolio. During his 11 years with Intel he has held roles in both marketing and as a field application engineer covering programmable technology. Prior to Intel\, Mark had worked for over 15 years in a variety of engineering roles\, spanning telecommunications through to designing instruments for ESA satellites. Mark has a BEng in Electrical Engineering from the University of Plymouth. \nSeptember 14 details in Copenhagen
URL:https://marketingeda.com/event/fpgaworld-conference-2023/
LOCATION:ÅF\, Frösundaleden 2A\, 169 70 Solna\, Sweden
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/FPGAworld-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20230907T080000
DTEND;TZID=Asia/Taipei:20230907T170000
DTSTAMP:20230406T174802Z
CREATED:20230406T174802Z
LAST-MODIFIED:20230406T174802Z
UID:6241-1694073600-1694106000@marketingeda.com
SUMMARY:DVCon Taiwan 2023
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. \nConference Sponsor: Accellera \nGlobal Sponsors: Synospys\, Cadence\, Siemens
URL:https://marketingeda.com/event/dvcon-taiwan-2023/
LOCATION:National Yang Ming Chiao Tung University\, 300\, Hsinchu City\, Taiwan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Taiwan-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230905T080000
DTEND;TZID=America/Los_Angeles:20230908T170000
DTSTAMP:20230413T202528Z
CREATED:20230413T202528Z
LAST-MODIFIED:20230413T202528Z
UID:6272-1693900800-1694192400@marketingeda.com
SUMMARY:IEEE SOCC 2023
DESCRIPTION:SoCs and SiPs for Edge Intelligence and Accelerated Computing \nSystem-on-Chip (SoC) and System-in-Package (SiP) devices\, comprising digital\, analog\, optical\, RF\, and Micro-Electro-Mechanical Systems (MEMS) are foundations of ubiquitous embedded high-performance computing (HPC). Such systems will provide solutions in communication\, entertainment\, medical and smart mobility technologies underpinning emerging “Digital Societies”. \nRecent advances in systems\, packaging and process technologies are enabling the computation of hundreds of teraflops per chip and chiplet system integration unleashing the massive rise of AI-based edge devices\, various accelerators\, new products and applications. This enormous demand for computing per silicon-based SoC and SiP integration creates new challenges with respect to storage\, memory\, security\, reliability\, power\, on- and off-chip communication\, packaging including reliable design and verification. \nFor over 35 years the IEEE International System-on-Chip Conference (SOCC) has been a premier forum for sharing latest advancements in SoC architectures\, systems\, logic and circuit design\, process technology\, test\, design tools\, and application scenarios. We consequently continue this tradition with the 2023 conference at the heart of Silicon Valley in Santa Clara\, CA. \nThe 36th SOCC offers a three days technical program including keynote and plenary speeches\, oral and poster presentations\, hot-topic panel sessions\, and one day of industrial talks. In addition\, SOCC has a long tradition of high-class social events complementing the technical program\, helping you to discuss your work with your colleagues\, and enhancing your professional network.
URL:https://marketingeda.com/event/ieee-socc-2023/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SOCC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230421T164718Z
CREATED:20230421T164718Z
LAST-MODIFIED:20230421T164718Z
UID:6311-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products. \nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse. \nAgenda:\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T100000
DTEND;TZID=America/Los_Angeles:20230831T110000
DTSTAMP:20230816T232407Z
CREATED:20230816T232407Z
LAST-MODIFIED:20230816T232407Z
UID:6717-1693476000-1693479600@marketingeda.com
SUMMARY:Accelerating Mainstream Adoption of Multi-Die Systems
DESCRIPTION:Synopsys recently hosted a panel discussion with Ansys\, Bosch\, Intel\, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology\, what challenges lie ahead\, and how companies can realize the promise of multi-die systems. Whether you are exploring multi-die systems or implementing the architecture in your current designs\, you’ll need the entire ecosystem across the semiconductor supply chain to help you make the adoption easier. Don’t miss the discussion. \nModerator: Marco Chiappetta\nHotTech Vision & Analysis​\nPrincipal Analyst​ \nPanelist: Murat Becer\nAnsys\nVice President\, Semiconductor R&D​ \nPanelist: Michael Schaffert\nBosch\nSenior Vice President E/E-Architecture​ \nPanelist: Lalitha Immaneni\nIntel\nVice President\, Architecture\, Design\, and Technology Solutions\, Technology Development \nPanelist: Cheolmin Park\nSamsung\nCorporate VP of AVP Business Development Team​ \nPanelist: Shekhar Kapoor\nSynopsys\nSenior Director of Product Line Management
URL:https://marketingeda.com/event/accelerating-mainstream-adoption-of-multi-die-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-203.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230830T110000
DTEND;TZID=America/Los_Angeles:20230830T120000
DTSTAMP:20230816T235150Z
CREATED:20230816T235150Z
LAST-MODIFIED:20230816T235150Z
UID:6724-1693393200-1693396800@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230827T080000
DTEND;TZID=America/Los_Angeles:20230829T170000
DTSTAMP:20230613T165859Z
CREATED:20230613T165859Z
LAST-MODIFIED:20230613T165859Z
UID:6490-1693123200-1693328400@marketingeda.com
SUMMARY:Hot Chips 2023
DESCRIPTION:Hot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29\, 2023. \nConference Format\nHot Chips 2023 will be a hybrid conference. You may register to attend virtual or in-person. The conference venue is the Dinkelspiel Auditorium on the Stanford University Conference. \n\nSunday (August 27) is a Tutorial Day.\nMonday and Tuesday (August 28 and 29) are Conference Days.\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs and Slack Channels for both Tutuorial and Conference Days. All talks are transmitted in real time and are also recorded so that you also may view them at a time convenient for your time zone. Details are here. \nIn-Person Conference: You may register for Conference Days only or both Conference and Tutorial Days. In either case you will have full access to Videos\, presentation PDFs and Slack channels. The conference fee includes breakfast\, lunch\, coffee breaks and receptions. Details are here.
URL:https://marketingeda.com/event/hot-chips-2023/
LOCATION:Stanford University\, 471 Lagunita Drive\, Stanford\, CA\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/14054931_10155065287553998_1856342906013349235_n.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230815T210853Z
CREATED:20230815T210838Z
LAST-MODIFIED:20230815T210853Z
UID:6706-1692784800-1692788400@marketingeda.com
SUMMARY:IP Lifecycle Management for Chiplet-Based SoCs
DESCRIPTION:Chiplet-based SoC architectures have seen increased interest over the past three years\, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups\, DoD projects\, and academic research. Chiplet-based architectures bring their own set of challenges however\, especially in the context of IP security. \nJoin Simon Butler\, founder of Methodics IPLM\, to learn best practices for managing IPs from inception through SoC integration\, including: \n\nEnsuring end-to-end traceability.\nManaging security concerns.\nEnforcing IP provenance.\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\nSimon Butler\n\nSimon Butler is the founder of Methodics Inc.\, acquired by Perforce in 2020. He is currently the General Manager of the Methodics IPLM business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to serve the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design.
URL:https://marketingeda.com/event/ip-lifecycle-management-for-chiplet-based-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Perforce-August-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230824T170000
DTSTAMP:20230802T171343Z
CREATED:20230802T171343Z
LAST-MODIFIED:20230802T171343Z
UID:6655-1692691200-1692896400@marketingeda.com
SUMMARY:ERI 2.0 Summit
DESCRIPTION:Watch as leaders from our government agencies\, the Defense Industrial Base\, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry\, national and economic security\, and future research directions. \nThe Electronics Resurgence Initiative (ERI)\, DARPA’s response to national-level microelectronics concerns\, is designed to ensure U.S. leadership in cross-functional\, next-generation microelectronics research\, development\, and manufacturing. The initiative\, aimed at both national security capabilities and commercial economic competitiveness and sustainability\, is a thematic portfolio of research programs primarily in the Microsystems Technology Office (MTO). These programs emphasize forward-looking partnerships with U.S. industry\, the defense industrial base\, and university researchers. \nDARPA expanded ERI’s focus with the announcement of ERI 2.0\, which seeks to reinvent domestic microelectronics manufacturing. ERI 2.0 will strengthen DARPA’s leadership in driving the next generation of microelectronics for national security by creating a national capability for 3DHI manufacturing and pursuing focused research in: \n\nManufacturing complex 3D systems\nDeveloping electronics for extreme environments\n\n…while maintaining the following thrust areas:\n  \n\nOptimizing design and test for complex circuits and prototypes\nOvercoming security threats across the entire hardware lifecycle\nIncreasing information processing density and efficiency\nAccelerating innovation in artificial intelligence hardware to make decisions at the edge faster\nSecuring communications
URL:https://marketingeda.com/event/eri-2-0-summit/
LOCATION:Hyatt Regency Seattle\, 805 Howell Street\, Seattle\, WA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ERI-2.0.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230809T080000
DTEND;TZID=Asia/Kolkata:20230810T170000
DTSTAMP:20230807T163442Z
CREATED:20230807T163442Z
LAST-MODIFIED:20230807T163442Z
UID:6683-1691568000-1691686800@marketingeda.com
SUMMARY:CadenceLIVE India
DESCRIPTION:CadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \n  \nKeynote Speakers \n\n\n\n\n\n\nNimish Modi\nSVP and GM – Strategy & New Ventures\, Cadence \n\n\n\n\n\n\nAlok Jain\nCorporate VP – System Verification Group\, Cadence \n\n\n\n\n\n\nVenugopal Puvvada\nVice-President\, Engineering\, Qualcomm \n\n\n\n\n\n\nHuzefa Cutlerywala\nSVP – WW Sales and Marketing\, Tessolve
URL:https://marketingeda.com/event/cadencelive-india/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-India-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T083000
DTEND;TZID=America/Los_Angeles:20230808T091500
DTSTAMP:20230801T170422Z
CREATED:20230801T170422Z
LAST-MODIFIED:20230801T170422Z
UID:6631-1691483400-1691486100@marketingeda.com
SUMMARY:Deliver Next-gen Smartphones
DESCRIPTION:Stefan Rosinger\, Senior Director\, Product Management – Arm \n\n\nAbout this talk\nJoin us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion\, AI intelligence and security while promoting greater efficiency in their mobiles\, laptops\, home\, and wearable devices. We will cover:\n\n-How Cortex-X4 achieves double-digit performance gains\, as well as great efficiency\n-Cortex-A720 & Cortex-A520 processor efficiency gains\, and how they are benefitting not just flagship but also mid-range and entry-level devices\n-The performance\, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)\n-How the cluster is being utilized for AI and other new demanding workloads\n-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance
URL:https://marketingeda.com/event/deliver-next-gen-smartphones/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-August-8-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T080000
DTEND;TZID=America/Los_Angeles:20230810T170000
DTSTAMP:20230726T200743Z
CREATED:20230726T200648Z
LAST-MODIFIED:20230726T200743Z
UID:6612-1691481600-1691686800@marketingeda.com
SUMMARY:Flash Memory Summit
DESCRIPTION:Why Attend Flash Memory Summit?\nFlash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions The scope of FMS23 will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nWhy You Should Participate\n• Establish your company as a leader in the emerging memory and storage market.\n• Display your products and expertise to an audience known to be interested in memory and storage.\n• Promote memory and storage to a wider market of equipment manufacturers\, solution providers\, system integrators\, consultants. \nHow You Can Participate:\n• Attend: Register online for the sessions\n• Exhibit: Promote your latest products – exhibit booths\n• Sponsor: Receive special recognition both at the event and in publicity\n• Present: Display your knowledge and commitment to flash memory
URL:https://marketingeda.com/event/flash-memory-summit-2/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2023.jpg
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