BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.2//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Stockholm
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Taipei
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Vienna
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Budapest
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230913T080000
DTEND;TZID=Asia/Kolkata:20230914T170000
DTSTAMP:20230907T175227Z
CREATED:20230727T164506Z
LAST-MODIFIED:20230907T175227Z
UID:6617-1694592000-1694710800@marketingeda.com
SUMMARY:DVCon India 2023
DESCRIPTION:On behalf of the DVCon India 2023 steering committee\, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference.  We want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThis year’s edition will have a good blend of Vision and Keynote talks\, lively panel discussions tutorials and technical sessions spread across both the days. We are looking at some of the feedback and see how to set an agenda that provides key takeaways to everyone at the conference. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling and New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co- verification. We want to remind you that this isn’t just a Verification conference\, but a Design AND Verification conference and we want to ensure that the Design community has greater participation. \nThis year\, we will be expanding our Technical Program Committee and we want to make it even stronger than what it is now. The entire team is planning and putting in the extra hours to ensure we deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, engage\, share learnings with the rest of the community and take an enthusiastic part in DVCon India 2023 and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2023
URL:https://marketingeda.com/event/dvcon-india-2023/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T100000
DTEND;TZID=America/Los_Angeles:20230912T110000
DTSTAMP:20230829T220653Z
CREATED:20230829T220628Z
LAST-MODIFIED:20230829T220653Z
UID:6759-1694512800-1694516400@marketingeda.com
SUMMARY:NoC IP- Transforming Chip Communication
DESCRIPTION:Webinar Agenda : \n\nIntroduction to Mesh and Crossbar Architecture\nCache Introduction\nSupport for latest AMBA 5\nSafety and security features as ASIL Standard.\nPort configurabilities\n\nWho Should Attend: \n\nProfessionals working on development of NoC IP.\nPeople keen to know how NoC IP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/noc-ip-transforming-chip-communication/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Webinar-Series-NoC-IP-01_02.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T080000
DTEND;TZID=America/Los_Angeles:20230914T170000
DTSTAMP:20230424T172221Z
CREATED:20230424T172221Z
LAST-MODIFIED:20230424T172221Z
UID:6320-1694505600-1694710800@marketingeda.com
SUMMARY:AI Hardware & Edge AI Summit
DESCRIPTION:The combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. \nFor Enterprise ML Experts: Attend a unique AI systems event that will give you both hardware and software tools and techniques for training\, deploying\, and serving machine learning – the program contains a mixture of state-of-the-art topics and practical tutorials\, so you know what is out there\, and what you can use. 40% of our audience are enterprise ML practitioners just like you! \nFor Technology Vendors: Attend the premier event for the AI infrastructure ecosystem\, which blends systems\, software\, tooling and applications for a unique proposition that focuses on making ML faster\, more efficient and more affordable. If your product fits into this category\, your peers and customers are here! \n2023 LUMINARY KEYNOTE ANNOUNCEMENTS\nAndrew Ng\, Founder & CEO\, Landing AI \nJim Keller\, CEO\, Tenstorrent
URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Summit-2023.jpg
ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T080000
DTEND;TZID=America/Los_Angeles:20230912T170000
DTSTAMP:20230719T195215Z
CREATED:20230719T195215Z
LAST-MODIFIED:20230719T195215Z
UID:6605-1694505600-1694538000@marketingeda.com
SUMMARY:CadenceLIVE Boston 2023
DESCRIPTION:CadenceLIVE Boston 2023 – experience the power of intelligent system design – brings together users\, developers\, and industry experts to network\, share ideas\, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nAttendees will be able to attend captivating keynotes\, watch user presentations packed full of innovation\, see new product demos\, and learn new ways to solve design challenges from industry leaders and Cadence experts. \nCadence® products\, solutions\, flow\, and techniques will be featured at the conference in the following areas: \n\nMultiphysics In-Design Analysis\nHeterogeneous Integration\nCustom IC / Mixed-Signal / RF\nDigital Full Flow\nPCB / Advanced Packaging\nVerification Hardware and Software\nWorkforce Development\n\nCadence customers and partners can attend the event for FREE. \nCheck out the agenda to see what’s in store. \nKeynote Speakers\nTom Beckley\nCadence\n\nThomas Smelker\nMercury Microsystems
URL:https://marketingeda.com/event/cadencelive-boston-2023/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Boston-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Stockholm:20230912T080000
DTEND;TZID=Europe/Stockholm:20230912T170000
DTSTAMP:20230216T012619Z
CREATED:20230216T011624Z
LAST-MODIFIED:20230216T012619Z
UID:5985-1694505600-1694538000@marketingeda.com
SUMMARY:FPGAworld Conference 2023 - Stockholm
DESCRIPTION:The FPGAworld Conference is an international forum for researchers\, engineers\, teachers\, students\, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems\, FPGA/ASIC-based products\, educational & industrial cases\, and more. Registration for attendees is free and includes 2*coffee\, lunch and go-home drink. \n\nKeynote Speaker Copenhagen and Stockholm 2023\n\n\nKeynote speaker: Martin Kellermann \, Microchip Technology GmbH\, Munich\n\n\nTitle: RISC-V: Paving the Path Together to a Safe\, Secure and Reliable Future\n\n\nAbstract: RISC-V is an open-source instruction set that has created opportunities for companies of all sizes to innovate and make decisions independently. It is predicted to shape the future of computing for the next 50 years by providing a processor architecture that allows for more processing with a smaller carbon footprint\, more features with less development resources\, and new ways to combat threats with existing technologies. Companies are already utilizing RISC-V to develop applications such as High-Performance Spaceflight Computing (HPSC) processors. This keynote will explore how companies can benefit from this independence and how the ecosystems can enable easy adoption and scalability. It will also highlight companies that are already a part of this revolution and discuss how they can help create a safe and secure future. Through RISC-V\, companies can reach their goals and protect their future. Together\, we can move mountains. \nCV: Martin Kellermann is an experienced FPGA and SoC engineer with a diploma in Electrical Engineering from the Landshut University of Applied Sciences. He has expertise in high-speed serial data transmission\, signal integrity\, and hardware debugging\, successfully delivering projects in the industrial\, automotive\, and data-center domains. As Marketing Manager at Microchip Technology GmbH\, Munich\, he works with the European Sales and Field Application team to showcase the strengths of their FPGAs and SoCs. \n\nKeynote Speakers Stockholm 2023\n\n\nKeynote speaker: Mark Frost\, Intel’s Programmable Solutions Group (previously Altera)\, England\n\n\nTitle: Key Factors for Success in Today’s and Tomorrow’s Markets\n\n\nAbstract: This presentation will explore the key areas that FPGA suppliers must consider in order to succeed: industry-leading supply chain management\, product leadership\, and an up-to-date developer experience. We will examine the current supply chain landscape\, which is facing an unprecedented imbalance in demand and supply\, leading to long lead times and product allocations. We will also discuss the need for FPGA companies to make strategic investments to achieve product leadership and remain competitive. Furthermore\, we will look at the importance of having up-to-date knowledge and skills\, fast and appropriate EDA tools\, the right SoCs\, and the right RTL\, SW\, and hardware IP from generation to generation for FPGA developers to be productive. The presentation will then provide an overview of the different options available to FPGA vendors\, preferred standards\, and flows. Finally\, we will look at how FPGA technology is being used in different parts of the world and provide a prediction of its future. \nCV: Mark is the FPGA Security and 5G Technical Marketing Manager within Intel’s Programmable Solutions Group (previously Altera). Within this role Mark liaises between customers\, sales and engineering teams worldwide for security and 5G communication topics\, and works to create market awareness of Intel’s portfolio. During his 11 years with Intel he has held roles in both marketing and as a field application engineer covering programmable technology. Prior to Intel\, Mark had worked for over 15 years in a variety of engineering roles\, spanning telecommunications through to designing instruments for ESA satellites. Mark has a BEng in Electrical Engineering from the University of Plymouth. \nSeptember 14 details in Copenhagen
URL:https://marketingeda.com/event/fpgaworld-conference-2023/
LOCATION:ÅF\, Frösundaleden 2A\, 169 70 Solna\, Sweden
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/FPGAworld-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20230907T080000
DTEND;TZID=Asia/Taipei:20230907T170000
DTSTAMP:20230406T174802Z
CREATED:20230406T174802Z
LAST-MODIFIED:20230406T174802Z
UID:6241-1694073600-1694106000@marketingeda.com
SUMMARY:DVCon Taiwan 2023
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. \nConference Sponsor: Accellera \nGlobal Sponsors: Synospys\, Cadence\, Siemens
URL:https://marketingeda.com/event/dvcon-taiwan-2023/
LOCATION:National Yang Ming Chiao Tung University\, 300\, Hsinchu City\, Taiwan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Taiwan-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230905T080000
DTEND;TZID=America/Los_Angeles:20230908T170000
DTSTAMP:20230413T202528Z
CREATED:20230413T202528Z
LAST-MODIFIED:20230413T202528Z
UID:6272-1693900800-1694192400@marketingeda.com
SUMMARY:IEEE SOCC 2023
DESCRIPTION:SoCs and SiPs for Edge Intelligence and Accelerated Computing \nSystem-on-Chip (SoC) and System-in-Package (SiP) devices\, comprising digital\, analog\, optical\, RF\, and Micro-Electro-Mechanical Systems (MEMS) are foundations of ubiquitous embedded high-performance computing (HPC). Such systems will provide solutions in communication\, entertainment\, medical and smart mobility technologies underpinning emerging “Digital Societies”. \nRecent advances in systems\, packaging and process technologies are enabling the computation of hundreds of teraflops per chip and chiplet system integration unleashing the massive rise of AI-based edge devices\, various accelerators\, new products and applications. This enormous demand for computing per silicon-based SoC and SiP integration creates new challenges with respect to storage\, memory\, security\, reliability\, power\, on- and off-chip communication\, packaging including reliable design and verification. \nFor over 35 years the IEEE International System-on-Chip Conference (SOCC) has been a premier forum for sharing latest advancements in SoC architectures\, systems\, logic and circuit design\, process technology\, test\, design tools\, and application scenarios. We consequently continue this tradition with the 2023 conference at the heart of Silicon Valley in Santa Clara\, CA. \nThe 36th SOCC offers a three days technical program including keynote and plenary speeches\, oral and poster presentations\, hot-topic panel sessions\, and one day of industrial talks. In addition\, SOCC has a long tradition of high-class social events complementing the technical program\, helping you to discuss your work with your colleagues\, and enhancing your professional network.
URL:https://marketingeda.com/event/ieee-socc-2023/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SOCC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230421T164718Z
CREATED:20230421T164718Z
LAST-MODIFIED:20230421T164718Z
UID:6311-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products. \nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse. \nAgenda:\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T100000
DTEND;TZID=America/Los_Angeles:20230831T110000
DTSTAMP:20230816T232407Z
CREATED:20230816T232407Z
LAST-MODIFIED:20230816T232407Z
UID:6717-1693476000-1693479600@marketingeda.com
SUMMARY:Accelerating Mainstream Adoption of Multi-Die Systems
DESCRIPTION:Synopsys recently hosted a panel discussion with Ansys\, Bosch\, Intel\, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology\, what challenges lie ahead\, and how companies can realize the promise of multi-die systems. Whether you are exploring multi-die systems or implementing the architecture in your current designs\, you’ll need the entire ecosystem across the semiconductor supply chain to help you make the adoption easier. Don’t miss the discussion. \nModerator: Marco Chiappetta\nHotTech Vision & Analysis​\nPrincipal Analyst​ \nPanelist: Murat Becer\nAnsys\nVice President\, Semiconductor R&D​ \nPanelist: Michael Schaffert\nBosch\nSenior Vice President E/E-Architecture​ \nPanelist: Lalitha Immaneni\nIntel\nVice President\, Architecture\, Design\, and Technology Solutions\, Technology Development \nPanelist: Cheolmin Park\nSamsung\nCorporate VP of AVP Business Development Team​ \nPanelist: Shekhar Kapoor\nSynopsys\nSenior Director of Product Line Management
URL:https://marketingeda.com/event/accelerating-mainstream-adoption-of-multi-die-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-203.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230830T110000
DTEND;TZID=America/Los_Angeles:20230830T120000
DTSTAMP:20230816T235150Z
CREATED:20230816T235150Z
LAST-MODIFIED:20230816T235150Z
UID:6724-1693393200-1693396800@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230827T080000
DTEND;TZID=America/Los_Angeles:20230829T170000
DTSTAMP:20230613T165859Z
CREATED:20230613T165859Z
LAST-MODIFIED:20230613T165859Z
UID:6490-1693123200-1693328400@marketingeda.com
SUMMARY:Hot Chips 2023
DESCRIPTION:Hot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29\, 2023. \nConference Format\nHot Chips 2023 will be a hybrid conference. You may register to attend virtual or in-person. The conference venue is the Dinkelspiel Auditorium on the Stanford University Conference. \n\nSunday (August 27) is a Tutorial Day.\nMonday and Tuesday (August 28 and 29) are Conference Days.\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs and Slack Channels for both Tutuorial and Conference Days. All talks are transmitted in real time and are also recorded so that you also may view them at a time convenient for your time zone. Details are here. \nIn-Person Conference: You may register for Conference Days only or both Conference and Tutorial Days. In either case you will have full access to Videos\, presentation PDFs and Slack channels. The conference fee includes breakfast\, lunch\, coffee breaks and receptions. Details are here.
URL:https://marketingeda.com/event/hot-chips-2023/
LOCATION:Stanford University\, 471 Lagunita Drive\, Stanford\, CA\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/14054931_10155065287553998_1856342906013349235_n.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230815T210853Z
CREATED:20230815T210838Z
LAST-MODIFIED:20230815T210853Z
UID:6706-1692784800-1692788400@marketingeda.com
SUMMARY:IP Lifecycle Management for Chiplet-Based SoCs
DESCRIPTION:Chiplet-based SoC architectures have seen increased interest over the past three years\, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups\, DoD projects\, and academic research. Chiplet-based architectures bring their own set of challenges however\, especially in the context of IP security. \nJoin Simon Butler\, founder of Methodics IPLM\, to learn best practices for managing IPs from inception through SoC integration\, including: \n\nEnsuring end-to-end traceability.\nManaging security concerns.\nEnforcing IP provenance.\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\nSimon Butler\n\nSimon Butler is the founder of Methodics Inc.\, acquired by Perforce in 2020. He is currently the General Manager of the Methodics IPLM business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to serve the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design.
URL:https://marketingeda.com/event/ip-lifecycle-management-for-chiplet-based-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Perforce-August-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230824T170000
DTSTAMP:20230802T171343Z
CREATED:20230802T171343Z
LAST-MODIFIED:20230802T171343Z
UID:6655-1692691200-1692896400@marketingeda.com
SUMMARY:ERI 2.0 Summit
DESCRIPTION:Watch as leaders from our government agencies\, the Defense Industrial Base\, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry\, national and economic security\, and future research directions. \nThe Electronics Resurgence Initiative (ERI)\, DARPA’s response to national-level microelectronics concerns\, is designed to ensure U.S. leadership in cross-functional\, next-generation microelectronics research\, development\, and manufacturing. The initiative\, aimed at both national security capabilities and commercial economic competitiveness and sustainability\, is a thematic portfolio of research programs primarily in the Microsystems Technology Office (MTO). These programs emphasize forward-looking partnerships with U.S. industry\, the defense industrial base\, and university researchers. \nDARPA expanded ERI’s focus with the announcement of ERI 2.0\, which seeks to reinvent domestic microelectronics manufacturing. ERI 2.0 will strengthen DARPA’s leadership in driving the next generation of microelectronics for national security by creating a national capability for 3DHI manufacturing and pursuing focused research in: \n\nManufacturing complex 3D systems\nDeveloping electronics for extreme environments\n\n…while maintaining the following thrust areas:\n  \n\nOptimizing design and test for complex circuits and prototypes\nOvercoming security threats across the entire hardware lifecycle\nIncreasing information processing density and efficiency\nAccelerating innovation in artificial intelligence hardware to make decisions at the edge faster\nSecuring communications
URL:https://marketingeda.com/event/eri-2-0-summit/
LOCATION:Hyatt Regency Seattle\, 805 Howell Street\, Seattle\, WA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ERI-2.0.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230809T080000
DTEND;TZID=Asia/Kolkata:20230810T170000
DTSTAMP:20230807T163442Z
CREATED:20230807T163442Z
LAST-MODIFIED:20230807T163442Z
UID:6683-1691568000-1691686800@marketingeda.com
SUMMARY:CadenceLIVE India
DESCRIPTION:CadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \n  \nKeynote Speakers \n\n\n\n\n\n\nNimish Modi\nSVP and GM – Strategy & New Ventures\, Cadence \n\n\n\n\n\n\nAlok Jain\nCorporate VP – System Verification Group\, Cadence \n\n\n\n\n\n\nVenugopal Puvvada\nVice-President\, Engineering\, Qualcomm \n\n\n\n\n\n\nHuzefa Cutlerywala\nSVP – WW Sales and Marketing\, Tessolve
URL:https://marketingeda.com/event/cadencelive-india/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-India-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T083000
DTEND;TZID=America/Los_Angeles:20230808T091500
DTSTAMP:20230801T170422Z
CREATED:20230801T170422Z
LAST-MODIFIED:20230801T170422Z
UID:6631-1691483400-1691486100@marketingeda.com
SUMMARY:Deliver Next-gen Smartphones
DESCRIPTION:Stefan Rosinger\, Senior Director\, Product Management – Arm \n\n\nAbout this talk\nJoin us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion\, AI intelligence and security while promoting greater efficiency in their mobiles\, laptops\, home\, and wearable devices. We will cover:\n\n-How Cortex-X4 achieves double-digit performance gains\, as well as great efficiency\n-Cortex-A720 & Cortex-A520 processor efficiency gains\, and how they are benefitting not just flagship but also mid-range and entry-level devices\n-The performance\, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)\n-How the cluster is being utilized for AI and other new demanding workloads\n-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance
URL:https://marketingeda.com/event/deliver-next-gen-smartphones/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-August-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T080000
DTEND;TZID=America/Los_Angeles:20230810T170000
DTSTAMP:20230726T200743Z
CREATED:20230726T200648Z
LAST-MODIFIED:20230726T200743Z
UID:6612-1691481600-1691686800@marketingeda.com
SUMMARY:Flash Memory Summit
DESCRIPTION:Why Attend Flash Memory Summit?\nFlash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions The scope of FMS23 will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nWhy You Should Participate\n• Establish your company as a leader in the emerging memory and storage market.\n• Display your products and expertise to an audience known to be interested in memory and storage.\n• Promote memory and storage to a wider market of equipment manufacturers\, solution providers\, system integrators\, consultants. \nHow You Can Participate:\n• Attend: Register online for the sessions\n• Exhibit: Promote your latest products – exhibit booths\n• Sponsor: Receive special recognition both at the event and in publicity\n• Present: Display your knowledge and commitment to flash memory
URL:https://marketingeda.com/event/flash-memory-summit-2/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Vienna:20230807T080000
DTEND;TZID=Europe/Vienna:20230808T170000
DTSTAMP:20230207T013618Z
CREATED:20230207T013618Z
LAST-MODIFIED:20230207T013618Z
UID:5914-1691395200-1691514000@marketingeda.com
SUMMARY:ISPLED 2023
DESCRIPTION:The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design\, ranging from process technologies and analog/digital circuits\, simulation and synthesis tools\, system-level design and optimization\, to system software and applications. \n  \n 
URL:https://marketingeda.com/event/ispled-2023/
LOCATION:TU Wien\, Gußhausstraße 27-29/384\, Vienna\, Austria
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISLPED-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T100000
DTEND;TZID=America/Los_Angeles:20230718T110000
DTSTAMP:20230713T200623Z
CREATED:20230713T200623Z
LAST-MODIFIED:20230713T200623Z
UID:6592-1689674400-1689678000@marketingeda.com
SUMMARY:Key MAC Considerations for the Road to 1.6T Ethernet Success
DESCRIPTION:224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations\, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions\, timing considerations\, and forward error correction.  We will shed light on key challenges for bandwidth hungry applications including latency optimization\, and SI techniques. Discover how Synopsys MAC IP solutions can help ensure your product is first to market. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys’ Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. \nPrior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\nJon Ames\n\n\nSr. Staff Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJon Ames is a Sr. Staff Product Marketing Manager for the Synopsys Ethernet Controller IP portfolio.  Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies.  Since graduating in Computer Science and Electronic Engineering the in UK\, Jon has worked at the leading companies in the networking and silicon solution industries.
URL:https://marketingeda.com/event/key-mac-considerations-for-the-road-to-1-6t-ethernet-success/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T080000
DTEND;TZID=America/Los_Angeles:20230719T170000
DTSTAMP:20230630T191347Z
CREATED:20230630T191347Z
LAST-MODIFIED:20230630T191347Z
UID:6568-1689667200-1689786000@marketingeda.com
SUMMARY:Rambus Design Summit 2023
DESCRIPTION:Back for its fourth year\, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center\, AI/ML\, automotive and IoT applications. \n\n\nAgenda + Abstracts\n\n\n\n\n\nRambus Design Summit will take place over two days\, with day one focusing on memory & interface solutions\, and day two on security solutions. Take a look at the agenda below – all times in Pacific Daylight Time (PDT). \n\n\n\n\n\n\n\nTuesday\, July 18: Memory & Interface Solutions\n\nTackling advanced data center workloads requires ever increasing levels of memory bandwidth and capacity\, as well as high-speed interconnects. Hear Rambus technology experts share their insights on future memory and interconnect requirements in the data center covering critical enabling technologies including DDR5\, HBM3\, PCIe 6.0\, GDDR6\, LPDDR5X\, CXL\, and MIPI/VESA video compression. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: CXL Technology: Revolutionizing the Data Center \nSpeaker: Mark Orthodoxou\, Vice President of Strategic Marketing\nAbstract: The need for more memory bandwidth and capacity continues to rise\, with applications like generative AI pushing current data center infrastructure to the limit. The leading companies at every level of the data center value chain are coalescing around CXL technology as a path to revolutionize the data center. Join Mark Orthodoxou to hear how CXL promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage\, as well as enabling new tiered-memory solutions and composable architectures.\n\n\n8:30am\nInnovations in CXL 3.0: Novel Device Types\, Capabilities\, and Interconnects \nSpeaker: Danny Moore\, Senior Product Marketing Manager\nAbstract: CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type\, CXL Multi-Headed Devices\, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.\n\n\n9:00am\nSystem Level Design Considerations for PCIe 6.0 \nSpeaker: Lou Ternullo\, Senior Director of Product Marketing\nAbstract: PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate\, PAM4 signaling\, forward error correction\, and a low power L0p mode. In this presentation\, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design\, including how to get the most out of each of the PCIe devices.\n\n\n9:30am\nLeveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays \nSpeakers: Simon Bussières\, Director of Systems Architecture\nJoe Rodriguez\, Product Marketing Manager\nAbstract: Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions\, faster refresh rates\, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality\, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.\n\n\n10:00am\nMeeting the Needs of Generative AI Training with HBM3 \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI training models are growing in both size and sophistication at a lightning pace\, requiring more and more bandwidth. With its unique 2.5D/3D architecture\, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.\n\n\n10:30am\nPowering AI/ML Inference with GDDR6 Memory \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: GDDR6 memory offers an impressive combination of bandwidth\, capacity\, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.\n\n\n11:00am\nLPDDR5X: Delivering High Bandwidth and Power Efficiency \nSpeaker: Vinitha Seevaratnam\, Senior Product Marketing Manager\nAbstract: The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT\, automotive\, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.\n\n\n11:30am\nWhat’s Next for DDR5 Memory? \nSpeaker: John Eble\, Vice President of Product Marketing\nAbstract: With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory\, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels\, be deployed in new applications beyond RDIMMs\, and how it is tailored for client computing systems.\n\n\n12:00pm\nHigh-Performance Memory: Ask Me Anything \nSpeakers: Tim Messegee\, Senior Director of Solutions Marketing\nSteven Woo\, Fellow and Distinguished Inventor\nJohn Eble\, Vice President of Product Marketing\nMark Orthodoxou\, Vice President of Strategic Marketing\nFrank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI is just one of the many applications driving the relentless need for better memory performance\, capacity and efficiency in the data center. Join our experts as they discuss some of the biggest memory challenges facing the industry today\, contemplate how the industry will innovate to meet future data center memory needs\, and answer all your questions!\n\n\n\n\n\n\nWednesday\, July 19: Security Solutions\n\nSecurity anchored in hardware provides the foundation for protecting data and devices at all stages of the semiconductor lifecycle. Join Rambus Security experts as they share their insights on security threats facing the industry including those that will arise in the era of quantum computers. Learn how you can protect hardware and data at rest\, in motion and in use with Root of Trust\, MACsec\, Inline Memory Encryption\, and more. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: Emerging Security Challenges in Highly Interconnected Semiconductor Systems \nSpeaker: Neeraj Paliwal\, VP General Manager\nAbstract: The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity\, reliability\, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats\, such as supply chain attacks\, intellectual property theft\, hardware Trojans\, side-channel attacks\, fault injection attacks\, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.\n\n\n8:30am\nSelecting the right Root of Trust HSM Design for Your Next Project \nSpeaker: Bart Stevens\, Senior Director of Product Marketing\nAbstract: A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation\, Bart Stevens will guide you through the labyrinth of Root of Trust designs\, including what problems they can solve and what solutions are available to implement in your next silicon design.\n\n\n9:00am\nProtecting Devices and Data in the Quantum Era \nSpeakers: Gijs Willemse\, Senior Director of Product Management\nAbstract: Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods\, that is\, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.\n\n\n9:30am\nHardware Security: Ask Me Anything \nSpeaker: Tim Messegee\, Senior Director of Solutions Marketing\nBart Stevens\, Senior Director of Product Marketing\nGijs Willemse\, Senior Director of Product Management\nScott Best\, Senior Technical Director\nAbstract: Whether it’s security technology trends\, the threat of quantum computers\, implementation issues or anything in between\, our security experts are ready to tackle your questions in this Ask Me Anything session.\n\n\n10:00am\nSecuring MCUs with SCA Protection in IoT Designs \nSpeaker: Marcel Van Loon\, Senior Principal Engineer Systems Architecture\nAbstract: A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.\n\n\n10:30am\nCybersecurity: A Top Priority for the Automotive Industry \nSpeaker: Adiel Bahrouch\, Director of Business Development\nAbstract: Automotive systems\, and the semiconductors used within them\, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation\, while meeting the safety and security requirements unique to the automotive industry.\n\n\n11:00am\nThe Convergence of MACsec and IPsec in Data Center Silicon Designs \nSpeaker: Maxim Demchenko\, Technical Director\nAbstract: Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.\n\n\n11:30am\nMemory Encryption for Data in Use Protection to Enable Confidential Computing in Data Center Designs \nSpeaker: Ajay Kapoor\, Senior Principal Engineer Systems Architecture\nAbstract: There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.\n\n\n12:00pm\nSecuring the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management \nSpeaker: Matt Orzen\, Technical Director Systems Architecture\nAbstract: The semiconductor industry is the lifeblood of the digital economy. The design\, manufacturing and consumption of chips is a global ecosystem\, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability\, functionality\, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon\, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.
URL:https://marketingeda.com/event/rambus-design-summit-2023/
CATEGORIES:IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-July-18-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230704T080000
DTEND;TZID=Europe/Paris:20230706T170000
DTSTAMP:20230120T171956Z
CREATED:20230120T171956Z
LAST-MODIFIED:20230120T171956Z
UID:5862-1688457600-1688662800@marketingeda.com
SUMMARY:FPGA Conference Europe 2023
DESCRIPTION:FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. \nThe FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is addressing that progress across all major manufacturers. It focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. At this year’s event\, one focus is on the energy efficiency of flexible logic devices. This applies in particular to small\, low-power components that rely on special production techniques or deliberately have only a limited number of programmable cells. \nPGAs belong to the hidden champions of microelectronics and are at the forefront of embedded development. From tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed on the FPGA Conference.
URL:https://marketingeda.com/event/fpga-conference-europe-2023/
LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Budapest:20230629T080000
DTEND;TZID=Europe/Budapest:20230630T170000
DTSTAMP:20230620T163638Z
CREATED:20230620T163638Z
LAST-MODIFIED:20230620T163638Z
UID:6532-1688025600-1688144400@marketingeda.com
SUMMARY:30th MIXDES Conference
DESCRIPTION:The aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design\, modeling\, simulation\, testing and manufacturing in various areas such as micro- and nanoelectronics\, semiconductors\, sensors\, actuators and power devices.\nThe MIXDES conference papers will be submitted for inclusion into IEEE Xplore\, subject to IEEE Xplore’s scope and quality requirements.
URL:https://marketingeda.com/event/30th-mixdes-conference/
LOCATION:Lodz Univesity of Technology\, Wólczańska 221/223\, Lodz\, Poland
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MIXDES-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230627T093000
DTEND;TZID=America/Los_Angeles:20230627T170000
DTSTAMP:20230523T005957Z
CREATED:20230523T005957Z
LAST-MODIFIED:20230523T005957Z
UID:6427-1687858200-1687885200@marketingeda.com
SUMMARY:2023 Andes RISC-V CON
DESCRIPTION:RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive\, data center\, communications\, and IoT. Its open-source instruction set architecture (ISA) provides higher performance\, lower power\, and compact silicon footprint\, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility. The upcoming RISC-V CON\, an annual conference organized by Andes Technology\, will focus on the theme of “RISC-V: Redefining AI’s Future in Automotive\, Data Center\, Communications\, and IoT” The event will provide a perfect opportunity to connect with the RISC-V community and showcase the latest trends\, market developments\, emerging applications\, and technological breakthroughs in this revolutionary ISA.
URL:https://marketingeda.com/event/2023-andes-risc-v-con/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230626T080000
DTEND;TZID=America/Los_Angeles:20230628T170000
DTSTAMP:20230424T194057Z
CREATED:20230424T194057Z
LAST-MODIFIED:20230424T194057Z
UID:6329-1687766400-1687971600@marketingeda.com
SUMMARY:3D & Systems Summit
DESCRIPTION:The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market\, products\, and tech advancements brought by disruptive technologies and Moore’s Law plateauing. Therefore\, continued developments and innovation are essential to growing the business. \nIndustry experts will share their insights into 3D and Heterogeneous Integration Roadmap (HIR) processes for semiconductor manufacturing and applications. \nParticipants can enjoy the exclusive exhibition areas that will feature the most prominent names in the industry alongside new and innovative companies. \nSeveral B2B matching opportunities await during the conference\, including networking reception\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise at the beautiful Elbe River.
URL:https://marketingeda.com/event/3d-systems-summit/
LOCATION:Dresden Hilton Hotel\, An der Frauenkirche 5 D\, Dresden\, Germany
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-June-26-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230626T080000
DTEND;TZID=Europe/Paris:20230627T170000
DTSTAMP:20230621T192056Z
CREATED:20230621T191832Z
LAST-MODIFIED:20230621T192056Z
UID:6553-1687766400-1687885200@marketingeda.com
SUMMARY:European Nanoelectronics Applications Design and Technology Conference
DESCRIPTION:FOCUS \nThe European Nanoelectronics Applications\, Design & Technology Conference will focus on electronic components\, electronic system design\, design automation\, and manufacturing topics related to micro- and nanoelectronics\, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA\, Horizon Europe\, and local governments in recent years. This conference will highlight the exciting and promising results primarily from the PENTA/XECS\, ECSEL/KDT & H2020/Horizon Europe projects. \nThis annual event has a clear focus on deep technical discussions between the leading European experts in the addressed fields\, independent from the research programs where the individual projects were started. All European projects related to electronic system design\, to design technology and to manufacturing topics are invited to contribute to the conference. \nThe 100 expected attendees will include project managers and leading experts in R&D projects in the fields of nanoelectronics and design technologies and their applications\, semiconductor-industry R&D managers\, microelectronics experts in applications industries like automotive and industrial\, and the major research organizations in the European scientific community. \nVENUE \nThis year\,  ADTC takes place in the Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\,  in “Attique” room. For more information\, please sroll down. \nFINANCIAL CONCEPT \nADTC is organized as collaboration event for experts in the field. All attendees benefit from the intensive information exchange and share the cost\, which will be kept low. It is a nonprofit event\, the local organisers do not get any compensation for their work. Most attendees contribute actively to the event\, e.g. as speaker or panelist\, therefore free participation is not possible.
URL:https://marketingeda.com/event/european-nanoelectronics-applications-design-and-technology-conference/
LOCATION:Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ADTC23-3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230620T090000
DTEND;TZID=Asia/Tokyo:20230620T203000
DTSTAMP:20230606T163917Z
CREATED:20230606T163917Z
LAST-MODIFIED:20230606T163917Z
UID:6456-1687251600-1687293000@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2023 Summer
DESCRIPTION:RISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20\, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center\, the University of Tokyo ). The “RISC-V Booth” will be held in the foyer and the Event space of Ito Hall. We will also have an “Online RISC-V Booth” on our website. RISC-V Day(s) Tokyo gathers excellent RISC-V related technologies and products\, as well as key persons and engineers\, to improve product recognition\, realize collaboration between companies\, exchange technology\, collect information\, etc. We aim to provide business opportunities for We are looking forward to your participation at this opportunity! At a later date (around the end of August)\, we are planning to post a video and the presentation material on the web page. Information will be provided on a website.
URL:https://marketingeda.com/event/risc-v-days-tokyo-2023-summer/
LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20230620T000000
DTEND;TZID=Asia/Taipei:20230620T000000
DTSTAMP:20230517T174045Z
CREATED:20230517T173815Z
LAST-MODIFIED:20230517T174045Z
UID:6410-1687219200-1687219200@marketingeda.com
SUMMARY:SNUG Taiwan 2023
DESCRIPTION:As the electronics industry’s largest user conference\, SNUG Taiwan is dedicated to demonstrating the state-of-the-art innovations from the chip design community around the globe. This year\, we are excited to announce that the SNUG Taiwan in-person event is back! \nSNUG Taiwan continues to foster the link between Synopsys’ tool users and technical experts so they can share best practices for electronic design and verification challenges. Join us at SNUG Taiwan to discuss cutting-edge technology and trends in the semiconductor industry\, explore the infinite possibilities of AI applications\, be ready for the challenges in the new era of chip design and verification. \nSNUG is restricted to Synopsys customers* only\, and offered at no charge.
URL:https://marketingeda.com/event/snug-taiwan-2023/
LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Taiwan-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230614T080000
DTEND;TZID=Europe/Berlin:20230615T170000
DTSTAMP:20230612T171200Z
CREATED:20230313T202424Z
LAST-MODIFIED:20230612T171200Z
UID:6114-1686729600-1686848400@marketingeda.com
SUMMARY:GSA 2023 European Executive Forum
DESCRIPTION:Dealing with Uncertainty\nThe global economy is sending mixed messages\, and with every new data release comes a new batch of upbeat or defeatist headlines. \nUncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in years\, on the other all major tech companies have announced significant layoffs.  The chip shortage is not over yet in some segments\, but in some others there is excess supply. Our new multipolar world order will enforce structural changes to the economy\, such as the need to rebuild reliable supply chains closer to home\, which often comes at higher prices. \nDespite these uncertainties\, innovation in our industry remains as strong as ever\, with relentless growth driven by automotive\, 5G and next generation connectivity\, new silicon design paradigms including RISC-V and chiplets\, big trends towards decarbonization and new materials like SiC\, the positive effects of increased diversity and inclusion. And large amounts of government money is made available globally to support this growth\, through “chips acts” and “green deals”. \nThere is therefore a strong belief that tech innovation and growth will continue to prevail and\, with a little more positive international cooperation\, deal with the apparent challenges altogether. \n\n\n\n\n\n\n\n\n\n\nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: close to 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region.
URL:https://marketingeda.com/event/gsa-2023-european-executive-forum/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:EDA,Forum,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-14-15-2023.jpg
END:VEVENT
END:VCALENDAR