BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.2//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Vienna
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Budapest
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Taipei
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Andorra
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20220313T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20221106T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230824T170000
DTSTAMP:20230802T171343Z
CREATED:20230802T171343Z
LAST-MODIFIED:20230802T171343Z
UID:6655-1692691200-1692896400@marketingeda.com
SUMMARY:ERI 2.0 Summit
DESCRIPTION:Watch as leaders from our government agencies\, the Defense Industrial Base\, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry\, national and economic security\, and future research directions. \nThe Electronics Resurgence Initiative (ERI)\, DARPA’s response to national-level microelectronics concerns\, is designed to ensure U.S. leadership in cross-functional\, next-generation microelectronics research\, development\, and manufacturing. The initiative\, aimed at both national security capabilities and commercial economic competitiveness and sustainability\, is a thematic portfolio of research programs primarily in the Microsystems Technology Office (MTO). These programs emphasize forward-looking partnerships with U.S. industry\, the defense industrial base\, and university researchers. \nDARPA expanded ERI’s focus with the announcement of ERI 2.0\, which seeks to reinvent domestic microelectronics manufacturing. ERI 2.0 will strengthen DARPA’s leadership in driving the next generation of microelectronics for national security by creating a national capability for 3DHI manufacturing and pursuing focused research in: \n\nManufacturing complex 3D systems\nDeveloping electronics for extreme environments\n\n…while maintaining the following thrust areas:\n  \n\nOptimizing design and test for complex circuits and prototypes\nOvercoming security threats across the entire hardware lifecycle\nIncreasing information processing density and efficiency\nAccelerating innovation in artificial intelligence hardware to make decisions at the edge faster\nSecuring communications
URL:https://marketingeda.com/event/eri-2-0-summit/
LOCATION:Hyatt Regency Seattle\, 805 Howell Street\, Seattle\, WA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ERI-2.0.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230809T080000
DTEND;TZID=Asia/Kolkata:20230810T170000
DTSTAMP:20230807T163442Z
CREATED:20230807T163442Z
LAST-MODIFIED:20230807T163442Z
UID:6683-1691568000-1691686800@marketingeda.com
SUMMARY:CadenceLIVE India
DESCRIPTION:CadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \n  \nKeynote Speakers \n\n\n\n\n\n\nNimish Modi\nSVP and GM – Strategy & New Ventures\, Cadence \n\n\n\n\n\n\nAlok Jain\nCorporate VP – System Verification Group\, Cadence \n\n\n\n\n\n\nVenugopal Puvvada\nVice-President\, Engineering\, Qualcomm \n\n\n\n\n\n\nHuzefa Cutlerywala\nSVP – WW Sales and Marketing\, Tessolve
URL:https://marketingeda.com/event/cadencelive-india/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-India-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T083000
DTEND;TZID=America/Los_Angeles:20230808T091500
DTSTAMP:20230801T170422Z
CREATED:20230801T170422Z
LAST-MODIFIED:20230801T170422Z
UID:6631-1691483400-1691486100@marketingeda.com
SUMMARY:Deliver Next-gen Smartphones
DESCRIPTION:Stefan Rosinger\, Senior Director\, Product Management – Arm \n\n\nAbout this talk\nJoin us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion\, AI intelligence and security while promoting greater efficiency in their mobiles\, laptops\, home\, and wearable devices. We will cover:\n\n-How Cortex-X4 achieves double-digit performance gains\, as well as great efficiency\n-Cortex-A720 & Cortex-A520 processor efficiency gains\, and how they are benefitting not just flagship but also mid-range and entry-level devices\n-The performance\, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)\n-How the cluster is being utilized for AI and other new demanding workloads\n-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance
URL:https://marketingeda.com/event/deliver-next-gen-smartphones/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-August-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T080000
DTEND;TZID=America/Los_Angeles:20230810T170000
DTSTAMP:20230726T200743Z
CREATED:20230726T200648Z
LAST-MODIFIED:20230726T200743Z
UID:6612-1691481600-1691686800@marketingeda.com
SUMMARY:Flash Memory Summit
DESCRIPTION:Why Attend Flash Memory Summit?\nFlash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions The scope of FMS23 will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nWhy You Should Participate\n• Establish your company as a leader in the emerging memory and storage market.\n• Display your products and expertise to an audience known to be interested in memory and storage.\n• Promote memory and storage to a wider market of equipment manufacturers\, solution providers\, system integrators\, consultants. \nHow You Can Participate:\n• Attend: Register online for the sessions\n• Exhibit: Promote your latest products – exhibit booths\n• Sponsor: Receive special recognition both at the event and in publicity\n• Present: Display your knowledge and commitment to flash memory
URL:https://marketingeda.com/event/flash-memory-summit-2/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Vienna:20230807T080000
DTEND;TZID=Europe/Vienna:20230808T170000
DTSTAMP:20230207T013618Z
CREATED:20230207T013618Z
LAST-MODIFIED:20230207T013618Z
UID:5914-1691395200-1691514000@marketingeda.com
SUMMARY:ISPLED 2023
DESCRIPTION:The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design\, ranging from process technologies and analog/digital circuits\, simulation and synthesis tools\, system-level design and optimization\, to system software and applications. \n  \n 
URL:https://marketingeda.com/event/ispled-2023/
LOCATION:TU Wien\, Gußhausstraße 27-29/384\, Vienna\, Austria
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISLPED-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T100000
DTEND;TZID=America/Los_Angeles:20230718T110000
DTSTAMP:20230713T200623Z
CREATED:20230713T200623Z
LAST-MODIFIED:20230713T200623Z
UID:6592-1689674400-1689678000@marketingeda.com
SUMMARY:Key MAC Considerations for the Road to 1.6T Ethernet Success
DESCRIPTION:224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations\, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions\, timing considerations\, and forward error correction.  We will shed light on key challenges for bandwidth hungry applications including latency optimization\, and SI techniques. Discover how Synopsys MAC IP solutions can help ensure your product is first to market. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys’ Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. \nPrior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\nJon Ames\n\n\nSr. Staff Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJon Ames is a Sr. Staff Product Marketing Manager for the Synopsys Ethernet Controller IP portfolio.  Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies.  Since graduating in Computer Science and Electronic Engineering the in UK\, Jon has worked at the leading companies in the networking and silicon solution industries.
URL:https://marketingeda.com/event/key-mac-considerations-for-the-road-to-1-6t-ethernet-success/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T080000
DTEND;TZID=America/Los_Angeles:20230719T170000
DTSTAMP:20230630T191347Z
CREATED:20230630T191347Z
LAST-MODIFIED:20230630T191347Z
UID:6568-1689667200-1689786000@marketingeda.com
SUMMARY:Rambus Design Summit 2023
DESCRIPTION:Back for its fourth year\, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center\, AI/ML\, automotive and IoT applications. \n\n\nAgenda + Abstracts\n\n\n\n\n\nRambus Design Summit will take place over two days\, with day one focusing on memory & interface solutions\, and day two on security solutions. Take a look at the agenda below – all times in Pacific Daylight Time (PDT). \n\n\n\n\n\n\n\nTuesday\, July 18: Memory & Interface Solutions\n\nTackling advanced data center workloads requires ever increasing levels of memory bandwidth and capacity\, as well as high-speed interconnects. Hear Rambus technology experts share their insights on future memory and interconnect requirements in the data center covering critical enabling technologies including DDR5\, HBM3\, PCIe 6.0\, GDDR6\, LPDDR5X\, CXL\, and MIPI/VESA video compression. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: CXL Technology: Revolutionizing the Data Center \nSpeaker: Mark Orthodoxou\, Vice President of Strategic Marketing\nAbstract: The need for more memory bandwidth and capacity continues to rise\, with applications like generative AI pushing current data center infrastructure to the limit. The leading companies at every level of the data center value chain are coalescing around CXL technology as a path to revolutionize the data center. Join Mark Orthodoxou to hear how CXL promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage\, as well as enabling new tiered-memory solutions and composable architectures.\n\n\n8:30am\nInnovations in CXL 3.0: Novel Device Types\, Capabilities\, and Interconnects \nSpeaker: Danny Moore\, Senior Product Marketing Manager\nAbstract: CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type\, CXL Multi-Headed Devices\, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.\n\n\n9:00am\nSystem Level Design Considerations for PCIe 6.0 \nSpeaker: Lou Ternullo\, Senior Director of Product Marketing\nAbstract: PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate\, PAM4 signaling\, forward error correction\, and a low power L0p mode. In this presentation\, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design\, including how to get the most out of each of the PCIe devices.\n\n\n9:30am\nLeveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays \nSpeakers: Simon Bussières\, Director of Systems Architecture\nJoe Rodriguez\, Product Marketing Manager\nAbstract: Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions\, faster refresh rates\, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality\, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.\n\n\n10:00am\nMeeting the Needs of Generative AI Training with HBM3 \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI training models are growing in both size and sophistication at a lightning pace\, requiring more and more bandwidth. With its unique 2.5D/3D architecture\, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.\n\n\n10:30am\nPowering AI/ML Inference with GDDR6 Memory \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: GDDR6 memory offers an impressive combination of bandwidth\, capacity\, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.\n\n\n11:00am\nLPDDR5X: Delivering High Bandwidth and Power Efficiency \nSpeaker: Vinitha Seevaratnam\, Senior Product Marketing Manager\nAbstract: The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT\, automotive\, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.\n\n\n11:30am\nWhat’s Next for DDR5 Memory? \nSpeaker: John Eble\, Vice President of Product Marketing\nAbstract: With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory\, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels\, be deployed in new applications beyond RDIMMs\, and how it is tailored for client computing systems.\n\n\n12:00pm\nHigh-Performance Memory: Ask Me Anything \nSpeakers: Tim Messegee\, Senior Director of Solutions Marketing\nSteven Woo\, Fellow and Distinguished Inventor\nJohn Eble\, Vice President of Product Marketing\nMark Orthodoxou\, Vice President of Strategic Marketing\nFrank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI is just one of the many applications driving the relentless need for better memory performance\, capacity and efficiency in the data center. Join our experts as they discuss some of the biggest memory challenges facing the industry today\, contemplate how the industry will innovate to meet future data center memory needs\, and answer all your questions!\n\n\n\n\n\n\nWednesday\, July 19: Security Solutions\n\nSecurity anchored in hardware provides the foundation for protecting data and devices at all stages of the semiconductor lifecycle. Join Rambus Security experts as they share their insights on security threats facing the industry including those that will arise in the era of quantum computers. Learn how you can protect hardware and data at rest\, in motion and in use with Root of Trust\, MACsec\, Inline Memory Encryption\, and more. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: Emerging Security Challenges in Highly Interconnected Semiconductor Systems \nSpeaker: Neeraj Paliwal\, VP General Manager\nAbstract: The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity\, reliability\, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats\, such as supply chain attacks\, intellectual property theft\, hardware Trojans\, side-channel attacks\, fault injection attacks\, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.\n\n\n8:30am\nSelecting the right Root of Trust HSM Design for Your Next Project \nSpeaker: Bart Stevens\, Senior Director of Product Marketing\nAbstract: A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation\, Bart Stevens will guide you through the labyrinth of Root of Trust designs\, including what problems they can solve and what solutions are available to implement in your next silicon design.\n\n\n9:00am\nProtecting Devices and Data in the Quantum Era \nSpeakers: Gijs Willemse\, Senior Director of Product Management\nAbstract: Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods\, that is\, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.\n\n\n9:30am\nHardware Security: Ask Me Anything \nSpeaker: Tim Messegee\, Senior Director of Solutions Marketing\nBart Stevens\, Senior Director of Product Marketing\nGijs Willemse\, Senior Director of Product Management\nScott Best\, Senior Technical Director\nAbstract: Whether it’s security technology trends\, the threat of quantum computers\, implementation issues or anything in between\, our security experts are ready to tackle your questions in this Ask Me Anything session.\n\n\n10:00am\nSecuring MCUs with SCA Protection in IoT Designs \nSpeaker: Marcel Van Loon\, Senior Principal Engineer Systems Architecture\nAbstract: A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.\n\n\n10:30am\nCybersecurity: A Top Priority for the Automotive Industry \nSpeaker: Adiel Bahrouch\, Director of Business Development\nAbstract: Automotive systems\, and the semiconductors used within them\, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation\, while meeting the safety and security requirements unique to the automotive industry.\n\n\n11:00am\nThe Convergence of MACsec and IPsec in Data Center Silicon Designs \nSpeaker: Maxim Demchenko\, Technical Director\nAbstract: Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.\n\n\n11:30am\nMemory Encryption for Data in Use Protection to Enable Confidential Computing in Data Center Designs \nSpeaker: Ajay Kapoor\, Senior Principal Engineer Systems Architecture\nAbstract: There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.\n\n\n12:00pm\nSecuring the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management \nSpeaker: Matt Orzen\, Technical Director Systems Architecture\nAbstract: The semiconductor industry is the lifeblood of the digital economy. The design\, manufacturing and consumption of chips is a global ecosystem\, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability\, functionality\, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon\, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.
URL:https://marketingeda.com/event/rambus-design-summit-2023/
CATEGORIES:IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-July-18-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230704T080000
DTEND;TZID=Europe/Paris:20230706T170000
DTSTAMP:20230120T171956Z
CREATED:20230120T171956Z
LAST-MODIFIED:20230120T171956Z
UID:5862-1688457600-1688662800@marketingeda.com
SUMMARY:FPGA Conference Europe 2023
DESCRIPTION:FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. \nThe FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is addressing that progress across all major manufacturers. It focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. At this year’s event\, one focus is on the energy efficiency of flexible logic devices. This applies in particular to small\, low-power components that rely on special production techniques or deliberately have only a limited number of programmable cells. \nPGAs belong to the hidden champions of microelectronics and are at the forefront of embedded development. From tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed on the FPGA Conference.
URL:https://marketingeda.com/event/fpga-conference-europe-2023/
LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Budapest:20230629T080000
DTEND;TZID=Europe/Budapest:20230630T170000
DTSTAMP:20230620T163638Z
CREATED:20230620T163638Z
LAST-MODIFIED:20230620T163638Z
UID:6532-1688025600-1688144400@marketingeda.com
SUMMARY:30th MIXDES Conference
DESCRIPTION:The aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design\, modeling\, simulation\, testing and manufacturing in various areas such as micro- and nanoelectronics\, semiconductors\, sensors\, actuators and power devices.\nThe MIXDES conference papers will be submitted for inclusion into IEEE Xplore\, subject to IEEE Xplore’s scope and quality requirements.
URL:https://marketingeda.com/event/30th-mixdes-conference/
LOCATION:Lodz Univesity of Technology\, Wólczańska 221/223\, Lodz\, Poland
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MIXDES-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230627T093000
DTEND;TZID=America/Los_Angeles:20230627T170000
DTSTAMP:20230523T005957Z
CREATED:20230523T005957Z
LAST-MODIFIED:20230523T005957Z
UID:6427-1687858200-1687885200@marketingeda.com
SUMMARY:2023 Andes RISC-V CON
DESCRIPTION:RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive\, data center\, communications\, and IoT. Its open-source instruction set architecture (ISA) provides higher performance\, lower power\, and compact silicon footprint\, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility. The upcoming RISC-V CON\, an annual conference organized by Andes Technology\, will focus on the theme of “RISC-V: Redefining AI’s Future in Automotive\, Data Center\, Communications\, and IoT” The event will provide a perfect opportunity to connect with the RISC-V community and showcase the latest trends\, market developments\, emerging applications\, and technological breakthroughs in this revolutionary ISA.
URL:https://marketingeda.com/event/2023-andes-risc-v-con/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230626T080000
DTEND;TZID=America/Los_Angeles:20230628T170000
DTSTAMP:20230424T194057Z
CREATED:20230424T194057Z
LAST-MODIFIED:20230424T194057Z
UID:6329-1687766400-1687971600@marketingeda.com
SUMMARY:3D & Systems Summit
DESCRIPTION:The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market\, products\, and tech advancements brought by disruptive technologies and Moore’s Law plateauing. Therefore\, continued developments and innovation are essential to growing the business. \nIndustry experts will share their insights into 3D and Heterogeneous Integration Roadmap (HIR) processes for semiconductor manufacturing and applications. \nParticipants can enjoy the exclusive exhibition areas that will feature the most prominent names in the industry alongside new and innovative companies. \nSeveral B2B matching opportunities await during the conference\, including networking reception\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise at the beautiful Elbe River.
URL:https://marketingeda.com/event/3d-systems-summit/
LOCATION:Dresden Hilton Hotel\, An der Frauenkirche 5 D\, Dresden\, Germany
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-June-26-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230626T080000
DTEND;TZID=Europe/Paris:20230627T170000
DTSTAMP:20230621T192056Z
CREATED:20230621T191832Z
LAST-MODIFIED:20230621T192056Z
UID:6553-1687766400-1687885200@marketingeda.com
SUMMARY:European Nanoelectronics Applications Design and Technology Conference
DESCRIPTION:FOCUS \nThe European Nanoelectronics Applications\, Design & Technology Conference will focus on electronic components\, electronic system design\, design automation\, and manufacturing topics related to micro- and nanoelectronics\, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA\, Horizon Europe\, and local governments in recent years. This conference will highlight the exciting and promising results primarily from the PENTA/XECS\, ECSEL/KDT & H2020/Horizon Europe projects. \nThis annual event has a clear focus on deep technical discussions between the leading European experts in the addressed fields\, independent from the research programs where the individual projects were started. All European projects related to electronic system design\, to design technology and to manufacturing topics are invited to contribute to the conference. \nThe 100 expected attendees will include project managers and leading experts in R&D projects in the fields of nanoelectronics and design technologies and their applications\, semiconductor-industry R&D managers\, microelectronics experts in applications industries like automotive and industrial\, and the major research organizations in the European scientific community. \nVENUE \nThis year\,  ADTC takes place in the Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\,  in “Attique” room. For more information\, please sroll down. \nFINANCIAL CONCEPT \nADTC is organized as collaboration event for experts in the field. All attendees benefit from the intensive information exchange and share the cost\, which will be kept low. It is a nonprofit event\, the local organisers do not get any compensation for their work. Most attendees contribute actively to the event\, e.g. as speaker or panelist\, therefore free participation is not possible.
URL:https://marketingeda.com/event/european-nanoelectronics-applications-design-and-technology-conference/
LOCATION:Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ADTC23-3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230620T090000
DTEND;TZID=Asia/Tokyo:20230620T203000
DTSTAMP:20230606T163917Z
CREATED:20230606T163917Z
LAST-MODIFIED:20230606T163917Z
UID:6456-1687251600-1687293000@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2023 Summer
DESCRIPTION:RISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20\, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center\, the University of Tokyo ). The “RISC-V Booth” will be held in the foyer and the Event space of Ito Hall. We will also have an “Online RISC-V Booth” on our website. RISC-V Day(s) Tokyo gathers excellent RISC-V related technologies and products\, as well as key persons and engineers\, to improve product recognition\, realize collaboration between companies\, exchange technology\, collect information\, etc. We aim to provide business opportunities for We are looking forward to your participation at this opportunity! At a later date (around the end of August)\, we are planning to post a video and the presentation material on the web page. Information will be provided on a website.
URL:https://marketingeda.com/event/risc-v-days-tokyo-2023-summer/
LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20230620T000000
DTEND;TZID=Asia/Taipei:20230620T000000
DTSTAMP:20230517T174045Z
CREATED:20230517T173815Z
LAST-MODIFIED:20230517T174045Z
UID:6410-1687219200-1687219200@marketingeda.com
SUMMARY:SNUG Taiwan 2023
DESCRIPTION:As the electronics industry’s largest user conference\, SNUG Taiwan is dedicated to demonstrating the state-of-the-art innovations from the chip design community around the globe. This year\, we are excited to announce that the SNUG Taiwan in-person event is back! \nSNUG Taiwan continues to foster the link between Synopsys’ tool users and technical experts so they can share best practices for electronic design and verification challenges. Join us at SNUG Taiwan to discuss cutting-edge technology and trends in the semiconductor industry\, explore the infinite possibilities of AI applications\, be ready for the challenges in the new era of chip design and verification. \nSNUG is restricted to Synopsys customers* only\, and offered at no charge.
URL:https://marketingeda.com/event/snug-taiwan-2023/
LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Taiwan-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230614T080000
DTEND;TZID=Europe/Berlin:20230615T170000
DTSTAMP:20230612T171200Z
CREATED:20230313T202424Z
LAST-MODIFIED:20230612T171200Z
UID:6114-1686729600-1686848400@marketingeda.com
SUMMARY:GSA 2023 European Executive Forum
DESCRIPTION:Dealing with Uncertainty\nThe global economy is sending mixed messages\, and with every new data release comes a new batch of upbeat or defeatist headlines. \nUncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in years\, on the other all major tech companies have announced significant layoffs.  The chip shortage is not over yet in some segments\, but in some others there is excess supply. Our new multipolar world order will enforce structural changes to the economy\, such as the need to rebuild reliable supply chains closer to home\, which often comes at higher prices. \nDespite these uncertainties\, innovation in our industry remains as strong as ever\, with relentless growth driven by automotive\, 5G and next generation connectivity\, new silicon design paradigms including RISC-V and chiplets\, big trends towards decarbonization and new materials like SiC\, the positive effects of increased diversity and inclusion. And large amounts of government money is made available globally to support this growth\, through “chips acts” and “green deals”. \nThere is therefore a strong belief that tech innovation and growth will continue to prevail and\, with a little more positive international cooperation\, deal with the apparent challenges altogether. \n\n\n\n\n\n\n\n\n\n\nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: close to 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region.
URL:https://marketingeda.com/event/gsa-2023-european-executive-forum/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:EDA,Forum,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-14-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230614T170000
DTSTAMP:20230608T190924Z
CREATED:20230608T190924Z
LAST-MODIFIED:20230608T190924Z
UID:6470-1686643200-1686762000@marketingeda.com
SUMMARY:PCI-SIG Developers Conference 2023
DESCRIPTION:The PCI-SIG Developers Conference 2023 is returning to Santa Clara on June 13-14\, 2023! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers agree that this is an event you won’t want to miss. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nAttendee Registration– Register Now!\nOnline attendee registration will close on Thursday\, June 8th at 5:00 pm PST. You can still register onsite! All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting – Register Now!\nThe PCI-SIG Annual Meeting will be held on June 13th\, 2023. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nAgenda\nThe 2023 US Developer Conference agenda has been posted to the PCI-SIG website. \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com.
URL:https://marketingeda.com/event/pci-sig-developers-conference-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/PCI-SIG_Web_Banner_US_DevCon_2023_1000x500_011923.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230524T191605Z
CREATED:20230524T191605Z
LAST-MODIFIED:20230524T191605Z
UID:6434-1686643200-1686646800@marketingeda.com
SUMMARY:Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
DESCRIPTION:Fueled by the recent adoption by leading smartphone brands\, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive\, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar\, enabling features such as Child Presence Detection (CPD). \nIn this webinar\, you will learn about: \n• UWB technology and ecosystem (UWB alliance\, CCC\, FiRa)\n• How does UWB Radar work\n• CEVA’s UWB and Radar solutions\n\n\nTarget Audience\nSystem engineers\, SoC designers\, and product managers targeting UWB devices\, that are looking to add radar capabilities to products for automotive\, industrial\, consumer\, and others\n\n\nSpeakers\n\n\n\n\n\n\n\nNavot Goren\nUWB Product Director\, CEVA Inc.
URL:https://marketingeda.com/event/driving-forward-with-uwb-radar-enhancing-child-safety-in-automotive/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230611T080000
DTEND;TZID=Asia/Tokyo:20230616T170000
DTSTAMP:20230228T182652Z
CREATED:20230228T182652Z
LAST-MODIFIED:20230228T182652Z
UID:6035-1686470400-1686934800@marketingeda.com
SUMMARY:2023 Symposium on VLSI Technology and Circuits
DESCRIPTION:VLSI Symposium is an international conference on semiconductor technology and circuits that offers an opportunity to interact and synergize on topics spanning the range from process technology to system-on-chip. \nWe appreciate you to visit the VLSI symposium website. We also would like to invite you to join “2023 Symposium on VLSI technology and Circuits\,” which will be held from Sunday\, June 11 to Friday\, June 16 at Rihga Royal Hotel Kyoto in Japan. 2023 Symposium is planned as a fully in-person event in Kyoto for the first time in four years. On-demand access to technical papers will be available for people who cannot travel to Kyoto. We keep monitoring the COVID-19 pandemic and will inform you any changes in the symposium program. \nAbout the Symposium\nProfessors Shoji Tanaka and Walter Kosonocky\, founders of the Symposium\, first organized the VLSI Technology Symposium in 1981 with the hope of offering an opportunity for world’s top technologists to engage in an open exchange of ideas on what was quickly becoming a revolution in the world’s industrial capability. Since then\, the Symposium has been held annually and has grown to be an important and valuable event for people working in the VLSI business. The presentation of high-quality papers has made it possible for attendees to learn about new directions in the development of VLSI technology. The friendly atmosphere has made this an enjoyable learning experience. \nThe Symposium on VLSI Technology has alternated each year between sites in US and Japan. In 1987\, the first Symposium on VLSI Circuits was held in conjunction with the Technology Symposium in recognition of the growing interest to provide the same small but intense and open forum for discussing circuit and system implementations. Since then\, this annual meeting has increased its value over the past 30 years. We are confident that so many new technologies and circuits were introduced in the past Symposia and thus have contributed to the prosperity of the world. Its sponsors continue to be the IEEE Electron Devices Society and Solid-State Circuits Society\, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics\, Information and Communication Engineers. \nFor many reasons\, these meetings have remained linked for the past years to provide opportunities for technology people and circuit and system designers to interact with each other. These interactions are augmented with short courses\, invited speakers and several evening panel discussions\, Forums\, Workshops. In recognition of the efforts of organizers\, authors and participants to make the Symposia successful\, there is ample banquet and entertainment prearranged. \nIn its 42nd year of delivering a unique convergence of technology and circuits for the microelectronics industry\, the 2022 Symposium on VLSI Technology & Circuits had been merged into one Symposium to maximize the synergy across both domains. \nAfter the 2020 meeting had been held in a fully virtual format due to COVID-19\, the 2022 meeting was held in Honolulu\, Hawaii. This year it will be returning to the RIHGA Royal Hotel in Kyoto\, Japan in June of 2023. \nDATE AND LOCATION\nThe 2023 Symposium on VLSI Technology and Circuits will be held on June 11-16\, 2023\, JST respectively.\nAll the meetings will be held at RIHGA Royal Hotel Kyoto\, Horikawa Shiokoji\, Shimogyo ku \, Kyoto 600 8237\, Japan. \nHeld as a six-day at the Rihga Royal Hotel\, as well as selected presentations and panel sessions\, the Symposium will feature advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nThe weeklong Symposium will continue its reputation as the microelectronics industry’s premiere international conference integrating technology\, circuits\, and systems with a range and scope unlike any other conferences. In addition to the technical presentations\, the Symposium program will feature a demonstration session\, evening panel discussions\, joint focus sessions\, short courses\, workshops\, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposium theme.
URL:https://marketingeda.com/event/2023-symposium-on-vlsi-technology-and-circuits/
LOCATION:Rihga Royal Hotel\, Kyoto\, Japan
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2023-Symposium.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Andorra:20230605T080000
DTEND;TZID=Europe/Andorra:20230609T170000
DTSTAMP:20230211T031337Z
CREATED:20230211T031337Z
LAST-MODIFIED:20230211T031337Z
UID:5944-1685952000-1686330000@marketingeda.com
SUMMARY:RISC-V Summit Europe
DESCRIPTION:On 5-9th June\, in Barcelona\, RISC-V Summit Europe brings together developers\, architects\, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia\, research\, SMEs\, industry and open source communities will gather to exchange knowledge\, ideas\, technologies\, and research shaping the future of RISC-V computing. \nThe event will include a single track of keynotes\, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions. \nRISC-V Summit Europe is an opportunity not to be missed\, comme to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation! \nThe Program Committee\n\nJan Andersson (Cobham Gaisler)\nHolger Blasum (Sysgo)\nAlex Bradbury (Igalia)\nRamon Canal (UPC)\nDenis Dutoit (CEA)\nAngelo Garofalo (ETH Zürich)\nBenedikt Gierlichs (KU Leuven)\nFrederic Heitzmann (Tiempo Secure)\nJohn Hengeveld (Intel)\nEyck Jentzsch (MINRES)\nNick Kossifidis (FORTH)\nMarie-Minerve Louerat (LIP6)\nAndreas Mauderer (Bosch)\nDaniel Müller-Gritschneder (TUM)\, PC Co-Chair\nJérôme Quévremont (Thales)\nRihards Novickis (EDI\, Latvia)\nKatzalin Olcoz Herrero (UCM)\nOlivier Savry (CEA)\nDavide Schiavone (OpenHW Group)\nGeorg Sigl (TUM)\, PC Co-Chair\nJonathan Woodruff (Cambridge Univ.)\nDaniel Müller-Gritschneder (TU Münich)\nJérôme Quévremont (Thales R&T)\nBorja Pérez Pavon (Univ. de Cantabria)\, Submission Chair\n\nThe Steering Committee\n\nNarcís Avellana (NVision)\nTeresa Cervero (BSC)\nRomain Dolbeau (SiPearl)\nWolfgang Ecker (Infineon)\nRoger Espasa (Semidynamics)\nChristian Fabre (CEA)\nFrank K. Gürkaynak (ETH Zürich)\nDaniel Müller-Gritschneder (TU Münich)\nBorja Pérez Pavon (Univ. de Cantabria)\nJérôme Quévremont (Thales R&T)\nOlivier Sentieys (INRIA\, France)\nPhilipp Tomsich (VRULL)\nStefan Wallentowitz (HM Münich)
URL:https://marketingeda.com/event/risc-v-summit-europe/
LOCATION:Barcelona\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230601T110000
DTEND;TZID=America/Los_Angeles:20230601T120000
DTSTAMP:20230421T164256Z
CREATED:20230421T164256Z
LAST-MODIFIED:20230421T164256Z
UID:6308-1685617200-1685620800@marketingeda.com
SUMMARY:Advanced Testbench for a Simple DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn part 2 of this webinar series\, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently\, check and prove that we have indeed verified our simple DUT more thoroughly\, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control\, and introduce functional coverage. \nHaving shown you these more advanced testbench techniques\, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability\, maintainability\, and extensibility. \nAgenda:\nWhat is required when verifying for higher quality?\nThe elements of an advanced testbench infrastructure\nAdvanced BFMs\nBFM vs Protocol Checkers\nBFM limitations\nAdvanced randomization\nSpecification Coverage\, aka Requirements Coverage\nIntroducing functional coverage\nUVVM advanced BFMs\nUVVM for high quality verification\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-simple-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230531T083000
DTEND;TZID=America/New_York:20230531T170000
DTSTAMP:20230530T203817Z
CREATED:20230530T203817Z
LAST-MODIFIED:20230530T203817Z
UID:6438-1685521800-1685552400@marketingeda.com
SUMMARY:STAC Summit
DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment.
URL:https://marketingeda.com/event/stac-summit/
LOCATION:New York Marriott Marquis\, 1535 Broadway\, New York City\, NY\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230525T120000
DTSTAMP:20230515T234754Z
CREATED:20230515T234719Z
LAST-MODIFIED:20230515T234754Z
UID:6394-1684918800-1685016000@marketingeda.com
SUMMARY:Requirements for Multi-Die System Success
DESCRIPTION:Wednesday\, May 24\, 2023 and Thursday\, May 25\, 2023  \n\n\n\n\n\n\n\n\n\n\nThe industry is moving to multi-die systems to benefit from the greater compute performance\, increased functionality\, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning\, die/package co-design\, secure and robust die-to-die connectivity\, reliability and health\, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful. \n\n\nMay 24th presentation topics will include: \n\n9:00 a.m. PDT: Multi-Die System Trends\, Challenges and Requirements\n10:00 a.m. PDT: Benefits of Early Architecture Design for Multi-Die Systems\n11:00 a.m. PDT: Innovations in Multi-Die System Co-Design and System Analysis\n\nMay 25th presentation topics will include: \n\n9:00 a.m. PDT: Successful Connectivity of Heterogeneous Dies with UCIe IP\n10:00 a.m. PDT: Identifying and Overcoming Multi-Die System Verification Challenges\n11:00 a.m. PDT: Optimizing Multi-Die System Health from Die to Package to In-Field\n\n  \nRegister once for access to all the webinars.
URL:https://marketingeda.com/event/requirements-for-multi-die-system-success/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230504T164101Z
CREATED:20230504T164101Z
LAST-MODIFIED:20230504T164101Z
UID:6359-1684918800-1684922400@marketingeda.com
SUMMARY:DENSO discusses Verification of network relay performance using VisualSim
DESCRIPTION:Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. \nEfficient in-vehicle network development through simulation combining network and ECU hardware and software elements \nTime Zone:\nJapan – 3:00 PM (In Japanese)\nAsia – 3:00 PM Korea | 2:00PM China | 11:30PM India\nEurope – 10:00 CEST\nAmericas – 09:00AM PST | 12:00PM EST
URL:https://marketingeda.com/event/denso-discusses-verification-of-network-relay-performance-using-visualsim/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T080000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230427T170718Z
CREATED:20230427T170718Z
LAST-MODIFIED:20230427T170718Z
UID:6343-1684915200-1684922400@marketingeda.com
SUMMARY:Extending RISC Processors into Flexible Accelerators using ASIP Designer
DESCRIPTION:Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications\n\nThe slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems\, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications. \n  \nWho Should Attend?\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\n\nAgenda\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAn Introduction to Domain-Specific Processors and ASIP Designer\n\n\nPatrick Verbist\, Sr. Product Manager\, Synopsys Belgium \nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n08:00am – 8:50am PT \nDomain-specific processors (also referred to as Application-specific processors\, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys’ ASIP Designer tool-suite. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: Energy-Efficient Application-Specific Instruction Set Processor for Feature Extraction in Smart Vision Systems\n\n\nLucas Ferreira\, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department\, Lund University\n \n8:50am – 9:20am PT \nIn computer-vision feature extraction algorithms\, compressing the image into a sparse set of trackable keypoints\, empowers navigation-critical systems such as Simultaneous Localization and Mapping (SLAM) in autonomous robots\, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First\, the overall on-chip memory requirements can be lessened\, and second\, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP)\, designed with Synopsys ASIP Designer\, optimized for performing feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) is thoroughly explored to validate the proposed architecture\, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale\, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: An ASIP for Post-Quantum Cryptography\n\n\nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n9:20am –10:00am PT \nKyber\, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers\, is computationally very demanding due to extensive use of hashing\, for example. In this case study\, an ASIP optimized for accelerating Kyber was developed\, starting from an open-source implementation compiled and profiled on a RISC-V base model\, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround\, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. \nMeet The Speakers\n\n\n\n\nPatrick Verbist \nSr. Product Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nPatrick Verbist is the Product Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\nFalco Munsche \nTechnical Marketing Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP Design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \nHe holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\nLucas Ferreira \nPhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department \nLund University \n\n\n\n\n\n\n\n\n\nLucas Ferreira was born in São Paulo\, Brazil\, 1993. He received his bachelors both in Science and Technology\, and Automation and Control Engineering respectively at Federal University of ABC 2015-2017 (São Paulo). In 2019 he received his M.Sc. degree in Embedded Electronics from Lund University. \nSince May 2019\, he is working at the department of Electrical and Information Technology\, Lund University as a doctoral candidate. His main focus of research is on domain-specific processor design with focus on computer vision\, machine learning\, and autonomous drones.
URL:https://marketingeda.com/event/extending-risc-processors-into-flexible-accelerators-using-asip-designer/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230522T080000
DTEND;TZID=America/Los_Angeles:20230524T170000
DTSTAMP:20230331T185032Z
CREATED:20230331T184530Z
LAST-MODIFIED:20230331T185032Z
UID:6216-1684742400-1684947600@marketingeda.com
SUMMARY:Embedded Vision Summit 2023
DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\n\nJoin us for four days of learning—from tutorials to deep-dive days\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\n\n4 Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\nWe’ve been doing this for 12 years.\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.\n\n\n\n\n\n\nLearn\n\n\n\n\n\nIn order to deliver real-world insights and know-how into the most current topics in the industry to our attendees\, we have packed the program with learning opportunities\, including: \nSpeakers and Sessions: Learn from the best and listen to over 100 expert speakers who actively work in the industry present on the latest applications\, techniques\, technologies and opportunities in computer vision and visual AI. \n\n\nSee\n\n\n\n\n\n100+ Exhibitors and Hundreds of Demos: Visit the exhibitors on the exhibit floor and see their latest technologies that enable perception—processors\, algorithms\, software\, sensors\, developer tools\, services and more! You’ll get to see technology in action by watching cool demos from building-block component suppliers to learn about new and existing solutions to your business and engineering challenges. \nEnabling Technologies Track: If you’re a product developer\, engineer or business leader looking for real-world\, commercial technologies that will help you add visual intelligence and AI to your new products\, you’ll want to attend this track’s sessions. You can see things\, like: \n\nProcessors and tools for deep-learning-based object recognition.\nOptimized software components for low-cost\, energy-efficient\, real-time vision.\nFrameworks and services for faster product development.\n\n\n\nConnect\n\n\n\n\n\nBuilding valuable business connections is crucial. At the Summit you can connect with engineers\, marketers\, executives—they’re all here! Here’s how: \n\nQ&A Sessions: Join in on post-talk Q&A sessions and have your important questions answered directly by the expert speakers.\nMeet the Exhibitors and Sponsors: Connect with key engineers and technologists from top computer vision building-block suppliers to learn about their latest processors\, software\, development tools and more.\nMingle at the Technology Exhibits Reception. The evening of Tuesday\, May 23\, enjoy great food and refreshing beverages while meeting new folks and seeing awesome tech demos at our Exhibits Reception!\nNetwork at the 3rd annual Women In Vision Reception sponsored by Perceive.
URL:https://marketingeda.com/event/embedded-vision-summit-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summit-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230521T080000
DTEND;TZID=America/Los_Angeles:20230525T170000
DTSTAMP:20230122T013506Z
CREATED:20230122T013506Z
LAST-MODIFIED:20230122T013506Z
UID:5867-1684656000-1685034000@marketingeda.com
SUMMARY:ISCAS 2023
DESCRIPTION:The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory\, design and implementation of circuits and systems. \nKeynote Speakers\n\nDr. Margaret Martonosi\n\n\n\nMargaret Martonosi is the US National Science Foundation’s (NSF) Assistant Director for Computer and information Science and Engineering (CISE). With an annual budget of more than $1B\, the CISE directorate at NSF has the mission to uphold the Nation’s leadership in scientific discovery and engineering innovation through its support of fundamental research and education in computer and information science and engineering as well as transformative advances in research cyberinfrastructure. While at NSF\, Dr. Martonosi is on leave from Princeton University where she is the Hugh Trumbull Adams ’35 Professor of Computer Science. \n\nStuart Russell\n\n\n\ntuart Russell is a Professor of Computer Science at the University of California at Berkeley\, holder of the Smith-Zadeh Chair in Engineering\, and Director of the Center for Human-Compatible AI. He is a recipient of the IJCAI Computers and Thought Award and Research Excellence Award and held the Chaire Blaise Pascal in Paris. In 2021 he received the OBE from Her Majesty Queen Elizabeth and gave the Reith Lectures. He is an Honorary Fellow of Wadham College\, Oxford\, an Andrew Carnegie Fellow\, and a Fellow of the American Association for Artificial Intelligence\, the Association for Computing Machinery\, and the American Association for the Advancement of Science. His book “Artificial Intelligence: A Modern Approach” (with Peter Norvig) is the standard text in AI\, used in 1500 universities in 135 countries. His research covers a wide range of topics in artificial intelligence\, with a current emphasis on the long-term future of artificial intelligence and its relation to humanity. He has developed a new global seismic monitoring system for the nuclear-test-ban treaty and is currently working to ban lethal autonomous weapons. \n\nYoky Matsuoka\n\n\n\nYoky Matsuoka is the Founder & CEO of Yohana\, an independently led subsidiary of Panasonic focused on building consumer technology products and services to help people live healthier and happier lives. As an accomplished executive and technologist\, Matsuoka brings more than two decades of leadership experience to her role where she also leads global innovation and serves as the Managing Executive Officer of Panasonic Corporation. \n\nDongjin (DJ) Seo\n\n\n\nDongjin (DJ) Seo is co-founder and VP of Brain Interfaces at Neuralink\, where he leads the team responsible for everything (electrodes\, materials\, electronics\, firmware\, packaging\, manufacturing\, algorithms\, and more) in the brain implant. DJ received his PhD from UC Berkeley in 2016 for his work on ultrasonic wireless neural implant technology called neural dust and BS in EE at Caltech in 2011 where he designed ICs and antennas for next-gen wireless communication and imaging systems. He also held several internships building high-performance and low-power circuits for sensor networks. For his work\, DJ was named one of MIT Technology Review’s Innovators Under 35 in 2020. \n\nDr. Thomas Anderson\n\n\n\nDr. Andersen heads the Artificial Intelligence and Silicon Innovation group at Synopsys\, where he focuses on developing new technologies in the AI\, ML and advanced technology space to automate the future of chip design. \nLieven Vandersypen\nProf. Dr. ir Lieven Vandersypen is Antoni van Leeuwenhoek professor in Quantum Nanoscience at Delft University of Technology and Scientific Director of QuTech\, an advanced research center for Quantum Computing and Quantum Internet. He received a MSc in Mechanical Engineering from KU Leuven\, and a MSc/PhD in Electrical Engineering from Stanford University for the first experiments in quantum computing.
URL:https://marketingeda.com/event/iscas-2023/
LOCATION:Monterey\, CA\, Monterey\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISCAS-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230518T170000
DTEND;TZID=America/Los_Angeles:20230518T193000
DTSTAMP:20230509T195717Z
CREATED:20230509T195527Z
LAST-MODIFIED:20230509T195717Z
UID:6378-1684429200-1684438200@marketingeda.com
SUMMARY:Annual ESDA Membership Meeting & CEO Outlook
DESCRIPTION:The evening begins at the Keysight office\, Thursday\, May 18\, at 5:00pm with the ESD Alliance Annual Membership Meeting. You’ll get an overview of the past year’s activities and discover what’s in store for 2023. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook. \nEnjoy a lively\, nourishing networking reception that kicks off the CEO Outlook panel. Hear influential executives share their insights on the current and future state of the design and semiconductor industries. \nAgenda \n\n5:00 pm – 5:30 pm\n\n\n\nBob Smith\nExecutive Director\nESD Alliance\n\n\n\nESD Alliance Annual Membership Meeting\n\nOverview of ESD Alliance activities for 2022 and plans for 2023. \n\n\n\n\n\n5:30 pm – 6:30 pm\n\n\nNetworking\n\nEnjoy light food and refreshments as you network with your peers \nCEO Outlook Panel\n\n6:30 pm – 7:30 pm\n\n\n\nEd Sperling | Moderator\nEditor in Chief\nSemiconductor Engineering\n\n\n\nModerator & Panelists\n\nHear panelists from Ansys | ESD Alliance | IC Manage | Keysight | PDF Solutions | Real Intent | Siemens EDA discuss the state of the electronic system design industry as well as their views of the outlook for the coming years. \nDean Drako | President and CEO | IC Manage\nNiels Faché | VP and GM Keysight EDA | Keysight\nJohn Kibarian | President and CEO | PDF Solutions\nJohn Lee | VP and GM | Ansys\nPrakash Narain | President and CEO | Real Intent\nJoseph Sawicki | Executive Vice President | Siemens IC EDA\nSimon Segars | Governing Council Chair | ESD Alliance
URL:https://marketingeda.com/event/annual-esda-membership-meeting-ceo-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESDA-2023.jpg
END:VEVENT
END:VCALENDAR