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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230626T080000
DTEND;TZID=America/Los_Angeles:20230628T170000
DTSTAMP:20230424T194057Z
CREATED:20230424T194057Z
LAST-MODIFIED:20230424T194057Z
UID:6329-1687766400-1687971600@marketingeda.com
SUMMARY:3D & Systems Summit
DESCRIPTION:The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market\, products\, and tech advancements brought by disruptive technologies and Moore’s Law plateauing. Therefore\, continued developments and innovation are essential to growing the business. \nIndustry experts will share their insights into 3D and Heterogeneous Integration Roadmap (HIR) processes for semiconductor manufacturing and applications. \nParticipants can enjoy the exclusive exhibition areas that will feature the most prominent names in the industry alongside new and innovative companies. \nSeveral B2B matching opportunities await during the conference\, including networking reception\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise at the beautiful Elbe River.
URL:https://marketingeda.com/event/3d-systems-summit/
LOCATION:Dresden Hilton Hotel\, An der Frauenkirche 5 D\, Dresden\, Germany
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-June-26-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230626T080000
DTEND;TZID=Europe/Paris:20230627T170000
DTSTAMP:20230621T192056Z
CREATED:20230621T191832Z
LAST-MODIFIED:20230621T192056Z
UID:6553-1687766400-1687885200@marketingeda.com
SUMMARY:European Nanoelectronics Applications Design and Technology Conference
DESCRIPTION:FOCUS \nThe European Nanoelectronics Applications\, Design & Technology Conference will focus on electronic components\, electronic system design\, design automation\, and manufacturing topics related to micro- and nanoelectronics\, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA\, Horizon Europe\, and local governments in recent years. This conference will highlight the exciting and promising results primarily from the PENTA/XECS\, ECSEL/KDT & H2020/Horizon Europe projects. \nThis annual event has a clear focus on deep technical discussions between the leading European experts in the addressed fields\, independent from the research programs where the individual projects were started. All European projects related to electronic system design\, to design technology and to manufacturing topics are invited to contribute to the conference. \nThe 100 expected attendees will include project managers and leading experts in R&D projects in the fields of nanoelectronics and design technologies and their applications\, semiconductor-industry R&D managers\, microelectronics experts in applications industries like automotive and industrial\, and the major research organizations in the European scientific community. \nVENUE \nThis year\,  ADTC takes place in the Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\,  in “Attique” room. For more information\, please sroll down. \nFINANCIAL CONCEPT \nADTC is organized as collaboration event for experts in the field. All attendees benefit from the intensive information exchange and share the cost\, which will be kept low. It is a nonprofit event\, the local organisers do not get any compensation for their work. Most attendees contribute actively to the event\, e.g. as speaker or panelist\, therefore free participation is not possible.
URL:https://marketingeda.com/event/european-nanoelectronics-applications-design-and-technology-conference/
LOCATION:Y-SPOT Building\, 5\, Place Nelson Mandela\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ADTC23-3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230620T090000
DTEND;TZID=Asia/Tokyo:20230620T203000
DTSTAMP:20230606T163917Z
CREATED:20230606T163917Z
LAST-MODIFIED:20230606T163917Z
UID:6456-1687251600-1687293000@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2023 Summer
DESCRIPTION:RISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20\, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center\, the University of Tokyo ). The “RISC-V Booth” will be held in the foyer and the Event space of Ito Hall. We will also have an “Online RISC-V Booth” on our website. RISC-V Day(s) Tokyo gathers excellent RISC-V related technologies and products\, as well as key persons and engineers\, to improve product recognition\, realize collaboration between companies\, exchange technology\, collect information\, etc. We aim to provide business opportunities for We are looking forward to your participation at this opportunity! At a later date (around the end of August)\, we are planning to post a video and the presentation material on the web page. Information will be provided on a website.
URL:https://marketingeda.com/event/risc-v-days-tokyo-2023-summer/
LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20230620T000000
DTEND;TZID=Asia/Taipei:20230620T000000
DTSTAMP:20230517T174045Z
CREATED:20230517T173815Z
LAST-MODIFIED:20230517T174045Z
UID:6410-1687219200-1687219200@marketingeda.com
SUMMARY:SNUG Taiwan 2023
DESCRIPTION:As the electronics industry’s largest user conference\, SNUG Taiwan is dedicated to demonstrating the state-of-the-art innovations from the chip design community around the globe. This year\, we are excited to announce that the SNUG Taiwan in-person event is back! \nSNUG Taiwan continues to foster the link between Synopsys’ tool users and technical experts so they can share best practices for electronic design and verification challenges. Join us at SNUG Taiwan to discuss cutting-edge technology and trends in the semiconductor industry\, explore the infinite possibilities of AI applications\, be ready for the challenges in the new era of chip design and verification. \nSNUG is restricted to Synopsys customers* only\, and offered at no charge.
URL:https://marketingeda.com/event/snug-taiwan-2023/
LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Taiwan-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230614T080000
DTEND;TZID=Europe/Berlin:20230615T170000
DTSTAMP:20230612T171200Z
CREATED:20230313T202424Z
LAST-MODIFIED:20230612T171200Z
UID:6114-1686729600-1686848400@marketingeda.com
SUMMARY:GSA 2023 European Executive Forum
DESCRIPTION:Dealing with Uncertainty\nThe global economy is sending mixed messages\, and with every new data release comes a new batch of upbeat or defeatist headlines. \nUncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in years\, on the other all major tech companies have announced significant layoffs.  The chip shortage is not over yet in some segments\, but in some others there is excess supply. Our new multipolar world order will enforce structural changes to the economy\, such as the need to rebuild reliable supply chains closer to home\, which often comes at higher prices. \nDespite these uncertainties\, innovation in our industry remains as strong as ever\, with relentless growth driven by automotive\, 5G and next generation connectivity\, new silicon design paradigms including RISC-V and chiplets\, big trends towards decarbonization and new materials like SiC\, the positive effects of increased diversity and inclusion. And large amounts of government money is made available globally to support this growth\, through “chips acts” and “green deals”. \nThere is therefore a strong belief that tech innovation and growth will continue to prevail and\, with a little more positive international cooperation\, deal with the apparent challenges altogether. \n\n\n\n\n\n\n\n\n\n\nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: close to 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region.
URL:https://marketingeda.com/event/gsa-2023-european-executive-forum/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:EDA,Forum,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-14-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230614T170000
DTSTAMP:20230608T190924Z
CREATED:20230608T190924Z
LAST-MODIFIED:20230608T190924Z
UID:6470-1686643200-1686762000@marketingeda.com
SUMMARY:PCI-SIG Developers Conference 2023
DESCRIPTION:The PCI-SIG Developers Conference 2023 is returning to Santa Clara on June 13-14\, 2023! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers agree that this is an event you won’t want to miss. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nAttendee Registration– Register Now!\nOnline attendee registration will close on Thursday\, June 8th at 5:00 pm PST. You can still register onsite! All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting – Register Now!\nThe PCI-SIG Annual Meeting will be held on June 13th\, 2023. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nAgenda\nThe 2023 US Developer Conference agenda has been posted to the PCI-SIG website. \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com.
URL:https://marketingeda.com/event/pci-sig-developers-conference-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/PCI-SIG_Web_Banner_US_DevCon_2023_1000x500_011923.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230524T191605Z
CREATED:20230524T191605Z
LAST-MODIFIED:20230524T191605Z
UID:6434-1686643200-1686646800@marketingeda.com
SUMMARY:Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
DESCRIPTION:Fueled by the recent adoption by leading smartphone brands\, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive\, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar\, enabling features such as Child Presence Detection (CPD). \nIn this webinar\, you will learn about: \n• UWB technology and ecosystem (UWB alliance\, CCC\, FiRa)\n• How does UWB Radar work\n• CEVA’s UWB and Radar solutions\n\n\nTarget Audience\nSystem engineers\, SoC designers\, and product managers targeting UWB devices\, that are looking to add radar capabilities to products for automotive\, industrial\, consumer\, and others\n\n\nSpeakers\n\n\n\n\n\n\n\nNavot Goren\nUWB Product Director\, CEVA Inc.
URL:https://marketingeda.com/event/driving-forward-with-uwb-radar-enhancing-child-safety-in-automotive/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230611T080000
DTEND;TZID=Asia/Tokyo:20230616T170000
DTSTAMP:20230228T182652Z
CREATED:20230228T182652Z
LAST-MODIFIED:20230228T182652Z
UID:6035-1686470400-1686934800@marketingeda.com
SUMMARY:2023 Symposium on VLSI Technology and Circuits
DESCRIPTION:VLSI Symposium is an international conference on semiconductor technology and circuits that offers an opportunity to interact and synergize on topics spanning the range from process technology to system-on-chip. \nWe appreciate you to visit the VLSI symposium website. We also would like to invite you to join “2023 Symposium on VLSI technology and Circuits\,” which will be held from Sunday\, June 11 to Friday\, June 16 at Rihga Royal Hotel Kyoto in Japan. 2023 Symposium is planned as a fully in-person event in Kyoto for the first time in four years. On-demand access to technical papers will be available for people who cannot travel to Kyoto. We keep monitoring the COVID-19 pandemic and will inform you any changes in the symposium program. \nAbout the Symposium\nProfessors Shoji Tanaka and Walter Kosonocky\, founders of the Symposium\, first organized the VLSI Technology Symposium in 1981 with the hope of offering an opportunity for world’s top technologists to engage in an open exchange of ideas on what was quickly becoming a revolution in the world’s industrial capability. Since then\, the Symposium has been held annually and has grown to be an important and valuable event for people working in the VLSI business. The presentation of high-quality papers has made it possible for attendees to learn about new directions in the development of VLSI technology. The friendly atmosphere has made this an enjoyable learning experience. \nThe Symposium on VLSI Technology has alternated each year between sites in US and Japan. In 1987\, the first Symposium on VLSI Circuits was held in conjunction with the Technology Symposium in recognition of the growing interest to provide the same small but intense and open forum for discussing circuit and system implementations. Since then\, this annual meeting has increased its value over the past 30 years. We are confident that so many new technologies and circuits were introduced in the past Symposia and thus have contributed to the prosperity of the world. Its sponsors continue to be the IEEE Electron Devices Society and Solid-State Circuits Society\, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics\, Information and Communication Engineers. \nFor many reasons\, these meetings have remained linked for the past years to provide opportunities for technology people and circuit and system designers to interact with each other. These interactions are augmented with short courses\, invited speakers and several evening panel discussions\, Forums\, Workshops. In recognition of the efforts of organizers\, authors and participants to make the Symposia successful\, there is ample banquet and entertainment prearranged. \nIn its 42nd year of delivering a unique convergence of technology and circuits for the microelectronics industry\, the 2022 Symposium on VLSI Technology & Circuits had been merged into one Symposium to maximize the synergy across both domains. \nAfter the 2020 meeting had been held in a fully virtual format due to COVID-19\, the 2022 meeting was held in Honolulu\, Hawaii. This year it will be returning to the RIHGA Royal Hotel in Kyoto\, Japan in June of 2023. \nDATE AND LOCATION\nThe 2023 Symposium on VLSI Technology and Circuits will be held on June 11-16\, 2023\, JST respectively.\nAll the meetings will be held at RIHGA Royal Hotel Kyoto\, Horikawa Shiokoji\, Shimogyo ku \, Kyoto 600 8237\, Japan. \nHeld as a six-day at the Rihga Royal Hotel\, as well as selected presentations and panel sessions\, the Symposium will feature advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nThe weeklong Symposium will continue its reputation as the microelectronics industry’s premiere international conference integrating technology\, circuits\, and systems with a range and scope unlike any other conferences. In addition to the technical presentations\, the Symposium program will feature a demonstration session\, evening panel discussions\, joint focus sessions\, short courses\, workshops\, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposium theme.
URL:https://marketingeda.com/event/2023-symposium-on-vlsi-technology-and-circuits/
LOCATION:Rihga Royal Hotel\, Kyoto\, Japan
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2023-Symposium.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Andorra:20230605T080000
DTEND;TZID=Europe/Andorra:20230609T170000
DTSTAMP:20230211T031337Z
CREATED:20230211T031337Z
LAST-MODIFIED:20230211T031337Z
UID:5944-1685952000-1686330000@marketingeda.com
SUMMARY:RISC-V Summit Europe
DESCRIPTION:On 5-9th June\, in Barcelona\, RISC-V Summit Europe brings together developers\, architects\, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia\, research\, SMEs\, industry and open source communities will gather to exchange knowledge\, ideas\, technologies\, and research shaping the future of RISC-V computing. \nThe event will include a single track of keynotes\, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions. \nRISC-V Summit Europe is an opportunity not to be missed\, comme to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation! \nThe Program Committee\n\nJan Andersson (Cobham Gaisler)\nHolger Blasum (Sysgo)\nAlex Bradbury (Igalia)\nRamon Canal (UPC)\nDenis Dutoit (CEA)\nAngelo Garofalo (ETH Zürich)\nBenedikt Gierlichs (KU Leuven)\nFrederic Heitzmann (Tiempo Secure)\nJohn Hengeveld (Intel)\nEyck Jentzsch (MINRES)\nNick Kossifidis (FORTH)\nMarie-Minerve Louerat (LIP6)\nAndreas Mauderer (Bosch)\nDaniel Müller-Gritschneder (TUM)\, PC Co-Chair\nJérôme Quévremont (Thales)\nRihards Novickis (EDI\, Latvia)\nKatzalin Olcoz Herrero (UCM)\nOlivier Savry (CEA)\nDavide Schiavone (OpenHW Group)\nGeorg Sigl (TUM)\, PC Co-Chair\nJonathan Woodruff (Cambridge Univ.)\nDaniel Müller-Gritschneder (TU Münich)\nJérôme Quévremont (Thales R&T)\nBorja Pérez Pavon (Univ. de Cantabria)\, Submission Chair\n\nThe Steering Committee\n\nNarcís Avellana (NVision)\nTeresa Cervero (BSC)\nRomain Dolbeau (SiPearl)\nWolfgang Ecker (Infineon)\nRoger Espasa (Semidynamics)\nChristian Fabre (CEA)\nFrank K. Gürkaynak (ETH Zürich)\nDaniel Müller-Gritschneder (TU Münich)\nBorja Pérez Pavon (Univ. de Cantabria)\nJérôme Quévremont (Thales R&T)\nOlivier Sentieys (INRIA\, France)\nPhilipp Tomsich (VRULL)\nStefan Wallentowitz (HM Münich)
URL:https://marketingeda.com/event/risc-v-summit-europe/
LOCATION:Barcelona\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230601T110000
DTEND;TZID=America/Los_Angeles:20230601T120000
DTSTAMP:20230421T164256Z
CREATED:20230421T164256Z
LAST-MODIFIED:20230421T164256Z
UID:6308-1685617200-1685620800@marketingeda.com
SUMMARY:Advanced Testbench for a Simple DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn part 2 of this webinar series\, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently\, check and prove that we have indeed verified our simple DUT more thoroughly\, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control\, and introduce functional coverage. \nHaving shown you these more advanced testbench techniques\, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability\, maintainability\, and extensibility. \nAgenda:\nWhat is required when verifying for higher quality?\nThe elements of an advanced testbench infrastructure\nAdvanced BFMs\nBFM vs Protocol Checkers\nBFM limitations\nAdvanced randomization\nSpecification Coverage\, aka Requirements Coverage\nIntroducing functional coverage\nUVVM advanced BFMs\nUVVM for high quality verification\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-simple-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230531T083000
DTEND;TZID=America/New_York:20230531T170000
DTSTAMP:20230530T203817Z
CREATED:20230530T203817Z
LAST-MODIFIED:20230530T203817Z
UID:6438-1685521800-1685552400@marketingeda.com
SUMMARY:STAC Summit
DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment.
URL:https://marketingeda.com/event/stac-summit/
LOCATION:New York Marriott Marquis\, 1535 Broadway\, New York City\, NY\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230525T120000
DTSTAMP:20230515T234754Z
CREATED:20230515T234719Z
LAST-MODIFIED:20230515T234754Z
UID:6394-1684918800-1685016000@marketingeda.com
SUMMARY:Requirements for Multi-Die System Success
DESCRIPTION:Wednesday\, May 24\, 2023 and Thursday\, May 25\, 2023  \n\n\n\n\n\n\n\n\n\n\nThe industry is moving to multi-die systems to benefit from the greater compute performance\, increased functionality\, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning\, die/package co-design\, secure and robust die-to-die connectivity\, reliability and health\, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful. \n\n\nMay 24th presentation topics will include: \n\n9:00 a.m. PDT: Multi-Die System Trends\, Challenges and Requirements\n10:00 a.m. PDT: Benefits of Early Architecture Design for Multi-Die Systems\n11:00 a.m. PDT: Innovations in Multi-Die System Co-Design and System Analysis\n\nMay 25th presentation topics will include: \n\n9:00 a.m. PDT: Successful Connectivity of Heterogeneous Dies with UCIe IP\n10:00 a.m. PDT: Identifying and Overcoming Multi-Die System Verification Challenges\n11:00 a.m. PDT: Optimizing Multi-Die System Health from Die to Package to In-Field\n\n  \nRegister once for access to all the webinars.
URL:https://marketingeda.com/event/requirements-for-multi-die-system-success/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230504T164101Z
CREATED:20230504T164101Z
LAST-MODIFIED:20230504T164101Z
UID:6359-1684918800-1684922400@marketingeda.com
SUMMARY:DENSO discusses Verification of network relay performance using VisualSim
DESCRIPTION:Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. \nEfficient in-vehicle network development through simulation combining network and ECU hardware and software elements \nTime Zone:\nJapan – 3:00 PM (In Japanese)\nAsia – 3:00 PM Korea | 2:00PM China | 11:30PM India\nEurope – 10:00 CEST\nAmericas – 09:00AM PST | 12:00PM EST
URL:https://marketingeda.com/event/denso-discusses-verification-of-network-relay-performance-using-visualsim/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T080000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230427T170718Z
CREATED:20230427T170718Z
LAST-MODIFIED:20230427T170718Z
UID:6343-1684915200-1684922400@marketingeda.com
SUMMARY:Extending RISC Processors into Flexible Accelerators using ASIP Designer
DESCRIPTION:Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications\n\nThe slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems\, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications. \n  \nWho Should Attend?\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\n\nAgenda\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAn Introduction to Domain-Specific Processors and ASIP Designer\n\n\nPatrick Verbist\, Sr. Product Manager\, Synopsys Belgium \nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n08:00am – 8:50am PT \nDomain-specific processors (also referred to as Application-specific processors\, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys’ ASIP Designer tool-suite. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: Energy-Efficient Application-Specific Instruction Set Processor for Feature Extraction in Smart Vision Systems\n\n\nLucas Ferreira\, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department\, Lund University\n \n8:50am – 9:20am PT \nIn computer-vision feature extraction algorithms\, compressing the image into a sparse set of trackable keypoints\, empowers navigation-critical systems such as Simultaneous Localization and Mapping (SLAM) in autonomous robots\, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First\, the overall on-chip memory requirements can be lessened\, and second\, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP)\, designed with Synopsys ASIP Designer\, optimized for performing feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) is thoroughly explored to validate the proposed architecture\, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale\, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: An ASIP for Post-Quantum Cryptography\n\n\nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n9:20am –10:00am PT \nKyber\, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers\, is computationally very demanding due to extensive use of hashing\, for example. In this case study\, an ASIP optimized for accelerating Kyber was developed\, starting from an open-source implementation compiled and profiled on a RISC-V base model\, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround\, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. \nMeet The Speakers\n\n\n\n\nPatrick Verbist \nSr. Product Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nPatrick Verbist is the Product Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\nFalco Munsche \nTechnical Marketing Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP Design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \nHe holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\nLucas Ferreira \nPhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department \nLund University \n\n\n\n\n\n\n\n\n\nLucas Ferreira was born in São Paulo\, Brazil\, 1993. He received his bachelors both in Science and Technology\, and Automation and Control Engineering respectively at Federal University of ABC 2015-2017 (São Paulo). In 2019 he received his M.Sc. degree in Embedded Electronics from Lund University. \nSince May 2019\, he is working at the department of Electrical and Information Technology\, Lund University as a doctoral candidate. His main focus of research is on domain-specific processor design with focus on computer vision\, machine learning\, and autonomous drones.
URL:https://marketingeda.com/event/extending-risc-processors-into-flexible-accelerators-using-asip-designer/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230522T080000
DTEND;TZID=America/Los_Angeles:20230524T170000
DTSTAMP:20230331T185032Z
CREATED:20230331T184530Z
LAST-MODIFIED:20230331T185032Z
UID:6216-1684742400-1684947600@marketingeda.com
SUMMARY:Embedded Vision Summit 2023
DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\n\nJoin us for four days of learning—from tutorials to deep-dive days\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\n\n4 Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\nWe’ve been doing this for 12 years.\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.\n\n\n\n\n\n\nLearn\n\n\n\n\n\nIn order to deliver real-world insights and know-how into the most current topics in the industry to our attendees\, we have packed the program with learning opportunities\, including: \nSpeakers and Sessions: Learn from the best and listen to over 100 expert speakers who actively work in the industry present on the latest applications\, techniques\, technologies and opportunities in computer vision and visual AI. \n\n\nSee\n\n\n\n\n\n100+ Exhibitors and Hundreds of Demos: Visit the exhibitors on the exhibit floor and see their latest technologies that enable perception—processors\, algorithms\, software\, sensors\, developer tools\, services and more! You’ll get to see technology in action by watching cool demos from building-block component suppliers to learn about new and existing solutions to your business and engineering challenges. \nEnabling Technologies Track: If you’re a product developer\, engineer or business leader looking for real-world\, commercial technologies that will help you add visual intelligence and AI to your new products\, you’ll want to attend this track’s sessions. You can see things\, like: \n\nProcessors and tools for deep-learning-based object recognition.\nOptimized software components for low-cost\, energy-efficient\, real-time vision.\nFrameworks and services for faster product development.\n\n\n\nConnect\n\n\n\n\n\nBuilding valuable business connections is crucial. At the Summit you can connect with engineers\, marketers\, executives—they’re all here! Here’s how: \n\nQ&A Sessions: Join in on post-talk Q&A sessions and have your important questions answered directly by the expert speakers.\nMeet the Exhibitors and Sponsors: Connect with key engineers and technologists from top computer vision building-block suppliers to learn about their latest processors\, software\, development tools and more.\nMingle at the Technology Exhibits Reception. The evening of Tuesday\, May 23\, enjoy great food and refreshing beverages while meeting new folks and seeing awesome tech demos at our Exhibits Reception!\nNetwork at the 3rd annual Women In Vision Reception sponsored by Perceive.
URL:https://marketingeda.com/event/embedded-vision-summit-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summit-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230521T080000
DTEND;TZID=America/Los_Angeles:20230525T170000
DTSTAMP:20230122T013506Z
CREATED:20230122T013506Z
LAST-MODIFIED:20230122T013506Z
UID:5867-1684656000-1685034000@marketingeda.com
SUMMARY:ISCAS 2023
DESCRIPTION:The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory\, design and implementation of circuits and systems. \nKeynote Speakers\n\nDr. Margaret Martonosi\n\n\n\nMargaret Martonosi is the US National Science Foundation’s (NSF) Assistant Director for Computer and information Science and Engineering (CISE). With an annual budget of more than $1B\, the CISE directorate at NSF has the mission to uphold the Nation’s leadership in scientific discovery and engineering innovation through its support of fundamental research and education in computer and information science and engineering as well as transformative advances in research cyberinfrastructure. While at NSF\, Dr. Martonosi is on leave from Princeton University where she is the Hugh Trumbull Adams ’35 Professor of Computer Science. \n\nStuart Russell\n\n\n\ntuart Russell is a Professor of Computer Science at the University of California at Berkeley\, holder of the Smith-Zadeh Chair in Engineering\, and Director of the Center for Human-Compatible AI. He is a recipient of the IJCAI Computers and Thought Award and Research Excellence Award and held the Chaire Blaise Pascal in Paris. In 2021 he received the OBE from Her Majesty Queen Elizabeth and gave the Reith Lectures. He is an Honorary Fellow of Wadham College\, Oxford\, an Andrew Carnegie Fellow\, and a Fellow of the American Association for Artificial Intelligence\, the Association for Computing Machinery\, and the American Association for the Advancement of Science. His book “Artificial Intelligence: A Modern Approach” (with Peter Norvig) is the standard text in AI\, used in 1500 universities in 135 countries. His research covers a wide range of topics in artificial intelligence\, with a current emphasis on the long-term future of artificial intelligence and its relation to humanity. He has developed a new global seismic monitoring system for the nuclear-test-ban treaty and is currently working to ban lethal autonomous weapons. \n\nYoky Matsuoka\n\n\n\nYoky Matsuoka is the Founder & CEO of Yohana\, an independently led subsidiary of Panasonic focused on building consumer technology products and services to help people live healthier and happier lives. As an accomplished executive and technologist\, Matsuoka brings more than two decades of leadership experience to her role where she also leads global innovation and serves as the Managing Executive Officer of Panasonic Corporation. \n\nDongjin (DJ) Seo\n\n\n\nDongjin (DJ) Seo is co-founder and VP of Brain Interfaces at Neuralink\, where he leads the team responsible for everything (electrodes\, materials\, electronics\, firmware\, packaging\, manufacturing\, algorithms\, and more) in the brain implant. DJ received his PhD from UC Berkeley in 2016 for his work on ultrasonic wireless neural implant technology called neural dust and BS in EE at Caltech in 2011 where he designed ICs and antennas for next-gen wireless communication and imaging systems. He also held several internships building high-performance and low-power circuits for sensor networks. For his work\, DJ was named one of MIT Technology Review’s Innovators Under 35 in 2020. \n\nDr. Thomas Anderson\n\n\n\nDr. Andersen heads the Artificial Intelligence and Silicon Innovation group at Synopsys\, where he focuses on developing new technologies in the AI\, ML and advanced technology space to automate the future of chip design. \nLieven Vandersypen\nProf. Dr. ir Lieven Vandersypen is Antoni van Leeuwenhoek professor in Quantum Nanoscience at Delft University of Technology and Scientific Director of QuTech\, an advanced research center for Quantum Computing and Quantum Internet. He received a MSc in Mechanical Engineering from KU Leuven\, and a MSc/PhD in Electrical Engineering from Stanford University for the first experiments in quantum computing.
URL:https://marketingeda.com/event/iscas-2023/
LOCATION:Monterey\, CA\, Monterey\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISCAS-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230518T170000
DTEND;TZID=America/Los_Angeles:20230518T193000
DTSTAMP:20230509T195717Z
CREATED:20230509T195527Z
LAST-MODIFIED:20230509T195717Z
UID:6378-1684429200-1684438200@marketingeda.com
SUMMARY:Annual ESDA Membership Meeting & CEO Outlook
DESCRIPTION:The evening begins at the Keysight office\, Thursday\, May 18\, at 5:00pm with the ESD Alliance Annual Membership Meeting. You’ll get an overview of the past year’s activities and discover what’s in store for 2023. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook. \nEnjoy a lively\, nourishing networking reception that kicks off the CEO Outlook panel. Hear influential executives share their insights on the current and future state of the design and semiconductor industries. \nAgenda \n\n5:00 pm – 5:30 pm\n\n\n\nBob Smith\nExecutive Director\nESD Alliance\n\n\n\nESD Alliance Annual Membership Meeting\n\nOverview of ESD Alliance activities for 2022 and plans for 2023. \n\n\n\n\n\n5:30 pm – 6:30 pm\n\n\nNetworking\n\nEnjoy light food and refreshments as you network with your peers \nCEO Outlook Panel\n\n6:30 pm – 7:30 pm\n\n\n\nEd Sperling | Moderator\nEditor in Chief\nSemiconductor Engineering\n\n\n\nModerator & Panelists\n\nHear panelists from Ansys | ESD Alliance | IC Manage | Keysight | PDF Solutions | Real Intent | Siemens EDA discuss the state of the electronic system design industry as well as their views of the outlook for the coming years. \nDean Drako | President and CEO | IC Manage\nNiels Faché | VP and GM Keysight EDA | Keysight\nJohn Kibarian | President and CEO | PDF Solutions\nJohn Lee | VP and GM | Ansys\nPrakash Narain | President and CEO | Real Intent\nJoseph Sawicki | Executive Vice President | Siemens IC EDA\nSimon Segars | Governing Council Chair | ESD Alliance
URL:https://marketingeda.com/event/annual-esda-membership-meeting-ceo-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESDA-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230518T110000
DTEND;TZID=America/New_York:20230518T120000
DTSTAMP:20230515T173657Z
CREATED:20230515T173657Z
LAST-MODIFIED:20230515T173657Z
UID:6390-1684407600-1684411200@marketingeda.com
SUMMARY:Addressing Silent Data Errors for Resilient Data Centers
DESCRIPTION:Mark your calendar to join us on Thursday\, May 18 at 11 a.m. EDT for an Open Compute Project (OCP) Foundation educational webinar on Addressing Silent Data Errors for Resilient Data Centers. \nDuring the webinar\, you will learn: \n\nWhat is the magnitude of silent data errors (SDE)\nHow does SDE impact end users\nWhat is the cost of detecting SDE using traditional methods\nNovel techniques for detecting and mitigating SDE\nData center efficiencies improvement with better SDE containment\n\n  \nSpeakers: \n\nCliff Grossner\, VP Market Intelligence & Innovation\, OCP \nAshish Nadkarni\, Group Vice President and General Manager\, IDC \nRama Govindaraju\, Director of Engineering\, Google\nWalter Abramsohn\, Director of Product Marketing\, proteanTecs
URL:https://marketingeda.com/event/addressing-silent-data-errors-for-resilient-data-centers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OCP-May-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230509T083000
DTEND;TZID=America/New_York:20230509T164000
DTSTAMP:20230404T200716Z
CREATED:20230404T200716Z
LAST-MODIFIED:20230404T200716Z
UID:6236-1683621000-1683650400@marketingeda.com
SUMMARY:TSMC - Boston Technology Workshop
DESCRIPTION:Join us and learn about:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-boston-technology-workshop/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,IP,Semiconductor,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-Technology-Symposium.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20230509T080000
DTEND;TZID=Europe/Rome:20230511T170000
DTSTAMP:20230214T182749Z
CREATED:20230214T182749Z
LAST-MODIFIED:20230214T182749Z
UID:5965-1683619200-1683824400@marketingeda.com
SUMMARY:Workshop on Open-Source Hardware\, CF23-OSHW
DESCRIPTION:Co-located with ACM International Conference on Computing Frontiers 2020 May 9 – May 11\, 2023 – Bologna\, Italy \nWe are excited to announce a new workshop on the topic of open-source hardware\, to be held concurrently with Computing Frontiers 2023. \nAim and Scope\nThe workshop aims to bring together researchers and practitioners working in the fields of computer architecture\, electrical engineering\, and computer science to discuss and share their latest research and developments in open hardware and open-source hardware. We welcome submissions on a wide range of topics\, including but not limited to: \n\nDesign/implementation of open-source processors\, memory systems\, and I/O devices\nOpen-source CAD tools and methodologies for hardware design\nOpen-source embedded systems and IoT devices\nOpen-source PCB\, FPGA\, and ASIC design and fabrication\nOpen-source firmware and software for embedded systems\nOpen-source test and verification frameworks for hardware\nOpen-source power and energy-efficient systems\nHardware security and trust in open-source systems\n\nSubmissions should be in the form of an extended abstract (2 pages)\, formatted according to the double-column ACM conference format\, accompanied by a link to a public repository (GitHub\, etc.). Accepted abstracts will be included in the workshop proceedings and published in the ACM Digital Library. At least one author of an accepted abstract is required to register for the whole Computing Frontiers 2023 conference. \nSubmission page and information\nSubmit at https://easychair.org/my/conference?conf=oshw23. \nProceedings from the workshop will be published by ACM along with regular Computing Frontiers papers. \nImportant dates\n\nAbstract submission deadline: March 6\, 2023\nNotification of acceptance: March 17\, 2023\nCamera ready deadline: March 24\, 2023\n\nWorkshop co-chairs:\nThe co-chairs: \n\nDavide Schiavone\, OpenHW group\, Switzerland\nAngelo Garofalo\, ETH Zurich\, Switzerland\nFrancesco Conti\, University of Bologna\, Italy\nFrank K. Gürkaynak\, ETH Zurich\, Switzerland\n\nFor more information or any questions\, please contact us. \nWe look forward to receiving your submissions and seeing you at the workshop!
URL:https://marketingeda.com/event/workshop-on-open-source-hardware-cf23-oshw/
LOCATION:Piazza San Giovanni in Mone\, 1/2\, Piazza San Giovanni in Monte\, Bologna\, Italy
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSHW-23.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230508T080000
DTEND;TZID=Asia/Jerusalem:20230509T170000
DTSTAMP:20230331T183459Z
CREATED:20230331T183459Z
LAST-MODIFIED:20230331T183459Z
UID:6212-1683532800-1683651600@marketingeda.com
SUMMARY:ChipEx 2023
DESCRIPTION:The major annual event of the Israeli semiconductor industry \nChipEx2023\, the largest annual event of the Israeli semiconductor industry\, will be held on May 9\, 2023 in Tel Aviv\, Israel. ChipEx2023 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2023 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2023 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2023 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2023 exhibition will take place on May 9\, 2023 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2023 technical seminar will take place on May 9\, 2023 at the Tel-Aviv Expo Center. \n  \nChipEx2023 Executive Summit \n  \nThe opening session of ChipEx2023 will take place on May 8\, 2023 at Hilton Hotel Tel-aviv and will include top industry figures and will act as the Executive summit of ChipEx2023 targeting Industry leaders and top executives from Israel and around the globe. \n  \nChipEx2023 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \n  \nWe invite you to take part in ChipEx2023 as an exhibitor\, a speaker and/or as a sponsor. \n  \nFor more details please contact us at:\nPhone: +972-9-7454007\nFax: +972-9-7748858\ninfo@chiportal.co.il\nwww.chipex.co.il
URL:https://marketingeda.com/event/chipex-2023/
LOCATION:Hilton Hotel Tel-aviv\, HaYarkon St 205\, Tel aviv\, Israel
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230505T170000
DTEND;TZID=America/Los_Angeles:20230505T190000
DTSTAMP:20230428T162407Z
CREATED:20230428T162407Z
LAST-MODIFIED:20230428T162407Z
UID:6346-1683306000-1683313200@marketingeda.com
SUMMARY:May 2023 Austin RISC-V Meetup
DESCRIPTION:The Austin RISC-V Group is back\, and we’re planning a regular schedule of the second Tuesday of every month. This will be an on-line event. We’ll be the RISC-V Bivy virtual meeting system\, and this is the same as the event on the RISC-V Community site. The use of a microphone and/or camera are not required to participate in the event\, chat will be monitored. \nAgenda: \nQuick overview current and future hardware releases\, state of various software projects. \nOverview of the RISC-V specifications and how all the pieces fit together to make a computer. \nFirst steps on the RISC-V Linux Capable SoC FPGA development (all those words will be explained in the previous section if you are confused). Expect lots of diagrams and maybe some bitstreams by the end of the night \n\nOrganizers\nJonah McLeod\nAndes Technology Corp \nCo-Organizer \nCarl Perry\nSingle Board Computing Inc \nHost
URL:https://marketingeda.com/event/may-2023-austin-risc-v-meetup/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-May-9-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230503T083000
DTEND;TZID=America/Los_Angeles:20230503T164000
DTSTAMP:20230404T200249Z
CREATED:20230404T200249Z
LAST-MODIFIED:20230404T200249Z
UID:6233-1683102600-1683132000@marketingeda.com
SUMMARY:TSMC - Austin Technology Workshop
DESCRIPTION:Join us and learn about:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-austin-technology-workshop/
LOCATION:Omni Barton Creek Resort & Spa\, 8312 Barton Club Drive\, Austin\, TX\, United States
CATEGORIES:EDA,IP,Semiconductor,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-Technology-Symposium.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230502T140000
DTEND;TZID=Asia/Jerusalem:20230502T170000
DTSTAMP:20230424T174117Z
CREATED:20230424T173840Z
LAST-MODIFIED:20230424T174117Z
UID:6323-1683036000-1683046800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Shine Chung\nChairman\nAttopsemi Technology \n\nRevolutionary Metal I-fuse® OTP in FinFET Tech\n\nUmesh Sisodia\nCEO\nCircuitSutra \n\nTransforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies\n\nRoger Espasa\nCEO & FounderSemidynamics \n\nRISC-V\, Out-of-Order IP Core\, Vector Unit\n\nSiddharth Ravikumar\nTechnical Product Manager\, Solido IP ValidationSiemens EDA \n\nIP\, QA\, Validation\, analog\, digital\, mixed-signal\n\nMichael Seaholm\nProduct Manager for Performance Oscilloscopes and Margin TestingTektronix Inc. \n\nPCIe Gen 3 and Gen 4 testing\nLarry LapidesVP Worldwide SalesImperas Software \n\nRISC-V Verification & Software Development
URL:https://marketingeda.com/event/semisrael-tech-webinar-5/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-May-2-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230501T080000
DTEND;TZID=America/Los_Angeles:20230504T170000
DTSTAMP:20230419T164215Z
CREATED:20230419T163913Z
LAST-MODIFIED:20230419T164215Z
UID:6300-1682928000-1683219600@marketingeda.com
SUMMARY:IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
DESCRIPTION:IEEE International Symposium on Hardware Oriented Security and Trust (HOST) is the premier symposium that facilitates the rapid growth of hardware-based security research and development. Since 2008\, HOST has served as the globally recognized event for researchers and practitioners to advance knowledge and technologies related to hardware security and assurance. \nRapid proliferation of computing and communication systems with increasing computational power and connectivity into every sphere of modern life has brought security to the forefront of system design\, test\, and validation processes. The emergence of new application spaces for these systems in the internet-of-things (IoT) regime is creating new attack surfaces as well as new requirements for secure and trusted system operation. Additionally\, the design\, manufacturing and the distribution of microchip\, PCB\, as well as other electronic components are becoming more sophisticated and globally distributed with a number of potential security vulnerabilities. Therefore\, hardware plays an increasingly important and integral role in system security with many emerging system and application vulnerabilities and defense mechanisms relating to hardware. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques\, tools\, design/test methods\, architectures\, circuits\, and applications of secure hardware.
URL:https://marketingeda.com/event/ieee-international-symposium-on-hardware-oriented-security-and-trust-host/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/HOST-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T100000
DTEND;TZID=America/Los_Angeles:20230427T110000
DTSTAMP:20230424T163637Z
CREATED:20230424T163637Z
LAST-MODIFIED:20230424T163637Z
UID:6317-1682589600-1682593200@marketingeda.com
SUMMARY:The Path to 1.6TbE with 224G Ethernet PHY IP
DESCRIPTION:The need for faster and more efficient Ethernet solutions has never been greater\, as the demands of high-performance computing and the rise of big data continue to grow. Join us as we explore the main challenges faced in scaling Ethernet to 1.6T and how the high-performance computing is changing the Ethernet landscape. In this webinar\, you will learn about the latest trends in 1.6T Ethernet\, when you can expect this standard\, and the deployment challenges. Discover the new electro-optical interfaces and how Synopsys 1.6T/800G Ethernet IP solution can help ensure your product is first to market. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. Prior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla\n\n\nSr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla is a Sr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio. He has broad experience in analog\, mixed-signal design with strong focus on high performance compute\, mobile and automotive SoCs. He is a contributing member to 802.3dj task force and a IEEE802.3 voter. Priyank has a US patent on low power RTC design.  He received an Electrical Engineering degree from the Indian Institute of Technology-Madras.
URL:https://marketingeda.com/event/the-path-to-1-6tbe-with-224g-ethernet-phy-ip/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-27-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T100000
DTEND;TZID=America/Los_Angeles:20230426T110000
DTSTAMP:20230424T162003Z
CREATED:20230424T162003Z
LAST-MODIFIED:20230424T162003Z
UID:6314-1682503200-1682506800@marketingeda.com
SUMMARY:Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
DESCRIPTION:This webinar will showcase the design\, analysis\, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect\, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC)\, such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys Platform Architect™ to improve the overall architecture of the multi-die system. \nA case study will illustrate how characteristic workload models can be used to analyze the performance of the architecture and identify potential bottlenecks. This webinar will provide attendees with valuable insights into removing these bottlenecks thereby providing high-bandwidth\, low-latency movement of data between processor cores\, IO and memory. Additional configuration\, debug and visualization capabilities of Synopsys Platform Architect that enable these optimizations will be demonstrated. \nWhether you are a chip architect or a system designer\, this webinar will provide valuable insights on how to design and optimize your high-performance\, multi-die chip architecture. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBarry Spotts\n\n\nPrincipal Specialty FAE \nArm \n\n\n\n\n\n\n\n\n\n\n\nBarry is a Field Application Engineer at Arm specializing in semiconductor interconnect solutions.  Barry works directly with Arm partners to assist in developing a IP strategy for their semiconductor architecture project requirements.  He works in tandem to bring design solutions to meet their project goals in relation to ARM Based Subsystems and Interconnect. Barry’s prior roles in the semiconductor industry has EDA knowledge and experience in SPICE\, Verilog\, System-C\, and Co-Verification simulation technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHolger Keding\n\n\nSolutions Application Engineer \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nHolger is a Solutions Application Engineer in the Systems Design Group at Synopsys\, focusing on Virtual Prototyping for early SoC architecture exploration and optimization. Holger is working with Synopsys customers and partners worldwide on system-level virtual prototyping solutions for early architecture exploration\, performance and power analysis\, and system validation. From his prior roles in the Synopsys Verification and Solutions Groups Holger also has a technical background in communication design and HDL Verification.
URL:https://marketingeda.com/event/maximize-performance-and-efficiency-of-multi-die-data-center-chip-designs-with-arm-corelink-cmn-700-and-synopsys-platform-architect/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-26-2023-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T080000
DTEND;TZID=America/Los_Angeles:20230426T170000
DTSTAMP:20230105T171520Z
CREATED:20230105T171520Z
LAST-MODIFIED:20230105T171520Z
UID:5833-1682496000-1682528400@marketingeda.com
SUMMARY:IP SoC Silicon Valley 23
DESCRIPTION:D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nPhysical meeting between vendors and consumers is the unique and non replaceable vehicle to engage business discussions between vendors and clients. Nevertheless this event will also be “replicated” on line after the event aiming at triggering more business opportunities. Posting their talk and recording their presentations on easily accessible platforms will extend innovation sharing among the worldwide IP-SoC Community. \nAny question? Please contact us \nImportant Dates \n\nSubmission Deadline : March 1st 2023\nSlides and presentation records available on April 1st 2023
URL:https://marketingeda.com/event/ip-soc-silicon-valley-23/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-23.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230424T080000
DTEND;TZID=America/Los_Angeles:20230427T170000
DTSTAMP:20230419T162907Z
CREATED:20230419T162847Z
LAST-MODIFIED:20230419T162907Z
UID:6295-1682323200-1682614800@marketingeda.com
SUMMARY:RSAConference 2023
DESCRIPTION:Where the World Talks Security™ \nDon’t miss the opportunity to take your knowledge and skills to the next level at RSAC 2023. Not sure if the complete Conference experience will work with your schedule and budget? We offer several pass options—including an On Demand Pass. But hurry\, our final discount ends Friday\, April 21! \nIn the cybersecurity industry\, no one goes it alone. Instead\, we build on each other’s diverse knowledge to create the next breakthrough—exchanging ideas\, sharing our success stories\, and bravely examining our failures. \nRSA Conference 2023. Stronger Together. \nConnect with Transformative Solutions\nThis year\, it will be easier than ever to find the products and solutions you’re interested in at RSAC 2023. Explore the Expo in person or visit RSAC Marketplace online—or both! Either way\, you’ll be able to connect with hundreds of industry vendors\, meet with their product experts\, discuss your challenges\, and demo the latest solutions. \nYou can visit RSAC Marketplace now to start finding the solutions you need. You can also use it to help you build a list of vendors you want to explore in the Expo during RSAC 2023.
URL:https://marketingeda.com/event/rsaconference-2023/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RSAC-2023.jpg
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