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BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230502T140000
DTEND;TZID=Asia/Jerusalem:20230502T170000
DTSTAMP:20230424T174117Z
CREATED:20230424T173840Z
LAST-MODIFIED:20230424T174117Z
UID:6323-1683036000-1683046800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Shine Chung\nChairman\nAttopsemi Technology \n\nRevolutionary Metal I-fuse® OTP in FinFET Tech\n\nUmesh Sisodia\nCEO\nCircuitSutra \n\nTransforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies\n\nRoger Espasa\nCEO & FounderSemidynamics \n\nRISC-V\, Out-of-Order IP Core\, Vector Unit\n\nSiddharth Ravikumar\nTechnical Product Manager\, Solido IP ValidationSiemens EDA \n\nIP\, QA\, Validation\, analog\, digital\, mixed-signal\n\nMichael Seaholm\nProduct Manager for Performance Oscilloscopes and Margin TestingTektronix Inc. \n\nPCIe Gen 3 and Gen 4 testing\nLarry LapidesVP Worldwide SalesImperas Software \n\nRISC-V Verification & Software Development
URL:https://marketingeda.com/event/semisrael-tech-webinar-5/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-May-2-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230501T080000
DTEND;TZID=America/Los_Angeles:20230504T170000
DTSTAMP:20230419T164215Z
CREATED:20230419T163913Z
LAST-MODIFIED:20230419T164215Z
UID:6300-1682928000-1683219600@marketingeda.com
SUMMARY:IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
DESCRIPTION:IEEE International Symposium on Hardware Oriented Security and Trust (HOST) is the premier symposium that facilitates the rapid growth of hardware-based security research and development. Since 2008\, HOST has served as the globally recognized event for researchers and practitioners to advance knowledge and technologies related to hardware security and assurance. \nRapid proliferation of computing and communication systems with increasing computational power and connectivity into every sphere of modern life has brought security to the forefront of system design\, test\, and validation processes. The emergence of new application spaces for these systems in the internet-of-things (IoT) regime is creating new attack surfaces as well as new requirements for secure and trusted system operation. Additionally\, the design\, manufacturing and the distribution of microchip\, PCB\, as well as other electronic components are becoming more sophisticated and globally distributed with a number of potential security vulnerabilities. Therefore\, hardware plays an increasingly important and integral role in system security with many emerging system and application vulnerabilities and defense mechanisms relating to hardware. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques\, tools\, design/test methods\, architectures\, circuits\, and applications of secure hardware.
URL:https://marketingeda.com/event/ieee-international-symposium-on-hardware-oriented-security-and-trust-host/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/HOST-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T100000
DTEND;TZID=America/Los_Angeles:20230427T110000
DTSTAMP:20230424T163637Z
CREATED:20230424T163637Z
LAST-MODIFIED:20230424T163637Z
UID:6317-1682589600-1682593200@marketingeda.com
SUMMARY:The Path to 1.6TbE with 224G Ethernet PHY IP
DESCRIPTION:The need for faster and more efficient Ethernet solutions has never been greater\, as the demands of high-performance computing and the rise of big data continue to grow. Join us as we explore the main challenges faced in scaling Ethernet to 1.6T and how the high-performance computing is changing the Ethernet landscape. In this webinar\, you will learn about the latest trends in 1.6T Ethernet\, when you can expect this standard\, and the deployment challenges. Discover the new electro-optical interfaces and how Synopsys 1.6T/800G Ethernet IP solution can help ensure your product is first to market. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. Prior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla\n\n\nSr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla is a Sr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio. He has broad experience in analog\, mixed-signal design with strong focus on high performance compute\, mobile and automotive SoCs. He is a contributing member to 802.3dj task force and a IEEE802.3 voter. Priyank has a US patent on low power RTC design.  He received an Electrical Engineering degree from the Indian Institute of Technology-Madras.
URL:https://marketingeda.com/event/the-path-to-1-6tbe-with-224g-ethernet-phy-ip/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T100000
DTEND;TZID=America/Los_Angeles:20230426T110000
DTSTAMP:20230424T162003Z
CREATED:20230424T162003Z
LAST-MODIFIED:20230424T162003Z
UID:6314-1682503200-1682506800@marketingeda.com
SUMMARY:Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
DESCRIPTION:This webinar will showcase the design\, analysis\, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect\, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC)\, such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys Platform Architect™ to improve the overall architecture of the multi-die system. \nA case study will illustrate how characteristic workload models can be used to analyze the performance of the architecture and identify potential bottlenecks. This webinar will provide attendees with valuable insights into removing these bottlenecks thereby providing high-bandwidth\, low-latency movement of data between processor cores\, IO and memory. Additional configuration\, debug and visualization capabilities of Synopsys Platform Architect that enable these optimizations will be demonstrated. \nWhether you are a chip architect or a system designer\, this webinar will provide valuable insights on how to design and optimize your high-performance\, multi-die chip architecture. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBarry Spotts\n\n\nPrincipal Specialty FAE \nArm \n\n\n\n\n\n\n\n\n\n\n\nBarry is a Field Application Engineer at Arm specializing in semiconductor interconnect solutions.  Barry works directly with Arm partners to assist in developing a IP strategy for their semiconductor architecture project requirements.  He works in tandem to bring design solutions to meet their project goals in relation to ARM Based Subsystems and Interconnect. Barry’s prior roles in the semiconductor industry has EDA knowledge and experience in SPICE\, Verilog\, System-C\, and Co-Verification simulation technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHolger Keding\n\n\nSolutions Application Engineer \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nHolger is a Solutions Application Engineer in the Systems Design Group at Synopsys\, focusing on Virtual Prototyping for early SoC architecture exploration and optimization. Holger is working with Synopsys customers and partners worldwide on system-level virtual prototyping solutions for early architecture exploration\, performance and power analysis\, and system validation. From his prior roles in the Synopsys Verification and Solutions Groups Holger also has a technical background in communication design and HDL Verification.
URL:https://marketingeda.com/event/maximize-performance-and-efficiency-of-multi-die-data-center-chip-designs-with-arm-corelink-cmn-700-and-synopsys-platform-architect/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-26-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T080000
DTEND;TZID=America/Los_Angeles:20230426T170000
DTSTAMP:20230105T171520Z
CREATED:20230105T171520Z
LAST-MODIFIED:20230105T171520Z
UID:5833-1682496000-1682528400@marketingeda.com
SUMMARY:IP SoC Silicon Valley 23
DESCRIPTION:D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nPhysical meeting between vendors and consumers is the unique and non replaceable vehicle to engage business discussions between vendors and clients. Nevertheless this event will also be “replicated” on line after the event aiming at triggering more business opportunities. Posting their talk and recording their presentations on easily accessible platforms will extend innovation sharing among the worldwide IP-SoC Community. \nAny question? Please contact us \nImportant Dates \n\nSubmission Deadline : March 1st 2023\nSlides and presentation records available on April 1st 2023
URL:https://marketingeda.com/event/ip-soc-silicon-valley-23/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-23.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230424T080000
DTEND;TZID=America/Los_Angeles:20230427T170000
DTSTAMP:20230419T162907Z
CREATED:20230419T162847Z
LAST-MODIFIED:20230419T162907Z
UID:6295-1682323200-1682614800@marketingeda.com
SUMMARY:RSAConference 2023
DESCRIPTION:Where the World Talks Security™ \nDon’t miss the opportunity to take your knowledge and skills to the next level at RSAC 2023. Not sure if the complete Conference experience will work with your schedule and budget? We offer several pass options—including an On Demand Pass. But hurry\, our final discount ends Friday\, April 21! \nIn the cybersecurity industry\, no one goes it alone. Instead\, we build on each other’s diverse knowledge to create the next breakthrough—exchanging ideas\, sharing our success stories\, and bravely examining our failures. \nRSA Conference 2023. Stronger Together. \nConnect with Transformative Solutions\nThis year\, it will be easier than ever to find the products and solutions you’re interested in at RSAC 2023. Explore the Expo in person or visit RSAC Marketplace online—or both! Either way\, you’ll be able to connect with hundreds of industry vendors\, meet with their product experts\, discuss your challenges\, and demo the latest solutions. \nYou can visit RSAC Marketplace now to start finding the solutions you need. You can also use it to help you build a list of vendors you want to explore in the Expo during RSAC 2023.
URL:https://marketingeda.com/event/rsaconference-2023/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RSAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230424T080000
DTEND;TZID=America/Los_Angeles:20230424T170000
DTSTAMP:20230310T173922Z
CREATED:20230310T173845Z
LAST-MODIFIED:20230310T173922Z
UID:6097-1682323200-1682355600@marketingeda.com
SUMMARY:D&R IP-SoC Silicon Valley 2023
DESCRIPTION:Where : Hyatt Regency Santa Clara\n5101 Great America Parkway\, Santa Clara\, CA \nD&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \nTentative list of first Contributions\, more to come… \nKeynote talk \n\nWelcome to D&R IP SOC community \, Gabrièle Saucier\, D&R\nAccelerating Innovation with Open Hardware \, Gordon Harling\, CMC Microsystems\n\nAnalog IP \n\nIntegrating RF PLLs into Complex SoC to support 5G and WiFi Radios \, Julian Jenkins\, Perceptia Devices Australia Pty Ltd\nPinless Clocking and Sensing \, Rounak Lokare\, Analog Bits Inc.\nAnalog lP Subsystems \, Graham Wood\, Agile Analog\n\nMemory IP \n\nLow Power Memory Solution for AIoT and Edge applications \, Bhavana Chaurasia\, Synopsys Inc.\n\nChiplet and Multi Die SoC System \n\nA Scalable\, Configurable\, Resilient Network-on-chip (NoC) for your complex SoC and Chiplet-based Systems \, Parag Bhatt\, Signature IP Corporation\nThe Future of UCIe for Multi-Die Systems \, Manuel Mota\, Synopsys\, Inc.\nHow to navigate today chiplet based design – Comprehensive toolset for an open ecosystem \, Letizia Giuliano\, AlphaWave SEMI\nA proven silicon project management platform for complex SoCs and Chiplet based systems \, Purna Mohanty\, Marquee Semiconductor\, Inc.\nIP Management Best Practices for Chiplet-Based SoCs \, Simon Butler\, Perforce Software\n\nLife cycle management \n\nEssential IP for the Enablement of Silicon Lifecycle Management \, Ash Patel\, Synopsys Inc.\nNext Generation Hardware based Cyber Security solution using advanced Embedded Analytics monitoring technology \, Lee Harrison\, Siemens Digital Industries Software\n\nInterface IP \n\nThe Future of USB Connectivity of FPGAs in Alternative Applications\, Products\, and Markets \, David Grugett\, GOWIN Semiconductor\nPAM4 PCIe — Gen6 and beyond — enabling the next gen of AI/ML \, David Kulansky\, AlphaWave SEMI\n\nProcessor IP \n\nThe Lost Art of Processor Verification \, Larry Lapides\, Imperas Software\nTWS Applications with RISC-V and HiFi DSP \, Casey Ng\, Cadence Design Systems\, Inc.\n\nArtificial Intelligence SoC \n\nFast\, accurate and adaptable AI at low power\, low cost \, Cheng Wang\, Flex Logix Technologies\, Inc.\nAdvancement in Multimedia interfaces servicing Edge AI markets \, Hezi Saar\, Synopsys\, Inc.\nAI ISP AI-ISP: Adding Real-Time AI Functionality to Image Signal Processing with Reduced Memory Footprint and Processing Latency \, Mankit LO\, VeriSilicon Inc.\n\nAutomotive IP and space application \n\nNew Horizontal Markets\, Reap Benefits from Greater Avenues\, using Controller Area Networks \, Avi Zakai\, Digital Core Design\nSpace Applications – IP Core Challenges and Opportunities \, Chinh Le\, Lewiz Communications Inc.\n\nSecurity Solutions \n\nHow to Secure Devices and Digital Assets with the Correct Root of Trust Solution \, Bart Stevens\, Rambus\, Inc.\nAccelerating the Way Toward a Quantum-Safe Future \, Dana Neustadter\, Synopsys\, Inc.\nEliminate CyberSecurity Threats\, from Product Designs\, at the Silicon Level with Post-Quantum Cryptographic Systems \, Alex Angelou\, Digital Core Design\nSecuring System-in-Package with PUF Technology \, Pim Tuyls\, Intrinsic ID\n\nEthernet IP and Networking \n\n5G drives exponential need in processing enabled by ASICs and IP ecosystem \, Keith Hawkins\, Ericsson\nDeterministic transmission of time critical information with TSN Ethernet (Time Sensitive Network \, Flemming Kongsfelt\, Comcores ApS\nDriving the Future of High-Performance Computing through 224G Ethernet IP \, Manmeet Walia\, Synopsys\, Inc.\n\nAnd more to come…
URL:https://marketingeda.com/event/dr-ip-soc-silicon-valley-2023/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230423T080000
DTEND;TZID=America/Los_Angeles:20230426T170000
DTSTAMP:20221121T190016Z
CREATED:20221121T190016Z
LAST-MODIFIED:20221121T190016Z
UID:5423-1682236800-1682528400@marketingeda.com
SUMMARY:CICC 2023
DESCRIPTION:Sponsored by IEEE and SSCS\, the IEEE Custom Integrated Circuits Conference – CICC –  is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society.
URL:https://marketingeda.com/event/cicc-2023/
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230420T100000
DTEND;TZID=America/Los_Angeles:20230420T110000
DTSTAMP:20230410T210633Z
CREATED:20230410T210633Z
LAST-MODIFIED:20230410T210633Z
UID:6253-1681984800-1681988400@marketingeda.com
SUMMARY:Taking the Risk out of RISC-V with Fast\, Architecture-Driven\, PPA Optimization
DESCRIPTION:The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to differentiate designs across application areas including AI\, machine learning\, automotive\, data center\, mobile\, and consumer. Traditionally\, designing proprietary cores with the right extensions has been challenging given the high degree of complexity and the high level of expertise required. Evaluating the impact of design decisions on power\, performance and area (PPA) can pose a significant hurdle. This webinar will cover two products from Synopsys’ portfolio of industry leading tools: Synopsys ASIP Designer and Synopsys RTL Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach\, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved. \nJim Schultz  \nJim is a Senior Product Manager at Synopsys. As a designer\, his experience includes physical verification\, design planning and design implementation on CPUs\, networking\, and security chips. As a product engineer\, he supported design implementation\, design planning\, and package design at various EDA companies. \nMaria Auras-Rodriguez  \nMaria joined the ASIP Designer R&D Team in 2019 where she focuses on the ASIP Designer’s HDL Generator tool\, including synthesis support for ASIPs. Before joining Synopsys\, she worked as a researcher at the Institute for Communication Technologies and Embedded Systems (ICE) at RWTH Aachen University. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://marketingeda.com/event/taking-the-risk-out-of-risc-v-with-fast-architecture-driven-ppa-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230419T080000
DTEND;TZID=America/Los_Angeles:20230420T170000
DTSTAMP:20230404T184000Z
CREATED:20230223T181353Z
LAST-MODIFIED:20230404T184000Z
UID:6014-1681891200-1682010000@marketingeda.com
SUMMARY:CadenceLIVE Silicon Valley 2023
DESCRIPTION:Join us for CadenceLIVE™ Silicon Valley 2023\, held on April 19-20 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend interesting user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot.
URL:https://marketingeda.com/event/cadencelive-silicon-valley-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230413T090000
DTEND;TZID=America/Los_Angeles:20230413T100000
DTSTAMP:20230411T182846Z
CREATED:20230411T182846Z
LAST-MODIFIED:20230411T182846Z
UID:6257-1681376400-1681380000@marketingeda.com
SUMMARY:Analog Layout with Thomas Parry and Tim Edwards
DESCRIPTION:In this webinar we will take the comparator circuit from last time and look at how to do the layout with the 2 most used open source layout tools. We will send the link to the webinar recording to those who registered. \nWe will cover: \n\nCreation of the transistors\nLayout with Magic\nLayout with Klayout\nCircuit extraction with Magic\nLVS with Netgen\n\nWe will have opportunity for Q&A during the webinar.
URL:https://marketingeda.com/event/analog-layout-with-thomas-parry-and-tim-edwards/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/efabless-April-13-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230413T080000
DTEND;TZID=America/Los_Angeles:20230413T170000
DTSTAMP:20230309T223424Z
CREATED:20230309T223424Z
LAST-MODIFIED:20230309T223424Z
UID:6093-1681372800-1681405200@marketingeda.com
SUMMARY:User2User North America
DESCRIPTION:U2U is your opportunity to learn\, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. \nU2U is focused on these areas: \n\nAnalog/Mixed-Signal Verification\nCalibre Design Solutions & Power Integrity Analysis\nDigital IC Implementation\nFunctional Design & Verification\nHardware-Assisted Verification\nHigh-Level Synthesis/Verification & RTL Power Estimation/Optimization\nNext Gen Packaging and DFM\nPCB Design & Simulation\nTessent Test and Embedded Analytics Solutions\n\nLearn\nPeer-delivered technical sessions will be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of expertise with fellow like-minded professionals. \nConnect\nLevel-up in the Big Ideas lounge where you can get expert advice from our technical teams\, get hands-on the tools in the Usability Lab\, and meet with our Learning team for certification and badging that you can share with your network. \nGrow\nEDA visionaries will share insights into global cross-industry challenges from companies who are optimizing their business using Siemens EDA tools. \nWhat to expect?\nA dedicated environment for exchanging ideas\, information\, and best practices that enable you to lead in your role and achieve success with your customers. \n\nTechnical agenda concentrated on the digital future\nIndustry leaders exploring macro trends and innovation\nSuper users sharing business challenges and roadblocks\nContent demonstrating business results\nNetworking with like-minded peers in EDA
URL:https://marketingeda.com/event/user2user-north-america/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230411T100000
DTEND;TZID=America/Los_Angeles:20230411T110000
DTSTAMP:20230316T183442Z
CREATED:20230316T183341Z
LAST-MODIFIED:20230316T183442Z
UID:6172-1681207200-1681210800@marketingeda.com
SUMMARY:Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
DESCRIPTION:Advanced semiconductor nanometer technology nodes\, together with smart IC design applications enable today very complex and powerful systems for communication\, automotive\, data transmission\, AI\, IoT\, medical\, industry\, energy harvesting\, and many more. However\, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows\, tools & methodologies to meet design requirements in a tight design schedule. Automated circuit sizing and optimization is becoming a very important tool to achieve that. \nMunEDA provides the necessary features to enhance designers’ productivity by circuit optimization within its EDA design tool suite WiCkeD. \nIn this webinar we’ll discuss state-of-the-art circuit optimization methodology\, and particularly how to use it most efficiently in order to enhance design quality and designers’ productivity. \nSpeakers: \nMichael Pronath. Michael is VP of Products & Solutions at MunEDA\, and author and co-author of several international publications about methods of analog integrated circuit design and testing of mixed-signal circuits. \nDave Johnson is President of FirstShift Technologies which represents MunEDA in North America. He has also worked at worked at NXP\, Neolinear\, and Cadence. Dave started his career as an I/O library circuit designer. \n*This webinar is in partnership with SemiWiki and MunEDA*
URL:https://marketingeda.com/event/enhance-productivity-with-machine-learning-in-the-analog-front-end-design-flow/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/MunEDA-April-11-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230405T090000
DTEND;TZID=America/Los_Angeles:20230405T100000
DTSTAMP:20230403T170217Z
CREATED:20230403T170217Z
LAST-MODIFIED:20230403T170217Z
UID:6226-1680685200-1680688800@marketingeda.com
SUMMARY:Choosing the best modeling abstraction for your analysis
DESCRIPTION:This webinar cover the modeling abstraction in the design of electronics\, semiconductors and software. This webinar will definitely improve your modeling skills! \n–Is the abstraction right for your application and design goal? \n–How do you accelerate the simulation using abstraction? \n–Can you change the model of computation using abstraction to simplify the modeling effort? \nDuring the webinar\, you’ll discover the importance of abstraction in modeling and learn how to use it to simplify complex problems. You’ll also explore different types of models and understand how to choose the right one for your specific needs. \nThis webinar is perfect for anyone looking to enhance their modeling skills\, including students\, researchers\, and professionals in fields such as engineering\, computer science\, and mathematics. Our experts will discuss the use of abstraction in complex models like computer systems\, processors\, radar and automotive TSN networks. So\, join us for an engaging discussion on modeling abstraction. Don’t miss this opportunity to gain valuable insights and take your modeling skills to the next level!
URL:https://marketingeda.com/event/choosing-the-best-modeling-abstraction-for-your-analysis/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230405T080000
DTEND;TZID=America/Los_Angeles:20230407T170000
DTSTAMP:20230213T214028Z
CREATED:20230213T214028Z
LAST-MODIFIED:20230213T214028Z
UID:5960-1680681600-1680886800@marketingeda.com
SUMMARY:ISQED 2023
DESCRIPTION:The 24th International Symposium on Quality Electronic Design (ISQED’23) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools\, integrated circuit technologies\, semiconductor technology\,packaging\, assembly & test to achieve total design quality. ISQED 2023 will held with the technical sponsorship of IEEE CASS\, IEEE EDS\, and in-cooperation with ACM/SigDA. Conference proceedings & Papers will be published in IEEE Xplore digital library and indexed by Scopus. \nThis important three day event will be packed full of tutorials and in-depth sessions. The program will also feature the following: \n\nEmbedded information-packed tutorials\nKeynotes by major industry & academia leaders and experts\nNear 100 papers highlighting the latest trends in electronic circuit and system design & automation\, test\, verification\, and semiconductor technologies\nInteract & network with the Experts and industry movers and shakers\n\n\nTechnical Sponsors\n\n\n \nIn-Cooperation With
URL:https://marketingeda.com/event/isqed-2023/
LOCATION:Seven Hills Conference Center\, 800 Font Blvd\, San Francisco\, CA\, 94132\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ISQED-2023-2.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230331T080000
DTEND;TZID=America/Los_Angeles:20230402T170000
DTSTAMP:20230222T174957Z
CREATED:20230122T015307Z
LAST-MODIFIED:20230222T174957Z
UID:5871-1680249600-1680454800@marketingeda.com
SUMMARY:Latch-Up 2023
DESCRIPTION:The FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday\, March 31 to Sunday\, April 2\, 2023 in Santa Barbara\, California\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and we encourage you to submit a presentation or proposal if you have a project or idea on the topic to share! \n  \nQuestions? Ping the organizers via @LatchUpConf or email. \nPrevious Latch-Ups: 2019 Portland \nSubmit a talk\n\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nRegistration\n\nAttendance of Latch-Up is free. To help us organizing the event\, you are required to register using the button below or via the EventBrite link. \nProfessional Tickets\nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. You can buy professional tickets using the button below or via the EventBrite link. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsorship and Volunteering at Latch-Up\n\nLatch-Up is free to attend\, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day\, and thousands more through recordings of the event. So please get in touch if you’d like to explore sponsorship opportunities. \nLatch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event\, so please do email us if you would like to volunteer for during the event with setup\, AV\, or even just local knowledge so we can plan the weekend better.
URL:https://marketingeda.com/event/latch-up-2023/
LOCATION:University of California\, Santa Barbara\, Santa Barbara\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230330T120000
DTEND;TZID=America/New_York:20230330T130000
DTSTAMP:20230321T184304Z
CREATED:20230321T184304Z
LAST-MODIFIED:20230321T184304Z
UID:6199-1680177600-1680181200@marketingeda.com
SUMMARY:How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
DESCRIPTION:Driven by the trend towards software-defined vehicles (SDV)\, more complex software stacks are now being integrated into innovative automotive E/E architectures. Today the early integration testing of automotive software is already supported by using virtual ECUs (vECUs). However\, the production basic software (BSW) is often not included because the virtualization of the hardware-specific microcontroller abstraction layer (MCAL) requires a very high modeling effort. This 30-minute Webinar will explore a new technology for automated generation of Level 3 vECUs to support comprehensive testing for AUTOSAR Classic Platform (CP). \nThis event will include: \n\nThe benefits of using vECUs for BSW testing such as cost savings\, faster turn-around time\, and better debug capabilities\nThe features and capabilities of the new technologies and how they simplify the process of configuring and generating Level 3 vECUs\nLive demonstrations for a hands-on understanding of how to use the new technologies to optimize BSW testing in AUTOSAR development projects\n\nA Q&A session will follow the technical presentation. \n\n\n\nSpeakers:\n \n\n\n\n \n\n\n\n\nSimon Dürr\, Senior Expert\, Elektrobit  \nSimon Dürr is the Senior Expert for Embedded Automotive Software and AUTOSAR at Elektrobit. He has more than 10 years of industry experience and focuses on embedded security\, functional safety\, AUTOSAR\, and automotive HPC architectures. Simon has a proven track record of bringing automotive software to mass production\, working on various automotive platforms and embedded software solutions for the world’s major OEMs. He now heads the virtualization activities at Elektrobit. \n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\nMarkus Stix\, Senior Applications Engineer\, Synopsys \nMarkus Stix is a Senior Applications Engineer at Synopsys\, where he is responsible for definition\, realization\, and deployment of the company’s Silver and TestWeaver products. He holds a bachelor’s degree in technical computer science and a master’s degree in information systems from the University of Applied Sciences Ulm. Markus has more than 10 years’ experience building complex software-in-the-loop (SiL) setups for ECUs as well as developing customized testing solutions in the automotive powertrain domain. As the leader of an application engineering team\, he has successfully established robust automation and virtualization processes at premium car manufacturers and suppliers. \n\n\n\n\n\n \n\n\n\nModerator: Amanda Hosey\, Editor\, SAE Media Group
URL:https://marketingeda.com/event/how-to-achieve-seamless-deployment-of-level-3-virtual-ecus-for-automotive-digital-twins/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAE-March-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230330T080000
DTEND;TZID=America/Los_Angeles:20230331T170000
DTSTAMP:20230313T213001Z
CREATED:20230313T212742Z
LAST-MODIFIED:20230313T213001Z
UID:6128-1680163200-1680282000@marketingeda.com
SUMMARY:Versal Adaptive SoCs ONLINE WORKSHOP
DESCRIPTION:Standard Level – 2 sessions (4 hours per session including breaks) \n\nWith thanks to AMD Xilinx for sponsoring this workshop:\nIt is available to attend FREE OF CHARGE (Usual price $990)  \nMarch 30-31 2023 – Americas – Register Now » \nMarch 30-31 2023 – EurAsia – Register Now » \n\nThe Versal® Adaptive SoC from AMD Xilinx is multi-featured\, offering unprecedented system level performance and integration. \nThis informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. \nWe’ll first cover the broader Versal Adaptive SoC device.  We’ll then focus on a practical example\, optimizing a given application for the AI Engine resources. \n \nThe workshop is designed to maximize individual engagement and learning.  Each attendee is encouraged to informally ask pertinent questions throughout\, to actively participate in the learning process. \nWho should attend & pre-requisites\nSoftware and hardware developers\, system architects\, and anyone who wants to learn about the Versal Adaptive SoC device from AMD Xilinx. \nWhat will I need?\nThe workshop has been created to be accessible by a wide audience with standard technology requirements. \nIf you have not attended a Doulos workshop or webinar before\, you can check your connection with the meeting service here » \n  \nWorkshop Agenda\nDelivered across 2 half-day sessions  \nVersal Adaptive SoC: Structural Overview – Big picture overview\, processing engines\, connections and capabilities.\n\nIntro to AI Engines – Scalar and vector processing unit\, SIMD data-path\, multi-kernel control and communication \nPS  Overview – Introduce the A72 and R5F processors\, MPSoC migration\, the role of the PMU\, device boot\, etc. \nPL Fabric – The traditional FPGA fabric\, encompassing enhanced layout\, clocking\, and slice capabilities \nNoC Resources – Overview for Versal Adaptive SoC communication backplane\, data-transfer\, DDR controller \nEnhanced DSP58 – New features\, layout and operational modes for PL fabric-based DSP building blocks \nAIE Vector Datatypes – Declaring vector datatypes required for the high-performance SIMD data-paths \nIntrinsic(s) Coding – Introduction to proprietary syntax for maximizing AI engine vector processing \nFIR Filter Coding for AIE – A step-by-step working example for 1GHz+ FIR filter targeting AI engine \n  \nPlease come prepared to actively participate and engage directly with the workshop facilitator. \nWhat’s the timetable?\nThis workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A. \n\nThe session duration is up to 4 hours including breaks\nStart times:\n\nEurope and Asia Time Zones:\n0830 BST | 0930 CEST | 1300 IST\nAmericas Time Zones:\n0830 PDT | 1030 CDT | 1130 EDT\n\n\nThere are no specific hardware requirements for this training please check your connection with GoToWebinar if you have not used it to attend a Doulos event before.\n\nWhat does it cost?\nThe workshops have kindly been sponsored by AMD Xilinx\, and are available to attend FREE OF CHARGE. \nUsual value of this training is $990 / €840  \n\nRegister for this FREE workshop using a link below:\nMarch 30-31 2023 – Americas – Register Now » \nMarch 30-31 2023 – EurAsia – Register Now »
URL:https://marketingeda.com/event/versal-adaptive-socs-online-workshop/
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/versal_workshop_2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230329T080000
DTEND;TZID=America/Los_Angeles:20230330T170000
DTSTAMP:20230201T180549Z
CREATED:20230201T180549Z
LAST-MODIFIED:20230201T180549Z
UID:5897-1680076800-1680195600@marketingeda.com
SUMMARY:SNUG Silicon Valley 2023
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \nWhy Attend?\n\n\n\n\n\n\nHear the latest on the Synopsys direction and vision from Dr. Aart de Geus\, Chairman and Chief Executive Officer \n\n\n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\n\n\nNetwork with users & Synopsys experts in over 85+ Technical presentations and during the famous SNUG Pub \nChoose from among 15 Technical Tracks and see other users showcase best practices for design & verification challenges: AI & Machine Learning\, Automotive\, AMS & Simulation\, Design and Verification in the Cloud\, Digital Design Implementation\, Energy-Efficient SoCs\, Multi-Die\, Memory\, Physical Verification\, Security Government & Aerospace\, Signoff\, Silicon Test and Lifecycle Management\, IP\, Verification Hardware & Virtual Prototyping and Verification Software.
URL:https://marketingeda.com/event/snug-silicon-valley-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230329T080000
DTEND;TZID=Europe/London:20230329T170000
DTSTAMP:20230302T001735Z
CREATED:20230302T001735Z
LAST-MODIFIED:20230302T001735Z
UID:6048-1680076800-1680109200@marketingeda.com
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:TechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th\, and will focus on FPGA Design using High Level Languages. \nThe FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge\, find out what is going on and network with like-minded people. \nThis event continues the theme of hosting at a member site\, and allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group. \nWe are also inviting students from across the UK to the event\, to bring them closer to the community\, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates. \n\n\nLooking for Accommodation?\nThe Village Edinburgh Hotel is directly opposite Leonardo and boasts a Pub & Grill\, Starbucks\, Swimming pool and state-of-the-art gym.  To find out more and book\,  visit their website: \nhttps://www.village-hotels.co.uk/edinburgh \n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIain Pearson\, Pr. ESC\, Microchip Technology Inc.\nPrinciple Embedded Solutions Engineer at Microchip Ltd covering FPGA\, IoT\, Security and Cloud applications. Ian has been with Microchip for 23years covering everything from 8bit thro the introduction of the 16bit\, 32bit networking and wireless products. He managed the Wireless and Networking function team in Europe where he was an advocate of Secure by Design best practices. In the post covid era and the acquisition of Microsemi the opportunity to join the FPGA team arose allowing him to step back 25 years into his youth and re-discover FPGA all over again. \nPresentation: SmartHLS – C++ to Verilog Toolsuite \nHigh Level Synthesis tools can provide a significant improvement in productivity over RTL. This is especially the case in systems employing both a processor core and software in combination with FPGA logic. In this session we will look at where the Microchip SmartHLS toolsuite can be best a utilised to gain most benefit and where it is best to leave code running in software \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPadrig Guillard\, Sales Account Manager\, reflex ces\nWith nearly 15 years of experience in the FPGA market and a Hardware engineer background\, Padrig provides sales and technical to his customers in various high-end applications and markets. \nPresentation: Overview of JESD204B/C implementation in FPGA SoM \nKey Points:\n• Evolution of JESD204B/C support in reflex ces SoM products\n• How reflex ces allow JESD204B/C prototyping to reduce design risks and time to market \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDaniel Ogilvie\, Managing Director\, SingMai Electronics\nDaniel Ogilvie has over 40 years’ experience designing video products\, from no-compromise broadcast quality analogue video decoders and encoders\, to forensic image analysis products which can still be occasionally glimpsed on the CSI television programs. Daniel has worked for companies\, large and small\, in the UK\, Canada\, Thailand and Singapore. Daniel is a senior member of the IEEE. Outside of work\, Daniel Ogilvie is the author of three novels and has a Master’s degree in Art History. \nPresentation: Moving from Altera to Efinix FPGAs. \nKey Points: \n\nThe motivation for change – cannot buy Altera FPGAs – trying to buy dodgy parts from China.\nMoving our designs to Efinix – changes needing to be made.\nChanging the mindset – instantiating the PLLs and assigning pins.
URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet/
LOCATION:Leonardo\, EH5 2XS\, Edinburgh\, United Kingdom
CATEGORIES:EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-March-29-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230328T083000
DTEND;TZID=America/Los_Angeles:20230328T113000
DTSTAMP:20230309T220902Z
CREATED:20230309T220840Z
LAST-MODIFIED:20230309T220902Z
UID:6090-1679992200-1680003000@marketingeda.com
SUMMARY:ESD Alliance Export Seminar
DESCRIPTION:The ESD Alliance Export Committee will hold a seminar called “The Impact of New Regulations on the Semiconductor Design Ecosystem.” This seminar is presented by the ESD Alliance\, a SEMI Technology Community\, and will be hosted by Cadence Design Systems at their San Jose Headquarters. The Cadence Government and Trade Team will cover general trade compliance concepts\, how export control and sanctions regulations affect the industry\, as well as current trends and emerging issues. \nBreakfast Hosted by Cadence \n\nTime\n8:30 am – 11:30 am \n\n\nADD TO CALENDAR\n\n\nLocation\nCadence Design Systems\n2655 Seely Avenue\nSan Jose\, CA 95134\nUnited States \nThe discussion will help attendees understand why and how governments implement trade controls\, what “exports” are and how they take place in different business contexts\, and common due diligence methods – such as customer screening – that United States companies use to incorporate regulatory compliance into their business processes. Finally\, the discussion will address recent regulatory updates which address current issues such as US-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem. \n\nMeet the Speakers\n \nAda Loo\nGroup Director and Associate General Counsel\,\nCadence Design Systems \nBiography\n \nWilliam Duffy\nCorporate Counsel (Government and Trade\, Cadence Legal) \nBiography
URL:https://marketingeda.com/event/esd-alliance-export-seminar/
LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States
CATEGORIES:EDA,IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESDA-March-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230326T080000
DTEND;TZID=America/Los_Angeles:20230329T170000
DTSTAMP:20230310T181227Z
CREATED:20230310T181227Z
LAST-MODIFIED:20230310T181227Z
UID:6101-1679817600-1680109200@marketingeda.com
SUMMARY:International Symposium on Physical Design (ISPD) 2023
DESCRIPTION:General Information\nThe International Symposium on Physical Design (ISPD) provides a premier forum to exchange ideas and promote innovative research in all aspects of physical design ranging from traditional topics for ASIC and FPGA designs to emerging technologies that impact physical design of integrated circuits (ICs). In 2023\, ISPD will be online with virtual participation\, with both live video and recorded sessions. The 32nd symposium will highlight key new directions and leading-edge theoretical and experimental contributions to the field. \nWe will also pay tribute to Professor Malgorzata Marek-Sadowska (University of California at Santa Barbara) for her contributions to the physical design community. \n  \nRegistration is now open. Please register here.\n  \nLocation\nISPD 2023 will be held online\, with virtual participation across the world. There is a strong technical program including peer-reviewed papers\, invited papers\, and keynotes. Continuing the tradition of ISPD\, we have a contest and a great social program. \nImportant Dates\n\n\n\nContest registration deadline\nJanuary 15\, 2023\n\n\nCamera-ready paper or abstract + bio for invited speakers\nJanuary 29\, 2023\n\n\nSpeaker presentation videos due\nFebruary 26\, 2023\n\n\nSymposium\nMarch 26-29\, 2023\n\n\n\nSponsors\n\n\n\n\nSponsor\n\n\n\n\n\nTechnical Sponsors\n\n\n\n\n\n\nSupporters\n\n\n\n\nGold\n\n\n\n\n\n\n\nSilver
URL:https://marketingeda.com/event/international-symposium-on-physical-design-ispd-2023/
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ISPD-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230320T080000
DTEND;TZID=America/Los_Angeles:20230323T170000
DTSTAMP:20230307T044258Z
CREATED:20230307T044258Z
LAST-MODIFIED:20230307T044258Z
UID:6073-1679299200-1679590800@marketingeda.com
SUMMARY:GOMACTech 2023
DESCRIPTION:GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \n\nDear 2023 Attendees: \nThis year’s conference is titled “Microelectronics – the Engine to Keep the US Moving Forward\,” and our robust technical program supports this theme with topics including Advanced Silicon-Based RF\, Alternative Computing Paradigms\, Counterfeit Detection and Avoidance\, GaN Power Electronics\, and much\, much more. \nThe conference kicks off on Monday\, 20 March\, with our annual Trusted Suppliers Industry Day\, created with the objective of promoting discussion among members of industry and government agencies that represent the interests of integrated-circuit and electronics producers who serve defense and aerospace applications. We have seen tremendous change since last year’s Industry Day\, not only with the enactment and funding of the CHIPS and Science Act but also with the increasing uncertainty regarding China’s intentions with Taiwan. To provide insight into these issues\, Dr. Tai Ming Cheung\, recipient of multiple DoD Minerva Research Initiative awards and director of the University of California Institute on Global Conflict and Cooperation (IGCC)\, is scheduled to deliver the keynote address on the emergence of the Chinese techno-security state. Monday also features four workshops/tutorials: Advanced GaN Modeling\, JFAC Hardware Assurance\, GEEGAH Fab Capabilities & PDK for Acoustoelectric Devices\, and AKOUSTIS Fab Capabilities & PDK for AIN/ScAIN. \nOur Monday programming will conclude with a reception on the resort’s Flamingo Lawn\, which is open to all registered attendees. Please join us! \nGOMACTech-23 formally opens on Tuesday\, 21 March\, with an outstanding morning Plenary Session that includes the keynote address “3DHI and the Coming Inflection Point in Microelectronics Manufacture” by Dr. Mark Rosker\, director of DARPA’s Microsystems Technology Office. Rosker will be followed by Ezra Hall\, senior director of Global Aerospace and Defense Business at GlobalFoundries\, whose talk is titled “Aligning Defense Microelectronics Technologies with Industry Needs: Fueling U.S. Success.” \nThe keynotes will be followed by the Jack S. Kilby Lecture Series\, with presentations from Dr. Waleed Khalil\, professor of electrical and computer engineering at Ohio State University and the ElectroScience Lab\, who will speak on “Analog Hardware Security: What We Don’t Know Will Hurt Us\,” and Krystal Puga\, Lunar Mission Architect for the Space Systems Sector at Northrop Grumman Corp.\, with the presentation\, “James Webb Space Telescope Development and Latest Discoveries.” \nThis year\, we are also hosting three panel discussions: “Chips and Science Act Impact to DoD\,” on Monday\, 20 March; “Perspectives on Computational Methods for Radiation Hardness Qualification;” on Wednesday\, 22 March; and “Sifting Through the Chaos: Are Best Practices Achievable?” on Thursday\, 23 March. \nThe plenary\, technical\, and topical sessions are the major venues for information exchange at the conference. Other opportunities for technical interaction are provided by the exhibits program\, which includes major IC manufacturers and commercial vendors of devices\, equipment\, systems\, and services for nearly every facet of the electronics business. The exhibition opens on Tuesday\, 21 March\, at noon\, and runs through Wednesday\, 22 March\, at 4:00 pm. On Tuesday evening\, all attendees can network in a relaxing atmosphere during the Exhibitors’ Reception. \nWednesday evening features the Evening Social\, held this year at the San Diego Zoo\, one of the country’s premier zoos. A buffet-style dinner will be included\, and we will have the opportunity to meet some of the animals “up close and personal.” This is a ticketed event with an attendance cap\, so if you’re planning on attending\, buy your ticket before Wednesday. \nOn Thursday morning\, 23 March\, a poster session that includes our annual student poster competition will take place. \nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and to provide a forum for government reviews. \nThe GOMACTech Conference is an Unclassified\, Export-Controlled event that requires participants to be U.S. Citizens or legal U.S. Permanent Residents. All registrants must provide proof of U.S. Citizenship or Permanent Resident status prior to being permitted entry into the conference. Additionally\, a signed Non-Disclosure Statement will be required. \nGOMACTech-23 provides a forum for discussing and demonstrating advanced microelectronics and microsystems that can provide the means to develop confidence in transformational\, leap-ahead technologies\, and capabilities. GOMACTech is the premier forum for reporting on government-funded microcircuit research and other research efforts that focus on the technology needs of government systems. \nThis year’s technical program is a result of the hard work and enthusiasm of the GOMACTech-23 Technical Program Committee. The committee members discussed and collaborated on the topics and presentations. The quality of the conference reflects this comprehensive team effort. We hope that you find GOMACTech-23 an enlightening\, rewarding\, and enjoyable experience. Thank you for your active participation. \n  \n\n\n\nDr. Morgan Thoma\nU.S. Army Research Laboratory\nDefense Microelectronics CFT\nGeneral Chair\nLuciano Boglione\nNaval Research Laboratory\nTechnical Program Chair
URL:https://marketingeda.com/event/gomactech-2023/
LOCATION:Town and Country San Diego Hotel\, 500 Hotel Circle North\, San Diego\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230317T153000
DTEND;TZID=Europe/Berlin:20230317T183000
DTSTAMP:20230302T210203Z
CREATED:20230302T210203Z
LAST-MODIFIED:20230302T210203Z
UID:6057-1679067000-1679077800@marketingeda.com
SUMMARY:Munich RISC-V Meetup
DESCRIPTION:Get ready for our next RISC-V meetup\, this time again as physical meeting.\nOne day after the doors of Embedded World close\, we will meet to bring together RISC-V enthusiasts from Munich\, Bavaria and the world. \nPlease get in touch with the organizers if you want to present!
URL:https://marketingeda.com/event/munich-risc-v-meetup/
LOCATION:Hochschule Munchen University of Applied Sciences\, Lothstr. 64\, Munich\, Germany
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Munich-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20230314T190000
DTEND;TZID=America/Chicago:20230314T210000
DTSTAMP:20230302T211620Z
CREATED:20230302T211620Z
LAST-MODIFIED:20230302T211620Z
UID:6061-1678820400-1678827600@marketingeda.com
SUMMARY:March Austin RISC-V Meetup
DESCRIPTION:This will be an on-line event. We’ll be the RISC-V Bivy virtual meeting system. The use of a microphone and/or camera are not required to participate in the event\, chat will be monitored. We’ll be discussing current and future hardware releases\, state of various software projects\, and plans for future meetups. We’re also going to be having some discussion on selection of an FPGA Development board for future meetings on synthesizing RISC-V SoCs and testing of new hardware features as well as running Linux.
URL:https://marketingeda.com/event/march-austin-risc-v-meetup/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Meetup.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230314T080000
DTEND;TZID=America/Los_Angeles:20230316T170000
DTSTAMP:20230313T200643Z
CREATED:20230124T193702Z
LAST-MODIFIED:20230313T200643Z
UID:5880-1678780800-1678986000@marketingeda.com
SUMMARY:Embedded World
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nMain topics in 2023\n\nembedded: A variety of technological challenges shape the modern design concepts of complex embedded systems – from sensors to the cloud\, from hardware to software to tools – smart\, intelligent\, efficient\, safe\, reliable\, interoperable…\n\n\nresponsible: Evermore embedded systems are being used in function-critical applications such as medical technology\, mobility and industrial automation. The industry meets these challenges with adaptive\, autonomous and intelligent systems that safely and reliably carry out critical tasks. Many questions ranging from responsibility by design to formal verification methods and ethical issues must be answered.\nsustainable: Embedded systems are central\, basic elements for many efficient and sustainable applications. Embedded systems themselves must also be sustainable over the entire life cycle -from design and manufacturing to operation and updateability\, refurbishment\, decommissioning and disposal.\n\nSpecialty areas at the trade fair and conferences focus on current megatrends\, such as embedded vision\, safety & security\, M2M communication\, IP & IC design and embedded intelligence. \nThe embedded world Exhibition&Conference facilitates direct interaction with a large number of experts and qualified suppliers from all over the world. Whether at specialist forums\, expert panels\, the embedded world Conference or electronic displays Conference\, experts from the embedded community meet at eye-level to jointly develop ideas and concepts for the future.  The embedded world Exhibition&Conference is essential for anyone who wants to stay on top of core topics and industry trends! \nTake advantage of the opportunity to expand your knowledge and make new\, international business contacts!
URL:https://marketingeda.com/event/embedded-world/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ew-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230227T080000
DTEND;TZID=America/Los_Angeles:20230302T170000
DTSTAMP:20230228T000703Z
CREATED:20230227T175620Z
LAST-MODIFIED:20230228T000703Z
UID:6024-1677484800-1677776400@marketingeda.com
SUMMARY:Mobile World Conference\, MWC 2023
DESCRIPTION:MWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months.
URL:https://marketingeda.com/event/mobile-world-conference-mwc-2023/
LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230224T110000
DTEND;TZID=America/New_York:20230224T122000
DTSTAMP:20230210T211004Z
CREATED:20230210T210952Z
LAST-MODIFIED:20230210T211004Z
UID:5939-1677236400-1677241200@marketingeda.com
SUMMARY:Hardware Security 2.0: What Are The New Frontiers?
DESCRIPTION:The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner\, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade\, including open-source license-free or ready-for-licensing tools\, associated metrics\, relevant publications\, and video-demos. \nWe are delighted to continue the series of virtual CAD for Assurance tool training webinars that started in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/. \nIf you are interested in receiving updates and emails about future CAD for Assurance webinars\, please signup using this form http://eepurl.com/hxTwWf. \n\n\n\n\nRegistration\n\n\nRegistration for the webinars is required. Please select the Zoom session for each webinar you wish to attend. For questions\, please contact the organizers. \nModerators:\nDomenic Forte (U. of Florida) and Qiaoyan Yu (U. of New Hampshire) \nPanelists:\n-David Kehlet\, Intel\n-Murthi Sadhasivan\, Aerospace Corporation\n-Serge Leef\, Microsoft\n-Rainer Leupers\, RWTH Aachen University\n-Chip Hong Chang\, Nanyang Technological University
URL:https://marketingeda.com/event/hardware-security-2-0-what-are-the-new-frontiers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEECEDA-Feb-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230223T183000
DTEND;TZID=America/Los_Angeles:20230223T213000
DTSTAMP:20230203T194838Z
CREATED:20230203T194838Z
LAST-MODIFIED:20230203T194838Z
UID:5907-1677177000-1677187800@marketingeda.com
SUMMARY:Phil Kaufman Award & Banquet
DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \n\nTime\n6:30 pm – 9:30 pm \nElectronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor \nDR. GIOVANNI DE MICHELI\nProfessor of Electrical Engineering and Computer Science in the Institute of Electrical Engineering (IEL)\nat the School of Engineering as well as at the School of Computer and Communication Sciences\nof the École Polytechnique Fédérale de Lausanne (EPFL) \nwith the \n2022 Phil Kaufman Award\n \nDr. Giovanni De Micheli is honored for his extensive contributions to electronic design automation (EDA). His research in EDA tools and methodologies has made a significant\, lasting impact on the industry\, including contributions to: \nHigh-level Synthesis\nLogic Synthesis and Minimization\nHardware Software Co-Design\nNetwork on Chip (NoC)\nCell Library Mapping \nHis academic advances in EDA have had a lasting impact on the industry\nwhich would not be where it is today without his groundbreaking research.
URL:https://marketingeda.com/event/phil-kaufman-award-banquet/
LOCATION:The GlassHouse\, 2 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Award,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semi-Feb-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230222T170000
DTEND;TZID=Asia/Tokyo:20230222T180000
DTSTAMP:20230206T182350Z
CREATED:20230206T182350Z
LAST-MODIFIED:20230206T182350Z
UID:5910-1677085200-1677088800@marketingeda.com
SUMMARY:RISC-V Webinar from Andes
DESCRIPTION:Andes Technology is going to host a webinar at 17:00 PM on February 22 (Japan Standard Time (JST) and Korea Standard Time (KST)). Andes speakers will present Andes comprehensive hardware and software solutions. Samuel Chiang\, Deputy Technical Director of Marketing\, will present a wide range of applications which have adopted RISC-V solutions and will introduce new product lines. Next\, Technical Manager\, Simon Wang\, will have an overview of Andes solutions for AI including RISC-V Vector and DSP/SIMD Processor\, AndeSight™ IDE SW development tools\, Andes NN SDK and more. If you’re interested in RISC-V applications and Andes future strategy\, please don’t miss this good chance to ask questions during Q&A session! \nJoin us to learn more about the leading AndesCore™ RISC-V processor IP solutions\, including N25F-SE\, the industry’s first and only ISO 26262 fully-compliant RISC-V CPU; AX65\, a multicore 4-way out-of-order superscalar processor; AX45MPV\, the leading-edge Linux multicore 1024-bit vector processor; and D23\, the new-generation compact\, versatile\, secured core for IoT applications! \n– Date and Time: February 22\, 17:00 PM (JST & KST)\n– Agenda:\n17:00 Opening\n17:05 “Expanding the RISC-V Horizon and Beyond” by Samuel Chiang\, Deputy Technical Director of Marketing\n17:30 “The Future of Edge is About RISC-V and AI” by Simon Wang\, Senior Technical Manger\n17:50 Q&A session
URL:https://marketingeda.com/event/risc-v-webinar-from-andes/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-Feb-22-2023.jpg
END:VEVENT
END:VCALENDAR