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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230411T100000
DTEND;TZID=America/Los_Angeles:20230411T110000
DTSTAMP:20230316T183442Z
CREATED:20230316T183341Z
LAST-MODIFIED:20230316T183442Z
UID:6172-1681207200-1681210800@marketingeda.com
SUMMARY:Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
DESCRIPTION:Advanced semiconductor nanometer technology nodes\, together with smart IC design applications enable today very complex and powerful systems for communication\, automotive\, data transmission\, AI\, IoT\, medical\, industry\, energy harvesting\, and many more. However\, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows\, tools & methodologies to meet design requirements in a tight design schedule. Automated circuit sizing and optimization is becoming a very important tool to achieve that. \nMunEDA provides the necessary features to enhance designers’ productivity by circuit optimization within its EDA design tool suite WiCkeD. \nIn this webinar we’ll discuss state-of-the-art circuit optimization methodology\, and particularly how to use it most efficiently in order to enhance design quality and designers’ productivity. \nSpeakers: \nMichael Pronath. Michael is VP of Products & Solutions at MunEDA\, and author and co-author of several international publications about methods of analog integrated circuit design and testing of mixed-signal circuits. \nDave Johnson is President of FirstShift Technologies which represents MunEDA in North America. He has also worked at worked at NXP\, Neolinear\, and Cadence. Dave started his career as an I/O library circuit designer. \n*This webinar is in partnership with SemiWiki and MunEDA*
URL:https://marketingeda.com/event/enhance-productivity-with-machine-learning-in-the-analog-front-end-design-flow/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/MunEDA-April-11-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230405T090000
DTEND;TZID=America/Los_Angeles:20230405T100000
DTSTAMP:20230403T170217Z
CREATED:20230403T170217Z
LAST-MODIFIED:20230403T170217Z
UID:6226-1680685200-1680688800@marketingeda.com
SUMMARY:Choosing the best modeling abstraction for your analysis
DESCRIPTION:This webinar cover the modeling abstraction in the design of electronics\, semiconductors and software. This webinar will definitely improve your modeling skills! \n–Is the abstraction right for your application and design goal? \n–How do you accelerate the simulation using abstraction? \n–Can you change the model of computation using abstraction to simplify the modeling effort? \nDuring the webinar\, you’ll discover the importance of abstraction in modeling and learn how to use it to simplify complex problems. You’ll also explore different types of models and understand how to choose the right one for your specific needs. \nThis webinar is perfect for anyone looking to enhance their modeling skills\, including students\, researchers\, and professionals in fields such as engineering\, computer science\, and mathematics. Our experts will discuss the use of abstraction in complex models like computer systems\, processors\, radar and automotive TSN networks. So\, join us for an engaging discussion on modeling abstraction. Don’t miss this opportunity to gain valuable insights and take your modeling skills to the next level!
URL:https://marketingeda.com/event/choosing-the-best-modeling-abstraction-for-your-analysis/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230405T080000
DTEND;TZID=America/Los_Angeles:20230407T170000
DTSTAMP:20230213T214028Z
CREATED:20230213T214028Z
LAST-MODIFIED:20230213T214028Z
UID:5960-1680681600-1680886800@marketingeda.com
SUMMARY:ISQED 2023
DESCRIPTION:The 24th International Symposium on Quality Electronic Design (ISQED’23) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools\, integrated circuit technologies\, semiconductor technology\,packaging\, assembly & test to achieve total design quality. ISQED 2023 will held with the technical sponsorship of IEEE CASS\, IEEE EDS\, and in-cooperation with ACM/SigDA. Conference proceedings & Papers will be published in IEEE Xplore digital library and indexed by Scopus. \nThis important three day event will be packed full of tutorials and in-depth sessions. The program will also feature the following: \n\nEmbedded information-packed tutorials\nKeynotes by major industry & academia leaders and experts\nNear 100 papers highlighting the latest trends in electronic circuit and system design & automation\, test\, verification\, and semiconductor technologies\nInteract & network with the Experts and industry movers and shakers\n\n\nTechnical Sponsors\n\n\n \nIn-Cooperation With
URL:https://marketingeda.com/event/isqed-2023/
LOCATION:Seven Hills Conference Center\, 800 Font Blvd\, San Francisco\, CA\, 94132\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ISQED-2023-2.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230331T080000
DTEND;TZID=America/Los_Angeles:20230402T170000
DTSTAMP:20230222T174957Z
CREATED:20230122T015307Z
LAST-MODIFIED:20230222T174957Z
UID:5871-1680249600-1680454800@marketingeda.com
SUMMARY:Latch-Up 2023
DESCRIPTION:The FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday\, March 31 to Sunday\, April 2\, 2023 in Santa Barbara\, California\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and we encourage you to submit a presentation or proposal if you have a project or idea on the topic to share! \n  \nQuestions? Ping the organizers via @LatchUpConf or email. \nPrevious Latch-Ups: 2019 Portland \nSubmit a talk\n\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nRegistration\n\nAttendance of Latch-Up is free. To help us organizing the event\, you are required to register using the button below or via the EventBrite link. \nProfessional Tickets\nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. You can buy professional tickets using the button below or via the EventBrite link. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsorship and Volunteering at Latch-Up\n\nLatch-Up is free to attend\, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day\, and thousands more through recordings of the event. So please get in touch if you’d like to explore sponsorship opportunities. \nLatch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event\, so please do email us if you would like to volunteer for during the event with setup\, AV\, or even just local knowledge so we can plan the weekend better.
URL:https://marketingeda.com/event/latch-up-2023/
LOCATION:University of California\, Santa Barbara\, Santa Barbara\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230330T120000
DTEND;TZID=America/New_York:20230330T130000
DTSTAMP:20230321T184304Z
CREATED:20230321T184304Z
LAST-MODIFIED:20230321T184304Z
UID:6199-1680177600-1680181200@marketingeda.com
SUMMARY:How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
DESCRIPTION:Driven by the trend towards software-defined vehicles (SDV)\, more complex software stacks are now being integrated into innovative automotive E/E architectures. Today the early integration testing of automotive software is already supported by using virtual ECUs (vECUs). However\, the production basic software (BSW) is often not included because the virtualization of the hardware-specific microcontroller abstraction layer (MCAL) requires a very high modeling effort. This 30-minute Webinar will explore a new technology for automated generation of Level 3 vECUs to support comprehensive testing for AUTOSAR Classic Platform (CP). \nThis event will include: \n\nThe benefits of using vECUs for BSW testing such as cost savings\, faster turn-around time\, and better debug capabilities\nThe features and capabilities of the new technologies and how they simplify the process of configuring and generating Level 3 vECUs\nLive demonstrations for a hands-on understanding of how to use the new technologies to optimize BSW testing in AUTOSAR development projects\n\nA Q&A session will follow the technical presentation. \n\n\n\nSpeakers:\n \n\n\n\n \n\n\n\n\nSimon Dürr\, Senior Expert\, Elektrobit  \nSimon Dürr is the Senior Expert for Embedded Automotive Software and AUTOSAR at Elektrobit. He has more than 10 years of industry experience and focuses on embedded security\, functional safety\, AUTOSAR\, and automotive HPC architectures. Simon has a proven track record of bringing automotive software to mass production\, working on various automotive platforms and embedded software solutions for the world’s major OEMs. He now heads the virtualization activities at Elektrobit. \n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\nMarkus Stix\, Senior Applications Engineer\, Synopsys \nMarkus Stix is a Senior Applications Engineer at Synopsys\, where he is responsible for definition\, realization\, and deployment of the company’s Silver and TestWeaver products. He holds a bachelor’s degree in technical computer science and a master’s degree in information systems from the University of Applied Sciences Ulm. Markus has more than 10 years’ experience building complex software-in-the-loop (SiL) setups for ECUs as well as developing customized testing solutions in the automotive powertrain domain. As the leader of an application engineering team\, he has successfully established robust automation and virtualization processes at premium car manufacturers and suppliers. \n\n\n\n\n\n \n\n\n\nModerator: Amanda Hosey\, Editor\, SAE Media Group
URL:https://marketingeda.com/event/how-to-achieve-seamless-deployment-of-level-3-virtual-ecus-for-automotive-digital-twins/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAE-March-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230330T080000
DTEND;TZID=America/Los_Angeles:20230331T170000
DTSTAMP:20230313T213001Z
CREATED:20230313T212742Z
LAST-MODIFIED:20230313T213001Z
UID:6128-1680163200-1680282000@marketingeda.com
SUMMARY:Versal Adaptive SoCs ONLINE WORKSHOP
DESCRIPTION:Standard Level – 2 sessions (4 hours per session including breaks) \n\nWith thanks to AMD Xilinx for sponsoring this workshop:\nIt is available to attend FREE OF CHARGE (Usual price $990)  \nMarch 30-31 2023 – Americas – Register Now » \nMarch 30-31 2023 – EurAsia – Register Now » \n\nThe Versal® Adaptive SoC from AMD Xilinx is multi-featured\, offering unprecedented system level performance and integration. \nThis informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. \nWe’ll first cover the broader Versal Adaptive SoC device.  We’ll then focus on a practical example\, optimizing a given application for the AI Engine resources. \n \nThe workshop is designed to maximize individual engagement and learning.  Each attendee is encouraged to informally ask pertinent questions throughout\, to actively participate in the learning process. \nWho should attend & pre-requisites\nSoftware and hardware developers\, system architects\, and anyone who wants to learn about the Versal Adaptive SoC device from AMD Xilinx. \nWhat will I need?\nThe workshop has been created to be accessible by a wide audience with standard technology requirements. \nIf you have not attended a Doulos workshop or webinar before\, you can check your connection with the meeting service here » \n  \nWorkshop Agenda\nDelivered across 2 half-day sessions  \nVersal Adaptive SoC: Structural Overview – Big picture overview\, processing engines\, connections and capabilities.\n\nIntro to AI Engines – Scalar and vector processing unit\, SIMD data-path\, multi-kernel control and communication \nPS  Overview – Introduce the A72 and R5F processors\, MPSoC migration\, the role of the PMU\, device boot\, etc. \nPL Fabric – The traditional FPGA fabric\, encompassing enhanced layout\, clocking\, and slice capabilities \nNoC Resources – Overview for Versal Adaptive SoC communication backplane\, data-transfer\, DDR controller \nEnhanced DSP58 – New features\, layout and operational modes for PL fabric-based DSP building blocks \nAIE Vector Datatypes – Declaring vector datatypes required for the high-performance SIMD data-paths \nIntrinsic(s) Coding – Introduction to proprietary syntax for maximizing AI engine vector processing \nFIR Filter Coding for AIE – A step-by-step working example for 1GHz+ FIR filter targeting AI engine \n  \nPlease come prepared to actively participate and engage directly with the workshop facilitator. \nWhat’s the timetable?\nThis workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A. \n\nThe session duration is up to 4 hours including breaks\nStart times:\n\nEurope and Asia Time Zones:\n0830 BST | 0930 CEST | 1300 IST\nAmericas Time Zones:\n0830 PDT | 1030 CDT | 1130 EDT\n\n\nThere are no specific hardware requirements for this training please check your connection with GoToWebinar if you have not used it to attend a Doulos event before.\n\nWhat does it cost?\nThe workshops have kindly been sponsored by AMD Xilinx\, and are available to attend FREE OF CHARGE. \nUsual value of this training is $990 / €840  \n\nRegister for this FREE workshop using a link below:\nMarch 30-31 2023 – Americas – Register Now » \nMarch 30-31 2023 – EurAsia – Register Now »
URL:https://marketingeda.com/event/versal-adaptive-socs-online-workshop/
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/versal_workshop_2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230329T080000
DTEND;TZID=America/Los_Angeles:20230330T170000
DTSTAMP:20230201T180549Z
CREATED:20230201T180549Z
LAST-MODIFIED:20230201T180549Z
UID:5897-1680076800-1680195600@marketingeda.com
SUMMARY:SNUG Silicon Valley 2023
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \nWhy Attend?\n\n\n\n\n\n\nHear the latest on the Synopsys direction and vision from Dr. Aart de Geus\, Chairman and Chief Executive Officer \n\n\n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\n\n\nNetwork with users & Synopsys experts in over 85+ Technical presentations and during the famous SNUG Pub \nChoose from among 15 Technical Tracks and see other users showcase best practices for design & verification challenges: AI & Machine Learning\, Automotive\, AMS & Simulation\, Design and Verification in the Cloud\, Digital Design Implementation\, Energy-Efficient SoCs\, Multi-Die\, Memory\, Physical Verification\, Security Government & Aerospace\, Signoff\, Silicon Test and Lifecycle Management\, IP\, Verification Hardware & Virtual Prototyping and Verification Software.
URL:https://marketingeda.com/event/snug-silicon-valley-2023/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230329T080000
DTEND;TZID=Europe/London:20230329T170000
DTSTAMP:20230302T001735Z
CREATED:20230302T001735Z
LAST-MODIFIED:20230302T001735Z
UID:6048-1680076800-1680109200@marketingeda.com
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:TechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th\, and will focus on FPGA Design using High Level Languages. \nThe FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge\, find out what is going on and network with like-minded people. \nThis event continues the theme of hosting at a member site\, and allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group. \nWe are also inviting students from across the UK to the event\, to bring them closer to the community\, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates. \n\n\nLooking for Accommodation?\nThe Village Edinburgh Hotel is directly opposite Leonardo and boasts a Pub & Grill\, Starbucks\, Swimming pool and state-of-the-art gym.  To find out more and book\,  visit their website: \nhttps://www.village-hotels.co.uk/edinburgh \n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIain Pearson\, Pr. ESC\, Microchip Technology Inc.\nPrinciple Embedded Solutions Engineer at Microchip Ltd covering FPGA\, IoT\, Security and Cloud applications. Ian has been with Microchip for 23years covering everything from 8bit thro the introduction of the 16bit\, 32bit networking and wireless products. He managed the Wireless and Networking function team in Europe where he was an advocate of Secure by Design best practices. In the post covid era and the acquisition of Microsemi the opportunity to join the FPGA team arose allowing him to step back 25 years into his youth and re-discover FPGA all over again. \nPresentation: SmartHLS – C++ to Verilog Toolsuite \nHigh Level Synthesis tools can provide a significant improvement in productivity over RTL. This is especially the case in systems employing both a processor core and software in combination with FPGA logic. In this session we will look at where the Microchip SmartHLS toolsuite can be best a utilised to gain most benefit and where it is best to leave code running in software \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPadrig Guillard\, Sales Account Manager\, reflex ces\nWith nearly 15 years of experience in the FPGA market and a Hardware engineer background\, Padrig provides sales and technical to his customers in various high-end applications and markets. \nPresentation: Overview of JESD204B/C implementation in FPGA SoM \nKey Points:\n• Evolution of JESD204B/C support in reflex ces SoM products\n• How reflex ces allow JESD204B/C prototyping to reduce design risks and time to market \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDaniel Ogilvie\, Managing Director\, SingMai Electronics\nDaniel Ogilvie has over 40 years’ experience designing video products\, from no-compromise broadcast quality analogue video decoders and encoders\, to forensic image analysis products which can still be occasionally glimpsed on the CSI television programs. Daniel has worked for companies\, large and small\, in the UK\, Canada\, Thailand and Singapore. Daniel is a senior member of the IEEE. Outside of work\, Daniel Ogilvie is the author of three novels and has a Master’s degree in Art History. \nPresentation: Moving from Altera to Efinix FPGAs. \nKey Points: \n\nThe motivation for change – cannot buy Altera FPGAs – trying to buy dodgy parts from China.\nMoving our designs to Efinix – changes needing to be made.\nChanging the mindset – instantiating the PLLs and assigning pins.
URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet/
LOCATION:Leonardo\, EH5 2XS\, Edinburgh\, United Kingdom
CATEGORIES:EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-March-29-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230328T083000
DTEND;TZID=America/Los_Angeles:20230328T113000
DTSTAMP:20230309T220902Z
CREATED:20230309T220840Z
LAST-MODIFIED:20230309T220902Z
UID:6090-1679992200-1680003000@marketingeda.com
SUMMARY:ESD Alliance Export Seminar
DESCRIPTION:The ESD Alliance Export Committee will hold a seminar called “The Impact of New Regulations on the Semiconductor Design Ecosystem.” This seminar is presented by the ESD Alliance\, a SEMI Technology Community\, and will be hosted by Cadence Design Systems at their San Jose Headquarters. The Cadence Government and Trade Team will cover general trade compliance concepts\, how export control and sanctions regulations affect the industry\, as well as current trends and emerging issues. \nBreakfast Hosted by Cadence \n\nTime\n8:30 am – 11:30 am \n\n\nADD TO CALENDAR\n\n\nLocation\nCadence Design Systems\n2655 Seely Avenue\nSan Jose\, CA 95134\nUnited States \nThe discussion will help attendees understand why and how governments implement trade controls\, what “exports” are and how they take place in different business contexts\, and common due diligence methods – such as customer screening – that United States companies use to incorporate regulatory compliance into their business processes. Finally\, the discussion will address recent regulatory updates which address current issues such as US-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem. \n\nMeet the Speakers\n \nAda Loo\nGroup Director and Associate General Counsel\,\nCadence Design Systems \nBiography\n \nWilliam Duffy\nCorporate Counsel (Government and Trade\, Cadence Legal) \nBiography
URL:https://marketingeda.com/event/esd-alliance-export-seminar/
LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States
CATEGORIES:EDA,IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESDA-March-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230326T080000
DTEND;TZID=America/Los_Angeles:20230329T170000
DTSTAMP:20230310T181227Z
CREATED:20230310T181227Z
LAST-MODIFIED:20230310T181227Z
UID:6101-1679817600-1680109200@marketingeda.com
SUMMARY:International Symposium on Physical Design (ISPD) 2023
DESCRIPTION:General Information\nThe International Symposium on Physical Design (ISPD) provides a premier forum to exchange ideas and promote innovative research in all aspects of physical design ranging from traditional topics for ASIC and FPGA designs to emerging technologies that impact physical design of integrated circuits (ICs). In 2023\, ISPD will be online with virtual participation\, with both live video and recorded sessions. The 32nd symposium will highlight key new directions and leading-edge theoretical and experimental contributions to the field. \nWe will also pay tribute to Professor Malgorzata Marek-Sadowska (University of California at Santa Barbara) for her contributions to the physical design community. \n  \nRegistration is now open. Please register here.\n  \nLocation\nISPD 2023 will be held online\, with virtual participation across the world. There is a strong technical program including peer-reviewed papers\, invited papers\, and keynotes. Continuing the tradition of ISPD\, we have a contest and a great social program. \nImportant Dates\n\n\n\nContest registration deadline\nJanuary 15\, 2023\n\n\nCamera-ready paper or abstract + bio for invited speakers\nJanuary 29\, 2023\n\n\nSpeaker presentation videos due\nFebruary 26\, 2023\n\n\nSymposium\nMarch 26-29\, 2023\n\n\n\nSponsors\n\n\n\n\nSponsor\n\n\n\n\n\nTechnical Sponsors\n\n\n\n\n\n\nSupporters\n\n\n\n\nGold\n\n\n\n\n\n\n\nSilver
URL:https://marketingeda.com/event/international-symposium-on-physical-design-ispd-2023/
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ISPD-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230320T080000
DTEND;TZID=America/Los_Angeles:20230323T170000
DTSTAMP:20230307T044258Z
CREATED:20230307T044258Z
LAST-MODIFIED:20230307T044258Z
UID:6073-1679299200-1679590800@marketingeda.com
SUMMARY:GOMACTech 2023
DESCRIPTION:GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \n\nDear 2023 Attendees: \nThis year’s conference is titled “Microelectronics – the Engine to Keep the US Moving Forward\,” and our robust technical program supports this theme with topics including Advanced Silicon-Based RF\, Alternative Computing Paradigms\, Counterfeit Detection and Avoidance\, GaN Power Electronics\, and much\, much more. \nThe conference kicks off on Monday\, 20 March\, with our annual Trusted Suppliers Industry Day\, created with the objective of promoting discussion among members of industry and government agencies that represent the interests of integrated-circuit and electronics producers who serve defense and aerospace applications. We have seen tremendous change since last year’s Industry Day\, not only with the enactment and funding of the CHIPS and Science Act but also with the increasing uncertainty regarding China’s intentions with Taiwan. To provide insight into these issues\, Dr. Tai Ming Cheung\, recipient of multiple DoD Minerva Research Initiative awards and director of the University of California Institute on Global Conflict and Cooperation (IGCC)\, is scheduled to deliver the keynote address on the emergence of the Chinese techno-security state. Monday also features four workshops/tutorials: Advanced GaN Modeling\, JFAC Hardware Assurance\, GEEGAH Fab Capabilities & PDK for Acoustoelectric Devices\, and AKOUSTIS Fab Capabilities & PDK for AIN/ScAIN. \nOur Monday programming will conclude with a reception on the resort’s Flamingo Lawn\, which is open to all registered attendees. Please join us! \nGOMACTech-23 formally opens on Tuesday\, 21 March\, with an outstanding morning Plenary Session that includes the keynote address “3DHI and the Coming Inflection Point in Microelectronics Manufacture” by Dr. Mark Rosker\, director of DARPA’s Microsystems Technology Office. Rosker will be followed by Ezra Hall\, senior director of Global Aerospace and Defense Business at GlobalFoundries\, whose talk is titled “Aligning Defense Microelectronics Technologies with Industry Needs: Fueling U.S. Success.” \nThe keynotes will be followed by the Jack S. Kilby Lecture Series\, with presentations from Dr. Waleed Khalil\, professor of electrical and computer engineering at Ohio State University and the ElectroScience Lab\, who will speak on “Analog Hardware Security: What We Don’t Know Will Hurt Us\,” and Krystal Puga\, Lunar Mission Architect for the Space Systems Sector at Northrop Grumman Corp.\, with the presentation\, “James Webb Space Telescope Development and Latest Discoveries.” \nThis year\, we are also hosting three panel discussions: “Chips and Science Act Impact to DoD\,” on Monday\, 20 March; “Perspectives on Computational Methods for Radiation Hardness Qualification;” on Wednesday\, 22 March; and “Sifting Through the Chaos: Are Best Practices Achievable?” on Thursday\, 23 March. \nThe plenary\, technical\, and topical sessions are the major venues for information exchange at the conference. Other opportunities for technical interaction are provided by the exhibits program\, which includes major IC manufacturers and commercial vendors of devices\, equipment\, systems\, and services for nearly every facet of the electronics business. The exhibition opens on Tuesday\, 21 March\, at noon\, and runs through Wednesday\, 22 March\, at 4:00 pm. On Tuesday evening\, all attendees can network in a relaxing atmosphere during the Exhibitors’ Reception. \nWednesday evening features the Evening Social\, held this year at the San Diego Zoo\, one of the country’s premier zoos. A buffet-style dinner will be included\, and we will have the opportunity to meet some of the animals “up close and personal.” This is a ticketed event with an attendance cap\, so if you’re planning on attending\, buy your ticket before Wednesday. \nOn Thursday morning\, 23 March\, a poster session that includes our annual student poster competition will take place. \nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and to provide a forum for government reviews. \nThe GOMACTech Conference is an Unclassified\, Export-Controlled event that requires participants to be U.S. Citizens or legal U.S. Permanent Residents. All registrants must provide proof of U.S. Citizenship or Permanent Resident status prior to being permitted entry into the conference. Additionally\, a signed Non-Disclosure Statement will be required. \nGOMACTech-23 provides a forum for discussing and demonstrating advanced microelectronics and microsystems that can provide the means to develop confidence in transformational\, leap-ahead technologies\, and capabilities. GOMACTech is the premier forum for reporting on government-funded microcircuit research and other research efforts that focus on the technology needs of government systems. \nThis year’s technical program is a result of the hard work and enthusiasm of the GOMACTech-23 Technical Program Committee. The committee members discussed and collaborated on the topics and presentations. The quality of the conference reflects this comprehensive team effort. We hope that you find GOMACTech-23 an enlightening\, rewarding\, and enjoyable experience. Thank you for your active participation. \n  \n\n\n\nDr. Morgan Thoma\nU.S. Army Research Laboratory\nDefense Microelectronics CFT\nGeneral Chair\nLuciano Boglione\nNaval Research Laboratory\nTechnical Program Chair
URL:https://marketingeda.com/event/gomactech-2023/
LOCATION:Town and Country San Diego Hotel\, 500 Hotel Circle North\, San Diego\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20230317T153000
DTEND;TZID=Europe/Berlin:20230317T183000
DTSTAMP:20230302T210203Z
CREATED:20230302T210203Z
LAST-MODIFIED:20230302T210203Z
UID:6057-1679067000-1679077800@marketingeda.com
SUMMARY:Munich RISC-V Meetup
DESCRIPTION:Get ready for our next RISC-V meetup\, this time again as physical meeting.\nOne day after the doors of Embedded World close\, we will meet to bring together RISC-V enthusiasts from Munich\, Bavaria and the world. \nPlease get in touch with the organizers if you want to present!
URL:https://marketingeda.com/event/munich-risc-v-meetup/
LOCATION:Hochschule Munchen University of Applied Sciences\, Lothstr. 64\, Munich\, Germany
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Munich-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20230314T190000
DTEND;TZID=America/Chicago:20230314T210000
DTSTAMP:20230302T211620Z
CREATED:20230302T211620Z
LAST-MODIFIED:20230302T211620Z
UID:6061-1678820400-1678827600@marketingeda.com
SUMMARY:March Austin RISC-V Meetup
DESCRIPTION:This will be an on-line event. We’ll be the RISC-V Bivy virtual meeting system. The use of a microphone and/or camera are not required to participate in the event\, chat will be monitored. We’ll be discussing current and future hardware releases\, state of various software projects\, and plans for future meetups. We’re also going to be having some discussion on selection of an FPGA Development board for future meetings on synthesizing RISC-V SoCs and testing of new hardware features as well as running Linux.
URL:https://marketingeda.com/event/march-austin-risc-v-meetup/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Meetup.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230314T080000
DTEND;TZID=America/Los_Angeles:20230316T170000
DTSTAMP:20230313T200643Z
CREATED:20230124T193702Z
LAST-MODIFIED:20230313T200643Z
UID:5880-1678780800-1678986000@marketingeda.com
SUMMARY:Embedded World
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nMain topics in 2023\n\nembedded: A variety of technological challenges shape the modern design concepts of complex embedded systems – from sensors to the cloud\, from hardware to software to tools – smart\, intelligent\, efficient\, safe\, reliable\, interoperable…\n\n\nresponsible: Evermore embedded systems are being used in function-critical applications such as medical technology\, mobility and industrial automation. The industry meets these challenges with adaptive\, autonomous and intelligent systems that safely and reliably carry out critical tasks. Many questions ranging from responsibility by design to formal verification methods and ethical issues must be answered.\nsustainable: Embedded systems are central\, basic elements for many efficient and sustainable applications. Embedded systems themselves must also be sustainable over the entire life cycle -from design and manufacturing to operation and updateability\, refurbishment\, decommissioning and disposal.\n\nSpecialty areas at the trade fair and conferences focus on current megatrends\, such as embedded vision\, safety & security\, M2M communication\, IP & IC design and embedded intelligence. \nThe embedded world Exhibition&Conference facilitates direct interaction with a large number of experts and qualified suppliers from all over the world. Whether at specialist forums\, expert panels\, the embedded world Conference or electronic displays Conference\, experts from the embedded community meet at eye-level to jointly develop ideas and concepts for the future.  The embedded world Exhibition&Conference is essential for anyone who wants to stay on top of core topics and industry trends! \nTake advantage of the opportunity to expand your knowledge and make new\, international business contacts!
URL:https://marketingeda.com/event/embedded-world/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ew-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230227T080000
DTEND;TZID=America/Los_Angeles:20230302T170000
DTSTAMP:20230228T000703Z
CREATED:20230227T175620Z
LAST-MODIFIED:20230228T000703Z
UID:6024-1677484800-1677776400@marketingeda.com
SUMMARY:Mobile World Conference\, MWC 2023
DESCRIPTION:MWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months.
URL:https://marketingeda.com/event/mobile-world-conference-mwc-2023/
LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230224T110000
DTEND;TZID=America/New_York:20230224T122000
DTSTAMP:20230210T211004Z
CREATED:20230210T210952Z
LAST-MODIFIED:20230210T211004Z
UID:5939-1677236400-1677241200@marketingeda.com
SUMMARY:Hardware Security 2.0: What Are The New Frontiers?
DESCRIPTION:The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner\, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade\, including open-source license-free or ready-for-licensing tools\, associated metrics\, relevant publications\, and video-demos. \nWe are delighted to continue the series of virtual CAD for Assurance tool training webinars that started in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/. \nIf you are interested in receiving updates and emails about future CAD for Assurance webinars\, please signup using this form http://eepurl.com/hxTwWf. \n\n\n\n\nRegistration\n\n\nRegistration for the webinars is required. Please select the Zoom session for each webinar you wish to attend. For questions\, please contact the organizers. \nModerators:\nDomenic Forte (U. of Florida) and Qiaoyan Yu (U. of New Hampshire) \nPanelists:\n-David Kehlet\, Intel\n-Murthi Sadhasivan\, Aerospace Corporation\n-Serge Leef\, Microsoft\n-Rainer Leupers\, RWTH Aachen University\n-Chip Hong Chang\, Nanyang Technological University
URL:https://marketingeda.com/event/hardware-security-2-0-what-are-the-new-frontiers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEECEDA-Feb-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230223T183000
DTEND;TZID=America/Los_Angeles:20230223T213000
DTSTAMP:20230203T194838Z
CREATED:20230203T194838Z
LAST-MODIFIED:20230203T194838Z
UID:5907-1677177000-1677187800@marketingeda.com
SUMMARY:Phil Kaufman Award & Banquet
DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \n\nTime\n6:30 pm – 9:30 pm \nElectronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor \nDR. GIOVANNI DE MICHELI\nProfessor of Electrical Engineering and Computer Science in the Institute of Electrical Engineering (IEL)\nat the School of Engineering as well as at the School of Computer and Communication Sciences\nof the École Polytechnique Fédérale de Lausanne (EPFL) \nwith the \n2022 Phil Kaufman Award\n \nDr. Giovanni De Micheli is honored for his extensive contributions to electronic design automation (EDA). His research in EDA tools and methodologies has made a significant\, lasting impact on the industry\, including contributions to: \nHigh-level Synthesis\nLogic Synthesis and Minimization\nHardware Software Co-Design\nNetwork on Chip (NoC)\nCell Library Mapping \nHis academic advances in EDA have had a lasting impact on the industry\nwhich would not be where it is today without his groundbreaking research.
URL:https://marketingeda.com/event/phil-kaufman-award-banquet/
LOCATION:The GlassHouse\, 2 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Award,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semi-Feb-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230222T170000
DTEND;TZID=Asia/Tokyo:20230222T180000
DTSTAMP:20230206T182350Z
CREATED:20230206T182350Z
LAST-MODIFIED:20230206T182350Z
UID:5910-1677085200-1677088800@marketingeda.com
SUMMARY:RISC-V Webinar from Andes
DESCRIPTION:Andes Technology is going to host a webinar at 17:00 PM on February 22 (Japan Standard Time (JST) and Korea Standard Time (KST)). Andes speakers will present Andes comprehensive hardware and software solutions. Samuel Chiang\, Deputy Technical Director of Marketing\, will present a wide range of applications which have adopted RISC-V solutions and will introduce new product lines. Next\, Technical Manager\, Simon Wang\, will have an overview of Andes solutions for AI including RISC-V Vector and DSP/SIMD Processor\, AndeSight™ IDE SW development tools\, Andes NN SDK and more. If you’re interested in RISC-V applications and Andes future strategy\, please don’t miss this good chance to ask questions during Q&A session! \nJoin us to learn more about the leading AndesCore™ RISC-V processor IP solutions\, including N25F-SE\, the industry’s first and only ISO 26262 fully-compliant RISC-V CPU; AX65\, a multicore 4-way out-of-order superscalar processor; AX45MPV\, the leading-edge Linux multicore 1024-bit vector processor; and D23\, the new-generation compact\, versatile\, secured core for IoT applications! \n– Date and Time: February 22\, 17:00 PM (JST & KST)\n– Agenda:\n17:00 Opening\n17:05 “Expanding the RISC-V Horizon and Beyond” by Samuel Chiang\, Deputy Technical Director of Marketing\n17:30 “The Future of Edge is About RISC-V and AI” by Simon Wang\, Senior Technical Manger\n17:50 Q&A session
URL:https://marketingeda.com/event/risc-v-webinar-from-andes/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-Feb-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230221T080000
DTEND;TZID=America/Los_Angeles:20230221T090000
DTSTAMP:20230213T195503Z
CREATED:20230213T195503Z
LAST-MODIFIED:20230213T195503Z
UID:5957-1676966400-1676970000@marketingeda.com
SUMMARY:Introduction to UCIe
DESCRIPTION:UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors\, packaging\, IP suppliers\, foundries\, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth\, low-latency\, power-efficient\, and cost-effective on-package connectivity between chiplets. \n\nJoin this educational webinar brought to you by the UCIe Consortium and presented by Dr. Debendra Das Sharma\, Chairman of the UCIe Consortium. The webinar will explore the industry demands and developments that brought about the need for a UCIe specification and share how end-users can easily mix and match chiplet components provided by a multi-vendor ecosystem for System-on-Chip (SoC) construction — including customized SoC. \n\nAttendees are encouraged to bring questions and participate in the live Q&A. \n\nRegister now to reserve your spot!
URL:https://marketingeda.com/event/introduction-to-ucie-2/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-Feb-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230219T080000
DTEND;TZID=America/Los_Angeles:20230223T170000
DTSTAMP:20221128T190714Z
CREATED:20221128T190714Z
LAST-MODIFIED:20221128T190714Z
UID:5472-1676793600-1677171600@marketingeda.com
SUMMARY:ISSCC 2023
DESCRIPTION:ISSCC 2023 is planned as a fully in-person event. On-demand access to ISSCC papers and educational material will be possible for people who cannot travel to San Francisco\, but the conference will be optimized for an in-person experience. We keep monitoring the COVID-19 pandemic and we will promptly inform you should any change in our program be needed. Looking forward to seeing you again in San Francisco! \nEugenio Cantatore – Conference Chair \nPiet Wambacq – Program Committee Chair \n\n\n2023 Plenary Sessions\n\n\n\n\n\n\nInnovation for the Next Decade of High-Performance Computing \nLisa Su\, Chair and Chief Executive Officer\, AMD\, Austin\, Texas \nShape the World with Mixed-Signal Integrated Circuits – Past\, Present\, and Future \nAkira Matsuzawa\, Professor Emeritus of Tokyo Institute of Technology and CEO of Tech Idea\, Kawasaki\, Japan \nEU Chips Act drives pan-European full-stack innovation partnerships \nJo De Boeck\, Executive Vice President and Chief Strategy Officer\, imec and KU Leuven\, Leuven\, Belgium \n5G drives exponential increase in processing needs across all industries \nErik Ekudden\, Senior Vice President\, Chief Technology Officer\, Ericsson\, Kista\, Sweden
URL:https://marketingeda.com/event/isscc-2023/
LOCATION:Marriott Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230216T100000
DTEND;TZID=America/Los_Angeles:20230216T103000
DTSTAMP:20230208T195641Z
CREATED:20230208T195641Z
LAST-MODIFIED:20230208T195641Z
UID:5930-1676541600-1676543400@marketingeda.com
SUMMARY:Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
DESCRIPTION:As an active semiconductor foundry\, SilTerra requires frequent process and technology development and enhancements\, which can result in an increased need for resources and longer time to market. To meet this ongoing challenge\, high productivity library optimization and validation are required. \nIn this webinar\, we will share the challenges of developing\, optimizing\, and validating different libraries\, and demonstrate how Cello\, Viola\, and SmartSpice contribute in a unique and dynamic way to realize fast and accurate results. We also show how using Cello and Viola ultimately result in a significant reduction in library development and validation time\, even with limited manpower and resources. \nWhat You Will Learn\n\nThe challenges of library optimization and validation\nHow Cello and Viola reduce development time and manpower requirements\nHow to optimize library characterization and validation\nHow to increase productivity without increasing resource requirements\n\n\n\n\nPresenter\n\n\n\n\nMr. Faris Amsyar Bin Ahmad Zhaki\, IP Staff Engineer\, SilTerra Malaysia Sdn. Bhd \nMr. Faris Amsyar Bin Ahmad Zhaki is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over five years. Mr. Faris Amsyar Bin Ahmad Zhaki holds a Bachelor of Electronics Engineering from University of Science\, Malaysia. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor device\, IP\, Circuit\, CAD\, SoC\, and system design engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/learn-how-silterra-uses-cello-and-viola-for-standard-cells-and-i-o-library-optimization-and-characterization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230216T080000
DTEND;TZID=America/Los_Angeles:20230216T090000
DTSTAMP:20230215T173547Z
CREATED:20230215T173547Z
LAST-MODIFIED:20230215T173547Z
UID:5981-1676534400-1676538000@marketingeda.com
SUMMARY:Removing the Risk from RISC-V using the RISC-V Trace Standard
DESCRIPTION:With the growing maturity of the RISC-V ISA\, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing\, with standards now defined for support technologies such as processor trace\, which gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems based on a new ISA. In this presentation Siemens\, as a lead technical contributor to the trace spec\, will give an overview of how processor trace is used to improve embedded software and applications\, what is contained in the trace specification\, and a description of the Enhanced Trace Encoder from Tessent Embedded Analytics\, the market-leading trace solution for RISC-V and the only commercial IP that is designed to meet the official RISC-V trace specification \nWho should attend:\n\nSoC Architects\nSoftware Architects\nEmbedded Software Engineers\nAnyone considering or already using RISC-V\n\nWhat you will learn:\n\nWe will examine the RISC-V trace standard and show how it reduces some of the risks of adopting RISC-V\nWe will see how the non-intrusive visibility which it provides can be used to understand program behavior for advanced debugging and code optimization\nWe will also examine suitability for the high-complexity heterogenous chip era by comparing the efficiency of this new standard against older methods\n\n\n\n\nSpeakers\n\n\n\n\nPeter Shields\nProduct Manager\nSiemens EDA\n\n\nPeter Shields is a Product Manager at Siemens Digital Industries Software\, with a particular focus on the Tessent Embedded Analytics family of products. He has more than 25 years of experience in Engineering\, Engineering Management and Customer Engineering roles in both EDA and semiconductor IP\, particularly for complex SoCs. Peter was a senior member of the Apps Engineering team at UltraSoC\, prior to its acquisition by Mentor/ Siemens\, and previously held roles at Synopsys\, Imagination Technologies\, Mentor/Logicvision and Cadence. He holds a BEng from the University of Birmingham\, UK.
URL:https://marketingeda.com/event/removing-the-risk-from-risc-v-using-the-risc-v-trace-standard/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-16-20223.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230214T133000
DTEND;TZID=Asia/Jerusalem:20230214T170000
DTSTAMP:20230208T181746Z
CREATED:20230208T181746Z
LAST-MODIFIED:20230208T181746Z
UID:5924-1676381400-1676394000@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:13:30 – 14:00 Low Power Design \n\nAn Effective Path to Low-Power Design\n\nThe demand for green and energy efficient products is increasing but getting there has never been easy. In this session\, we will look at how to design low-power\, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. PowerPro’s low-power design methodology has been effectively used by Arm\, Samsung\, Cisco\, and many others.\n\nQazi Ahmed\nPrincipal Product Manager for PowerPro\nSiemens EDA\nBIO:\nQazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 17 years of experience spanning across ASIC/FPGA design and EDA. \n\n14:00 – 14:30 Advanced Process Nodes \nJourney to the Best Performance-per-Watt at 3nm and Below\nIn this session\, Synopsys will discuss the journey to achieving best design results at 3nm and below technology nodes\, especially designs utilizing the unique Hybrid-row placement\, and how innovative AI-driven design methodologies\, that can shift-left downstream physical effects and signoff requirements\, are necessary to unlock the full performance-per-watt potential the latest advanced process nodes. \nJames Chuang\nProduct Manager\nSynopsys \nBIO: \nJames Chuang is a Product Manager at Synopsys. He has worked in the EDA industry for more than 15 years\, with experience in Digital Implementation and Signoff solutions. He is currently responsible for Product Management for Fusion Compiler and DSO.ai at Synopsys. \n\n14:30 – 15:00 Formal Verification \nHow Much Formal Verification is Enough? A Verification Method For High-Consequence Systems\nIn hardware verification world there is a question that is being asked always – how much verification is enough? It applies to all verification techniques. Several techniques developed means to measure it with functional and code coverage and it does apply to formal verification without reserves. \nThe question we tackle with current talk is: how much formal verification is enough? \nOne would suggest a flow that should answer the question\, starting with requirements specification\, planning\, testbench development\, prove properties\, coverage measure and sign-off. This approach has its pitfalls like missing requirements leading to missing properties\, verification pitfalls: over and under constraining\, mistakes in assertion writing\, all leading to a negative outcome of verification: re-design and re-verification. \nWith current presentation we will walk you through an automated and formal check on the properties to check for completeness where all possible input sequences are examined\, all outputs are verified at all times. The complete property set forms an abstract model of the system where all design behavior is exposed and can back-out undocumented specification from the abstract model building a closed-loop verification process using SystemVerilog Assertions. \nThe GapFree verification method is ideal for high-consequence systems where the complete verification is required and is unique among formal property verification tool capabilities. \nNicolae Tusinschi\nFormal Verification Solutions Product Manager\nSiemens EDA \nBIO: \nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a Master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a Master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n15:00 – 15:30 High-Level Synthesis \nHigh-Level Synthesis – Are You Still Missing Out?\nIn this session we will look at how C++ and SystemC High-Level Synthesis is more than just converting C++/SystemC to RTL. We’ll cover language choice\, architecture exploration\, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. Customers who have spoken publicly about Catapult HLS usage include NVIDIA\, Facebook\, Google\, Qualcomm\, ST\, Bosch\, NXP\, NASA JPL\, and many more. You won’t be first\, but you don’t have to be last. \nStuart Clubb\nTechnical Product Management Director\nSiemens EDA \nBIO: \nStuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this new role\, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics\, Stuart held the position of Technical Marketing Engineer\, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University\, London\, with a Bachelors of Science. \n\n15:30 – 16:00 Physical Planning and Timing Closure \nExcellicon Product Portfolio\nPhysical Planning and Timing Closure. Excellicon focus is on helping designer from early stages to ensure timing requirements are properly developed and  verified prior to handoff to physical design implementation. Product portfolio is designed to ensure quickest and most efficient path to timing closure and reducing unnecessary iterations. \nHimanshu Bhatnagar\nCEO\nExcellicon \nBIO: \nOver 20 years of chip design experience\, designing complex SOCs in networking\, communications\, imaging\, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon\, Himanshu served as an advisory board member of several EDA companies. His experience is crucial to ensuring development of tools fit for everyday design by front and back-end engineers and shaping the future direction of Excellicon. \n\n16:00 – 16:30 Custom Silicon \nAccelerating Data For a Connected World: The Power of Optimized Silicon\nIn this webinar we will explore the ways in which purpose-built silicon IP and system-on-a-chip (SoC) solutions are of paramount importance to the development of faster and more power efficient data networks\, as well as the growth of cloud computing and other emerging applications. We will also discuss the challenges and opportunities associated with the adoption of these solutions and provide insights into how SoCs with application-optimized chiplets in highly advanced multi-die packages are the wave of the future for accelerating data connectivity in the digital infrastructure world. \nSudhir Mallya\nSVP Corporate Marketing\nAlphawave Semi \nBIO: \nSudhir Mallya is Senior Vice President of Corporate Marketing at Alphawave IP. He is based in Silicon Valley and has over 25 years of experience at leading global semiconductor companies with executive positions in engineering\, marketing\, and business unit management. His experience spans custom silicon (ASICs) and application-specific (ASSPs) products across multiple application domains including data centers\, networking\, storage\, and edge-computing. He has an MSEE from the University of Cincinnati and a bachelor’s in electrical engineering from the Indian Institute of Technology\, Bombay.​ \n\n16:30 – 17:00 RISC-V Verification & Software Development \nRISC-V Models For Verification\, Architectural Exploration\, and Software Development\nThe design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs\, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations\, or support new multi-core communication methods. Software development with virtual prototypes is well established\, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device\, well before silicon is available. For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification\, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP. This talk highlights the RISC-V models that are unifying the hardware\, software\, and verification teams across all phases of RISC-V projects with dependable quality and efficiency. \nLarry Lapides\nVice President Sales\nImperas Software \nBIO: \nPrior to joining Imperas\, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001)\, and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity)\, Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University’s Graduate School of Management\, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
URL:https://marketingeda.com/event/semisrael-tech-webinar-4/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230209T093000
DTEND;TZID=America/Los_Angeles:20230209T103000
DTSTAMP:20230201T231144Z
CREATED:20230201T231144Z
LAST-MODIFIED:20230201T231144Z
UID:5900-1675935000-1675938600@marketingeda.com
SUMMARY:Webinar: The Rise of the Chiplet
DESCRIPTION:Join us this Thursday\, February 9th to talk about The Rise of the Chiplet. Moderated by SemiEngineering’s Brian Bailey\, this webinar will dive into the current landscape for chiplet technology\, predictions for the coming years\, what’s needed for chiplet adoption\, and the status and evolution of die-to-die interface standards. Achronix’s Nick Ilyadis\, Semico’s Rich Wawrzyniak\, and ODSA’s Bapi Vinnakota will panel the session and answer your questions live!
URL:https://marketingeda.com/event/webinar-the-rise-of-the-chiplet/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Achronix-Feb-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230125T080000
DTEND;TZID=America/Los_Angeles:20230125T090000
DTSTAMP:20230124T194950Z
CREATED:20230124T194950Z
LAST-MODIFIED:20230124T194950Z
UID:5885-1674633600-1674637200@marketingeda.com
SUMMARY:Making Way for Open-Source Hardware
DESCRIPTION:This is a thought leadership piece that highlights the significance of open-source hardware. Tony McDowell (Rapid Silicon) and Adam Taylor (Adiuvo) will discuss the innovations and changes required to bring awareness to open-source. Rapid Silicon’s Raptor Design Suite toolchain has already proven that designs can be secure even in an open-source environment. \nRapid Silicon\nThe world is getting hyper connected and hyper intelligent through aggressive adoption of AI and 5G technology. Billions of sensors are being integrated into embedded and edge applications\, creating new standards and protocols. Rapid Silicon is taking the lead with a revolutionary approach to provide solutions that meet the ever-changing needs of these new intelligent embedded and edge applications. Our nimble engineering methodology and the Open FPGA framework give us the ability to iterate quickly and bring highly differentiated products to market. This\, coupled with open-source software\, unleashes the power of the community and diverse ecosystem to develop application specific SW\, IP and solutions at an accelerated pace with thousands of members worldwide. \nAdiuvo\nFrom satellite systems in space\, to predictive maintenance in the factory\, to ADAS  on the road\, Adiuvo has experience helping our clients design systems that are reliable and meet the most stringent standards.
URL:https://marketingeda.com/event/making-way-for-open-source-hardware/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RapidSilicon-January-25-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230116T080000
DTEND;TZID=Asia/Tokyo:20230119T170000
DTSTAMP:20230104T174652Z
CREATED:20230104T174652Z
LAST-MODIFIED:20230104T174652Z
UID:5828-1673856000-1674147600@marketingeda.com
SUMMARY:ASP-DAC 2023
DESCRIPTION:ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2023 is 28th conference. ASP-DAC 2023 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2023. \n\nDate: Jan. 16-19\, 2023\nPlace: Tokyo Odaiba Miraikan\, Japan\nGeneral Chair: Atsushi Takahashi (Tokyo Institute of Technology\, Japan)\nTechnical Program Chair: Gi-Joon Nam (IBM Research\, USA)\nDesign Contest Co-Chairs: Mahfuzul Islam (Kyoto University\, Japan)\, Akira Tsuchiya (The University of Shiga Prefecture\, Japan)\n\nThe format of the conference is hybrid but mainly in-person for speakers. All speakers are expected to attend ASP-DAC 2023 physically unless a speaker has some inevitable reasons such as medical reasons and government orders.\nRestrictions on new entry into Japan due to COVID-19 have been relaxed since October 11\, 2022. Please check the following announcement from the Ministry of Foreign Affairs of Japan.\nhttps://www.mofa.go.jp/j_info/visit/visa/index.html
URL:https://marketingeda.com/event/asp-dac-2023/
LOCATION:Tokyo Odaiba Miraikan\, 2 Chome-3-6 Aomi\, Tokyo\, Koto CIty\, 135-0064\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230116T080000
DTEND;TZID=Europe/Paris:20230118T170000
DTSTAMP:20230113T205251Z
CREATED:20230113T205251Z
LAST-MODIFIED:20230113T205251Z
UID:5845-1673856000-1674061200@marketingeda.com
SUMMARY:HiPEAC
DESCRIPTION:The HiPEAC conference is the premier European forum for experts in computer architecture\, programming models\, compilers and operating systems for general-purpose\, embedded and cyber-physical systems. Areas of focus and integration include safety-critical dependencies\, cybersecurity\, energy efficiency and machine learning. \nThe HiPEAC 2023 conference will take place in Toulouse\, France. Associated workshops\, tutorials\, special sessions\, several large poster session and an industrial exhibition will run in parallel with the conference.
URL:https://marketingeda.com/event/hipeac/
LOCATION:Pierre Baudis Convention Centre\, 11 esplanade Compans Caffarelli\, Toulouse\, France
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/HiPEAC.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20230108T080000
DTEND;TZID=Asia/Karachi:20230112T170000
DTSTAMP:20221122T174938Z
CREATED:20221122T174938Z
LAST-MODIFIED:20221122T174938Z
UID:5464-1673164800-1673542800@marketingeda.com
SUMMARY:VLSID 2023
DESCRIPTION:International VLSI Design & Embedded Systems conference is a Premier Global conference with legacy of over three and half decades. This Global Annual technical conference that focusses on latest advancements in VLSI and Embedded Systems\, is attended by over 2000 engineers\, students & faculty\, industry\, academia\, researchers\, bureaucrats and government bodies. \nSemiconductors are the intangible backbone of every industry across the globe. Silicon took the lion’s share over the past decades and remained the primary enabler for digitization of the world. With scaling reaching its fundamental limits\, it is time to look at addressing technological challenges at higher levels of abstraction in CMOS based design and at the same time\, look beyond Silicon for further performance enhancement. \nVLSID 2023 – the first physical conference post pandemic\, acts a platform for industry and academia alike to discuss\, deliberate and explore into the frontiers of semiconductor eco-system that could eventually enable disruptive technologies for global digitalization \nVLSID 2023 will be hosted in the best stand-alone convention center\, HICC Hyderabad. The city is home to some of the best universities\, top global companies in research and manufacturing\, strong defense sector and thriving start-ups. Hyderabad has a rich culture with numerous historic places to visit and world famous Hyderabad Biryani to cherish. We look forward to hosting and giving you the best experience at the conference. We encourage your participation to the conference and call you to be part of the exciting know-how’s of the industry and spend quality time exploring Hyderabad.
URL:https://marketingeda.com/event/vlsid-2023/
LOCATION:Hyderabad International Convention Cente\, Hyderabad\, Telangana\, India
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Hong_Kong:20221226T080000
DTEND;TZID=Asia/Hong_Kong:20221227T170000
DTSTAMP:20221220T184858Z
CREATED:20221220T184858Z
LAST-MODIFIED:20221220T184858Z
UID:5582-1672041600-1672160400@marketingeda.com
SUMMARY:CSIA-ICCAD 2022
DESCRIPTION:As a strategic\, basic and leading industry in national economic and social development\, integrated circuit(IC) industry is an important support for cultivating strategic emerging industries and developing information economy\, and plays an important role in the core of information technology field.  Promoting the healthy development of IC industry is the only way to realize the autonomous control of core technology.  With the independent innovation and development of China’s IC industry\, its market scale and enterprise competitiveness continue to improve\, China has become the world’s largest and fastest growing IC market.  At present\, the global IC industry has entered a major period of transformation and reform. As the industry leader and an important link of technology and product innovation\, the IC design industry bears an important responsibility in the development of the industry\, and is also the key to achieve independent control of the semiconductor industry. \nDuring the development of China’s IC design industry\, CSIA – ICCAD Annual Conference has played an important role in promoting industry cluster\, linking industrial resources\, and keeping abreast of industry trends. Over the years\, the theme of the Annual Conference has been combined with the actual development of the electronic information industry in the host city of the conference. The Conference has promoted the simultaneous development of the related industries in the host cities and the national IC industry. Therefore\, the “CSIA – ICCAD 2022 Annual Conference & Guangzhou IC Industry Innovation and Development Summit (ICCAD 2022)” is planned to be held in Guangzhou from November 9 to 10\, 2022. \nThe theme of this year’s conference is “Bay Area has you\, core to the future”. The Conference will discuss the opportunities and challenges faced by the IC industry\, especially the IC design industry\, and enhance the innovation capability and the integration capability of China’s IC industry chain to meet market demands and improve international competitiveness. The conference will create a platform for communication and cooperation for enterprises in all aspects of the IC industry chain\, and a platform for communication and cooperation in technology\, market\, application\, investment and other fields for IC design enterprises. \nThe related matters of this annual conference are hereby notified as follows: \n\nGuidanced by:\n\n  Industry and Information Technology Department of Guangdong \nThe People’s Government of Guangzhou Municipality \nChina Semiconductor Industry Association \n\nHosted by:\n\nChina Semiconductor Industry Association IC Design Branch (CSIA – ICCAD) \nNational S&T Major Project(NMP) 01 General Expert Group \nChina Integrated Circuit Design Innovative Alliance \nIII. Supported by: \n     The People’s Government of Guangzhou Huangpu District \nGuangzhou Municipal Industry and Information Technology Bureau \n\nOrganizedby:\n\n     Guangzhou Huangpu District Industry and Information Bureau \nGuangdong Integrated Circuit Industry Association \nShanghai Xinmei Conference Service Co.\, Ltd. \nShanghai Yaxun Shangwu Zixun Co.\, Ltd. \nV.Co-organized by: \nChina Institute of Communications-ASIC Committee \nChina Integrated Circuit(CIC) \nVI.Registration Date: November 8\, 2022 (Tuesday) \nConference Date: November 9-10\, 2022 \nVII. Registration Location: The Westin Pazhou Guangzhou \n (Address: No. 681\, Fengpuzhong Road\, Haizhu District\, Guangzhou) \nConference Location: Guangzhou PWTC Expo \n (Address: No.1000\, Xingangdong Road\, Haizhu District\, Guangzhou) \nVIII. Conference Content \n\nKeynote Speeches\n\n(1) China IC Design Industry Current Development Situation Report \n(2) Coordinate Science & Technology Resources to Realize Innovation Development Report \n(3) Global IC Technology and Industry Development Trend Report \n\nSeminars\n\nl  IC Design and Innovation Application \nl  IC Design and EDA Software \nl  Foundry and Process Technology \nl  IC Packaging and Testing \nl  IP and IC Design Services \nl  Capital and Entrepreneurship \nl  Guangzhou IC Innovation and Entrepreneurship Forum \n\nChina IC Design Industry Exhibition\nIX. Participants\n\nThe relevant authorities and local leaders\, relevant domestic and foreign experts\, representatives from local bases and industry associations\, IC design companies\, IP service vendors\, EDA vendors\, foundry companies\, packaging testing vendors\, system vendors and venture capital firms at home and abroad\, representatives from IC industries Parks and related media. \n\n Contacts\n\nContact:Shirley Hu \nTel: 18917192814\, E-mail: shirleyhp@cicmag.com \nContact:Yuanyuan Wang \nTel:18600095161\, E-mail: wangyy@csia-iccad.net.cn \n\nThe organizers of the annual conference are required to conscientiously and carefully organize and prepare for the conference and ensure a complete success. \nAnnex: Registration Form
URL:https://marketingeda.com/event/csia-iccad-2022/
LOCATION:Xiamen International Convention Center\, 198 Exhibition Road\, Xiamen City\, China
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CSIA-ICCAD-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221220T100000
DTEND;TZID=America/Los_Angeles:20221220T110000
DTSTAMP:20221212T220742Z
CREATED:20221212T220611Z
LAST-MODIFIED:20221212T220742Z
UID:5498-1671530400-1671534000@marketingeda.com
SUMMARY:Using Formal Datapath Validation to Verify AI Processor Computations
DESCRIPTION:For over a decade\, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs\, AI processors are also datapath heavy with mathematical functions like addition\, subtraction\, matrix multiplication\, and square root in its compute engines\, making these designs a good fit for formal datapath validation. \nThis webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions. The Synopsys ARC NPX6 processor supports the latest and most complex neural networks\, such as CNN\, RNN\, and transformers\, targeted for AI SoCs that are widely used in automotive\, data center\, high end gaming\, next generation augmented reality\, and surveillance. At the heart of the NPX6 neural network processor are convolution and tensor accelerators that are optimized to perform light speed computations. Correctness of these functional units are key to correct facial\, audio\, image processing and recognition which could have safety implications for automotive applications. We will explore Synopsys VC Formal DPV\, the gold standard for datapath validation and signoff for the last 20 years\, and how it is used to ensure correctness of the core algorithms of the ARC NPX6 processor’s compute engines. \n\n\n\nSpeakers\n\n\n\nNeelabja Dutta\nSr. Manager\, Applications Engineering\nSynopsys\n\n\n\n\n\nShuaiyu Jiang\nSr. ASIC Digital Design Engineer\nSynopsys
URL:https://marketingeda.com/event/using-formal-datapath-validation-to-verify-ai-processor-computations/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-December-20-2022.png
END:VEVENT
END:VCALENDAR