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BEGIN:DAYLIGHT
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DTSTART;TZID=America/Chicago:20230314T190000
DTEND;TZID=America/Chicago:20230314T210000
DTSTAMP:20230302T211620Z
CREATED:20230302T211620Z
LAST-MODIFIED:20230302T211620Z
UID:6061-1678820400-1678827600@marketingeda.com
SUMMARY:March Austin RISC-V Meetup
DESCRIPTION:This will be an on-line event. We’ll be the RISC-V Bivy virtual meeting system. The use of a microphone and/or camera are not required to participate in the event\, chat will be monitored. We’ll be discussing current and future hardware releases\, state of various software projects\, and plans for future meetups. We’re also going to be having some discussion on selection of an FPGA Development board for future meetings on synthesizing RISC-V SoCs and testing of new hardware features as well as running Linux.
URL:https://marketingeda.com/event/march-austin-risc-v-meetup/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Meetup.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230314T080000
DTEND;TZID=America/Los_Angeles:20230316T170000
DTSTAMP:20230313T200643Z
CREATED:20230124T193702Z
LAST-MODIFIED:20230313T200643Z
UID:5880-1678780800-1678986000@marketingeda.com
SUMMARY:Embedded World
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nMain topics in 2023\n\nembedded: A variety of technological challenges shape the modern design concepts of complex embedded systems – from sensors to the cloud\, from hardware to software to tools – smart\, intelligent\, efficient\, safe\, reliable\, interoperable…\n\n\nresponsible: Evermore embedded systems are being used in function-critical applications such as medical technology\, mobility and industrial automation. The industry meets these challenges with adaptive\, autonomous and intelligent systems that safely and reliably carry out critical tasks. Many questions ranging from responsibility by design to formal verification methods and ethical issues must be answered.\nsustainable: Embedded systems are central\, basic elements for many efficient and sustainable applications. Embedded systems themselves must also be sustainable over the entire life cycle -from design and manufacturing to operation and updateability\, refurbishment\, decommissioning and disposal.\n\nSpecialty areas at the trade fair and conferences focus on current megatrends\, such as embedded vision\, safety & security\, M2M communication\, IP & IC design and embedded intelligence. \nThe embedded world Exhibition&Conference facilitates direct interaction with a large number of experts and qualified suppliers from all over the world. Whether at specialist forums\, expert panels\, the embedded world Conference or electronic displays Conference\, experts from the embedded community meet at eye-level to jointly develop ideas and concepts for the future.  The embedded world Exhibition&Conference is essential for anyone who wants to stay on top of core topics and industry trends! \nTake advantage of the opportunity to expand your knowledge and make new\, international business contacts!
URL:https://marketingeda.com/event/embedded-world/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ew-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230227T080000
DTEND;TZID=America/Los_Angeles:20230302T170000
DTSTAMP:20230228T000703Z
CREATED:20230227T175620Z
LAST-MODIFIED:20230228T000703Z
UID:6024-1677484800-1677776400@marketingeda.com
SUMMARY:Mobile World Conference\, MWC 2023
DESCRIPTION:MWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months.
URL:https://marketingeda.com/event/mobile-world-conference-mwc-2023/
LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230224T110000
DTEND;TZID=America/New_York:20230224T122000
DTSTAMP:20230210T211004Z
CREATED:20230210T210952Z
LAST-MODIFIED:20230210T211004Z
UID:5939-1677236400-1677241200@marketingeda.com
SUMMARY:Hardware Security 2.0: What Are The New Frontiers?
DESCRIPTION:The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner\, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade\, including open-source license-free or ready-for-licensing tools\, associated metrics\, relevant publications\, and video-demos. \nWe are delighted to continue the series of virtual CAD for Assurance tool training webinars that started in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/. \nIf you are interested in receiving updates and emails about future CAD for Assurance webinars\, please signup using this form http://eepurl.com/hxTwWf. \n\n\n\n\nRegistration\n\n\nRegistration for the webinars is required. Please select the Zoom session for each webinar you wish to attend. For questions\, please contact the organizers. \nModerators:\nDomenic Forte (U. of Florida) and Qiaoyan Yu (U. of New Hampshire) \nPanelists:\n-David Kehlet\, Intel\n-Murthi Sadhasivan\, Aerospace Corporation\n-Serge Leef\, Microsoft\n-Rainer Leupers\, RWTH Aachen University\n-Chip Hong Chang\, Nanyang Technological University
URL:https://marketingeda.com/event/hardware-security-2-0-what-are-the-new-frontiers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEECEDA-Feb-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230223T183000
DTEND;TZID=America/Los_Angeles:20230223T213000
DTSTAMP:20230203T194838Z
CREATED:20230203T194838Z
LAST-MODIFIED:20230203T194838Z
UID:5907-1677177000-1677187800@marketingeda.com
SUMMARY:Phil Kaufman Award & Banquet
DESCRIPTION:The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations\, education/mentoring\, or business or industry leadership. The award was established as a tribute to Phil Kaufman\, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. \n\nTime\n6:30 pm – 9:30 pm \nElectronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor \nDR. GIOVANNI DE MICHELI\nProfessor of Electrical Engineering and Computer Science in the Institute of Electrical Engineering (IEL)\nat the School of Engineering as well as at the School of Computer and Communication Sciences\nof the École Polytechnique Fédérale de Lausanne (EPFL) \nwith the \n2022 Phil Kaufman Award\n \nDr. Giovanni De Micheli is honored for his extensive contributions to electronic design automation (EDA). His research in EDA tools and methodologies has made a significant\, lasting impact on the industry\, including contributions to: \nHigh-level Synthesis\nLogic Synthesis and Minimization\nHardware Software Co-Design\nNetwork on Chip (NoC)\nCell Library Mapping \nHis academic advances in EDA have had a lasting impact on the industry\nwhich would not be where it is today without his groundbreaking research.
URL:https://marketingeda.com/event/phil-kaufman-award-banquet/
LOCATION:The GlassHouse\, 2 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Award,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semi-Feb-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230222T170000
DTEND;TZID=Asia/Tokyo:20230222T180000
DTSTAMP:20230206T182350Z
CREATED:20230206T182350Z
LAST-MODIFIED:20230206T182350Z
UID:5910-1677085200-1677088800@marketingeda.com
SUMMARY:RISC-V Webinar from Andes
DESCRIPTION:Andes Technology is going to host a webinar at 17:00 PM on February 22 (Japan Standard Time (JST) and Korea Standard Time (KST)). Andes speakers will present Andes comprehensive hardware and software solutions. Samuel Chiang\, Deputy Technical Director of Marketing\, will present a wide range of applications which have adopted RISC-V solutions and will introduce new product lines. Next\, Technical Manager\, Simon Wang\, will have an overview of Andes solutions for AI including RISC-V Vector and DSP/SIMD Processor\, AndeSight™ IDE SW development tools\, Andes NN SDK and more. If you’re interested in RISC-V applications and Andes future strategy\, please don’t miss this good chance to ask questions during Q&A session! \nJoin us to learn more about the leading AndesCore™ RISC-V processor IP solutions\, including N25F-SE\, the industry’s first and only ISO 26262 fully-compliant RISC-V CPU; AX65\, a multicore 4-way out-of-order superscalar processor; AX45MPV\, the leading-edge Linux multicore 1024-bit vector processor; and D23\, the new-generation compact\, versatile\, secured core for IoT applications! \n– Date and Time: February 22\, 17:00 PM (JST & KST)\n– Agenda:\n17:00 Opening\n17:05 “Expanding the RISC-V Horizon and Beyond” by Samuel Chiang\, Deputy Technical Director of Marketing\n17:30 “The Future of Edge is About RISC-V and AI” by Simon Wang\, Senior Technical Manger\n17:50 Q&A session
URL:https://marketingeda.com/event/risc-v-webinar-from-andes/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-Feb-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230221T080000
DTEND;TZID=America/Los_Angeles:20230221T090000
DTSTAMP:20230213T195503Z
CREATED:20230213T195503Z
LAST-MODIFIED:20230213T195503Z
UID:5957-1676966400-1676970000@marketingeda.com
SUMMARY:Introduction to UCIe
DESCRIPTION:UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors\, packaging\, IP suppliers\, foundries\, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth\, low-latency\, power-efficient\, and cost-effective on-package connectivity between chiplets. \n\nJoin this educational webinar brought to you by the UCIe Consortium and presented by Dr. Debendra Das Sharma\, Chairman of the UCIe Consortium. The webinar will explore the industry demands and developments that brought about the need for a UCIe specification and share how end-users can easily mix and match chiplet components provided by a multi-vendor ecosystem for System-on-Chip (SoC) construction — including customized SoC. \n\nAttendees are encouraged to bring questions and participate in the live Q&A. \n\nRegister now to reserve your spot!
URL:https://marketingeda.com/event/introduction-to-ucie-2/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-Feb-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230219T080000
DTEND;TZID=America/Los_Angeles:20230223T170000
DTSTAMP:20221128T190714Z
CREATED:20221128T190714Z
LAST-MODIFIED:20221128T190714Z
UID:5472-1676793600-1677171600@marketingeda.com
SUMMARY:ISSCC 2023
DESCRIPTION:ISSCC 2023 is planned as a fully in-person event. On-demand access to ISSCC papers and educational material will be possible for people who cannot travel to San Francisco\, but the conference will be optimized for an in-person experience. We keep monitoring the COVID-19 pandemic and we will promptly inform you should any change in our program be needed. Looking forward to seeing you again in San Francisco! \nEugenio Cantatore – Conference Chair \nPiet Wambacq – Program Committee Chair \n\n\n2023 Plenary Sessions\n\n\n\n\n\n\nInnovation for the Next Decade of High-Performance Computing \nLisa Su\, Chair and Chief Executive Officer\, AMD\, Austin\, Texas \nShape the World with Mixed-Signal Integrated Circuits – Past\, Present\, and Future \nAkira Matsuzawa\, Professor Emeritus of Tokyo Institute of Technology and CEO of Tech Idea\, Kawasaki\, Japan \nEU Chips Act drives pan-European full-stack innovation partnerships \nJo De Boeck\, Executive Vice President and Chief Strategy Officer\, imec and KU Leuven\, Leuven\, Belgium \n5G drives exponential increase in processing needs across all industries \nErik Ekudden\, Senior Vice President\, Chief Technology Officer\, Ericsson\, Kista\, Sweden
URL:https://marketingeda.com/event/isscc-2023/
LOCATION:Marriott Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230216T100000
DTEND;TZID=America/Los_Angeles:20230216T103000
DTSTAMP:20230208T195641Z
CREATED:20230208T195641Z
LAST-MODIFIED:20230208T195641Z
UID:5930-1676541600-1676543400@marketingeda.com
SUMMARY:Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
DESCRIPTION:As an active semiconductor foundry\, SilTerra requires frequent process and technology development and enhancements\, which can result in an increased need for resources and longer time to market. To meet this ongoing challenge\, high productivity library optimization and validation are required. \nIn this webinar\, we will share the challenges of developing\, optimizing\, and validating different libraries\, and demonstrate how Cello\, Viola\, and SmartSpice contribute in a unique and dynamic way to realize fast and accurate results. We also show how using Cello and Viola ultimately result in a significant reduction in library development and validation time\, even with limited manpower and resources. \nWhat You Will Learn\n\nThe challenges of library optimization and validation\nHow Cello and Viola reduce development time and manpower requirements\nHow to optimize library characterization and validation\nHow to increase productivity without increasing resource requirements\n\n\n\n\nPresenter\n\n\n\n\nMr. Faris Amsyar Bin Ahmad Zhaki\, IP Staff Engineer\, SilTerra Malaysia Sdn. Bhd \nMr. Faris Amsyar Bin Ahmad Zhaki is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over five years. Mr. Faris Amsyar Bin Ahmad Zhaki holds a Bachelor of Electronics Engineering from University of Science\, Malaysia. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor device\, IP\, Circuit\, CAD\, SoC\, and system design engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/learn-how-silterra-uses-cello-and-viola-for-standard-cells-and-i-o-library-optimization-and-characterization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230216T080000
DTEND;TZID=America/Los_Angeles:20230216T090000
DTSTAMP:20230215T173547Z
CREATED:20230215T173547Z
LAST-MODIFIED:20230215T173547Z
UID:5981-1676534400-1676538000@marketingeda.com
SUMMARY:Removing the Risk from RISC-V using the RISC-V Trace Standard
DESCRIPTION:With the growing maturity of the RISC-V ISA\, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing\, with standards now defined for support technologies such as processor trace\, which gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems based on a new ISA. In this presentation Siemens\, as a lead technical contributor to the trace spec\, will give an overview of how processor trace is used to improve embedded software and applications\, what is contained in the trace specification\, and a description of the Enhanced Trace Encoder from Tessent Embedded Analytics\, the market-leading trace solution for RISC-V and the only commercial IP that is designed to meet the official RISC-V trace specification \nWho should attend:\n\nSoC Architects\nSoftware Architects\nEmbedded Software Engineers\nAnyone considering or already using RISC-V\n\nWhat you will learn:\n\nWe will examine the RISC-V trace standard and show how it reduces some of the risks of adopting RISC-V\nWe will see how the non-intrusive visibility which it provides can be used to understand program behavior for advanced debugging and code optimization\nWe will also examine suitability for the high-complexity heterogenous chip era by comparing the efficiency of this new standard against older methods\n\n\n\n\nSpeakers\n\n\n\n\nPeter Shields\nProduct Manager\nSiemens EDA\n\n\nPeter Shields is a Product Manager at Siemens Digital Industries Software\, with a particular focus on the Tessent Embedded Analytics family of products. He has more than 25 years of experience in Engineering\, Engineering Management and Customer Engineering roles in both EDA and semiconductor IP\, particularly for complex SoCs. Peter was a senior member of the Apps Engineering team at UltraSoC\, prior to its acquisition by Mentor/ Siemens\, and previously held roles at Synopsys\, Imagination Technologies\, Mentor/Logicvision and Cadence. He holds a BEng from the University of Birmingham\, UK.
URL:https://marketingeda.com/event/removing-the-risk-from-risc-v-using-the-risc-v-trace-standard/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-16-20223.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230214T133000
DTEND;TZID=Asia/Jerusalem:20230214T170000
DTSTAMP:20230208T181746Z
CREATED:20230208T181746Z
LAST-MODIFIED:20230208T181746Z
UID:5924-1676381400-1676394000@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:13:30 – 14:00 Low Power Design \n\nAn Effective Path to Low-Power Design\n\nThe demand for green and energy efficient products is increasing but getting there has never been easy. In this session\, we will look at how to design low-power\, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. PowerPro’s low-power design methodology has been effectively used by Arm\, Samsung\, Cisco\, and many others.\n\nQazi Ahmed\nPrincipal Product Manager for PowerPro\nSiemens EDA\nBIO:\nQazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 17 years of experience spanning across ASIC/FPGA design and EDA. \n\n14:00 – 14:30 Advanced Process Nodes \nJourney to the Best Performance-per-Watt at 3nm and Below\nIn this session\, Synopsys will discuss the journey to achieving best design results at 3nm and below technology nodes\, especially designs utilizing the unique Hybrid-row placement\, and how innovative AI-driven design methodologies\, that can shift-left downstream physical effects and signoff requirements\, are necessary to unlock the full performance-per-watt potential the latest advanced process nodes. \nJames Chuang\nProduct Manager\nSynopsys \nBIO: \nJames Chuang is a Product Manager at Synopsys. He has worked in the EDA industry for more than 15 years\, with experience in Digital Implementation and Signoff solutions. He is currently responsible for Product Management for Fusion Compiler and DSO.ai at Synopsys. \n\n14:30 – 15:00 Formal Verification \nHow Much Formal Verification is Enough? A Verification Method For High-Consequence Systems\nIn hardware verification world there is a question that is being asked always – how much verification is enough? It applies to all verification techniques. Several techniques developed means to measure it with functional and code coverage and it does apply to formal verification without reserves. \nThe question we tackle with current talk is: how much formal verification is enough? \nOne would suggest a flow that should answer the question\, starting with requirements specification\, planning\, testbench development\, prove properties\, coverage measure and sign-off. This approach has its pitfalls like missing requirements leading to missing properties\, verification pitfalls: over and under constraining\, mistakes in assertion writing\, all leading to a negative outcome of verification: re-design and re-verification. \nWith current presentation we will walk you through an automated and formal check on the properties to check for completeness where all possible input sequences are examined\, all outputs are verified at all times. The complete property set forms an abstract model of the system where all design behavior is exposed and can back-out undocumented specification from the abstract model building a closed-loop verification process using SystemVerilog Assertions. \nThe GapFree verification method is ideal for high-consequence systems where the complete verification is required and is unique among formal property verification tool capabilities. \nNicolae Tusinschi\nFormal Verification Solutions Product Manager\nSiemens EDA \nBIO: \nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a Master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a Master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n15:00 – 15:30 High-Level Synthesis \nHigh-Level Synthesis – Are You Still Missing Out?\nIn this session we will look at how C++ and SystemC High-Level Synthesis is more than just converting C++/SystemC to RTL. We’ll cover language choice\, architecture exploration\, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. Customers who have spoken publicly about Catapult HLS usage include NVIDIA\, Facebook\, Google\, Qualcomm\, ST\, Bosch\, NXP\, NASA JPL\, and many more. You won’t be first\, but you don’t have to be last. \nStuart Clubb\nTechnical Product Management Director\nSiemens EDA \nBIO: \nStuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this new role\, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics\, Stuart held the position of Technical Marketing Engineer\, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University\, London\, with a Bachelors of Science. \n\n15:30 – 16:00 Physical Planning and Timing Closure \nExcellicon Product Portfolio\nPhysical Planning and Timing Closure. Excellicon focus is on helping designer from early stages to ensure timing requirements are properly developed and  verified prior to handoff to physical design implementation. Product portfolio is designed to ensure quickest and most efficient path to timing closure and reducing unnecessary iterations. \nHimanshu Bhatnagar\nCEO\nExcellicon \nBIO: \nOver 20 years of chip design experience\, designing complex SOCs in networking\, communications\, imaging\, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon\, Himanshu served as an advisory board member of several EDA companies. His experience is crucial to ensuring development of tools fit for everyday design by front and back-end engineers and shaping the future direction of Excellicon. \n\n16:00 – 16:30 Custom Silicon \nAccelerating Data For a Connected World: The Power of Optimized Silicon\nIn this webinar we will explore the ways in which purpose-built silicon IP and system-on-a-chip (SoC) solutions are of paramount importance to the development of faster and more power efficient data networks\, as well as the growth of cloud computing and other emerging applications. We will also discuss the challenges and opportunities associated with the adoption of these solutions and provide insights into how SoCs with application-optimized chiplets in highly advanced multi-die packages are the wave of the future for accelerating data connectivity in the digital infrastructure world. \nSudhir Mallya\nSVP Corporate Marketing\nAlphawave Semi \nBIO: \nSudhir Mallya is Senior Vice President of Corporate Marketing at Alphawave IP. He is based in Silicon Valley and has over 25 years of experience at leading global semiconductor companies with executive positions in engineering\, marketing\, and business unit management. His experience spans custom silicon (ASICs) and application-specific (ASSPs) products across multiple application domains including data centers\, networking\, storage\, and edge-computing. He has an MSEE from the University of Cincinnati and a bachelor’s in electrical engineering from the Indian Institute of Technology\, Bombay.​ \n\n16:30 – 17:00 RISC-V Verification & Software Development \nRISC-V Models For Verification\, Architectural Exploration\, and Software Development\nThe design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs\, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations\, or support new multi-core communication methods. Software development with virtual prototypes is well established\, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device\, well before silicon is available. For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification\, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP. This talk highlights the RISC-V models that are unifying the hardware\, software\, and verification teams across all phases of RISC-V projects with dependable quality and efficiency. \nLarry Lapides\nVice President Sales\nImperas Software \nBIO: \nPrior to joining Imperas\, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001)\, and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity)\, Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University’s Graduate School of Management\, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
URL:https://marketingeda.com/event/semisrael-tech-webinar-4/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230209T093000
DTEND;TZID=America/Los_Angeles:20230209T103000
DTSTAMP:20230201T231144Z
CREATED:20230201T231144Z
LAST-MODIFIED:20230201T231144Z
UID:5900-1675935000-1675938600@marketingeda.com
SUMMARY:Webinar: The Rise of the Chiplet
DESCRIPTION:Join us this Thursday\, February 9th to talk about The Rise of the Chiplet. Moderated by SemiEngineering’s Brian Bailey\, this webinar will dive into the current landscape for chiplet technology\, predictions for the coming years\, what’s needed for chiplet adoption\, and the status and evolution of die-to-die interface standards. Achronix’s Nick Ilyadis\, Semico’s Rich Wawrzyniak\, and ODSA’s Bapi Vinnakota will panel the session and answer your questions live!
URL:https://marketingeda.com/event/webinar-the-rise-of-the-chiplet/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Achronix-Feb-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230125T080000
DTEND;TZID=America/Los_Angeles:20230125T090000
DTSTAMP:20230124T194950Z
CREATED:20230124T194950Z
LAST-MODIFIED:20230124T194950Z
UID:5885-1674633600-1674637200@marketingeda.com
SUMMARY:Making Way for Open-Source Hardware
DESCRIPTION:This is a thought leadership piece that highlights the significance of open-source hardware. Tony McDowell (Rapid Silicon) and Adam Taylor (Adiuvo) will discuss the innovations and changes required to bring awareness to open-source. Rapid Silicon’s Raptor Design Suite toolchain has already proven that designs can be secure even in an open-source environment. \nRapid Silicon\nThe world is getting hyper connected and hyper intelligent through aggressive adoption of AI and 5G technology. Billions of sensors are being integrated into embedded and edge applications\, creating new standards and protocols. Rapid Silicon is taking the lead with a revolutionary approach to provide solutions that meet the ever-changing needs of these new intelligent embedded and edge applications. Our nimble engineering methodology and the Open FPGA framework give us the ability to iterate quickly and bring highly differentiated products to market. This\, coupled with open-source software\, unleashes the power of the community and diverse ecosystem to develop application specific SW\, IP and solutions at an accelerated pace with thousands of members worldwide. \nAdiuvo\nFrom satellite systems in space\, to predictive maintenance in the factory\, to ADAS  on the road\, Adiuvo has experience helping our clients design systems that are reliable and meet the most stringent standards.
URL:https://marketingeda.com/event/making-way-for-open-source-hardware/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RapidSilicon-January-25-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230116T080000
DTEND;TZID=Asia/Tokyo:20230119T170000
DTSTAMP:20230104T174652Z
CREATED:20230104T174652Z
LAST-MODIFIED:20230104T174652Z
UID:5828-1673856000-1674147600@marketingeda.com
SUMMARY:ASP-DAC 2023
DESCRIPTION:ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2023 is 28th conference. ASP-DAC 2023 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2023. \n\nDate: Jan. 16-19\, 2023\nPlace: Tokyo Odaiba Miraikan\, Japan\nGeneral Chair: Atsushi Takahashi (Tokyo Institute of Technology\, Japan)\nTechnical Program Chair: Gi-Joon Nam (IBM Research\, USA)\nDesign Contest Co-Chairs: Mahfuzul Islam (Kyoto University\, Japan)\, Akira Tsuchiya (The University of Shiga Prefecture\, Japan)\n\nThe format of the conference is hybrid but mainly in-person for speakers. All speakers are expected to attend ASP-DAC 2023 physically unless a speaker has some inevitable reasons such as medical reasons and government orders.\nRestrictions on new entry into Japan due to COVID-19 have been relaxed since October 11\, 2022. Please check the following announcement from the Ministry of Foreign Affairs of Japan.\nhttps://www.mofa.go.jp/j_info/visit/visa/index.html
URL:https://marketingeda.com/event/asp-dac-2023/
LOCATION:Tokyo Odaiba Miraikan\, 2 Chome-3-6 Aomi\, Tokyo\, Koto CIty\, 135-0064\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230116T080000
DTEND;TZID=Europe/Paris:20230118T170000
DTSTAMP:20230113T205251Z
CREATED:20230113T205251Z
LAST-MODIFIED:20230113T205251Z
UID:5845-1673856000-1674061200@marketingeda.com
SUMMARY:HiPEAC
DESCRIPTION:The HiPEAC conference is the premier European forum for experts in computer architecture\, programming models\, compilers and operating systems for general-purpose\, embedded and cyber-physical systems. Areas of focus and integration include safety-critical dependencies\, cybersecurity\, energy efficiency and machine learning. \nThe HiPEAC 2023 conference will take place in Toulouse\, France. Associated workshops\, tutorials\, special sessions\, several large poster session and an industrial exhibition will run in parallel with the conference.
URL:https://marketingeda.com/event/hipeac/
LOCATION:Pierre Baudis Convention Centre\, 11 esplanade Compans Caffarelli\, Toulouse\, France
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/HiPEAC.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20230108T080000
DTEND;TZID=Asia/Karachi:20230112T170000
DTSTAMP:20221122T174938Z
CREATED:20221122T174938Z
LAST-MODIFIED:20221122T174938Z
UID:5464-1673164800-1673542800@marketingeda.com
SUMMARY:VLSID 2023
DESCRIPTION:International VLSI Design & Embedded Systems conference is a Premier Global conference with legacy of over three and half decades. This Global Annual technical conference that focusses on latest advancements in VLSI and Embedded Systems\, is attended by over 2000 engineers\, students & faculty\, industry\, academia\, researchers\, bureaucrats and government bodies. \nSemiconductors are the intangible backbone of every industry across the globe. Silicon took the lion’s share over the past decades and remained the primary enabler for digitization of the world. With scaling reaching its fundamental limits\, it is time to look at addressing technological challenges at higher levels of abstraction in CMOS based design and at the same time\, look beyond Silicon for further performance enhancement. \nVLSID 2023 – the first physical conference post pandemic\, acts a platform for industry and academia alike to discuss\, deliberate and explore into the frontiers of semiconductor eco-system that could eventually enable disruptive technologies for global digitalization \nVLSID 2023 will be hosted in the best stand-alone convention center\, HICC Hyderabad. The city is home to some of the best universities\, top global companies in research and manufacturing\, strong defense sector and thriving start-ups. Hyderabad has a rich culture with numerous historic places to visit and world famous Hyderabad Biryani to cherish. We look forward to hosting and giving you the best experience at the conference. We encourage your participation to the conference and call you to be part of the exciting know-how’s of the industry and spend quality time exploring Hyderabad.
URL:https://marketingeda.com/event/vlsid-2023/
LOCATION:Hyderabad International Convention Cente\, Hyderabad\, Telangana\, India
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Hong_Kong:20221226T080000
DTEND;TZID=Asia/Hong_Kong:20221227T170000
DTSTAMP:20221220T184858Z
CREATED:20221220T184858Z
LAST-MODIFIED:20221220T184858Z
UID:5582-1672041600-1672160400@marketingeda.com
SUMMARY:CSIA-ICCAD 2022
DESCRIPTION:As a strategic\, basic and leading industry in national economic and social development\, integrated circuit(IC) industry is an important support for cultivating strategic emerging industries and developing information economy\, and plays an important role in the core of information technology field.  Promoting the healthy development of IC industry is the only way to realize the autonomous control of core technology.  With the independent innovation and development of China’s IC industry\, its market scale and enterprise competitiveness continue to improve\, China has become the world’s largest and fastest growing IC market.  At present\, the global IC industry has entered a major period of transformation and reform. As the industry leader and an important link of technology and product innovation\, the IC design industry bears an important responsibility in the development of the industry\, and is also the key to achieve independent control of the semiconductor industry. \nDuring the development of China’s IC design industry\, CSIA – ICCAD Annual Conference has played an important role in promoting industry cluster\, linking industrial resources\, and keeping abreast of industry trends. Over the years\, the theme of the Annual Conference has been combined with the actual development of the electronic information industry in the host city of the conference. The Conference has promoted the simultaneous development of the related industries in the host cities and the national IC industry. Therefore\, the “CSIA – ICCAD 2022 Annual Conference & Guangzhou IC Industry Innovation and Development Summit (ICCAD 2022)” is planned to be held in Guangzhou from November 9 to 10\, 2022. \nThe theme of this year’s conference is “Bay Area has you\, core to the future”. The Conference will discuss the opportunities and challenges faced by the IC industry\, especially the IC design industry\, and enhance the innovation capability and the integration capability of China’s IC industry chain to meet market demands and improve international competitiveness. The conference will create a platform for communication and cooperation for enterprises in all aspects of the IC industry chain\, and a platform for communication and cooperation in technology\, market\, application\, investment and other fields for IC design enterprises. \nThe related matters of this annual conference are hereby notified as follows: \n\nGuidanced by:\n\n  Industry and Information Technology Department of Guangdong \nThe People’s Government of Guangzhou Municipality \nChina Semiconductor Industry Association \n\nHosted by:\n\nChina Semiconductor Industry Association IC Design Branch (CSIA – ICCAD) \nNational S&T Major Project(NMP) 01 General Expert Group \nChina Integrated Circuit Design Innovative Alliance \nIII. Supported by: \n     The People’s Government of Guangzhou Huangpu District \nGuangzhou Municipal Industry and Information Technology Bureau \n\nOrganizedby:\n\n     Guangzhou Huangpu District Industry and Information Bureau \nGuangdong Integrated Circuit Industry Association \nShanghai Xinmei Conference Service Co.\, Ltd. \nShanghai Yaxun Shangwu Zixun Co.\, Ltd. \nV.Co-organized by: \nChina Institute of Communications-ASIC Committee \nChina Integrated Circuit(CIC) \nVI.Registration Date: November 8\, 2022 (Tuesday) \nConference Date: November 9-10\, 2022 \nVII. Registration Location: The Westin Pazhou Guangzhou \n (Address: No. 681\, Fengpuzhong Road\, Haizhu District\, Guangzhou) \nConference Location: Guangzhou PWTC Expo \n (Address: No.1000\, Xingangdong Road\, Haizhu District\, Guangzhou) \nVIII. Conference Content \n\nKeynote Speeches\n\n(1) China IC Design Industry Current Development Situation Report \n(2) Coordinate Science & Technology Resources to Realize Innovation Development Report \n(3) Global IC Technology and Industry Development Trend Report \n\nSeminars\n\nl  IC Design and Innovation Application \nl  IC Design and EDA Software \nl  Foundry and Process Technology \nl  IC Packaging and Testing \nl  IP and IC Design Services \nl  Capital and Entrepreneurship \nl  Guangzhou IC Innovation and Entrepreneurship Forum \n\nChina IC Design Industry Exhibition\nIX. Participants\n\nThe relevant authorities and local leaders\, relevant domestic and foreign experts\, representatives from local bases and industry associations\, IC design companies\, IP service vendors\, EDA vendors\, foundry companies\, packaging testing vendors\, system vendors and venture capital firms at home and abroad\, representatives from IC industries Parks and related media. \n\n Contacts\n\nContact:Shirley Hu \nTel: 18917192814\, E-mail: shirleyhp@cicmag.com \nContact:Yuanyuan Wang \nTel:18600095161\, E-mail: wangyy@csia-iccad.net.cn \n\nThe organizers of the annual conference are required to conscientiously and carefully organize and prepare for the conference and ensure a complete success. \nAnnex: Registration Form
URL:https://marketingeda.com/event/csia-iccad-2022/
LOCATION:Xiamen International Convention Center\, 198 Exhibition Road\, Xiamen City\, China
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CSIA-ICCAD-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221220T100000
DTEND;TZID=America/Los_Angeles:20221220T110000
DTSTAMP:20221212T220742Z
CREATED:20221212T220611Z
LAST-MODIFIED:20221212T220742Z
UID:5498-1671530400-1671534000@marketingeda.com
SUMMARY:Using Formal Datapath Validation to Verify AI Processor Computations
DESCRIPTION:For over a decade\, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs\, AI processors are also datapath heavy with mathematical functions like addition\, subtraction\, matrix multiplication\, and square root in its compute engines\, making these designs a good fit for formal datapath validation. \nThis webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions. The Synopsys ARC NPX6 processor supports the latest and most complex neural networks\, such as CNN\, RNN\, and transformers\, targeted for AI SoCs that are widely used in automotive\, data center\, high end gaming\, next generation augmented reality\, and surveillance. At the heart of the NPX6 neural network processor are convolution and tensor accelerators that are optimized to perform light speed computations. Correctness of these functional units are key to correct facial\, audio\, image processing and recognition which could have safety implications for automotive applications. We will explore Synopsys VC Formal DPV\, the gold standard for datapath validation and signoff for the last 20 years\, and how it is used to ensure correctness of the core algorithms of the ARC NPX6 processor’s compute engines. \n\n\n\nSpeakers\n\n\n\nNeelabja Dutta\nSr. Manager\, Applications Engineering\nSynopsys\n\n\n\n\n\nShuaiyu Jiang\nSr. ASIC Digital Design Engineer\nSynopsys
URL:https://marketingeda.com/event/using-formal-datapath-validation-to-verify-ai-processor-computations/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-December-20-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221215T080000
DTEND;TZID=America/Los_Angeles:20221215T170000
DTSTAMP:20221130T191032Z
CREATED:20221130T191032Z
LAST-MODIFIED:20221130T191032Z
UID:5487-1671091200-1671123600@marketingeda.com
SUMMARY:CHIPS Alliance\, Fall Technology Update
DESCRIPTION:Join us in-person for our second biannual technology update featuring informative\, technical talks on open source hardware collaborative development\, hosted by Google and including speakers from Microsoft\, Google\, Intel\, Antmicro\, Efabless and others. \nCHIPS’ Thursday event follows the main RISC-V Summit days (Tuesday-Wednesday) to allow easy participation for open source hardware professionals traveling to the Bay Area for the Summit\, and is free to attend (registration required).
URL:https://marketingeda.com/event/chips-alliance-fall-technology-update/
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CHIPS-Alliance-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221213T080000
DTEND;TZID=America/Los_Angeles:20221214T170000
DTSTAMP:20221202T202132Z
CREATED:20220926T163457Z
LAST-MODIFIED:20221202T202132Z
UID:5232-1670918400-1671037200@marketingeda.com
SUMMARY:RISC-V Summit
DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance the most prolific open\, license and royalty-free computing architecture. They share technical investment and help shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from the open intellectual property contributed by RISC-V. \nThis December\, the RISC-V community – including the technical\, industry\, domain and special interest groups who define the architecture’s specifications – will be in San Jose\, California for four days of technology breakthroughs\, industry milestones\, tutorials\, and relationship building.  \n\n\n\n\nIt all kicks off with a RISC-V Member Day where technical and industry working groups meet in person\, running alongside a new RISC-V FutureWatch track featuring breaking news of products\, technologies\, ecosystem expansion\, and more.\nThen it’s the centerpiece of the week: Our Summit featuring two days of compelling technical and industry keynotes and conference sessions\, paired with a showfloor of the latest community innovations.\nThe week wraps up with a full day of information-rich tutorials.\n\n\n\n\nThe community-curated content you’ll experience is unparalleled. \nAutomotive. High-performance Computing. Data Centers. ML and AI. Security. Software Stacks. Development Tools. Systems on a Chip. It’s all here. And it’s all new. \nBreak new ground. Define the future. Grow your network. Build your expertise. Meet your heroes. It’s all during RISC-V Summit North America\, this December in San Jose.
URL:https://marketingeda.com/event/risc-v-summit/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221207T100000
DTEND;TZID=America/Los_Angeles:20221207T110000
DTSTAMP:20221115T190148Z
CREATED:20221115T190148Z
LAST-MODIFIED:20221115T190148Z
UID:5400-1670407200-1670410800@marketingeda.com
SUMMARY:Successful Management of Semiconductor Intellectual Property
DESCRIPTION:Do you develop\, procure or distribute semiconductor intellectual property (IP) within your enterprise? If so\, how is the IP managed? In this 30 minute presentation\, we will show you a solution\, which has been adopted by large institutions\, by creating a catalog of all your IP and aid you through the process of publishing the IP and sharing it across the enterprise. \nWhat you will learn: \nWhat IP Designers learn: \nHow to create or update\, release & notify IP and designs with complete control & management. \nWhat will System IntegrationTeams learn: \nHow to receive notifications of updated IP and designs to help guide selection\, updates and integration. \nWhat will managers learn: \nHow to review changes\, analyze conflicts\, and approve releases – easily.
URL:https://marketingeda.com/event/successful-management-of-semiconductor-intellectual-property/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Cliosoft-December-7-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221205T080000
DTEND;TZID=Europe/Berlin:20221205T203000
DTSTAMP:20221116T201152Z
CREATED:20221116T201152Z
LAST-MODIFIED:20221116T201152Z
UID:5407-1670227200-1670272200@marketingeda.com
SUMMARY:The 26262 Club - Technical Conference
DESCRIPTION:MEET US AT THE 26262 CLUB TECHNICAL CONFERENCE THIS COMING DECEMBER 5\, 2022\nIn this edition\, the 26262 club continues the discussion on the anticipated third edition and the emerging role of ISO 26262 within the evolving standards ecosystem. We bring on stage key global players from WG8 alongside authors of the most prominent upcoming standards and share must-have insights from the global standardisation community. Goal of the day is to facilitate collaboration and open discussion between different groups and practitioners and present applicable case studies and lessons learnt to take back with you. \nWHO WILL YOU MEET\nThe expert speaker line up includes 20 international experts from the ISO 26262 WGs and international members of Germany\, UK\, France\, Italy\, Austria\, USA – together we welcome experts from WGs of SOTIF\, IEEE\, Accellera\, ISO 21434 among other. Presenting companies include OEMS\, Tier 1s\, Semiconductor and notable solution providers. Meet our expert speaker panel here.
URL:https://marketingeda.com/event/the-26262-club-technical-conference/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/The-26262-Club.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20221129T080000
DTEND;TZID=Asia/Jerusalem:20221129T170000
DTSTAMP:20221107T193748Z
CREATED:20221107T193748Z
LAST-MODIFIED:20221107T193748Z
UID:5383-1669708800-1669741200@marketingeda.com
SUMMARY:SEMISRAEL Expo 2022
DESCRIPTION:SemIsrael Expo 2022 is the premier professional semiconductor event in Israel. \nThe event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. \nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities. \n\nThe event will be hosted at Avenue Convention and Events Center on November 29\, 2022. \nSemIsrael Expo events are produced by SemIsrael – The Israeli Semiconductor Portal.
URL:https://marketingeda.com/event/semisrael-expo-2022/
LOCATION:Avenue Convention Center\, Airport City\, Israel
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMISRAEL-Expo-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221129T080000
DTEND;TZID=America/Los_Angeles:20221129T120000
DTSTAMP:20221011T180112Z
CREATED:20221011T180041Z
LAST-MODIFIED:20221011T180112Z
UID:5291-1669708800-1669723200@marketingeda.com
SUMMARY:Memory Technology Symposium
DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \nWhy attend?\nThe Synopsys Memory Technology Symposium\, a first-of-its-kind virtual event dedicated to memory design and development\, aims to provide a forum for leading Memory\, IP\, SoC Companies and Synopsys experts to share their perspectives on the industry’s most compelling and topical challenges across four themes: Design Technology Co-optimization (DTCO)\, Design Shift Left\, IP\, and Silicon Reliability. Register to learn more!​
URL:https://marketingeda.com/event/memory-technology-symposium/
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Screen-Shot-2022-10-11-at-10.57.56-AM.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221121T080000
DTEND;TZID=Europe/Berlin:20221122T170000
DTSTAMP:20221117T181728Z
CREATED:20221117T181728Z
LAST-MODIFIED:20221117T181728Z
UID:5419-1669017600-1669136400@marketingeda.com
SUMMARY:CadenceLIVE Europe 2022
DESCRIPTION:CadenceLIVE Europe 2022 will be held on November 21-22 at the Hilton Munich Park hotel. It will feature peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees will have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \nKeynote Speakers\n\n\n\n\n\n\nTom Beckley\nSenior Vice President and General Manager\, Custom IC & PCB Group\nCadence Design Systems \n\n\n\n\n\n\nDr. Oliver Wolst\nSenior Vice President\, Automotive Semiconductor Integrated Circuits\nRobert Bosch GmbH
URL:https://marketingeda.com/event/cadencelive-europe-2022/
LOCATION:Hilton Munich Park\, Am Tucherpark 7\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221116T090000
DTEND;TZID=America/New_York:20221116T140000
DTSTAMP:20221025T170717Z
CREATED:20221025T170717Z
LAST-MODIFIED:20221025T170717Z
UID:5332-1668589200-1668607200@marketingeda.com
SUMMARY:ASIP University Day 2022
DESCRIPTION:Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. Synopsys’ ASIP Designer is the market leading tool for ASIP design\, verification and programming\, and is used by leading companies around the globe with hundreds of successful projects to date. \nPlease join us at the ASIP University Day virtual event on Wednesday\, November 16\, 2022. In this informal forum you will be able to exchange ideas\, build up networks and gain first-hand insight about ASIP Designer directly from your peers. \n\nSynopsys will share its insight into market trends\, and provide a technical update on ASIP Designer along with reference examples. In addition\, several university partners will present results from their ASIP Design projects.
URL:https://marketingeda.com/event/asip-university-day-2022/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221116T090000
DTEND;TZID=America/Los_Angeles:20221116T100000
DTSTAMP:20221103T212350Z
CREATED:20221103T212350Z
LAST-MODIFIED:20221103T212350Z
UID:5370-1668589200-1668592800@marketingeda.com
SUMMARY:The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
DESCRIPTION:As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law\, it has created new challenges. \nJoin us on Wednesday\, November 16 at 9:00 a.m. PST for an informative webinar on The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging \nHear 3 unique perspectives on this growing market:\n\n\nStefan Chitoraga\, Technology and Market Analyst at Yole Développement will present the latest market insights on the adoption of chiplets and heterogeneous integration and will address what is driving advanced packaging toward 2.5D and 3D solutions.\nIgor Elkanovich\, CTO at Global Unichip Corp. (GUC) will discuss the GUC GLink™ chiplet interconnect\, including its architecture and roadmap; HBM3 memory interfaces; and will also highlight some of the 2.5D and 3D packaging challenges.\nNir Sever\, Senior Director of Business Development at proteanTecs will reveal silicon results from a GUC GLink chip\, which used D2D interconnect monitoring for comprehensive visibility and parametric lane grading.
URL:https://marketingeda.com/event/the-era-of-chiplets-and-heterogeneous-integration-challenges-and-emerging-solutions-to-support-2-5d-and-3d-advanced-packaging/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteantecs-november-16-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221115T080000
DTEND;TZID=Europe/Berlin:20221118T170000
DTSTAMP:20221017T181636Z
CREATED:20221017T181636Z
LAST-MODIFIED:20221017T181636Z
UID:5312-1668499200-1668790800@marketingeda.com
SUMMARY:Semicon Europa
DESCRIPTION:SEMICON Europa 2022 is co-located with electronica in Munich\, Germany creating the strongest single event for electronics manufacturing in Europe\, and broadening the range of attendees across the electronics chain. \n– Top-notch Keynotes\n– Market Trends\n– Exhibition\n– Networking\n– Advanced Packaging Forum / Fab Management Forum\n– ITF Beyond 5G -powered by imec\n– Smart Manufacturing / Mobility / MedTech\n– Workforce Development and many more!
URL:https://marketingeda.com/event/semicon-europa/
LOCATION:Messe Munchen\, Messegelände\, Munich\, 81823\, Germany
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DB580CC6-16B1-4DBA-A5A3-38C39181F164-e1666030379723.jpeg
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BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20221113T080000
DTEND;TZID=America/Chicago:20221118T170000
DTSTAMP:20221102T200714Z
CREATED:20221102T200714Z
LAST-MODIFIED:20221102T200714Z
UID:5362-1668326400-1668790800@marketingeda.com
SUMMARY:Super Computing 2022
DESCRIPTION:Come see your friends and colleagues\, explore incredible learning experiences in HPC\, and walk the exhibit floor! There are several registration options available. Choose the one that’s right for you. We look forward to seeing you in Dallas or via the Digital Experience.
URL:https://marketingeda.com/event/super-computing-2022/
LOCATION:Kay Bailey Hutchison Convention Center\, 650 S Griffin Street\, Dallas\, TX\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SC22.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Amsterdam:20221108T090000
DTEND;TZID=Europe/Amsterdam:20221108T180000
DTSTAMP:20221104T201045Z
CREATED:20221104T201045Z
LAST-MODIFIED:20221104T201045Z
UID:5373-1667898000-1667930400@marketingeda.com
SUMMARY:TSMC 2022 EU OIP Ecosystem Forum
DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum!
URL:https://marketingeda.com/event/tsmc-2022-eu-oip-ecosystem-forum/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2022-EU.jpg
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END:VCALENDAR