BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Madrid BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Stockholm BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20230312T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20231105T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20240310T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20241103T070000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:20250309T080000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:20251102T070000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/New_York:20241113T090000 DTEND;TZID=America/New_York:20241113T100000 DTSTAMP:20241016T181319Z CREATED:20241016T181319Z LAST-MODIFIED:20241016T181319Z UID:8422-1731488400-1731492000@marketingeda.com SUMMARY:ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer DESCRIPTION:The AI revolution and other application domains\, like data centers\, advanced wireless communications\, image and video processing\, automated driving assistance\, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). \nASIPs have become a mainstream implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. This growth has driven many university projects and increased interest in initiatives like RISC-V\, which has significantly expanded beyond UC Berkeley. \n\nWhy Attend? \nYou will hear from leading university teams about their ASIP design project results across various application domains. Additionally\, Synopsys will provide a technical update on ASIP Designer with reference examples. \nThis event offers a great opportunity to exchange ideas\, build networks\, and gain valuable insights from university partners. \nDon’t miss out – register now to secure your spot! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/asip-university-day-2024-domain-specific-processor-design-using-asip-designer/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T080000 DTEND;TZID=America/Los_Angeles:20241114T170000 DTSTAMP:20241030T174154Z CREATED:20241030T174154Z LAST-MODIFIED:20241030T174154Z UID:8463-1731398400-1731603600@marketingeda.com SUMMARY:IEEE World Technology Summit - AI INFRASTRUCTURE DESCRIPTION:This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems\, focusing on these core areas: \n\nAI applications and their required infrastructure\nSilicon to support AI applications\nSystems to support AI applications\nSecurity and Standards\n\nAI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit\, where companies\, governments\, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions. \nThe main focus of this conference is AI Infrastructure. \nTo deliver value we need the infrastructure for AI to work!!! This infrastructure includes software\, data storage\, computing\, communications\, power and energy\, standards\, and security. \nTo form an event to address the above issues\, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns\, challenges\, solutions\, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI\, which is critical to make AI work. \nCompanies are invited to sponsor\, engage\, and have employees attend this event. \nIf interested\, contact us at: wtscontact@ieee.org \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ieee-world-technology-summit-ai-infrastructure/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/WTS-November-12-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20241023T171101Z CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20240805T221745Z CREATED:20240805T221455Z LAST-MODIFIED:20240805T221745Z UID:8202-1729584000-1729702800@marketingeda.com SUMMARY:RISC-V Summit - North America 2024 DESCRIPTION:RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped\, powering new innovations in AI/ML\, wireless\, automotive. data center\, space\, IoT\, embedded and more. Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy a new level of design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis October\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies\, as well as to network and build relationships. Come be part of the RISC-V movement. \n\n\n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo featuring dozens of community members showcasing their the latest solutions.\n\nIt’s community-curated content\, research and innovation driving the next wave of growth for RISC-V. \nLearn about software\, systems\, development tools\, security\, the latest use cases in key markets and more. It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-summit-north-america-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-US-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20241014T214312Z CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20241008T164139Z CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20241014T202014Z CREATED:20241014T202014Z LAST-MODIFIED:20241014T202014Z UID:8413-1728979200-1729184400@marketingeda.com SUMMARY:2024 OCP Global Summit DESCRIPTION:The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights\, foster partnerships and showcase cutting-edge advancements in open hardware and software. \nThe 2024 OCP Global Summit theme is “From Ideas to Impact”. This encapsulates the transformative journey at the heart of the Open Compute Project. This year’s theme reflects OCP’s commitment to fostering innovation that transcends theoretical discussions and manifests into real-world solutions. As the pace of technological evolution accelerates and development cycles shorten\, our industry is forced to rapidly respond to emerging trends and needs. By harnessing the collective expertise of our global community\, we turn visionary ideas into groundbreaking technologies that drive openness\, efficiency\, sustainability\, scalability and growth in the data center industry. Our focus honors the relentless pursuit of progress and the profound impact that OCP’s community-driven innovation can achieve. OCP transforms concepts into impactful advancements. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ocp-global-summit/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-OCP-Global-Summit.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20241008T080000 DTEND;TZID=Europe/Madrid:20241010T170000 DTSTAMP:20240923T170650Z CREATED:20240923T170650Z LAST-MODIFIED:20240923T170650Z UID:8345-1728374400-1728579600@marketingeda.com SUMMARY:AutoSens Europe 2024 DESCRIPTION:Join us as we embark on an exciting new journey in the vibrant city of Barcelona!\n\n\n\n\nFrom 8-10 October 2024\, we will unite the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV. \nExpect over 60 expert speakers\, engaging panels\, technical case studies\, and exploration of 12 key themes. Dive into an exhibition with cutting-edge demos from sensor and computer vision leaders. \nDon’t miss AutoSens Europe 2024 in Barcelona – the future of sensing tech awaits! \n\n\nDiscover the latest technology\n\n\n\n\nFrom innovative start-ups to industry giants\, the AutoSens exhibition floor is where our community comes together to make key connections over coffee\, have critical conversations in our igloo meeting pods\, and negotiate new partnerships over drinks at our networking sessions. \nRegister now to make the most of:\n\n\n\nAccess to an expert community of over 500 experts and engineers \n\n\n\n\n\nExtensive exhibition with over 50 stands showcasing the latest technology\n\n\n\n\n\n\n\nVehicle demos from leading Tier 1 and systems companies\n\n\n\n\n\n\n\nHigh quality technical presentations from genuine experts\n\n\n\n\n\n\n\nThought-leader panel discussions that shape the industry’s future direction\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/autosens-europe-2024/ LOCATION:Palau de Congressos\, Av. de la Reina Maria Cristina\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AutoSense-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241002T090000 DTEND;TZID=America/Los_Angeles:20241002T100000 DTSTAMP:20240906T215750Z CREATED:20240906T215750Z LAST-MODIFIED:20240906T215750Z UID:8307-1727859600-1727863200@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI - Session 2 DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nThe CPU Cluster on Wednesday\, Oct 2\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nAn overview of Arm’s most performant\, efficient\, and versatile CPU cluster based on the Armv9 architecture for maximum performance and power efficiency.\nFeatures\, benefits\, and performance enhancements of Arm Cortex-X925\, Cortex-A725 CPU\, Cortex-A520 CPU and Arm DSU-120.\nHow this CPU cluster can improve consumer experiences on mobile devices.\n\nSpeaker: Manish Pandey\, Senior Product Manager\, Arm \nFirst Session – September 18th \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai-session-2/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20241002T080000 DTEND;TZID=Asia/Taipei:20241002T170000 DTSTAMP:20240826T192110Z CREATED:20240826T192110Z LAST-MODIFIED:20240826T192110Z UID:8276-1727856000-1727888400@marketingeda.com SUMMARY:Memory Users Conference 2024 - China\, Taiwan DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024-china-taiwan/ CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T080000 DTEND;TZID=America/Los_Angeles:20241001T120000 DTSTAMP:20240826T192125Z CREATED:20240826T191744Z LAST-MODIFIED:20240826T192125Z UID:8273-1727769600-1727784000@marketingeda.com SUMMARY:Memory Users Conference 2024 DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \n  \nWhy Attend?\nMemory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth\, high performance memories driven by AI applications. \nThese next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated\, and some new ones have been introduced. \nThe Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more \n\n\n\n\n\nAgenda At-a-Glance\n\n\nLearn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily\, so be sure to check back often for new information. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTime\nTopic\n\n\n08:00 am\nOpening Keynote\n\n\n08:30 am\nAccelerating the Path from Technology Development to High-Volume Manufacturing\nwith participation of Western Digital\n\n\n09:00 am\n\n\n09:30 am\nSolving “Unsolvable Problems” in Memory Design & Verification\nwith participation of Samsung\n\n\n10:00 am\n\n\n\n10 Minute Break\n\n\n10:40 am\nAccelerating SoC Development with Memory IP\nwith participation of STMicroelectronics and Weebit Nano\n\n\n11:10 am\n\n\n11:40 am\nEnsuring Memory Reliability for Mission Critical Applications\n\n\n12:10 pm\n\n\n12:40 pm\nIndustry Panel\n\n\n\n\nVirtual Event \n\nOctober 1st\, 8:00AM PST\nOctober 2nd\, 8:00AM GMT +8\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/memory-users-conference-2024/ CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240925T093000 DTEND;TZID=America/Los_Angeles:20240925T180000 DTSTAMP:20240917T003907Z CREATED:20240917T003541Z LAST-MODIFIED:20240917T003907Z UID:8337-1727256600-1727287200@marketingeda.com SUMMARY:TSMC North America OIP Ecosystem Forum 2024 DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for A16\, N2 and N3 processes\nLatest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes\, InFO\, CoWoS®\, and SoIC\, 3DFabric Alliance\, and 3Dblox™ standard\, plus innovative 3Dblox-based design enablement technologies and solutions\, targeting HPC\, AI/ML\, and mobile applications\nComprehensive design solutions for specialty technologies enabling ultra-low power\, ultra-low voltage\, analog migration\, RF\, mmWave\, and automotive designs targeting 5G\, automotive\, and IoT designs\nEcosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization\nSuccessful\, real-life applications of design technologies\, IP solutions\, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC OIP Ecosystem Forum! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-north-america-oip-ecosystem-forum-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,Forum,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T090000 DTEND;TZID=America/Los_Angeles:20240918T100000 DTSTAMP:20240906T215837Z CREATED:20240906T215234Z LAST-MODIFIED:20240906T215837Z UID:8304-1726650000-1726653600@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240917T080000 DTEND;TZID=Asia/Tokyo:20240917T170000 DTSTAMP:20240823T182503Z CREATED:20240823T182145Z LAST-MODIFIED:20240823T182503Z UID:8269-1726560000-1726592400@marketingeda.com SUMMARY:IP-SoC Japan 24 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-japan-24/ LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Stockholm:20240913T080000 DTEND;TZID=Europe/Stockholm:20240915T170000 DTSTAMP:20240717T214406Z CREATED:20240717T214315Z LAST-MODIFIED:20240717T214406Z UID:8159-1726214400-1726419600@marketingeda.com SUMMARY:ORConf 2024 DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/orconf-2024/ LOCATION:Gothenburg\, Gothenburg\, Sweden CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DTSTAMP:20240823T181126Z CREATED:20240823T181114Z LAST-MODIFIED:20240823T181126Z UID:8265-1726142400-1726146000@marketingeda.com SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240813T193558Z CREATED:20240813T193538Z LAST-MODIFIED:20240813T193558Z UID:8234-1726135200-1726138800@marketingeda.com SUMMARY:Addressing 3D-IC Power Integrity Design Challenges DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240912T080000 DTEND;TZID=Asia/Shanghai:20240912T170000 DTSTAMP:20240605T173645Z CREATED:20240605T173645Z LAST-MODIFIED:20240605T173645Z UID:8079-1726128000-1726160400@marketingeda.com SUMMARY:D&R IP-SoC China 2024 Day DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/ LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Chicago:20240912T080000 DTEND;TZID=America/Chicago:20240912T170000 DTSTAMP:20240409T162326Z CREATED:20240409T162326Z LAST-MODIFIED:20240409T162326Z UID:7817-1726128000-1726160400@marketingeda.com SUMMARY:Verification Futures Conference 2024 Austin DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \nWe have the first speaker details on CPU User Presentations \nAccelerating RISC-V testbench development with open source RISC-V RTL and emulation\n– Varun Koyyalagunta\, Design Verification Engineer\, Tenstorrent\nToday’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also\, we should have all test collaterals ready to go\, which involves firmware\, drivers\, applications etc. \nAt Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface\, AXI\, standard instruction interface\, RISC-V Formal Interface (RVFI)\, and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready\, we could be able to replace our custom CPU RTL with open source CVA-6 processor. \nThis methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this\, we could able to innovate in the area of test collateral creation\, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL. \n3 Key Points  \n·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP \n·       Emulation is a must for software development and function verification \n·       How do we keep DV out of the critical path? \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nPresentation Title Hemendra Talesara (Company Name)\n\n\n\n\n10:15\nUser Top Verification Challenges\n\n\n\n\n10:15\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nCPU User Presentations\n\n\n\n\n11:30\nPresentation Title Mike Thompson (OpenHW Group)\n\n\n\n\n11:50\nAccelerating RISC-V testbench development development with open source RISC-V RTL and emulation \nVarun Koyyalagunta(Tenstorrent)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n14:00\nPresentation Title Speaker Name (Company Name) Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 4 – VHDL Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:30\nEvent Closes\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verification-futures-conference-2024-austin/ LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Verification-Futures-2024-Austin.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240911T080000 DTEND;TZID=America/Los_Angeles:20240911T090000 DTSTAMP:20240821T163437Z CREATED:20240821T163437Z LAST-MODIFIED:20240821T163437Z UID:8259-1726041600-1726045200@marketingeda.com SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240910T090000 DTEND;TZID=America/Los_Angeles:20240910T100000 DTSTAMP:20240820T162341Z CREATED:20240820T162341Z LAST-MODIFIED:20240820T162341Z UID:8252-1725958800-1725962400@marketingeda.com SUMMARY:Can AI make cameras see in the dark? DESCRIPTION:Abstract\n  \n\nAs cameras become ubiquitous in applications such as surveillance\, mobile\, drones\, and automotive systems\, achieving clear vision 24/7 under any condition—including extreme low light and high dynamic range scenarios—has become essential. By leveraging Edge AI processors\, a software ISP based on neural network technology can process and optimize video in real-time\, surpassing human vision capabilities in these challenging conditions.\nIn this webinar\, we will explore how to harness the power of Ceva’s NPU alongside Visionary.ai’s advanced AI software Image Signal Processing (ISP) to significantly enhance video quality across various camera-enabled applications. Visionary.ai utilizes Neural Processing Units (NPUs) to boost camera performance\, especially in demanding environments like extreme low-light and high dynamic range (HDR) scenarios.\nFinally\, we will introduce an available reference design for this joint solution and showcase the impressive results achieved. \nJoin Ceva and Visionary.ai experts to learn about: \n\nThe power of Edge AI for computer vision\nModern NPU architecture fundamentals\nTrue Night Vision software ISP\nThe role of video denoising in solving the low-light challenge\nThe technical challenges to implement an AI based ISP on an NPU\nHow can Ceva and Visionary.ai enhance your camera enabled application\n\n\nTarget Audience\n  \nVision system architects\, hardware and software engineers\, and product managers targeting camera enabled devices\, that are looking to enhance their product ability to cope with extreme low-light conditions using the power of Edge AI.\n\nSpeakers\n\n\n\n\n\n\n\nRonny Vatelmacher\nDirector of Product Marketing\, Vision and AI\, Ceva\n\n\n\n\n\n\n\n\n\nDavid Jarmon\nSVP Worldwide Sales\, Visionary.ai\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/can-ai-make-cameras-see-in-the-dark/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ceva-September-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240909T080000 DTEND;TZID=America/Los_Angeles:20240912T170000 DTSTAMP:20240718T193601Z CREATED:20240718T193601Z LAST-MODIFIED:20240718T193601Z UID:8164-1725868800-1726160400@marketingeda.com SUMMARY:AI Hardware & Edge AI Summit 2024 DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/ LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240905T090000 DTEND;TZID=America/Los_Angeles:20240905T183000 DTSTAMP:20240711T225247Z CREATED:20240711T225247Z LAST-MODIFIED:20240711T225247Z UID:8138-1725526800-1725561000@marketingeda.com SUMMARY:Synopsys Processor IP Summit 2024: RISC-V\, DSP and NPU IP for Your Diverse SoC Processing Needs DESCRIPTION:As electronic systems continue to become more complex and integrate greater functionality\, SoC developers are faced with the challenge of developing more powerful\, yet more energy-efficient devices. The processors used in these applications must be efficient to deliver high levels of performance within limited power and silicon area budgets. \n  \nWhy Attend?\nJoin us for the Processor IP Summit to get in-depth information from industry leaders on the latest in ARC-V™ RISC-V processor IP\, ARC® VPX DSP IP and ARC NPX NPU IP along with related hardware/software technologies that enable you to achieve PPA differentiation in your chip or system design. Synopsys experts\, partners\, and our processor IP user community will discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, software development and more. Sessions will be followed by a networking reception where you can see live demos. \n  \nWho Should Attend?\nWhether you are a developer of chips\, systems or software\, the Synopsys Processor IP Summit will give you practical information to help you create more differentiated products in the shortest amount of time. \n  \nAgenda\nAgenda is coming soon \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-processor-ip-summit-2024-risc-v-dsp-and-npu-ip-for-your-diverse-soc-processing-needs/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240904T090000 DTEND;TZID=America/Los_Angeles:20240904T100000 DTSTAMP:20240806T194128Z CREATED:20240806T194128Z LAST-MODIFIED:20240806T194128Z UID:8205-1725440400-1725444000@marketingeda.com SUMMARY:Elevate Your Analog Layout Design to New Heights DESCRIPTION:Are you ready to transform your career and become a master of analog layout design? Look no further than The Advanced Analog Layout Course! This course is meticulously crafted to enhance your physical design skills\, guiding you through the advanced techniques essential for creating top-notch\, well-matched\, and noise-resistant layouts on a CMOS process. \nLearn Anytime\, Anywhere! Our course is delivered through a user-friendly online portal\, granting you the power to learn at your own pace. Enjoy the flexibility of completing modules and watching nearly 100 instructional videos whenever it suits you best. \nTailored for Excellence! Whether you’re a seasoned layout engineer aiming to refine your skills or a front-end schematic designer eager to enhance your design methods\, this course is designed for you. With over 19 hours of content\, including seven comprehensive modules and regular assessments\, you’ll be equipped to produce more efficient and superior quality layouts. \nComprehensive Learning Experience! Dive into a wealth of knowledge with our extensive video library\, totalling over 19 hours of expert content. Our regular assessments ensure that you’re on track\, solidifying your understanding and boosting your confidence. \nJoin the ranks of the industry’s best and make your mark in the world of analog layout design. Enroll in The Advanced Analog Layout Course today and start your journey to becoming an analog layout virtuoso! \nReady to take the next step in your career? Join this webinar to learn more and sign up for the course that will set you apart in the competitive field of analog layout design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/elevate-your-analog-layout-design-to-new-heights/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IC-Mask-Design-September-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240829T080000 DTEND;TZID=America/Los_Angeles:20240829T170000 DTSTAMP:20240729T162620Z CREATED:20240729T162620Z LAST-MODIFIED:20240729T162620Z UID:8188-1724918400-1724950800@marketingeda.com SUMMARY:GlobalFoundries Technology Summit 2024 - North America DESCRIPTION:The annual GTS conference brings GF executives and technologists together with customers and partners to discuss the latest breakthroughs and innovations in the semiconductor industry. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/globalfoundries-technology-summit-2024-north-america/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GlobalFoundries-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240827T090000 DTEND;TZID=America/Los_Angeles:20240827T170000 DTSTAMP:20240827T162200Z CREATED:20240827T162200Z LAST-MODIFIED:20240827T162200Z UID:8279-1724749200-1724778000@marketingeda.com SUMMARY:Q3 Memory Fabric Forum DESCRIPTION:Memory fabrics unlock the power to pool\, tier\, and share memory in a data center fabric. The results will be vastly more memory capacity and lower cost due to higher utilization—the things needed to support memory-hungry generative AI apps. \n  \nAttend this webinar for a comprehensive update on CXL® market adoption\, technology\, products\, and use cases. \n\nRegister to attend and/or watch on YouTube after the event. \n  \nPart 1 – Industry Landscape. Highlighted by the presentation at 9:10 PT by Samsung of a “Moonshot” project to leapfrog from 10\,000 AI cluster nodes to 1\,000\,000 nodes. \nPart 2 – Technologies and products for the Enterprise. Highlighted by an overview from NVIDIA at 12:09 PT of their portfolio of high-bandwidth\, low-latency networking products for AI. \nPart 3 – Technologies and products for developers. Highlighted by new CXL forecast data presented by Montage at 1:26 PT. \n  \nBest\, Frank Berry\, VP of Marketing at MemVerge.\n\n\n \n\n\n\n\n\n \n\n\nQ3 Memory Fabric Forum Agenda \nRegister to attend\n\n\n \n\n\n\n\n\n\nIndustry Landscape\n\n\n1\n9:00 PT\nFrank Berry\nMemVerge\nThe AI Big Bang\n\n\n2\n9:10 PT\nSiamak Tavallaei\nSamsung\nAt-scale Systems: Interconnecting Massively Parallel xPUs\n\n\n3\n9:41 PT\nKurtis Bowman\nCXL Consortium\nCXL® Advancing Coherent Connectivity\n\n\n4\n9:53 PT\nJim Handy\nObjective Analysis\nCXL Is Exciting\, But Where is It Headed?\n\n\n5\n10:16 PT\nMark Nossokoff\nHyperion Research\nHPC/AI Market Update and Industry Composability Snapshot\n\n\n6\n10:32 PT\nJack Gidding\nSTAC Research\nSTAC Overview\n\n\n7\n10:46 PT\nSeth Friedman\nLiquid Markets\nLiquid-Markets-Solutions: Introduction to UberNIC\n\n\nTechnology and Products for the Enterprise\n\n\n8\n11:10 PT\nAnil Godbole\nIntel\nIntel Compute Express Link™ Enablement\n\n\n9\n11:25 PT\nMichael Abraham\nMicron\nCXL-Compatible Memory Modules\n\n\n10\n11:45 PT\nTorry Steed\nSMART Modular\nCXL Memory Expansion Advantages\n\n\n11\n12:09 PT\nReggie Reynolds\nNVIDIA\nNVIDIA Networking for HPC\, AI\, and Accelerated IO\n\n\n12\n12:41 PT\nSteve Scargall\nMemVerge\nMemory Machine™ for CXL\n\n\n13\n1:00 PT\nPhilip Maher\nMSI\nS2301 CXL Memory Expansion Server\n\n\nTechnology and Products for the Enterprise\n\n\n14\n1:08 PT\nMichael Ocampo\nAstera Labs\nAccelerating AI & ML with CXL-Attached Memory\n\n\n15\n1:26 PT\nGeof Findley\nMontage\nCXL 2.0 Use Case: Using Both DDR4 & DDR5 on the Same Server\n\n\n16\n1:43 PT\nJP Jiang\nXConn\nCXL Switch for Scalable & Composable Memory Pooling/Sharing\n\n\n17\n2:05 PT\nGary Ruggles\nSynopsys\nEnabling New Memory Applications Using CXL IP\n\n\n18\n2:37 PT\nNilesh Shah\nZeroPoint\nHyperscale Composable Memory Systems with Dynamically Adjusting Compressed Tier\n\n\n19\n3:00 PT\nGrant Mackey\nJackrabbit Labs\nYou Don’t Know Jack: CXL Fabric Orchestration and Management\n\n\n20\n3:19 PT\nBill Gervasi\nWolley\nNVMe Over CXL: How CXL Lets Us Do Controller Memory Buffers the Right Way\n\n\n21\n3:39 PT\nBill Gervasi\nWolley\nFleX: Bringing CXL to the Motherboard\n\n\n22\n3:59 PT\nBill Gervasi\nWolley\nCXL Native Memory: Do We Really Need DDR?\n\n\n23\n4:20 PT\nArvind Jagannath\nVMware\nVMware Memory Tiering: Customer-Ready Today\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/q3-memory-fabric-forum/ CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Q3-Memory-Fabric-Forum.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240825T080000 DTEND;TZID=America/Los_Angeles:20240827T170000 DTSTAMP:20240712T004207Z CREATED:20240712T004207Z LAST-MODIFIED:20240712T004207Z UID:8141-1724572800-1724778000@marketingeda.com SUMMARY:Hot Chips 2024 DESCRIPTION:Hot Chips 2024 will be held as a hybrid conference with in-person attendance at Memorial Auditorium\, Stanford University from August 25 to 27\, 2024. \nConference Format\nHot Chips 2024 is a hybrid conference. You may register to attend Virtually or In-Person. The In-Person conference is held at Memorial Auditorium\, Stanford University. \n\nTutorials: Sunday\, August 25\nConference: Monday-Tuesday\, August 26-27\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs\, and Slack channels for BOTH tutorial and conference days. All talks are transmitted in real time and are also recorded so they may be viewed later. Details are here. \nIn-Person Conference: Includes all on-line access described above for the Virtual Conference. In addition\, In-Person registration includes breakfast\, lunch\, break snacks and receptions on Sunday and Monday evenings. \nIn-Person registrations options: \n\nConference Days only (includes Sunday evening reception)\nBoth Conference and Tutorial Days\n\nThere is no registration option for the Tutorial Day only nor for single session attendance. \nRegistration Deadlines\nEarly Registration Deadline: 11:59 PM (PDT) Friday\, August 02\, 2024. \nPlease Read: General Registration Policies. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hot-chips-2024/ LOCATION:Memorial Auditorium\, 551 Jane Stanford Way\, Stanford\, CA\, 94305\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/1681617277049-HC-Logo-Trasparent.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20240822T080000 DTEND;TZID=Asia/Taipei:20240822T170000 DTSTAMP:20240821T171827Z CREATED:20240821T171827Z LAST-MODIFIED:20240821T171827Z UID:8262-1724313600-1724346000@marketingeda.com SUMMARY:CadenceCONNECT Taiwan 2024 DESCRIPTION:CadenceCONNECT Taiwan event will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users\, developers\, and industry experts for networking\, sharing best practices on critical design and verification issues and discovering new techniques for designing advanced silicon\, SoCs\, and systems. Don’t miss this opportunity to learn from industry experts and connect with peers in the electronics community. Registration is now open\, and seats are limited. \n\n\n\n\nWe introduce a new CadenceCONNECT Taiwan conference that encompasses a range of technology and vertical topics. \nCadenceCONNECT Taiwan 2024 will be held on August 22 at the Sheraton Hsinchu Hotel. CadenceCONNECT Taiwan provides a forum to share best practices on critical design implementation and verification issues\, and to discover inspiring new techniques for realizing advanced silicon\, system-on-chip (SoC ) designs\, and systems in different vertical markets. This event is organized to inspire and network with emerging technical experts to continue creating revolutionary possibilities with semiconductors. \nIn the face of today’s fierce international competition\, increasingly complex process development and application challenges\, design can not only realize creativity\, but also shape future innovation. Cadence has been based in Taiwan for more than 35 years and has always been the best assistant to local customers and partners. It will continue to work hard for electronic design innovation. This year\, the CadenceCONNECT Taiwan conference will be grandly presented at the Sheraton Hsinchu Hotel on August 22 (Thursday)\, providing an interactive platform to invite Cadence customers\, partners and industry elites to gather\, propose the best policies and case sharing for today’s electronic design\, and deeply discuss and exchange ideas for the future of Taiwan’s semiconductors\, and help and prosper together! \nThank you for your eagerness to register. Registration is now full! \nEvent Info\nEvent Date/Time: August 22\, 2024 (Thursday) 09:00-17:30PM \nVenue: 3F\, Sheraton Hsinchu Hotel \n\n\n\n\n\n\n\n\n\n\nKeynotes\nBe inspired by visionary keynotes as they discuss the latest trends and breakthrough technologies shaping the AI ​​era. \nChin-Chi Teng\nSenior Vice President and General Manager\nDigital & Signoff Group\, Cadence\n\n\n\nKS Pua\nFounder and CEO\nPhison Electronics\n\n\n\nAlbert Kuo\nHead of Automotive Business Unit\nRealtek\n\n\n\n\nCY Chang\nHardware and Operations Vice President\nMetanoia\n\n\n\nBen Gu\nCorporate Vice President\, Multi-Physics System Analysis Group\nCadence\n\n\nEunice Chiu\nVice President and General Manager Taiwan\nNVIDIA\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cadenceconnect-taiwan-2024/ LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-22-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240806T080000 DTEND;TZID=America/Los_Angeles:20240808T170000 DTSTAMP:20240729T183004Z CREATED:20240723T173747Z LAST-MODIFIED:20240729T183004Z UID:8167-1722931200-1723136400@marketingeda.com SUMMARY:Future of Memory and Storage - 2024 DESCRIPTION:FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions. The scope of FMS will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.” \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/future-of-memory-and-storage-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240724T080000 DTEND;TZID=America/Los_Angeles:20240725T170000 DTSTAMP:20240711T164050Z CREATED:20240711T160540Z LAST-MODIFIED:20240711T164050Z UID:8135-1721808000-1721926800@marketingeda.com SUMMARY:Chiplets: Building the Future of SoCs DESCRIPTION:Chiplets\, also known as heterogeneous multi-die systems\, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries\, particularly fueled by the widespread adoption of AI technology. However\, while the concept of using chiplets to construct larger chips to overcome the limitations associated with building monolithic chips using advanced process technologies is promising in theory\, the practical implementation poses challenges. \nThe “Chiplets: Building the Future of SoCs” virtual event will delve into the complex considerations surrounding chiplet-based systems. Discussions will encompass the entire value chain and ecosystem\, spanning from initial concept and design exploration to packaging and testing. Moreover\, the event will examine the emergence of initiatives aiming to establish a chiplet marketplace\, exploring relevant standards and the actual feasibility of such endeavors. \nKey questions to be addressed include how to effectively integrate multiple dies from various foundries\, the methods for pre-validating these chips\, ensuring they meet specified standards\, and managing the integration of components and software. Additionally\, attention will be given to the development of a system integrator community\, strategies for enabling traceability and security within the chiplet supply chain\, and the potential economic viability of chiplet-based systems. \nCrucially\, the event will assess the industry’s readiness to foster the collaborative ecosystems necessary to support a chiplet economy. Will there be a proliferation of competing standards\, or will the industry converge around a unified standard like UCIe? Moreover\, the feasibility of economically designing chiplet-based systems will be scrutinized\, considering factors such as production costs and market demand. \n  \n\nWhat to expect?\nWith a conference space and resource center\, this event will function similarly to a live exhibition and conference. The conference includes keynotes\, panel discussions\, and technical presentations on a variety of subject matters\, including significant technical trends\, market demand and application areas. \nAttendees can expect an immersive exploration of the dynamic landscape of the chiplet and multi-die systems market. \nJuly 24: We’ll look at chiplet definitions\, standards\, and technologies. \nJuly 25: We’ll explore some real-world implementations of chiplet technologies\, and also the chiplet ecosystem. \n  \n\nWho should attend?\nBuilding future SoCs using chiplets involves a diverse range of disciplines\, making this event relevant to anyone involved in the value chain of constructing 2.5D\, 3D stacked heterogeneous systems that incorporate chiplet-style architectures. Whether you specialize in design\, validation\, packaging\, testing\, or provide services related to building these systems\, there will be valuable insights for you at this event. \nFrom automotive industry system developers to those working in data centers and beyond\, we’ll look to explore the technologies\, challenges\, opportunities\, and solutions. \nThis event caters to engineers\, researchers\, developers\, technical marketing professionals\, and industry professionals keen on understanding the potential opportunities and realities of working with and building chiplet-based systems. \n  \n\n\n\n\n\n\n\n  \n\n\n\n\n\n\n\n\n\n\nAgenda\n\n  \n\n\n\n\n\n\n\nAll Dates\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Concepts – Principles and Promise”\n\nWelcome and Opening Nitin Dahad\, Editor-in-Chief\, Embedded.com \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:10 am – 8:45 am PDT \n\n\n\n(CC1) Multi-Die Design in the Pervasive Intelligence Era\n\nThis Keynote is presented by Shankar Krishnamoorthy\, General Manager\, EDA Group\, Synopsys \nArtificial intelligence and silicon proliferation are shaping a new era of pervasive intelligence. At the forefront is the shift to multi-die\, driving the advancements of trillion-transistor systems and the march to angstroms. With its promise to enable significant compute performance\, heterogenous integration is a critical requirement in today’s AI-driven world. Join Shankar Krishnamoorthy\, the General Manager of Synopsys’ EDA Group\, as he explores the opportunities presented by multi-die design. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n8:50 am – 9:25 am PDT \n\n\n\n(CC2) Universal Memory Interface (UMI): The solution to break the memory wall for AI ASICs\n\nThis Keynote is presented by Ramin Farjadrad is the founding CEO of Eliyan. \nCompute performance demand has been growing exponentially in recent years\, and with the advent of Generative AI\, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (memory bandwidth & capacity) and IO Wall are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry’s solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs\, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2\, which is ~1/4 the largest standard package substrate. Thus\, a SiP with silicon interposer has limited compute & memory chiplets\, thus limited performance. This presentation introduces Universal Memory Interface (UMI)\, a high bandwidth efficient D2D connectivity technology between XPU-Memory & XPU-XPU\, which enables innovative architectures that help remove Memory & IO walls for next generation AI\, specifically Gen AI\, systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:35 am – 10:35 am PDT \n\n\n\n(CC3) The A to Z of Multi-Die Design\n\nThis Tutorial is presented by Tim Kogel\, Sr. Director for Technical Product Management\, Synopsys \nThis tutorial explains the intricacies of multi-die design\, covering topics from functional architecture and IP integration to implementation and signoff. It uses case studies to highlight the steps\, considerations\, and new innovations in multi-die designs. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n10:40 am – 11:25 am PDT \n\n\n\n(CC4) Panel Discussion: Taming Complexity – Building a Successful Open Chiplet Ecosystem\n\nThis Panel Discussion with industry experts is moderated by Nitin Dahad\, Editor-in-Chief\, Embedded.com. \nWhat is the current state of the commercial chiplet ecosystem\, and is a multi-company open ecosystem needed for chiplets to achieve their full potential? As we move from single company effort to a complex\, multi-supplier ecosystem\, we’ll discuss the biggest challenges we face\, including the need to manage and reduce supply chain complexity\, and doing so at reasonable cost. We’ll also talk about some of the practicalities. Do we have sufficient standards in place to enable the chiplet economy\, and is there appetite for industry and vendors to collaborate on these standards? Who takes ownership of the process when chiplets come from multiple suppliers\, and who is responsible for overall yield? And how do we ensure that all parts of the supply chain make money\, including smaller companies and startups? \nPanelists:\n– Ramin Farjadrad \, founding CEO\, Eliyan\n– Mohit Gupta\, Senior Vice President\, Alphawave Semi\n– Nick Ilyadis\, Vice President of Product Planning\, Achronix\n– Kenneth Larsen\, Product Management Director\, EDA Group\, Synopsys \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:25 am – 11:30 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Automotive companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:30 am – 11:50 am PDT \n\n\n\n(CC5) Optimizing Next-Gen I/O Chiplet: Pioneering UCIe D2D Interconnects from 1.6 Terabits to 224 Gigabits\n\nPresented by Letizia Giuliano\, Vice President\, Alphawave Semi \nIn this presentation\, we will explore the benefits of adopting UCIe-enabled chiplet IP subsystems\, featuring state-of-the-art Multi-Standard SerDes I/O connectivity for advanced AI solutions. As the need for more powerful compute capability continues to grow\, the landscape and role of chiplets has become increasingly crucial for providing essential avenues for scalability\, efficiency\, and innovation in the infrastructure of next-generation AI data networks. We will review the obstacles associated with developing an interoperable 112G Multi-Lane and Multi-Standard I/O chiplet\, and share detailed implementation insights and outcomes from Alphawave Semi’s Chiplet portfolio. Furthermore\, we will demonstrate how AI connectivity use cases can be rapidly enhanced through the deployment of I/O Chiplets\, which are vital for today’s multi-Terabit I/O systems. The presentation will conclude with a discussion on the challenges facing the industry and propose solutions for advancing scale-up and scale-out connectivity options to meet the networking bandwidth demands of future AI systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:50 am – 12:10 pm PDT \n\n\n\n(CC6) Chiplets for Everyone – Modular Re-usable Solution Powered by Patented Technology\n\nPresented by Kash Johal\, CEO and Founder\, YorChip \nToday\, Chiplets are primarily being deployed by MegaCap companies due to economics\, long lead-times\, and the complexity of development. QuickLogic and YorChip present a solution to deploy re-usable off-the-shelf Chiplets for everyone. Our solution empowers engineers at companies of any size to leverage chiplets:\n– Modular Chiplets: Ease connectivity and enable reuse across diverse customer designs.\n– Patented PHY: Supports both advanced and standard packaging\, lowering development cost and production deployment.\n– Legacy-Node PHY: Extends chiplet benefits to mix older process nodes (up to 90nm) with advanced nodes.\n– Routing Link Layer: Reduces Latency and helps eliminate signal integrity challenges.\n– AI Friendly: Chiplets specifically optimized for running Generative AI models at the edge. \nThe QuickLogic and YorChip collaboration empowers engineers at any size company to deploy chiplets for any application quickly and at low cost. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:10 pm – 12:30 pm PDT \n\n\n\n(CC7) The Role of EDA as Chips Transform Into 3D Systems\n\nPresented by John Park\, Product Director\, Cadence \nWhat challenges will you face when pivoting from monolithic IC design to 3D heterogenous package design? How can electronic design automation (EDA) address these challenges? As we go from Moore’s Law to More-than-Moore\, technologies begin to converge across IC and systems design. This shift requires new advanced design flows combining EDA tools. These system-level design flows must enable seamless cross-domain co-design and analysis. The days of IC and package designers “throwing data over the wall” are over. Heterogeneous integration presents a new era of electronic product design with collaboration at its core – one that depends on the seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller\, discrete chiplets into one SiP not only pushes the need for more advanced multi-die packaging\, but also makes packaging part of the process. This significantly reduces dependence on Moore’s Law at a time when building advanced monolithic SoCs is no longer the best option from a cost and technology perspective. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:30 pm – 12:50 pm PDT \n\n\n\n(CC8) Taking 3DIC Heterogeneous Integration Mainstream\n\nPresented by Tony Mastroianni\, Advanced Packaging Solutions Director\, Siemens EDA \nHeterogeneous integration itself isn’t new\, but new design and manufacturing technologies\, combined with new product demands from system integrators\, means that heterogeneous integration and 3DIC are now becoming a necessity in mainstream design. This shift however is not without its challenges as 3D IC is not a simple extension of existing packaging solutions but creates a whole new set of Multiphysics integration considerations. The interaction of thermal\, mechanical\, reliability\, test\, and core semiconductor design increases complexity and requires disparate domains to seemly collaborate.In this presentation we will explore the challenges introduced by 3D IC\, the current state of the industry to address those challenges\, the ecosystem needed to support 3DIC\, and how users today can successfully adopt 3D IC leveraging new solutions\, workflows\, and 3D IC Design Kits (3D K) from Siemens EDA that are designed specifically with 3D IC in mind. \n  \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:50 pm – 1:10 pm PDT \n\n\n\n(CC9) UCIe Standard Versus UCIe Advanced – What Designers Need to Know\n\nPresented by Manuel Mota\, Principal Product Manager\, Synopsys \nThis technical presentation delves into the requirements and considerations for UCIe in standard and advanced packaging\, including density\, testing\, and the power and performance impact on the die-to-die implementation. The presentation will use real examples of UCIe silicon proofs to showcase the two variants of UCIe interfaces. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n1:10 pm – 1:20 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:20 pm – 1:40 pm PDT \n\n\n\n(CC10) Celestial AI Photonic Fabric based 14.4Tbps Optical Chiplets for AI XPU Connectivity\n\nPresented by Dave Lazovsky\, CEO\, Celestial AI \nWith the growth in GenAI\, AI infrastructure is not just about the System on Chip but about the System of Chips. The bottleneck is no longer compute performance of a single XPU but scale-up interconnect bandwidth\, memory bandwidth and capacity. Photonic Fabric is the next generation optical interconnect technology offering >10X more performance than any competitive technology. Chiplets based on the Photonic Fabric and incorporating D2D interfaces like UCIe\, MAX3 etc are built in TSMC 5nm process and are fully compatible with standard 2.5D packaging flows for easy integration with XPUs. This enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver Tbps bandwidth with nano-second latencies. XPUs can also seamlessly integrate with Photonic Fabric based memory solutions offering TBs of memory capacity at full HBM3 bandwidth. This innovation empowers hyperscalers to optimize the number of XPUs needed for training & inference\, improving the efficiency and economics of AI processing with significantly lower TCO2 impact. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:40 pm – 2:00 pm PDT \n\n\n\n(CC11) Traceability and security for chiplet supply chain\n\nPresented by Jun Kawaguchi\, Marketing Executive\, Winbond \nThis presentation describes the issues relating to authenticity of individual chiplet and how to ensure the supply chain security is assured. A secure supply chain is becoming increasingly critical topic to counter cybersecurity concerns and the operation of critical systems such as infrastructure systems and autonomous vehicle application. There are trusted certification organizations that will audit and assure the supply chain to be intact\, however this becomes complex as multiple chiplets enter the supply chain. We will discuss these issues in the context of certified\, secure memory product that Winbond provides. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:00 pm – 2:20 pm PDT \n\n\n\n(CC12) Innovations in AI Chip Packaging: Advanced Processes & Equipment Technologies\n\nPresented by Aaron Fellis\, Corporate Vice President\, Lam Research \nAs artificial intelligence (AI) continues to permeate diverse sectors\, from autonomous vehicles to healthcare\, there is increasing demand for more powerful and efficient AI chips. This has led to a paradigm shift\, with a focus not only on the performance of AI chips but also on their packaging. As the demand for higher processing power and energy efficiency grows\, advanced packaging becomes more essential to support these requirements\, driving sophisticated processes and equipment technologies that can handle the complexity of packaging AI chips. The presentation will shed light on equipment innovations and packaging methodologies that are shaping the future of AI chip technology. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:20 pm – 2:55 pm PDT \n\n\n\n(CC13) Packaging matters: extending Moore’s law with “re-aggregation”\n\nThis Keynote is presented by Lalitha Immaneni\, VP of Semiconductor R&D\, Intel \nWith the arrival of ChatGPT\, Large Language Models (LLMs) have transformed AI into an interactive and accessible technology that recursively builds on its prior accomplishments\, fueling a new gold rush era of applications. AI models have exploded in complexity and size\, exerting demand pressure on both compute and memory. Over time\, Moore’s law has yielded a roughly 2x increase in compute every 2 years\, compared to the enormous 750x per year growth demand from the LLMs. Memory is an even trickier problem as it needs to address capacity\, speed and cost of data transport. Packaging plays a pivotal role in this era\, architecting bespoke solutions for a highly differentiated set of applications. We take a look at the role of disaggregation\, chiplets and interconnects in enabling the future of AI and HPC and illustrate this with solutions that can help create unique functionality\, performance\, and cost while enabling reuse and modularity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:55 pm – 3:15 pm PDT \n\n\n\n(CC14) Emerging Chiplet Ecosystems Enable Innovative Multi-Vendor Designs\n\nPresented by Elad Alon\, CEO and Co-Founder\, Blue Cheetah Analog Design \nChiplets reduce the rising costs of innovation. Heterogeneous compute\, especially AI applications\, stands to gain the most from chiplet-based designs. System architects are discovering that the keys to successful chiplet integration are an application-appropriate ecosystem and a customizable die-to-die (D2D) interconnect tailored for their end applications. \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Technologies – Practicalities and Performance”\n\nWelcome and Opening by Sally Ward-Foxton\, Senior Reporter\, EE Times \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:10 am – 8:45 am PDT \n\n\n\n(CP1) Jumpstart Your Chiplets Journey with End-to-End System Silicon Solutions\n\nThis Keynote is presented by David Glasco\, Vice President\, Compute Solutions Group\, Cadence. \nExplore the chiplet journey and gain insights into the reasons behind the increasing adoption of chiplets and the vital role that partners play in helping engineers succeed in their chiplet journey.  Learn how the right IP portfolio and IP teams can deliver on this journey with multiple engineering engagement models and strong industry partnerships.  See how design automation flows can help accelerate product time-to-market and reduce engineering costs. Understand how the design process can be automated and how virtual platforms and package design flows can significantly improve the engineering efficiency of chiplets. Join this keynote to discover the advantages and future potential of chiplets and how partners can help you succeed. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n8:50 am – 9:25 am PDT \n\n\n\n(CP2) Chipletonomics : Economic foundation of future AI and HPC supercomputing.\n\nThis Keynote is presented by Sambit Sahu\, Senior Vice President at Krutrim\, an Ola company. \nThere is a huge surge in AI and HPC supercomputing currently and this will continue to accelerate. Generative AI explosion and associated multi-trillion dollar impact to revenue is triggering huge innovations in the AI space. HPC computing is on a rapid growth path with multiple supercomputers (multiple chips interconnected with high bandwidth and highly reliable network fabric and infrastructure) being built worldwide. Chiplets\, which are small pieces of silicon dies targeting a particular functionality\, are evolving rapidly as a concept and implementation style. In this presentation\, we will talk about how chiplets are going to address some of the key challenges of building next generation AI and HPC supercomputers. We will also demonstrate the significant economic advantages of chiplets architecture over conventional monolithic architectures. We will also demonstrate methodologies and approaches on how to use chiplets for your cost advantage. We will walk through how we are capitalizing on the chiplet strategy for economic advantage in building our high end AI server\, scaling upto a supercomputer. We will walk through strategies in optimizing NRE costs\, optimizing TCO\, optimizing on scaleout costs\, and optimizing on time to market\, and extending the benefits to additional products. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:35 am – 10:35 am PDT \n\n\n\n(CP3) Semiconductor design: Linking design to manufacturing for a sustainable semiconductor future\n\nTechnical Talk with Michael Munsey\, Vice President\, Siemens EDA and Sally Ward-Foxton\, Senior Reporter\, EE Times \nSemiconductor sustainability starts with design and the decisions made during the design process affect sustainability. This is amplified as we transition to the heterogeneous integration of chiplets using advanced substrate platforms such as 2.5/3D in order to continue silicon scaling. By linking the digital twins for semiconductor design to the digital twin of a semiconductor fab\, design details can be fed forward to optimize fabs for sustainability and manufacturing data can be fed back to optimize design libraries and decisions. In this talk\, we will talk about the evolution of the digital twin\, how new solutions aid design and manufacturability\, and the start of a new semiconductor era. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n10:40 am – 11:25 am PDT \n\n\n\n(CP4) Panel Discussion: Lowering Barriers – Making Chiplets Work Together\n\nThis Panel Discussion with industry experts is moderated by Sally Ward-Foxton\, Senior Reporter\, EE Times. \nChiplets are attracting a lot of attention\, but which industries or verticals will benefit most from chiplets in the short term\, and why? We’ll start by talking about applications for chiplets and how they will evolve as the technology matures.We’ll discuss the biggest challenges to designing successful multi-die systems today. How do we ensure dies from different processes work together\, and what about dies designed by different companies? Are standards ready for this challenge\, and how are design tool vendors\, silicon vendors and IP providers taking it on? We’ll cover topics like multi-die system simulation\, emulation and verification\, and whether the complexity of these processes is limiting the size and scope of multi-die designs today. \nPanelists:\n– David Glasco\, Vice President\, Compute Solutions Group\, Cadence\n– Andreas Olofsson\, CEO\, Zero ASIC\n– Sambit Sahu\, Senior Vice President\, Krutrim\, an Ola company\n– John Sotir\, Senior Director\, Altera\, an Intel Company \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:25 am – 11:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:35 am – 12:10 pm PDT \n\n\n\n(CP5) Using composable chiplets to reduce ASIC design costs\n\nThis Keynote is presented by Andreas Olofsson\, CEO and founder of Zero ASIC. \nThe compounding effect of monolithic miniaturization on electronics has been nothing short of miraculous. Fifty plus years of Moore’s Law has resulted in a million fold improvement in computing cost and efficiency. Now that physical device scaling is approaching hard atomic limits\, the question is: Where will the next million fold computing efficiency improvement come from? Extreme domain specific circuit specialization can provide the next 1\,000 bost\, but the path is blocked by the prohibitive cost and complexity of ASIC design. Chiplets offer a compelling solution to reducing the cost and time of ASIC design\, but challenges remain. In this talk\, I will present my experience with chiplets over the last decade\, review the current obstacles\, and propose some potential paths for the future. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n12:15 pm – 1:15 pm PDT \n\n\n\n(CP6) Unleashing AI Potential Through Advanced Chiplet Architecture\n\nThis Tutorial is presented by Dr. Tony Chan Carusone\, Chief Technology Officer\, Alphawave Semi \nIn this tutorial\, Tony Chan Carusone\, CTO of Alphawave Semi\, explores the crucial advancements required to propel the next generation of computing\, with a particular emphasis on AI as a transformative force reshaping our daily lives and data management systems. He highlights how pervasive connectivity\, from extensive optical fiber networks to intricate chiplet wirings\, is critical for AI functionalities. The discussion traces AI’s evolution over the last two decades. These developments are pivotal in meeting the computational demands\, from teraflops to petaflops\, while focusing on sustainability through chiplet-based designs. Additionally\, he will delve deeper into the chiplet architecture\, discussing how it revolutionizes cost and power efficiencies in AI applications. Tony will detail Alphawave Semi’s leadership in providing connectivity solutions specifically designed for chiplet architectures\, including the groundbreaking UCIe interface that offers a path up to 10 Tbps/mm bandwidth density. The session will further examine how AI is transforming data infrastructure connectivity\, highlighting the necessity for robust inter-chip links within datacenters and the reengineering of optical networks that cater to AI’s specific needs. The session wraps up by addressing the trend toward disaggregated computing and distributed data centers\, facilitated by low-latency connectivity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:15 pm – 1:25 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:25 pm – 1:45 pm PDT \n\n\n\n(CP7) MIPS Accelerating the Chiplet Revolution: Powering the Future of GenAI\n\nPresented by Durgesh Srivastava\, Chief Technology Officer\, MIPS \nCompute requirements have outpaced supply by 10x. Historically\, HW advancements consistently outpaced SW. However\, the advent of GenAI has reversed this trend\, with SW developments now outstripping HW. Advanced algorithms\, especially those involving deep learning and large-scale data processing\, require vast processing power\, memory\, and efficient data handling. The computational demands of training and running GenAI models have pushed traditional silicon-based processors to their limits\, necessitating new hardware designs. Concurrently\, the slowdown of Moore’s Law has worsened these challenges. The chiplet architecture has emerged as a promising solution. This presentation will discuss how MIPS’ data-centric approach\, with the integration of the RISC-V ISA\, is driving the chiplet revolution\, optimizing data flow and processing efficiency to bridge the HW-SW gap and ensure ongoing computational advancements. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:45 pm – 2:05 pm PDT \n\n\n\n(CP8) Multi-Die Health Management\n\nPresented by Dr. Yervant Zorian\, Chief Architect and Fellow\, Synopsys \nThis technical presentation discusses four multi-die health management solutions for different chiplet-to-chiplet configurations: Using IEEE 1838 for testing interconnects and dies (or chiplets) in a GPIO-based configuration\, using Synopsys SLM SMS EXT-RAM for test and repair of interconnects and DRAMs in an HBM-based logic-to-memory chiplet configuration\, using MTR for monitoring\, test\, and repair of interconnects in a UCIe-based chiplet-to-chiplet configuration\, using lane test and repair (LTR) for monitoring\, test\, and repair of light I/O in a TSV-based hybrid bonding configuration. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:05 pm – 2:25 pm PDT \n\n\n\n(CP9) The Rise of Chiplets in Advanced AI/ML/High Performance Compute SoCs\n\nPresented by Jeff Twombly\, VP Business Development\, Credo \nThis presentation will cover critical SerDes IP development\, chiplet productization\, testing considerations to enable volume at scale\, and how Credo’s experience and infrastructure will enable more chiplet variants required for emerging I/O standards such as UCIe. Credo is a proven industry leader in providing high-performance\, low power chiplet solutions. Credo has two 3.2Tbps chiplets shipping in production. Credo developed all the necessary IP inhouse and combined our purpose built SerDes blocks to create the chiplet products. The 3.2Tbps Nutcracker device utilizes 32-lanes of 112G XSR SerDes to connect to the ASIC/SoC die and 32-lanes of 112G MR SerDes for the off-package\, line-side connectivity. The XSR interface can connect up to 50mm trace lengths on standard organic packaging substrates. The 3.2Tbps BlueJay device was developed to enable multi-chip module solutions using TSMCs CoWoS\, InFO\, and/or SoIC 3DFabric configuration technology. Credo developed a BoW (bunch of wires) interface to connect to the ASIC/SoC die and enables the off-package\, line-side connectivity with 64-lanes of 56Gbps LR SerDes. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:25 pm – 2:45 pm PDT \n\n\n\n(CP10) Architecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment\n\nPresented by Deepak Shankar\, Founder and Chief Visionary\, Mirabilis Design \nDesign of chiplet architectures must transition from silicon-centric to system-centric. Early application-specific architecture exploration provides power\, latency\, throughput and thermal impact statistics to measure quality and efficiency. The exploration covers partitioning of heterogeneous compute resources onto chiplets\, task assignment\, maximize throughput and minimize latency\, manage power and thermal below the threshold for corner cases\, and scalability across workloads and tasks. System modeling using IP blocks enables this using multi-abstraction methodology with rapid modeling\, extensive exploration with constraints and optimization of the specification. During the session\, we will explain the exploration of real-life examples using system modeling. How to determine the best assignment of caches and memory at the host processor vs chiplet hub vs accelerator? How do you ensure chiplets are of the same dimension and thermal is equally distributed? How do you decide between UCIe standard vs advanced\, number of UCIe interfaces\, memory request distribution and coherency on performance? \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:45 pm – 2:55 pm PDT \n\n\n\nWrap-Up Session\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplets-building-the-future-of-socs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EE-Times-July-24-25-2024.jpg END:VEVENT END:VCALENDAR