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DTSTART;TZID=America/Los_Angeles:20230125T080000
DTEND;TZID=America/Los_Angeles:20230125T090000
DTSTAMP:20230124T194950Z
CREATED:20230124T194950Z
LAST-MODIFIED:20230124T194950Z
UID:5885-1674633600-1674637200@marketingeda.com
SUMMARY:Making Way for Open-Source Hardware
DESCRIPTION:This is a thought leadership piece that highlights the significance of open-source hardware. Tony McDowell (Rapid Silicon) and Adam Taylor (Adiuvo) will discuss the innovations and changes required to bring awareness to open-source. Rapid Silicon’s Raptor Design Suite toolchain has already proven that designs can be secure even in an open-source environment. \nRapid Silicon\nThe world is getting hyper connected and hyper intelligent through aggressive adoption of AI and 5G technology. Billions of sensors are being integrated into embedded and edge applications\, creating new standards and protocols. Rapid Silicon is taking the lead with a revolutionary approach to provide solutions that meet the ever-changing needs of these new intelligent embedded and edge applications. Our nimble engineering methodology and the Open FPGA framework give us the ability to iterate quickly and bring highly differentiated products to market. This\, coupled with open-source software\, unleashes the power of the community and diverse ecosystem to develop application specific SW\, IP and solutions at an accelerated pace with thousands of members worldwide. \nAdiuvo\nFrom satellite systems in space\, to predictive maintenance in the factory\, to ADAS  on the road\, Adiuvo has experience helping our clients design systems that are reliable and meet the most stringent standards.
URL:https://marketingeda.com/event/making-way-for-open-source-hardware/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RapidSilicon-January-25-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230116T080000
DTEND;TZID=Asia/Tokyo:20230119T170000
DTSTAMP:20230104T174652Z
CREATED:20230104T174652Z
LAST-MODIFIED:20230104T174652Z
UID:5828-1673856000-1674147600@marketingeda.com
SUMMARY:ASP-DAC 2023
DESCRIPTION:ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2023 is 28th conference. ASP-DAC 2023 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2023. \n\nDate: Jan. 16-19\, 2023\nPlace: Tokyo Odaiba Miraikan\, Japan\nGeneral Chair: Atsushi Takahashi (Tokyo Institute of Technology\, Japan)\nTechnical Program Chair: Gi-Joon Nam (IBM Research\, USA)\nDesign Contest Co-Chairs: Mahfuzul Islam (Kyoto University\, Japan)\, Akira Tsuchiya (The University of Shiga Prefecture\, Japan)\n\nThe format of the conference is hybrid but mainly in-person for speakers. All speakers are expected to attend ASP-DAC 2023 physically unless a speaker has some inevitable reasons such as medical reasons and government orders.\nRestrictions on new entry into Japan due to COVID-19 have been relaxed since October 11\, 2022. Please check the following announcement from the Ministry of Foreign Affairs of Japan.\nhttps://www.mofa.go.jp/j_info/visit/visa/index.html
URL:https://marketingeda.com/event/asp-dac-2023/
LOCATION:Tokyo Odaiba Miraikan\, 2 Chome-3-6 Aomi\, Tokyo\, Koto CIty\, 135-0064\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230116T080000
DTEND;TZID=Europe/Paris:20230118T170000
DTSTAMP:20230113T205251Z
CREATED:20230113T205251Z
LAST-MODIFIED:20230113T205251Z
UID:5845-1673856000-1674061200@marketingeda.com
SUMMARY:HiPEAC
DESCRIPTION:The HiPEAC conference is the premier European forum for experts in computer architecture\, programming models\, compilers and operating systems for general-purpose\, embedded and cyber-physical systems. Areas of focus and integration include safety-critical dependencies\, cybersecurity\, energy efficiency and machine learning. \nThe HiPEAC 2023 conference will take place in Toulouse\, France. Associated workshops\, tutorials\, special sessions\, several large poster session and an industrial exhibition will run in parallel with the conference.
URL:https://marketingeda.com/event/hipeac/
LOCATION:Pierre Baudis Convention Centre\, 11 esplanade Compans Caffarelli\, Toulouse\, France
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/HiPEAC.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20230108T080000
DTEND;TZID=Asia/Karachi:20230112T170000
DTSTAMP:20221122T174938Z
CREATED:20221122T174938Z
LAST-MODIFIED:20221122T174938Z
UID:5464-1673164800-1673542800@marketingeda.com
SUMMARY:VLSID 2023
DESCRIPTION:International VLSI Design & Embedded Systems conference is a Premier Global conference with legacy of over three and half decades. This Global Annual technical conference that focusses on latest advancements in VLSI and Embedded Systems\, is attended by over 2000 engineers\, students & faculty\, industry\, academia\, researchers\, bureaucrats and government bodies. \nSemiconductors are the intangible backbone of every industry across the globe. Silicon took the lion’s share over the past decades and remained the primary enabler for digitization of the world. With scaling reaching its fundamental limits\, it is time to look at addressing technological challenges at higher levels of abstraction in CMOS based design and at the same time\, look beyond Silicon for further performance enhancement. \nVLSID 2023 – the first physical conference post pandemic\, acts a platform for industry and academia alike to discuss\, deliberate and explore into the frontiers of semiconductor eco-system that could eventually enable disruptive technologies for global digitalization \nVLSID 2023 will be hosted in the best stand-alone convention center\, HICC Hyderabad. The city is home to some of the best universities\, top global companies in research and manufacturing\, strong defense sector and thriving start-ups. Hyderabad has a rich culture with numerous historic places to visit and world famous Hyderabad Biryani to cherish. We look forward to hosting and giving you the best experience at the conference. We encourage your participation to the conference and call you to be part of the exciting know-how’s of the industry and spend quality time exploring Hyderabad.
URL:https://marketingeda.com/event/vlsid-2023/
LOCATION:Hyderabad International Convention Cente\, Hyderabad\, Telangana\, India
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Hong_Kong:20221226T080000
DTEND;TZID=Asia/Hong_Kong:20221227T170000
DTSTAMP:20221220T184858Z
CREATED:20221220T184858Z
LAST-MODIFIED:20221220T184858Z
UID:5582-1672041600-1672160400@marketingeda.com
SUMMARY:CSIA-ICCAD 2022
DESCRIPTION:As a strategic\, basic and leading industry in national economic and social development\, integrated circuit(IC) industry is an important support for cultivating strategic emerging industries and developing information economy\, and plays an important role in the core of information technology field.  Promoting the healthy development of IC industry is the only way to realize the autonomous control of core technology.  With the independent innovation and development of China’s IC industry\, its market scale and enterprise competitiveness continue to improve\, China has become the world’s largest and fastest growing IC market.  At present\, the global IC industry has entered a major period of transformation and reform. As the industry leader and an important link of technology and product innovation\, the IC design industry bears an important responsibility in the development of the industry\, and is also the key to achieve independent control of the semiconductor industry. \nDuring the development of China’s IC design industry\, CSIA – ICCAD Annual Conference has played an important role in promoting industry cluster\, linking industrial resources\, and keeping abreast of industry trends. Over the years\, the theme of the Annual Conference has been combined with the actual development of the electronic information industry in the host city of the conference. The Conference has promoted the simultaneous development of the related industries in the host cities and the national IC industry. Therefore\, the “CSIA – ICCAD 2022 Annual Conference & Guangzhou IC Industry Innovation and Development Summit (ICCAD 2022)” is planned to be held in Guangzhou from November 9 to 10\, 2022. \nThe theme of this year’s conference is “Bay Area has you\, core to the future”. The Conference will discuss the opportunities and challenges faced by the IC industry\, especially the IC design industry\, and enhance the innovation capability and the integration capability of China’s IC industry chain to meet market demands and improve international competitiveness. The conference will create a platform for communication and cooperation for enterprises in all aspects of the IC industry chain\, and a platform for communication and cooperation in technology\, market\, application\, investment and other fields for IC design enterprises. \nThe related matters of this annual conference are hereby notified as follows: \n\nGuidanced by:\n\n  Industry and Information Technology Department of Guangdong \nThe People’s Government of Guangzhou Municipality \nChina Semiconductor Industry Association \n\nHosted by:\n\nChina Semiconductor Industry Association IC Design Branch (CSIA – ICCAD) \nNational S&T Major Project(NMP) 01 General Expert Group \nChina Integrated Circuit Design Innovative Alliance \nIII. Supported by: \n     The People’s Government of Guangzhou Huangpu District \nGuangzhou Municipal Industry and Information Technology Bureau \n\nOrganizedby:\n\n     Guangzhou Huangpu District Industry and Information Bureau \nGuangdong Integrated Circuit Industry Association \nShanghai Xinmei Conference Service Co.\, Ltd. \nShanghai Yaxun Shangwu Zixun Co.\, Ltd. \nV.Co-organized by: \nChina Institute of Communications-ASIC Committee \nChina Integrated Circuit(CIC) \nVI.Registration Date: November 8\, 2022 (Tuesday) \nConference Date: November 9-10\, 2022 \nVII. Registration Location: The Westin Pazhou Guangzhou \n (Address: No. 681\, Fengpuzhong Road\, Haizhu District\, Guangzhou) \nConference Location: Guangzhou PWTC Expo \n (Address: No.1000\, Xingangdong Road\, Haizhu District\, Guangzhou) \nVIII. Conference Content \n\nKeynote Speeches\n\n(1) China IC Design Industry Current Development Situation Report \n(2) Coordinate Science & Technology Resources to Realize Innovation Development Report \n(3) Global IC Technology and Industry Development Trend Report \n\nSeminars\n\nl  IC Design and Innovation Application \nl  IC Design and EDA Software \nl  Foundry and Process Technology \nl  IC Packaging and Testing \nl  IP and IC Design Services \nl  Capital and Entrepreneurship \nl  Guangzhou IC Innovation and Entrepreneurship Forum \n\nChina IC Design Industry Exhibition\nIX. Participants\n\nThe relevant authorities and local leaders\, relevant domestic and foreign experts\, representatives from local bases and industry associations\, IC design companies\, IP service vendors\, EDA vendors\, foundry companies\, packaging testing vendors\, system vendors and venture capital firms at home and abroad\, representatives from IC industries Parks and related media. \n\n Contacts\n\nContact:Shirley Hu \nTel: 18917192814\, E-mail: shirleyhp@cicmag.com \nContact:Yuanyuan Wang \nTel:18600095161\, E-mail: wangyy@csia-iccad.net.cn \n\nThe organizers of the annual conference are required to conscientiously and carefully organize and prepare for the conference and ensure a complete success. \nAnnex: Registration Form
URL:https://marketingeda.com/event/csia-iccad-2022/
LOCATION:Xiamen International Convention Center\, 198 Exhibition Road\, Xiamen City\, China
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CSIA-ICCAD-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221220T100000
DTEND;TZID=America/Los_Angeles:20221220T110000
DTSTAMP:20221212T220742Z
CREATED:20221212T220611Z
LAST-MODIFIED:20221212T220742Z
UID:5498-1671530400-1671534000@marketingeda.com
SUMMARY:Using Formal Datapath Validation to Verify AI Processor Computations
DESCRIPTION:For over a decade\, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs\, AI processors are also datapath heavy with mathematical functions like addition\, subtraction\, matrix multiplication\, and square root in its compute engines\, making these designs a good fit for formal datapath validation. \nThis webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions. The Synopsys ARC NPX6 processor supports the latest and most complex neural networks\, such as CNN\, RNN\, and transformers\, targeted for AI SoCs that are widely used in automotive\, data center\, high end gaming\, next generation augmented reality\, and surveillance. At the heart of the NPX6 neural network processor are convolution and tensor accelerators that are optimized to perform light speed computations. Correctness of these functional units are key to correct facial\, audio\, image processing and recognition which could have safety implications for automotive applications. We will explore Synopsys VC Formal DPV\, the gold standard for datapath validation and signoff for the last 20 years\, and how it is used to ensure correctness of the core algorithms of the ARC NPX6 processor’s compute engines. \n\n\n\nSpeakers\n\n\n\nNeelabja Dutta\nSr. Manager\, Applications Engineering\nSynopsys\n\n\n\n\n\nShuaiyu Jiang\nSr. ASIC Digital Design Engineer\nSynopsys
URL:https://marketingeda.com/event/using-formal-datapath-validation-to-verify-ai-processor-computations/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-December-20-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221215T080000
DTEND;TZID=America/Los_Angeles:20221215T170000
DTSTAMP:20221130T191032Z
CREATED:20221130T191032Z
LAST-MODIFIED:20221130T191032Z
UID:5487-1671091200-1671123600@marketingeda.com
SUMMARY:CHIPS Alliance\, Fall Technology Update
DESCRIPTION:Join us in-person for our second biannual technology update featuring informative\, technical talks on open source hardware collaborative development\, hosted by Google and including speakers from Microsoft\, Google\, Intel\, Antmicro\, Efabless and others. \nCHIPS’ Thursday event follows the main RISC-V Summit days (Tuesday-Wednesday) to allow easy participation for open source hardware professionals traveling to the Bay Area for the Summit\, and is free to attend (registration required).
URL:https://marketingeda.com/event/chips-alliance-fall-technology-update/
LOCATION:Koto CIty
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CHIPS-Alliance-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221213T080000
DTEND;TZID=America/Los_Angeles:20221214T170000
DTSTAMP:20221202T202132Z
CREATED:20220926T163457Z
LAST-MODIFIED:20221202T202132Z
UID:5232-1670918400-1671037200@marketingeda.com
SUMMARY:RISC-V Summit
DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance the most prolific open\, license and royalty-free computing architecture. They share technical investment and help shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from the open intellectual property contributed by RISC-V. \nThis December\, the RISC-V community – including the technical\, industry\, domain and special interest groups who define the architecture’s specifications – will be in San Jose\, California for four days of technology breakthroughs\, industry milestones\, tutorials\, and relationship building.  \n\n\n\n\nIt all kicks off with a RISC-V Member Day where technical and industry working groups meet in person\, running alongside a new RISC-V FutureWatch track featuring breaking news of products\, technologies\, ecosystem expansion\, and more.\nThen it’s the centerpiece of the week: Our Summit featuring two days of compelling technical and industry keynotes and conference sessions\, paired with a showfloor of the latest community innovations.\nThe week wraps up with a full day of information-rich tutorials.\n\n\n\n\nThe community-curated content you’ll experience is unparalleled. \nAutomotive. High-performance Computing. Data Centers. ML and AI. Security. Software Stacks. Development Tools. Systems on a Chip. It’s all here. And it’s all new. \nBreak new ground. Define the future. Grow your network. Build your expertise. Meet your heroes. It’s all during RISC-V Summit North America\, this December in San Jose.
URL:https://marketingeda.com/event/risc-v-summit/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221207T100000
DTEND;TZID=America/Los_Angeles:20221207T110000
DTSTAMP:20221115T190148Z
CREATED:20221115T190148Z
LAST-MODIFIED:20221115T190148Z
UID:5400-1670407200-1670410800@marketingeda.com
SUMMARY:Successful Management of Semiconductor Intellectual Property
DESCRIPTION:Do you develop\, procure or distribute semiconductor intellectual property (IP) within your enterprise? If so\, how is the IP managed? In this 30 minute presentation\, we will show you a solution\, which has been adopted by large institutions\, by creating a catalog of all your IP and aid you through the process of publishing the IP and sharing it across the enterprise. \nWhat you will learn: \nWhat IP Designers learn: \nHow to create or update\, release & notify IP and designs with complete control & management. \nWhat will System IntegrationTeams learn: \nHow to receive notifications of updated IP and designs to help guide selection\, updates and integration. \nWhat will managers learn: \nHow to review changes\, analyze conflicts\, and approve releases – easily.
URL:https://marketingeda.com/event/successful-management-of-semiconductor-intellectual-property/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Cliosoft-December-7-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221205T080000
DTEND;TZID=Europe/Berlin:20221205T203000
DTSTAMP:20221116T201152Z
CREATED:20221116T201152Z
LAST-MODIFIED:20221116T201152Z
UID:5407-1670227200-1670272200@marketingeda.com
SUMMARY:The 26262 Club - Technical Conference
DESCRIPTION:MEET US AT THE 26262 CLUB TECHNICAL CONFERENCE THIS COMING DECEMBER 5\, 2022\nIn this edition\, the 26262 club continues the discussion on the anticipated third edition and the emerging role of ISO 26262 within the evolving standards ecosystem. We bring on stage key global players from WG8 alongside authors of the most prominent upcoming standards and share must-have insights from the global standardisation community. Goal of the day is to facilitate collaboration and open discussion between different groups and practitioners and present applicable case studies and lessons learnt to take back with you. \nWHO WILL YOU MEET\nThe expert speaker line up includes 20 international experts from the ISO 26262 WGs and international members of Germany\, UK\, France\, Italy\, Austria\, USA – together we welcome experts from WGs of SOTIF\, IEEE\, Accellera\, ISO 21434 among other. Presenting companies include OEMS\, Tier 1s\, Semiconductor and notable solution providers. Meet our expert speaker panel here.
URL:https://marketingeda.com/event/the-26262-club-technical-conference/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/The-26262-Club.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20221129T080000
DTEND;TZID=Asia/Jerusalem:20221129T170000
DTSTAMP:20221107T193748Z
CREATED:20221107T193748Z
LAST-MODIFIED:20221107T193748Z
UID:5383-1669708800-1669741200@marketingeda.com
SUMMARY:SEMISRAEL Expo 2022
DESCRIPTION:SemIsrael Expo 2022 is the premier professional semiconductor event in Israel. \nThe event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. \nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities. \n\nThe event will be hosted at Avenue Convention and Events Center on November 29\, 2022. \nSemIsrael Expo events are produced by SemIsrael – The Israeli Semiconductor Portal.
URL:https://marketingeda.com/event/semisrael-expo-2022/
LOCATION:Avenue Convention Center\, Airport City\, Israel
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMISRAEL-Expo-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221129T080000
DTEND;TZID=America/Los_Angeles:20221129T120000
DTSTAMP:20221011T180112Z
CREATED:20221011T180041Z
LAST-MODIFIED:20221011T180112Z
UID:5291-1669708800-1669723200@marketingeda.com
SUMMARY:Memory Technology Symposium
DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \nWhy attend?\nThe Synopsys Memory Technology Symposium\, a first-of-its-kind virtual event dedicated to memory design and development\, aims to provide a forum for leading Memory\, IP\, SoC Companies and Synopsys experts to share their perspectives on the industry’s most compelling and topical challenges across four themes: Design Technology Co-optimization (DTCO)\, Design Shift Left\, IP\, and Silicon Reliability. Register to learn more!​
URL:https://marketingeda.com/event/memory-technology-symposium/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Screen-Shot-2022-10-11-at-10.57.56-AM.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221121T080000
DTEND;TZID=Europe/Berlin:20221122T170000
DTSTAMP:20221117T181728Z
CREATED:20221117T181728Z
LAST-MODIFIED:20221117T181728Z
UID:5419-1669017600-1669136400@marketingeda.com
SUMMARY:CadenceLIVE Europe 2022
DESCRIPTION:CadenceLIVE Europe 2022 will be held on November 21-22 at the Hilton Munich Park hotel. It will feature peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees will have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \nKeynote Speakers\n\n\n\n\n\n\nTom Beckley\nSenior Vice President and General Manager\, Custom IC & PCB Group\nCadence Design Systems \n\n\n\n\n\n\nDr. Oliver Wolst\nSenior Vice President\, Automotive Semiconductor Integrated Circuits\nRobert Bosch GmbH
URL:https://marketingeda.com/event/cadencelive-europe-2022/
LOCATION:Hilton Munich Park\, Am Tucherpark 7\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221116T090000
DTEND;TZID=America/New_York:20221116T140000
DTSTAMP:20221025T170717Z
CREATED:20221025T170717Z
LAST-MODIFIED:20221025T170717Z
UID:5332-1668589200-1668607200@marketingeda.com
SUMMARY:ASIP University Day 2022
DESCRIPTION:Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. Synopsys’ ASIP Designer is the market leading tool for ASIP design\, verification and programming\, and is used by leading companies around the globe with hundreds of successful projects to date. \nPlease join us at the ASIP University Day virtual event on Wednesday\, November 16\, 2022. In this informal forum you will be able to exchange ideas\, build up networks and gain first-hand insight about ASIP Designer directly from your peers. \n\nSynopsys will share its insight into market trends\, and provide a technical update on ASIP Designer along with reference examples. In addition\, several university partners will present results from their ASIP Design projects.
URL:https://marketingeda.com/event/asip-university-day-2022/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221116T090000
DTEND;TZID=America/Los_Angeles:20221116T100000
DTSTAMP:20221103T212350Z
CREATED:20221103T212350Z
LAST-MODIFIED:20221103T212350Z
UID:5370-1668589200-1668592800@marketingeda.com
SUMMARY:The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
DESCRIPTION:As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law\, it has created new challenges. \nJoin us on Wednesday\, November 16 at 9:00 a.m. PST for an informative webinar on The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging \nHear 3 unique perspectives on this growing market:\n\n\nStefan Chitoraga\, Technology and Market Analyst at Yole Développement will present the latest market insights on the adoption of chiplets and heterogeneous integration and will address what is driving advanced packaging toward 2.5D and 3D solutions.\nIgor Elkanovich\, CTO at Global Unichip Corp. (GUC) will discuss the GUC GLink™ chiplet interconnect\, including its architecture and roadmap; HBM3 memory interfaces; and will also highlight some of the 2.5D and 3D packaging challenges.\nNir Sever\, Senior Director of Business Development at proteanTecs will reveal silicon results from a GUC GLink chip\, which used D2D interconnect monitoring for comprehensive visibility and parametric lane grading.
URL:https://marketingeda.com/event/the-era-of-chiplets-and-heterogeneous-integration-challenges-and-emerging-solutions-to-support-2-5d-and-3d-advanced-packaging/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteantecs-november-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221115T080000
DTEND;TZID=Europe/Berlin:20221118T170000
DTSTAMP:20221017T181636Z
CREATED:20221017T181636Z
LAST-MODIFIED:20221017T181636Z
UID:5312-1668499200-1668790800@marketingeda.com
SUMMARY:Semicon Europa
DESCRIPTION:SEMICON Europa 2022 is co-located with electronica in Munich\, Germany creating the strongest single event for electronics manufacturing in Europe\, and broadening the range of attendees across the electronics chain. \n– Top-notch Keynotes\n– Market Trends\n– Exhibition\n– Networking\n– Advanced Packaging Forum / Fab Management Forum\n– ITF Beyond 5G -powered by imec\n– Smart Manufacturing / Mobility / MedTech\n– Workforce Development and many more!
URL:https://marketingeda.com/event/semicon-europa/
LOCATION:Messe Munchen\, Messegelände\, Munich\, 81823\, Germany
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DB580CC6-16B1-4DBA-A5A3-38C39181F164-e1666030379723.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20221113T080000
DTEND;TZID=America/Chicago:20221118T170000
DTSTAMP:20221102T200714Z
CREATED:20221102T200714Z
LAST-MODIFIED:20221102T200714Z
UID:5362-1668326400-1668790800@marketingeda.com
SUMMARY:Super Computing 2022
DESCRIPTION:Come see your friends and colleagues\, explore incredible learning experiences in HPC\, and walk the exhibit floor! There are several registration options available. Choose the one that’s right for you. We look forward to seeing you in Dallas or via the Digital Experience.
URL:https://marketingeda.com/event/super-computing-2022/
LOCATION:Kay Bailey Hutchison Convention Center\, 650 S Griffin Street\, Dallas\, TX\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SC22.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Amsterdam:20221108T090000
DTEND;TZID=Europe/Amsterdam:20221108T180000
DTSTAMP:20221104T201045Z
CREATED:20221104T201045Z
LAST-MODIFIED:20221104T201045Z
UID:5373-1667898000-1667930400@marketingeda.com
SUMMARY:TSMC 2022 EU OIP Ecosystem Forum
DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum!
URL:https://marketingeda.com/event/tsmc-2022-eu-oip-ecosystem-forum/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2022-EU.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221102T110000
DTEND;TZID=America/Los_Angeles:20221102T120000
DTSTAMP:20221026T175641Z
CREATED:20221026T175641Z
LAST-MODIFIED:20221026T175641Z
UID:5342-1667386800-1667390400@marketingeda.com
SUMMARY:How CXL Technology will Revolutionize the Data Center
DESCRIPTION:Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly\, the need for more bandwidth and capacity continues to rise. \nJoin us for a live webinar next week on November 2nd and hear IDC guest speaker\, Jeff Janukowicz\, and Rambus’ Mark Orthodoxou discuss how CXL technology can address the compute\, memory and storage needs of a wide range of workloads. Listen as they set the market context\, describe use cases and provide adoption expectations for the industry. \nIn this webinar\, you’ll learn about: \n\nThe evolution from CXL 1.1\, to 2.0\, to 3.0\nHow CXL builds on PCI Express technology\nMemory expansion\nMemory pooling\nFabric switching\nThe expertise needed for the successful implementation of CXL solutions\n\nCan’t attend live? Register anyway and get a link to an on-demand replay. \nSpeakers\nJeff Janukowicz\nResearch Vice President\, Solid State Drives and Enabling Technologies\n \nJeff Janukowicz is a Research Vice President at IDC where he provides insight and analysis on the SSD market for the Client PC\, Enterprise Data Center\, and Cloud market segments. In this role\, Jeff provides expert opinion\, in-depth market research\, and strategic analysis on the dynamics\, trends\, and opportunities facing the industry. His research includes market forecasts\, market share reports\, and technology trends of clients\, investor\, suppliers\, and manufacturers. \nMark Orthodoxou\nVice President of Strategic Marketing\, Interconnect SoCs\, Rambus\nMark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Interconnects Business Unit. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines\, including enterprise storage\, data center compute\, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip\, Microsemi\, PMC-Sierra\, and IDT.
URL:https://marketingeda.com/event/how-cxl-technology-will-revolutionize-the-data-center/
LOCATION:Koto CIty
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-November-2-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221101T080000
DTEND;TZID=America/Los_Angeles:20221102T170000
DTSTAMP:20221012T185511Z
CREATED:20221012T185511Z
LAST-MODIFIED:20221012T185511Z
UID:5300-1667289600-1667408400@marketingeda.com
SUMMARY:Linley Fall Processor Conference 2022
DESCRIPTION:TechInsights is pleased to announce that the Linley Fall Processor Conference powered by TechInsights – a Hybrid Event\, will be held in Santa Clara\, California on November 1-2\, 2022. If you cannot attend in person\, tune in to our virtual livestream or watch the presentations OnDemand at your convenience. \nPresentations will address processors and IP cores for AI applications\, embedded\, data-center\, automotive\, and server designs. In-person attendees will be able to hear presentations and interact with the speakers during Q&A\, lunch\, and the networking reception. \nAnalyst and Industry Keynotes\nLinley Gwennap\, principal analyst\, TechInsights\, will open the conference with an overview of the latest market\, technologies\, equipment-design\, and silicon trends. We will also feature a keynote from another industry leader. \nIn-Depth Technical Sessions\nUnlike many conferences\, we ensure that the presentations deliver real technical content\, not marketing hype. We are the conference of choice for many companies who announce new products or make technology disclosures. \nTechInsights analysts carefully select session topics and choose leading speakers who are experts in their fields. In addition\, the analysts ensure that the content of the presentations are full of insightful\, technical information that will help attendees select the right components and systems for their next project. The program will feature talks and panel discussions covering a broad range of topics that will be announced later. \nWhy Attend\nTechInsights Processor Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear\, question\, and network with key providers of advanced technology products. \nThe Conferences analyze products and design strategies in a particular technology segment\, providing information that engineers can immediately use to improve their designs. The events feature in-depth technical presentations from our own analysts as well as leading technologists from the industry. This conference is intended for system designers\, chip designers\, software designers\, OEM/ODMs\, press\, and financial analysts. \nCovid-19 Policies and Precautions\nWe are working closely with the Hyatt Regency to reduce the risk of attending our in-person event. Individuals and their employers\, however\, must decide what level of risk is acceptable. For those unable to attend in person\, we offer our virtual livestream. \nAttendees will be required to provide proof of vaccination before receiving their conference badge. Consistent with local health orders\, masks are now recommended but not required. Policies are subject to change; we will update this page as needed.
URL:https://marketingeda.com/event/linley-fall-processor-conference-2022/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Linley-Fall-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221027T100000
DTEND;TZID=America/Los_Angeles:20221027T110000
DTSTAMP:20221022T002741Z
CREATED:20221022T002741Z
LAST-MODIFIED:20221022T002741Z
UID:5321-1666864800-1666868400@marketingeda.com
SUMMARY:Evaluating UCIe based multi-die architectures to meet timing and power constraints
DESCRIPTION:Multi-die architectures have evolved from proprietary to industry standard UCIe.  UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey\, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and verify use cases and optimize the power\, timing\, throughput and functionality.\n\nThis Webinar looks at the system-wide view of performance and power in a UCIe multi-die SOC. We will be showcasing processor\, data center and imaging use cases that combines various types of processing engines across PCIe and UCIe. This modeling effort will present the user with different performance and system architecture models and a guide on design aspects that optimizes for power efficiency\, low latency\, high bandwidth to transfer massive amounts of data\, and error-free operation. Simulating multi-die system architectures with large payloads and multiple streaming protocols can be done in minutes\, thus greatly expanding the usefulness of simulation.
URL:https://marketingeda.com/event/evaluating-ucie-based-multi-die-architectures-to-meet-timing-and-power-constraints/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221027T090000
DTEND;TZID=America/Los_Angeles:20221027T150000
DTSTAMP:20220912T184223Z
CREATED:20220912T184223Z
LAST-MODIFIED:20220912T184223Z
UID:5183-1666861200-1666882800@marketingeda.com
SUMMARY:Silvaco - SURGE\, North America
DESCRIPTION:Silvaco is pleased to invite you to join its annual Silvaco UseRs Global Event (SURGE)\, taking place virtually on October 27\, 2022. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \nEveryone that registers will be entered to win one of several $100 Amazon gift cards. \nAll attendees that complete the post-event survey will receive their choice of either an Amazon or Starbucks Gift Card and be entered to win a AfterShokz Wireless Bone Conduction Bluetooth Headphones. \n  \n\n\nAgenda\n\n\n\n\n\n\n\nTIME\nGENERAL SESSION\n\n\n9:00 AM\nWelcome and Introductions – Farhad Hayat\, Silvaco\, Inc.​\n\n\n9:20 AM​\nDr. Babak Taheri – CEO and Board Member\, Silvaco\, Inc.​\n\n\n9:40 AM​\nDesign and Optimization of Superconducting Circuits – Giovanni De Micheli\, École Polytechnique Fédérale de Lausanne (EPFL)\, Switzerland.\n\n\n10:00 AM​\nAnalysis of Multi Patterning Strategies and Control Techniques That Change The Baseline Capability of Manufacturing Printed Circuits – Anton deVilliers\, Fellow\, Vice President Technology Department\, Advanced Tool\, Patterning and 3D Logic Incubation\, Tokyo Electron Ltd.​\n\n\n\n\n\n\n\nTIME\nTCAD TRACK\n\n\n10:30 AM\nTCAD Simulation Update – Dr. Eric Guichard\, Silvaco​\, Inc.\n\n\n10:35 AM​\nRevised Mobility Model for Predictive TCAD Simulations of 4H-SiC – Hemant Dixit\, Ph.D.\, Research Scientist\, Wolfspeed\, Inc.​\n\n\n11:05 AM​\nTCAD as Key Enabler for Photodiode Design – Sungwon Kong\, Silvaco\, Inc.​\n\n\n11:35 AM​\nCustomer Presentation – Sumeet Pandey\, Micron​ (Title to be announced)\n\n\n12:00 PM\nLunch Break\n\n\n1:00 PM​\nBehavior of FinFET at Very Low Temperatures and Creation of Qubits – Sanam Moslemi-Tabrizi\, Hardware Engineer\, Ciena​\n\n\n1:20PM​\nPerformance Improvement for Cu Interconnects by SAM and ELD Technologies – Yuki Kikuchi\, Tokyo Electron Ltd.​\n\n\n1:40PM​\nLatest Quantum Transport Models for Atomistic Materials and Device Performance Predictions – Tillmann Kubis\, Purdue University​​\n\n\n2:00PM​\nAchieving Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution – Alexander Toifl\, Silvaco\, Inc.​\n\n\n2:25PM​\nAdvanced Flux Models in Victory Process: Low-Bias SF6 Etching and Thermal Atomic Layer Processing – Luiz Felipe Aguinsky\, Silvaco\, Inc. / TU Vienna​​\n\n\n\n\n\n\n\nTIME\nEDA TRACK\n\n\n10:30 AM​\nAnalog Custom Design Update – Thomas Blaesi\, Silvaco\, Inc.​\n\n\n10:40 AM​\nDevice Modeling – Bogdan Tudor\, Silvaco\, Inc.​\n\n\n11:00 AM​\nA Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations​​\n\n\n11:30 AM​\nCustomer Presentation – Mobile Semicondutor (Title and speaker to be announced)​\n\n\n12:00 PM​\nLunch Break\n\n\n1:00 PM​\nSmartDRC – Richard Lum\, MPics Innovations  (Title to be announced)\n\n\n1:30 PM​\nVarMan / VarMan XMA Variation and Yield Analysis – Silvaco Presentation ​​\n\n\n1:50 PM​\nJivaro Parasitic Reduction – Silvaco Presentation\n\n\n2:10 PM​\nViso Parasitic Analysis and Exploration – Silvaco Presentation ​\n\n\n\n\n\n\n\nTIME\nIP SESSION\n\n\n10:30 AM​\nDesign IP Solutions Update – Ben Louie\, Silvaco\, Inc.​\n\n\n10:45 AM​\nChallenges of Designing Quantum Computer SoCs – Jack Berg\,VP of Operations\, PsiQuantum​\n\n\n11:15 AM​\nImplementing Debug for I3C – Rajalakshmi Arumugompillai\, Silvaco\, Inc.​\n\n\n11:35 AM​\nLunch Break\n\n\n1:00 PM​\nHow to Transition from Obsolete Parts with Silvaco IP​ – Silvaco\, Inc.​\n\n\n1:30 PM​\nCustomer Presentation​ (Title and speaker to be announced)​​​\n\n\n2:00 PM​\nCello FinFET PDK Automation – Silvaco\, Inc.​
URL:https://marketingeda.com/event/silvaco-surge-north-america/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-October-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221026T090000
DTEND;TZID=America/Los_Angeles:20221026T183000
DTSTAMP:20221013T003013Z
CREATED:20221013T003013Z
LAST-MODIFIED:20221013T003013Z
UID:5303-1666774800-1666809000@marketingeda.com
SUMMARY:TSMC 2022 OIP - California
DESCRIPTION:Join the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! \nRegister Now\n\n\n\n\nLearn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum! \nYour health and safety are important to us. TSMC continues to monitor guidelines for health safety measures from the Centers for Disease Control and Prevention\, California Department of Public Health\, and the Santa Clara County Department of Public Health. TSMC will follow applicable federal\, state and local laws\, then adapt TSMC plans accordingly and share updates with you.
URL:https://marketingeda.com/event/tsmc-2022-oip-california/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Forum,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-OIP-2022-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221026T080000
DTEND;TZID=America/Los_Angeles:20221027T170000
DTSTAMP:20220816T192711Z
CREATED:20220816T192711Z
LAST-MODIFIED:20220816T192711Z
UID:5068-1666771200-1666890000@marketingeda.com
SUMMARY:Arm DevSummit
DESCRIPTION:After two years of virtual networking\, we’re thrilled to announce the return of Arm DevSummit in-person in October. As you’re a past attendee\, we’re delighted to welcome you to this milestone event. \nArm DevSummit is for people developing and deploying on Arm-based hardware. We want to give you\, the future builders\, the insight and edge to do your best work. Join us live and in person on October 26 – 27\, 2022 at the Palace of Fine Arts in San Francisco. \nDevelop and Deploy on Arm \nWe’re planning an action-packed two-day event to share ideas\, learn new skills and connect. And it’s all centered around helping you work on\, or get started on the Arm architecture: \n\nHands-on workshops\, limited capacity (1 per attendee)\nMasterclasses\nKeynotes\nChill and charge lounge\nMini theaters\nArm DevSummit party\nFree food and drinks\nOn-demand technical sessions\nCertificate of participation
URL:https://marketingeda.com/event/arm-devsummit/
LOCATION:Palace of Fine Arts\, 3601 Lyon Street\, San Francisco\, CA\, 94123\, United States
CATEGORIES:IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-October-26-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221018T100000
DTEND;TZID=America/Los_Angeles:20221018T180000
DTSTAMP:20221011T163924Z
CREATED:20220926T195009Z
LAST-MODIFIED:20221011T163924Z
UID:5236-1666087200-1666116000@marketingeda.com
SUMMARY:RISC-V Con
DESCRIPTION:In order to foster stronger collaboration on RISC-V across the computing industry\, RISC-V CON focuses on this disruptive technology\, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON\, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. \nSeventeen years in business and a Founding Premier member of RISC-V International\, Andes Technology is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions\, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP\, FPU\, Vector\, Linux\, superscalar\, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021\, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. \nBy bringing the leading companies in the RISC-V ecosystem together at RISC-V CON\, Andes aims to boost RISC-V adoption by collaborating with partners and customers to quickly bring innovative designs based on the open RISC-V ISA to market.
URL:https://marketingeda.com/event/risc-v-con/
LOCATION:DoubleTree Hotel\, 2050 Gateway Place\, San Jose\, CA\, 95110\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Con.png
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BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221017T080000
DTEND;TZID=Europe/Berlin:20221018T170000
DTSTAMP:20220916T202247Z
CREATED:20220916T202247Z
LAST-MODIFIED:20220916T202247Z
UID:5210-1665993600-1666112400@marketingeda.com
SUMMARY:SNUG Europe
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. Join your fellow engineers at SNUG to hear practical information you can use on your current projects and spark the inspiration to create Smart Everything. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \nWhy Attend? \n\n\n\n\n\n\nLearn from Synopsys keynote by Alessandra Costa\, Senior Vice President\, Applications Engineering\, Customer Success Group:\n“A Renaissance Era of Innovation – Then and Now”\nAttend tutorials for the latest advancements in Synopsys technology\nGain practical knowledge you can apply today\nHear users showcase best practices for design & verification challenges\nTechnical tracks include: Artificial Intelligence\, Automotive\, Cloud\, Custom Implementation & AMS\, Digital Implementation\, IP\, Low Power\, Signoff\, Test\, and Verification Continuum.\nNetwork with User & Synopsys experts in over 40+ Technical presentations\n\nKeynote Spotlight \nChip Design: Prerequisite for Europe’s Economic Sovereignty\nMonday\, October 17th at 13:15\nProfessor Dr.-Ing Wolfgang Nebel\nUniversität Oldenburg and Chairman of the Board\, edacentrum e.V. \nA Renaissance Era of Innovation – Then and Now\nTuesday\, October 18th at 9:15\nAlessandra Costa\nSVP\, Applications Engineering\, Customer Success Group\, Synopsys \nVirtual Development in Automotive E/E\nTuesday\, October 18th at 13:25\nRalph Schleifer\nHead of HW/SW CoDesign & Virtual Platforms\, CARIAD SE
URL:https://marketingeda.com/event/snug-europe/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221006T080000
DTEND;TZID=America/Los_Angeles:20221007T170000
DTSTAMP:20220920T032644Z
CREATED:20220920T032644Z
LAST-MODIFIED:20220920T032644Z
UID:5217-1665043200-1665162000@marketingeda.com
SUMMARY:2022 IEEE Electronic Design Process Symposium (EDPS)
DESCRIPTION:We are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. \n\n\nAbout this event\n\n\n\n2022 IEEE EDPS will be held on Oct 6 and Oct 7 2022 in Milpitas\, CA. \nWe have invited industry practitioners and leaders from academia to present their work in following areas: \n\nInnovative Designs and Design Techniques including Design Co-optimization\nDesign for Trust/Design for Security\nAdvanced Packaging\, 3DIC\nDesign Technology Co-optimization/Systems Technology Co-optimization\nMachine Learning/Artificial Intelligence in System Design and EDA\nSystem Reliability\n5G Infrastructure\nSilicon Photonics\nSmart Manufacturing\n\nCheck out 2022 IEEE EDPS website for additional program details. \nPlease join us at SEMI facility in Milpitas\, CA this fall! The registration includes refreshments\, breakfast\, and lunch on both days\, as well as dinner on Thursday!
URL:https://marketingeda.com/event/2022-ieee-electronic-design-process-symposium-edps/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20220928T080000
DTEND;TZID=Europe/Berlin:20220929T170000
DTSTAMP:20220914T220520Z
CREATED:20220914T220520Z
LAST-MODIFIED:20220914T220520Z
UID:5202-1664352000-1664470800@marketingeda.com
SUMMARY:Global Foundries Technology Summit - EMEA
DESCRIPTION:DAY 1 \nWednesday\, September 28\, 2022\nDoors Open 3:00pm CET \n  \nDINNER \nRestaurant KULTURWIRTSCHAFT\, 7pm – 10pm \n  \nDAY 2 \nThursday\, September 29\, 2022\nDoors Open 8:30am CET \n  \nEVENT LOCATION\nGlobalFoundries FAB 1\nWilschdorfer Landstrasse 101\n01109 Dresden\, Germany \n  \nWe are thrilled to welcome you to GF Technology Summit 2022. \nThis exclusive\, invitation-only event is in-person again\, located in GF’s FAB 1 facility! \n\n(RE)CONNECT Join CEO Tom Caulfield\, the GF team\, partners and industry experts for lively\, interactive discussions\nLEARN See how GF’s differentiated solutions and technology roadmap is delivering a new era of more\nDELIVER Collaborate\, partner and invest with GF to drive transformation in your industry\n\nWe look forward to seeing you (in-person!) at GTS 2022 EMEA. \n  \n\nYour Host  \n\n\n\n\n\n\n\n\n\n\nRuth Hernandez\nPartnerships & Business Development\, EMEA\nGlobalFoundries \n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n“We look forward to seeing you at GF Technology Summit 2022 EMEA\, in-person in Dresden\, on September 28 and 29. Join us to connect\, build relationships and discover new ways of collaborating and innovating.” \n 
URL:https://marketingeda.com/event/global-foundries-technology-summit-emea/
LOCATION:GlobalFoundries Fab 1\, Wilschdorfer Landstrasse 101\, Dresden\, 01109\, Germany
CATEGORIES:EDA,Foundry,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GF-September-28-29-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220927T080000
DTEND;TZID=America/Los_Angeles:20220927T170000
DTSTAMP:20220705T205605Z
CREATED:20220705T205605Z
LAST-MODIFIED:20220705T205605Z
UID:4906-1664265600-1664298000@marketingeda.com
SUMMARY:U.S. Executive Forum
DESCRIPTION:The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park\, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it’s too late. \nIn this unique and exclusive gathering\, thought leaders\, visionaries and innovators will shed light on the leadership role that the semiconductor industry must embrace to lead the world to a brighter future. Our program features some of the biggest names in semis fostering discussions on the industry’s most pressing issues. We hope you’ll join us at USEF 2022 for a day of leadership\, networking and enrichment. \nTraditionally\, even as semiconductors have been at the core of technological innovation and have changed the world beyond any other technology\, they have often been seen as a commodity and rarely in the spotlight or getting noticed. \nThis has all changed with the acceleration of digital transformation across industries and digitalization of work and life styles. Semiconductors are enabling new technologies and applications\, such as AI and IoT\, that have sparked a new wave of innovation for the industry. \nIn addition\, the implementation of 5G networks coincides with the growing demand for faster high-performance computing devices in the cloud and at the edge. \nIt is time for the industry to step up and show leadership in not only the technology field but also as a responsible global industry in areas of social impact. Climate change\, digital inequality\, diversity\, are all areas that the industry impacts and can show leadership in change. \nIn this unique and exclusive gathering\, thought leaders\, visionaries\, and innovators will shed light on the leadership role that the semiconductor industry needs to embrace and lead the world for a brighter future.
URL:https://marketingeda.com/event/u-s-executive-forum/
LOCATION:Koto CIty
CATEGORIES:EDA,Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA.-September-27-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220921T080000
DTEND;TZID=America/Los_Angeles:20220921T090000
DTSTAMP:20220826T190645Z
CREATED:20220826T190645Z
LAST-MODIFIED:20220826T190645Z
UID:5148-1663747200-1663750800@marketingeda.com
SUMMARY:Protocol and Memory Interface Verification in the Shrinking World of 3DIC
DESCRIPTION:Emerging 2.5D and 3DIC packaging technologies enable more design complexity\, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. \nPackaging technologies for 2.5D and 3DIC are becoming more available and more accessible\, with solutions addressing both the economics problem and the technical scalability challenge of building ever more complex SoCs. Standards are competing and emerging for interconnect protocols\, memory interfaces\, backplane-like and motherboard-like solutions within the IC package. \nIn this session\, we take a look at how to scale your verification capability to match those designs\, divide and conquer\, and use the right abstractions to equip projects with high quality and faster time-to-market\, and to equip design/verification engineers with scalable tools and solutions for verification. We will dive into the interface and memory protocols driving High Performance Compute innovation – PCIe Gen6\, CXL\, HBM3\, and future UCIe\, as well as important aspects of enabling scalability such as IDE security. \nWhat You Will Learn: \n\nThe challenges of verifying today’s advanced die-to-die interface and memory protocols\nThe broad portfolio of Siemens EDA Verification IP solutions available today\nHow our automated approach and flexible VIP can enable your productivity\n\nWho Should Attend: \n\nDesign & Verification Engineers & Managers and those interested in Protocol or Memory Interface verification\n\nProduct Covered: \n\nQuesta Verification IP solutions for protocols and memories including PCIe\, CXL\, IDE\, HBM\n\n\n\n\nSpeakers\n\n\n\n\nGordon Allan\nVerification IP Product Manager\nSiemens EDA\n\n\nGordon Allan is Product Manager for Verification IP at Siemens EDA. Gordon was one of the authors of Accellera UVM\, and he published the online UVM Cookbook on our Verification Academy site where it is appreciated by over 65\,000 engineers today. Prior to joining the EDA industry he gained over 18 years of Design/Verification experience leading & developing SoC and complex protocol IP/VIP projects in several semiconductor companies\, fabless startups\, EDA and system houses. Gordon is based in Silicon Valley. \n\n\n\n\n\nJoe Hupcey III\nVerification Product Technologist\nSiemens EDA\n\n\nJoe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley\, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens\, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies\, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing\, Joe worked as an electrical engineer in FPGA design\, EDA tools for FPGAs and ASICs\, and ASIC verification. Joe’s educational background includes BSEE\, MSEE\, and MBA degrees from Cornell University in Ithaca\, NY.
URL:https://marketingeda.com/event/protocol-and-memory-interface-verification-in-the-shrinking-world-of-3dic/
LOCATION:Koto CIty
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/004B10F7-2E47-47CD-9F94-8AD8C4D98D58.jpeg
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END:VCALENDAR