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BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221121T080000
DTEND;TZID=Europe/Berlin:20221122T170000
DTSTAMP:20221117T181728Z
CREATED:20221117T181728Z
LAST-MODIFIED:20221117T181728Z
UID:5419-1669017600-1669136400@marketingeda.com
SUMMARY:CadenceLIVE Europe 2022
DESCRIPTION:CadenceLIVE Europe 2022 will be held on November 21-22 at the Hilton Munich Park hotel. It will feature peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users\, developers\, and industry experts to connect\, share ideas\, and inspire design creativity. \nAttendees will have the opportunity to attend captivating keynotes and interesting user presentations and interact with Cadence experts\, peers\, and our sponsors in our Designer Expo. \nKeynote Speakers\n\n\n\n\n\n\nTom Beckley\nSenior Vice President and General Manager\, Custom IC & PCB Group\nCadence Design Systems \n\n\n\n\n\n\nDr. Oliver Wolst\nSenior Vice President\, Automotive Semiconductor Integrated Circuits\nRobert Bosch GmbH
URL:https://marketingeda.com/event/cadencelive-europe-2022/
LOCATION:Hilton Munich Park\, Am Tucherpark 7\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221116T090000
DTEND;TZID=America/New_York:20221116T140000
DTSTAMP:20221025T170717Z
CREATED:20221025T170717Z
LAST-MODIFIED:20221025T170717Z
UID:5332-1668589200-1668607200@marketingeda.com
SUMMARY:ASIP University Day 2022
DESCRIPTION:Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. Synopsys’ ASIP Designer is the market leading tool for ASIP design\, verification and programming\, and is used by leading companies around the globe with hundreds of successful projects to date. \nPlease join us at the ASIP University Day virtual event on Wednesday\, November 16\, 2022. In this informal forum you will be able to exchange ideas\, build up networks and gain first-hand insight about ASIP Designer directly from your peers. \n\nSynopsys will share its insight into market trends\, and provide a technical update on ASIP Designer along with reference examples. In addition\, several university partners will present results from their ASIP Design projects.
URL:https://marketingeda.com/event/asip-university-day-2022/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221116T090000
DTEND;TZID=America/Los_Angeles:20221116T100000
DTSTAMP:20221103T212350Z
CREATED:20221103T212350Z
LAST-MODIFIED:20221103T212350Z
UID:5370-1668589200-1668592800@marketingeda.com
SUMMARY:The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
DESCRIPTION:As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law\, it has created new challenges. \nJoin us on Wednesday\, November 16 at 9:00 a.m. PST for an informative webinar on The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging \nHear 3 unique perspectives on this growing market:\n\n\nStefan Chitoraga\, Technology and Market Analyst at Yole Développement will present the latest market insights on the adoption of chiplets and heterogeneous integration and will address what is driving advanced packaging toward 2.5D and 3D solutions.\nIgor Elkanovich\, CTO at Global Unichip Corp. (GUC) will discuss the GUC GLink™ chiplet interconnect\, including its architecture and roadmap; HBM3 memory interfaces; and will also highlight some of the 2.5D and 3D packaging challenges.\nNir Sever\, Senior Director of Business Development at proteanTecs will reveal silicon results from a GUC GLink chip\, which used D2D interconnect monitoring for comprehensive visibility and parametric lane grading.
URL:https://marketingeda.com/event/the-era-of-chiplets-and-heterogeneous-integration-challenges-and-emerging-solutions-to-support-2-5d-and-3d-advanced-packaging/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteantecs-november-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221115T080000
DTEND;TZID=Europe/Berlin:20221118T170000
DTSTAMP:20221017T181636Z
CREATED:20221017T181636Z
LAST-MODIFIED:20221017T181636Z
UID:5312-1668499200-1668790800@marketingeda.com
SUMMARY:Semicon Europa
DESCRIPTION:SEMICON Europa 2022 is co-located with electronica in Munich\, Germany creating the strongest single event for electronics manufacturing in Europe\, and broadening the range of attendees across the electronics chain. \n– Top-notch Keynotes\n– Market Trends\n– Exhibition\n– Networking\n– Advanced Packaging Forum / Fab Management Forum\n– ITF Beyond 5G -powered by imec\n– Smart Manufacturing / Mobility / MedTech\n– Workforce Development and many more!
URL:https://marketingeda.com/event/semicon-europa/
LOCATION:Messe Munchen\, Messegelände\, Munich\, 81823\, Germany
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DB580CC6-16B1-4DBA-A5A3-38C39181F164-e1666030379723.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20221113T080000
DTEND;TZID=America/Chicago:20221118T170000
DTSTAMP:20221102T200714Z
CREATED:20221102T200714Z
LAST-MODIFIED:20221102T200714Z
UID:5362-1668326400-1668790800@marketingeda.com
SUMMARY:Super Computing 2022
DESCRIPTION:Come see your friends and colleagues\, explore incredible learning experiences in HPC\, and walk the exhibit floor! There are several registration options available. Choose the one that’s right for you. We look forward to seeing you in Dallas or via the Digital Experience.
URL:https://marketingeda.com/event/super-computing-2022/
LOCATION:Kay Bailey Hutchison Convention Center\, 650 S Griffin Street\, Dallas\, TX\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SC22.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Amsterdam:20221108T090000
DTEND;TZID=Europe/Amsterdam:20221108T180000
DTSTAMP:20221104T201045Z
CREATED:20221104T201045Z
LAST-MODIFIED:20221104T201045Z
UID:5373-1667898000-1667930400@marketingeda.com
SUMMARY:TSMC 2022 EU OIP Ecosystem Forum
DESCRIPTION:Learn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum!
URL:https://marketingeda.com/event/tsmc-2022-eu-oip-ecosystem-forum/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2022-EU.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221102T110000
DTEND;TZID=America/Los_Angeles:20221102T120000
DTSTAMP:20221026T175641Z
CREATED:20221026T175641Z
LAST-MODIFIED:20221026T175641Z
UID:5342-1667386800-1667390400@marketingeda.com
SUMMARY:How CXL Technology will Revolutionize the Data Center
DESCRIPTION:Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly\, the need for more bandwidth and capacity continues to rise. \nJoin us for a live webinar next week on November 2nd and hear IDC guest speaker\, Jeff Janukowicz\, and Rambus’ Mark Orthodoxou discuss how CXL technology can address the compute\, memory and storage needs of a wide range of workloads. Listen as they set the market context\, describe use cases and provide adoption expectations for the industry. \nIn this webinar\, you’ll learn about: \n\nThe evolution from CXL 1.1\, to 2.0\, to 3.0\nHow CXL builds on PCI Express technology\nMemory expansion\nMemory pooling\nFabric switching\nThe expertise needed for the successful implementation of CXL solutions\n\nCan’t attend live? Register anyway and get a link to an on-demand replay. \nSpeakers\nJeff Janukowicz\nResearch Vice President\, Solid State Drives and Enabling Technologies\n \nJeff Janukowicz is a Research Vice President at IDC where he provides insight and analysis on the SSD market for the Client PC\, Enterprise Data Center\, and Cloud market segments. In this role\, Jeff provides expert opinion\, in-depth market research\, and strategic analysis on the dynamics\, trends\, and opportunities facing the industry. His research includes market forecasts\, market share reports\, and technology trends of clients\, investor\, suppliers\, and manufacturers. \nMark Orthodoxou\nVice President of Strategic Marketing\, Interconnect SoCs\, Rambus\nMark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Interconnects Business Unit. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines\, including enterprise storage\, data center compute\, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip\, Microsemi\, PMC-Sierra\, and IDT.
URL:https://marketingeda.com/event/how-cxl-technology-will-revolutionize-the-data-center/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-November-2-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221101T080000
DTEND;TZID=America/Los_Angeles:20221102T170000
DTSTAMP:20221012T185511Z
CREATED:20221012T185511Z
LAST-MODIFIED:20221012T185511Z
UID:5300-1667289600-1667408400@marketingeda.com
SUMMARY:Linley Fall Processor Conference 2022
DESCRIPTION:TechInsights is pleased to announce that the Linley Fall Processor Conference powered by TechInsights – a Hybrid Event\, will be held in Santa Clara\, California on November 1-2\, 2022. If you cannot attend in person\, tune in to our virtual livestream or watch the presentations OnDemand at your convenience. \nPresentations will address processors and IP cores for AI applications\, embedded\, data-center\, automotive\, and server designs. In-person attendees will be able to hear presentations and interact with the speakers during Q&A\, lunch\, and the networking reception. \nAnalyst and Industry Keynotes\nLinley Gwennap\, principal analyst\, TechInsights\, will open the conference with an overview of the latest market\, technologies\, equipment-design\, and silicon trends. We will also feature a keynote from another industry leader. \nIn-Depth Technical Sessions\nUnlike many conferences\, we ensure that the presentations deliver real technical content\, not marketing hype. We are the conference of choice for many companies who announce new products or make technology disclosures. \nTechInsights analysts carefully select session topics and choose leading speakers who are experts in their fields. In addition\, the analysts ensure that the content of the presentations are full of insightful\, technical information that will help attendees select the right components and systems for their next project. The program will feature talks and panel discussions covering a broad range of topics that will be announced later. \nWhy Attend\nTechInsights Processor Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear\, question\, and network with key providers of advanced technology products. \nThe Conferences analyze products and design strategies in a particular technology segment\, providing information that engineers can immediately use to improve their designs. The events feature in-depth technical presentations from our own analysts as well as leading technologists from the industry. This conference is intended for system designers\, chip designers\, software designers\, OEM/ODMs\, press\, and financial analysts. \nCovid-19 Policies and Precautions\nWe are working closely with the Hyatt Regency to reduce the risk of attending our in-person event. Individuals and their employers\, however\, must decide what level of risk is acceptable. For those unable to attend in person\, we offer our virtual livestream. \nAttendees will be required to provide proof of vaccination before receiving their conference badge. Consistent with local health orders\, masks are now recommended but not required. Policies are subject to change; we will update this page as needed.
URL:https://marketingeda.com/event/linley-fall-processor-conference-2022/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Linley-Fall-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221027T100000
DTEND;TZID=America/Los_Angeles:20221027T110000
DTSTAMP:20221022T002741Z
CREATED:20221022T002741Z
LAST-MODIFIED:20221022T002741Z
UID:5321-1666864800-1666868400@marketingeda.com
SUMMARY:Evaluating UCIe based multi-die architectures to meet timing and power constraints
DESCRIPTION:Multi-die architectures have evolved from proprietary to industry standard UCIe.  UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey\, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and verify use cases and optimize the power\, timing\, throughput and functionality.\n\nThis Webinar looks at the system-wide view of performance and power in a UCIe multi-die SOC. We will be showcasing processor\, data center and imaging use cases that combines various types of processing engines across PCIe and UCIe. This modeling effort will present the user with different performance and system architecture models and a guide on design aspects that optimizes for power efficiency\, low latency\, high bandwidth to transfer massive amounts of data\, and error-free operation. Simulating multi-die system architectures with large payloads and multiple streaming protocols can be done in minutes\, thus greatly expanding the usefulness of simulation.
URL:https://marketingeda.com/event/evaluating-ucie-based-multi-die-architectures-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221027T090000
DTEND;TZID=America/Los_Angeles:20221027T150000
DTSTAMP:20220912T184223Z
CREATED:20220912T184223Z
LAST-MODIFIED:20220912T184223Z
UID:5183-1666861200-1666882800@marketingeda.com
SUMMARY:Silvaco - SURGE\, North America
DESCRIPTION:Silvaco is pleased to invite you to join its annual Silvaco UseRs Global Event (SURGE)\, taking place virtually on October 27\, 2022. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \nEveryone that registers will be entered to win one of several $100 Amazon gift cards. \nAll attendees that complete the post-event survey will receive their choice of either an Amazon or Starbucks Gift Card and be entered to win a AfterShokz Wireless Bone Conduction Bluetooth Headphones. \n  \n\n\nAgenda\n\n\n\n\n\n\n\nTIME\nGENERAL SESSION\n\n\n9:00 AM\nWelcome and Introductions – Farhad Hayat\, Silvaco\, Inc.​\n\n\n9:20 AM​\nDr. Babak Taheri – CEO and Board Member\, Silvaco\, Inc.​\n\n\n9:40 AM​\nDesign and Optimization of Superconducting Circuits – Giovanni De Micheli\, École Polytechnique Fédérale de Lausanne (EPFL)\, Switzerland.\n\n\n10:00 AM​\nAnalysis of Multi Patterning Strategies and Control Techniques That Change The Baseline Capability of Manufacturing Printed Circuits – Anton deVilliers\, Fellow\, Vice President Technology Department\, Advanced Tool\, Patterning and 3D Logic Incubation\, Tokyo Electron Ltd.​\n\n\n\n\n\n\n\nTIME\nTCAD TRACK\n\n\n10:30 AM\nTCAD Simulation Update – Dr. Eric Guichard\, Silvaco​\, Inc.\n\n\n10:35 AM​\nRevised Mobility Model for Predictive TCAD Simulations of 4H-SiC – Hemant Dixit\, Ph.D.\, Research Scientist\, Wolfspeed\, Inc.​\n\n\n11:05 AM​\nTCAD as Key Enabler for Photodiode Design – Sungwon Kong\, Silvaco\, Inc.​\n\n\n11:35 AM​\nCustomer Presentation – Sumeet Pandey\, Micron​ (Title to be announced)\n\n\n12:00 PM\nLunch Break\n\n\n1:00 PM​\nBehavior of FinFET at Very Low Temperatures and Creation of Qubits – Sanam Moslemi-Tabrizi\, Hardware Engineer\, Ciena​\n\n\n1:20PM​\nPerformance Improvement for Cu Interconnects by SAM and ELD Technologies – Yuki Kikuchi\, Tokyo Electron Ltd.​\n\n\n1:40PM​\nLatest Quantum Transport Models for Atomistic Materials and Device Performance Predictions – Tillmann Kubis\, Purdue University​​\n\n\n2:00PM​\nAchieving Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution – Alexander Toifl\, Silvaco\, Inc.​\n\n\n2:25PM​\nAdvanced Flux Models in Victory Process: Low-Bias SF6 Etching and Thermal Atomic Layer Processing – Luiz Felipe Aguinsky\, Silvaco\, Inc. / TU Vienna​​\n\n\n\n\n\n\n\nTIME\nEDA TRACK\n\n\n10:30 AM​\nAnalog Custom Design Update – Thomas Blaesi\, Silvaco\, Inc.​\n\n\n10:40 AM​\nDevice Modeling – Bogdan Tudor\, Silvaco\, Inc.​\n\n\n11:00 AM​\nA Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations​​\n\n\n11:30 AM​\nCustomer Presentation – Mobile Semicondutor (Title and speaker to be announced)​\n\n\n12:00 PM​\nLunch Break\n\n\n1:00 PM​\nSmartDRC – Richard Lum\, MPics Innovations  (Title to be announced)\n\n\n1:30 PM​\nVarMan / VarMan XMA Variation and Yield Analysis – Silvaco Presentation ​​\n\n\n1:50 PM​\nJivaro Parasitic Reduction – Silvaco Presentation\n\n\n2:10 PM​\nViso Parasitic Analysis and Exploration – Silvaco Presentation ​\n\n\n\n\n\n\n\nTIME\nIP SESSION\n\n\n10:30 AM​\nDesign IP Solutions Update – Ben Louie\, Silvaco\, Inc.​\n\n\n10:45 AM​\nChallenges of Designing Quantum Computer SoCs – Jack Berg\,VP of Operations\, PsiQuantum​\n\n\n11:15 AM​\nImplementing Debug for I3C – Rajalakshmi Arumugompillai\, Silvaco\, Inc.​\n\n\n11:35 AM​\nLunch Break\n\n\n1:00 PM​\nHow to Transition from Obsolete Parts with Silvaco IP​ – Silvaco\, Inc.​\n\n\n1:30 PM​\nCustomer Presentation​ (Title and speaker to be announced)​​​\n\n\n2:00 PM​\nCello FinFET PDK Automation – Silvaco\, Inc.​
URL:https://marketingeda.com/event/silvaco-surge-north-america/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-October-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221026T090000
DTEND;TZID=America/Los_Angeles:20221026T183000
DTSTAMP:20221013T003013Z
CREATED:20221013T003013Z
LAST-MODIFIED:20221013T003013Z
UID:5303-1666774800-1666809000@marketingeda.com
SUMMARY:TSMC 2022 OIP - California
DESCRIPTION:Join the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! \nRegister Now\n\n\n\n\nLearn About:\n\nEmerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E\, N4/N4P\, N5/N5A\, N6/N7\, N12e\, N22\, and 28eF technologies\nLatest 3DIC chip stacking and advanced packaging processes\, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications\nUpdated design solutions for specialty technologies enabling ultra-low voltage\, analog migration\, mmWave RF\, and automotive designs targeting automotive and IoT designs\nEcosystem-specific TSMC reference flow implementations\, P& R optimization\, machine learning to improve design quality and productivity\, and cloud-based design solutions\nSuccessful\, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers\n\nFor more information on the TSMC OIP Ecosystem Forum\, e-mail us at: tsmcevents@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC OIP Ecosystem Forum! \nYour health and safety are important to us. TSMC continues to monitor guidelines for health safety measures from the Centers for Disease Control and Prevention\, California Department of Public Health\, and the Santa Clara County Department of Public Health. TSMC will follow applicable federal\, state and local laws\, then adapt TSMC plans accordingly and share updates with you.
URL:https://marketingeda.com/event/tsmc-2022-oip-california/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Forum,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-OIP-2022-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221026T080000
DTEND;TZID=America/Los_Angeles:20221027T170000
DTSTAMP:20220816T192711Z
CREATED:20220816T192711Z
LAST-MODIFIED:20220816T192711Z
UID:5068-1666771200-1666890000@marketingeda.com
SUMMARY:Arm DevSummit
DESCRIPTION:After two years of virtual networking\, we’re thrilled to announce the return of Arm DevSummit in-person in October. As you’re a past attendee\, we’re delighted to welcome you to this milestone event. \nArm DevSummit is for people developing and deploying on Arm-based hardware. We want to give you\, the future builders\, the insight and edge to do your best work. Join us live and in person on October 26 – 27\, 2022 at the Palace of Fine Arts in San Francisco. \nDevelop and Deploy on Arm \nWe’re planning an action-packed two-day event to share ideas\, learn new skills and connect. And it’s all centered around helping you work on\, or get started on the Arm architecture: \n\nHands-on workshops\, limited capacity (1 per attendee)\nMasterclasses\nKeynotes\nChill and charge lounge\nMini theaters\nArm DevSummit party\nFree food and drinks\nOn-demand technical sessions\nCertificate of participation
URL:https://marketingeda.com/event/arm-devsummit/
LOCATION:Palace of Fine Arts\, 3601 Lyon Street\, San Francisco\, CA\, 94123\, United States
CATEGORIES:IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-October-26-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221018T100000
DTEND;TZID=America/Los_Angeles:20221018T180000
DTSTAMP:20221011T163924Z
CREATED:20220926T195009Z
LAST-MODIFIED:20221011T163924Z
UID:5236-1666087200-1666116000@marketingeda.com
SUMMARY:RISC-V Con
DESCRIPTION:In order to foster stronger collaboration on RISC-V across the computing industry\, RISC-V CON focuses on this disruptive technology\, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON\, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. \nSeventeen years in business and a Founding Premier member of RISC-V International\, Andes Technology is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions\, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP\, FPU\, Vector\, Linux\, superscalar\, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021\, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. \nBy bringing the leading companies in the RISC-V ecosystem together at RISC-V CON\, Andes aims to boost RISC-V adoption by collaborating with partners and customers to quickly bring innovative designs based on the open RISC-V ISA to market.
URL:https://marketingeda.com/event/risc-v-con/
LOCATION:DoubleTree Hotel\, 2050 Gateway Place\, San Jose\, CA\, 95110\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Con.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221017T080000
DTEND;TZID=Europe/Berlin:20221018T170000
DTSTAMP:20220916T202247Z
CREATED:20220916T202247Z
LAST-MODIFIED:20220916T202247Z
UID:5210-1665993600-1666112400@marketingeda.com
SUMMARY:SNUG Europe
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. Join your fellow engineers at SNUG to hear practical information you can use on your current projects and spark the inspiration to create Smart Everything. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \nWhy Attend? \n\n\n\n\n\n\nLearn from Synopsys keynote by Alessandra Costa\, Senior Vice President\, Applications Engineering\, Customer Success Group:\n“A Renaissance Era of Innovation – Then and Now”\nAttend tutorials for the latest advancements in Synopsys technology\nGain practical knowledge you can apply today\nHear users showcase best practices for design & verification challenges\nTechnical tracks include: Artificial Intelligence\, Automotive\, Cloud\, Custom Implementation & AMS\, Digital Implementation\, IP\, Low Power\, Signoff\, Test\, and Verification Continuum.\nNetwork with User & Synopsys experts in over 40+ Technical presentations\n\nKeynote Spotlight \nChip Design: Prerequisite for Europe’s Economic Sovereignty\nMonday\, October 17th at 13:15\nProfessor Dr.-Ing Wolfgang Nebel\nUniversität Oldenburg and Chairman of the Board\, edacentrum e.V. \nA Renaissance Era of Innovation – Then and Now\nTuesday\, October 18th at 9:15\nAlessandra Costa\nSVP\, Applications Engineering\, Customer Success Group\, Synopsys \nVirtual Development in Automotive E/E\nTuesday\, October 18th at 13:25\nRalph Schleifer\nHead of HW/SW CoDesign & Virtual Platforms\, CARIAD SE
URL:https://marketingeda.com/event/snug-europe/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221006T080000
DTEND;TZID=America/Los_Angeles:20221007T170000
DTSTAMP:20220920T032644Z
CREATED:20220920T032644Z
LAST-MODIFIED:20220920T032644Z
UID:5217-1665043200-1665162000@marketingeda.com
SUMMARY:2022 IEEE Electronic Design Process Symposium (EDPS)
DESCRIPTION:We are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. \n\n\nAbout this event\n\n\n\n2022 IEEE EDPS will be held on Oct 6 and Oct 7 2022 in Milpitas\, CA. \nWe have invited industry practitioners and leaders from academia to present their work in following areas: \n\nInnovative Designs and Design Techniques including Design Co-optimization\nDesign for Trust/Design for Security\nAdvanced Packaging\, 3DIC\nDesign Technology Co-optimization/Systems Technology Co-optimization\nMachine Learning/Artificial Intelligence in System Design and EDA\nSystem Reliability\n5G Infrastructure\nSilicon Photonics\nSmart Manufacturing\n\nCheck out 2022 IEEE EDPS website for additional program details. \nPlease join us at SEMI facility in Milpitas\, CA this fall! The registration includes refreshments\, breakfast\, and lunch on both days\, as well as dinner on Thursday!
URL:https://marketingeda.com/event/2022-ieee-electronic-design-process-symposium-edps/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20220928T080000
DTEND;TZID=Europe/Berlin:20220929T170000
DTSTAMP:20220914T220520Z
CREATED:20220914T220520Z
LAST-MODIFIED:20220914T220520Z
UID:5202-1664352000-1664470800@marketingeda.com
SUMMARY:Global Foundries Technology Summit - EMEA
DESCRIPTION:DAY 1 \nWednesday\, September 28\, 2022\nDoors Open 3:00pm CET \n  \nDINNER \nRestaurant KULTURWIRTSCHAFT\, 7pm – 10pm \n  \nDAY 2 \nThursday\, September 29\, 2022\nDoors Open 8:30am CET \n  \nEVENT LOCATION\nGlobalFoundries FAB 1\nWilschdorfer Landstrasse 101\n01109 Dresden\, Germany \n  \nWe are thrilled to welcome you to GF Technology Summit 2022. \nThis exclusive\, invitation-only event is in-person again\, located in GF’s FAB 1 facility! \n\n(RE)CONNECT Join CEO Tom Caulfield\, the GF team\, partners and industry experts for lively\, interactive discussions\nLEARN See how GF’s differentiated solutions and technology roadmap is delivering a new era of more\nDELIVER Collaborate\, partner and invest with GF to drive transformation in your industry\n\nWe look forward to seeing you (in-person!) at GTS 2022 EMEA. \n  \n\nYour Host  \n\n\n\n\n\n\n\n\n\n\nRuth Hernandez\nPartnerships & Business Development\, EMEA\nGlobalFoundries \n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n“We look forward to seeing you at GF Technology Summit 2022 EMEA\, in-person in Dresden\, on September 28 and 29. Join us to connect\, build relationships and discover new ways of collaborating and innovating.” \n 
URL:https://marketingeda.com/event/global-foundries-technology-summit-emea/
LOCATION:GlobalFoundries Fab 1\, Wilschdorfer Landstrasse 101\, Dresden\, 01109\, Germany
CATEGORIES:EDA,Foundry,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GF-September-28-29-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220927T080000
DTEND;TZID=America/Los_Angeles:20220927T170000
DTSTAMP:20220705T205605Z
CREATED:20220705T205605Z
LAST-MODIFIED:20220705T205605Z
UID:4906-1664265600-1664298000@marketingeda.com
SUMMARY:U.S. Executive Forum
DESCRIPTION:The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park\, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it’s too late. \nIn this unique and exclusive gathering\, thought leaders\, visionaries and innovators will shed light on the leadership role that the semiconductor industry must embrace to lead the world to a brighter future. Our program features some of the biggest names in semis fostering discussions on the industry’s most pressing issues. We hope you’ll join us at USEF 2022 for a day of leadership\, networking and enrichment. \nTraditionally\, even as semiconductors have been at the core of technological innovation and have changed the world beyond any other technology\, they have often been seen as a commodity and rarely in the spotlight or getting noticed. \nThis has all changed with the acceleration of digital transformation across industries and digitalization of work and life styles. Semiconductors are enabling new technologies and applications\, such as AI and IoT\, that have sparked a new wave of innovation for the industry. \nIn addition\, the implementation of 5G networks coincides with the growing demand for faster high-performance computing devices in the cloud and at the edge. \nIt is time for the industry to step up and show leadership in not only the technology field but also as a responsible global industry in areas of social impact. Climate change\, digital inequality\, diversity\, are all areas that the industry impacts and can show leadership in change. \nIn this unique and exclusive gathering\, thought leaders\, visionaries\, and innovators will shed light on the leadership role that the semiconductor industry needs to embrace and lead the world for a brighter future.
URL:https://marketingeda.com/event/u-s-executive-forum/
CATEGORIES:EDA,Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA.-September-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220921T080000
DTEND;TZID=America/Los_Angeles:20220921T090000
DTSTAMP:20220826T190645Z
CREATED:20220826T190645Z
LAST-MODIFIED:20220826T190645Z
UID:5148-1663747200-1663750800@marketingeda.com
SUMMARY:Protocol and Memory Interface Verification in the Shrinking World of 3DIC
DESCRIPTION:Emerging 2.5D and 3DIC packaging technologies enable more design complexity\, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. \nPackaging technologies for 2.5D and 3DIC are becoming more available and more accessible\, with solutions addressing both the economics problem and the technical scalability challenge of building ever more complex SoCs. Standards are competing and emerging for interconnect protocols\, memory interfaces\, backplane-like and motherboard-like solutions within the IC package. \nIn this session\, we take a look at how to scale your verification capability to match those designs\, divide and conquer\, and use the right abstractions to equip projects with high quality and faster time-to-market\, and to equip design/verification engineers with scalable tools and solutions for verification. We will dive into the interface and memory protocols driving High Performance Compute innovation – PCIe Gen6\, CXL\, HBM3\, and future UCIe\, as well as important aspects of enabling scalability such as IDE security. \nWhat You Will Learn: \n\nThe challenges of verifying today’s advanced die-to-die interface and memory protocols\nThe broad portfolio of Siemens EDA Verification IP solutions available today\nHow our automated approach and flexible VIP can enable your productivity\n\nWho Should Attend: \n\nDesign & Verification Engineers & Managers and those interested in Protocol or Memory Interface verification\n\nProduct Covered: \n\nQuesta Verification IP solutions for protocols and memories including PCIe\, CXL\, IDE\, HBM\n\n\n\n\nSpeakers\n\n\n\n\nGordon Allan\nVerification IP Product Manager\nSiemens EDA\n\n\nGordon Allan is Product Manager for Verification IP at Siemens EDA. Gordon was one of the authors of Accellera UVM\, and he published the online UVM Cookbook on our Verification Academy site where it is appreciated by over 65\,000 engineers today. Prior to joining the EDA industry he gained over 18 years of Design/Verification experience leading & developing SoC and complex protocol IP/VIP projects in several semiconductor companies\, fabless startups\, EDA and system houses. Gordon is based in Silicon Valley. \n\n\n\n\n\nJoe Hupcey III\nVerification Product Technologist\nSiemens EDA\n\n\nJoe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley\, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens\, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies\, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing\, Joe worked as an electrical engineer in FPGA design\, EDA tools for FPGAs and ASICs\, and ASIC verification. Joe’s educational background includes BSEE\, MSEE\, and MBA degrees from Cornell University in Ithaca\, NY.
URL:https://marketingeda.com/event/protocol-and-memory-interface-verification-in-the-shrinking-world-of-3dic/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/004B10F7-2E47-47CD-9F94-8AD8C4D98D58.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220920T080000
DTEND;TZID=America/Los_Angeles:20220921T170000
DTSTAMP:20220822T190157Z
CREATED:20220822T190157Z
LAST-MODIFIED:20220822T190157Z
UID:5119-1663660800-1663779600@marketingeda.com
SUMMARY:MIPI DevCon 2022
DESCRIPTION:MIPI DevCon 2022 will be held 20-21 September\, offering developers and implementers of MIPI specifications a forum for training\, education and networking. The virtual event will feature conference presentations by MIPI experts and working group leaders sharing use cases\, implementation experiences and application examples – all from a technical perspective. \nOpen to all Alliance members and industry representatives\, MIPI DevCon is targeted towards developers\, system architects and engineering managers\, including design\, test\, application\, system\, hardware\, firmware and other engineers. \n\nPrevious MIPI DevCon Sessions\nInterested in learning more about MIPI specifiations and their implementations in mobile and beyond? Presentations from past MIPI DevCons are available in the MIPI Knowledge Library. \nVisit the MIPI DevCon 2021 Agenda page to learn more about last year’s sessions\, access the recordings and download all presentations (including Japanese\, Korean and Chinese translations of the Asia track sessions)\, or visit our YouTube page for access to all DevCon session and demo recordings\, along with other MIPI Alliance educational videos.
URL:https://marketingeda.com/event/mipi-devcon-2022/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MIPI-DevCon-2022-Learn-More-1024x576-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220920T080000
DTEND;TZID=Asia/Jerusalem:20220920T170000
DTSTAMP:20220817T222547Z
CREATED:20220817T222547Z
LAST-MODIFIED:20220817T222547Z
UID:5092-1663660800-1663693200@marketingeda.com
SUMMARY:SNUG Israel 2022
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. By attending SNUG Israel\, you gain knowledge to use on current projects and discover ideas to spark future innovations. \nSNUG is offered at no charge to Synopsys customers. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nLearn from Keynote\, Shankar Krishnamoorthy – GM\, Silicon Realization Group\, Synopsys \n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\nGain practical knowledge you can apply today \n\n\n\n\n\nHear users showcase best practices for design & verification challenges \n\n\n\n\n\n\n\n\n\n\nStay connected and inspired by industry keynotes \n\n\n\n\n\n\n\n\n\n\nNetwork with User & Synopsys experts in over 30+ Technical presentations
URL:https://marketingeda.com/event/snug-israel-2022/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/1C26AE4C-66F9-4EB4-934D-F1F55430B1A0-e1660774735313.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20220919T080000
DTEND;TZID=Europe/Rome:20220922T170000
DTSTAMP:20220919T015335Z
CREATED:20220919T015335Z
LAST-MODIFIED:20220919T015335Z
UID:5213-1663574400-1663866000@marketingeda.com
SUMMARY:ESSCIRC 2022
DESCRIPTION:The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore\, more than ever before\, a deeper interaction among technologists\, device experts\, IC designers and system designers is necessary. \nWhile keeping separate Technical Program Committees\, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions\, regardless to which conference they belong. \n\n​ \nCONFERENCE HIGHLIGHTS \n\n\n4 joint keynote presentations \n\n\n3 ESSDERC keynote presentations \n\n\n3 ESSCIRC keynote presentations \n\n\nInvited papers with overall coverage of all aspects of advanced devices and circuits \n\n\nPresentation of IEEE and ESSDERC/ESSCIRC Awards \n\n\nESSDERC/ESSCIRC Welcome Reception on Tuesday\, September 20\, 2022 \n\n\nESSDERC/ESSCIRC Gala Dinner on Wednesday\, September 21\, 2022 \n\n\nTutorials and workshops \n\n\n\nThe venue of the conference events\, including workshops and tutorials\, will be at the University of Milan-Bicocca (Milan\, IT)\, that is well connected (metro\, bus\, train with Milan downtown). \nThe working language of the conference is English. \n​ \n​ \nBEST PAPER AWARDS \nPapers presented at the conference will be considered for the ”Best Paper Award” and ”Best Young Scientist Paper Award”. \nThe selection will be based on the results of the paper selection process and the judgment of the conference participants. \nThe 2022 Award Ceremony will take place during ESSDERC/ESSCIRC 2023. \n\n​ \nCONFERENCE TARGET AND EVOLUTION \nESSDERC and ESSCIRC have evolved over the last years to follow recent R&D device\, circuit and system fast-growing topics. Besides the traditional ESSDERC and ESSCIRC tracks\, a number of JOINT tracks have been introduced\, to encourage and facilitate interactions between circuit\, system and device researchers. \n\nESSDERC/ESSCIRC encourages submissions in all areas of solid-state devices\, circuits and systems\, with special emphasis on: \n\n\nAnalog\, Power and RF Devices \n\n\nElectron Device Simulation and Modeling \n\n\nAdvanced Technology\, Processes and Materials \n\n\nNeuromorphic Computing\, Advanced Memories\, Al Accelerators\, in-Memory-Computing\, Security \n\n\nAdvanced Computing Devices and Circuits: Advanced CMOS\, Post-CMOS\, Quantum Computing \n\n\nSensors\, MEMS\, Bioelectronics\, Biomedical Electronics\, Optoelectronics\, Display and Imaging \n\n\nAnalog Circuits \n\n\nData Converters \n\n\nRF and mm-Wave Circuits \n\n\nFrequency Generation \n\n\nWireless and Wireline Interfaces \n\n\nIntegrated Power Electronics and Power Management \n\n\nDigital Circuits & Systems \n\n\n\nStudent papers are welcome and encouraged. \n\n​ \nPAPERS SUBMISSION \nPapers submitted for review must clearly state: \n\n\nThe purpose of the work \n\n\nHow and to what extent it advances the state-of-the art \n\n\nSpecific results and their impact \n\n\nOnly material that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. \nManuscript guidelines\, as well as instructions on how to electronically submit papers will be available in the 1st Call for Papers and on this website. \nPapers must not exceed four A4 pages with all illustrations and references included. \n\nPapers submission deadline: April\, 12\, 2022
URL:https://marketingeda.com/event/esscirc-2022/
LOCATION:Università degli Studi di MILANO – BICOCCA\, Viale Piero e Alberto Pirelli\, 22\, Milano\, 20126\, Italy
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESSCIRC-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220914T080000
DTEND;TZID=America/New_York:20220914T183000
DTSTAMP:20220817T161455Z
CREATED:20220817T161455Z
LAST-MODIFIED:20220817T161455Z
UID:5072-1663142400-1663180200@marketingeda.com
SUMMARY:CadenceLIVE Boston 2022
DESCRIPTION:CadenceLIVE Boston 2022 is back\, this time in person and will be held on September 14 at the Boston Marriott Burlington. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users\, developers\, and industry experts together to network\, share ideas\, and inspire design creativity. \nAttendees have the opportunity to attend captivating keynotes\, watch interesting user presentations\, and learn new ways to solve your design challenges from industry leaders and Cadence experts. \n\nCadence®  products\, solutions\, flows\, and techniques will be featured at the conference in the following areas: \n\nSystem Design Analysis\nCustom IC / Mixed-Signal RF\nDigital Design and Signoff\n3D-IC\nPCB / Advanced Packaging\nVerification Hardware and Software\n\nThe event is  FREE  of charge for Cadence customers and partners. Please reach out to your Cadence contact for a promo code\, or contact us \n\n\n\n\n\n\n\n\n\n\nCOVID-19 Vaccination Requirement \n\n\n\n\n\n\n\n\n\n\nIn line with its current vaccination policy\, Cadence will require proof of vaccination to attend CadenceLIVE Boston 2022\, a Cadence-sponsored event. We accept verification your vaccination status by one of the following options: \n\nCOVID-19 Vaccination Record Card (issued by the Department of Health and Human Services Centers for Disease Control & Prevention or WHO Yellow Card1) which includes the name of the person vaccinated\, type of vaccine provided and date doses administered); OR\nA photo of a vaccination card as a separate document; OR\nA photo of the attendee’s vaccine card stored on a phone or electronic device; OR\nDocumentation of vaccination from a healthcare provider;\n\nYou can find more information regarding vaccine records and types of vaccines accepted HERE. \nCadence continues to follow local\, state\, and federal regulations and CDC guidelines and recommendations\, and will make adjustments to our protocols accordingly. \n\nKeynote Speakers \nTom Beckley\nVice President and General Manager\, Custom IC & PCB Group \nVern Boyle\nVice President\, Northrop Grumman
URL:https://marketingeda.com/event/cadencelive-boston-2022/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-14-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220913T080000
DTEND;TZID=America/Los_Angeles:20220913T170000
DTSTAMP:20220831T195020Z
CREATED:20220804T155555Z
LAST-MODIFIED:20220831T195020Z
UID:5007-1663056000-1663088400@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Stay Tuned… \nAdvanced RISC-V processor verification and methodologies\nThis talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications\, including the innovations in processor designs with features such as: out-of-order pipelines\, hardware multi-threading\, multi-hart\, custom extensions and advanced privileged modes\, plus vector accelerators. Key updates will focus on functional coverage\, Verification IP (VIP) and testbenches for asynchronous events\, with examples from customers\, partners and users at the forefront of RISC-V adoption. \nSpeaker:    Larry Lapides\, Imperas Software Ltd\nWhen:        September 13\, 2022 – TBD (Tel Aviv\, Israel)
URL:https://marketingeda.com/event/semisrael-tech-webinar-3/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-September-13-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220908T110000
DTEND;TZID=America/Los_Angeles:20220908T120000
DTSTAMP:20220908T010855Z
CREATED:20220908T010855Z
LAST-MODIFIED:20220908T010855Z
UID:5168-1662634800-1662638400@marketingeda.com
SUMMARY:CDC Verification with Hard IP Blocks
DESCRIPTION:Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code\, and therefore are excluded from advanced linting. In fact\, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic verification. However\, clock domain crossing verification still requires hard IP block constraining. These block-level constraints serve the following purposes: \n\nIdentify clock and reset ports\, as well as required reset polarity and synchronization\nIdentify required clock phases for I/O ports\nDescribe hard IP as one of valid CDC synchronizer circuits\n\nDuring automated conversion of FPGA vendor projects\, hard IPs were automatically constrained by the tool. These constraints are extracted from hard IP instance connectivity. In most cases\, these IP-level constraints are not complete and require special attention from designers\, as the top-level CDC analysis relies on the quality and completeness of hard IP constraints.\n\nIn this webinar\, we will present a robust hard IP design constraints development methodology. This methodology is illustrated for different IP block types and on the number of FPGA designs.\n\nAgenda:\n\nShort CDC Analysis Overview\nAldec Design Constraints for block-level constraining\nConstraining Single-Clock hard IP blocks\nConstraining Multiple-Clock hard IP blocks\nCDC Analysis of design with Hard IP blocks\nLive Demo\nConclusion\nQ&A\n\n\nWebinar Duration:\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nAlexander Gnusin\, Design Verification Technologist.\nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/cdc-verification-with-hard-ip-blocks/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-September-8-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220908T093000
DTEND;TZID=America/Los_Angeles:20220908T170000
DTSTAMP:20220726T205633Z
CREATED:20220726T205620Z
LAST-MODIFIED:20220726T205633Z
UID:4968-1662629400-1662656400@marketingeda.com
SUMMARY:ARC Processor Summit 2022
DESCRIPTION:Attend this free one-day event to get in-depth information from industry leaders on the latest ARC processor IP and related hardware/software technologies that enable you to achieve differentiation in your chip or system design. You will hear Synopsys experts\, partners\, and the ARC user community discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, security\, software development for embedded systems and much\, much more.\nWhether you are a developer of chips\, systems or software\, the ARC Processor Summit will give you practical information to help you create more differentiated products in the shortest amount of time.\nWe look forward to seeing you in person this year!
URL:https://marketingeda.com/event/arc-processor-summit-2022/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-8-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220907T080000
DTEND;TZID=America/Los_Angeles:20220907T170000
DTSTAMP:20220823T024532Z
CREATED:20220823T024532Z
LAST-MODIFIED:20220823T024532Z
UID:5126-1662537600-1662570000@marketingeda.com
SUMMARY:IP-SOC China 22
DESCRIPTION:The semiconductor world has to face a worldwide accelerated evolution\, never seen before\, both in terms of technology evolution (3D Packaging\, advanced nodes) as well as new applications (IoT\, Artificial Intelligence\, Automotive\, Security\, etc) triggering an increasing demand of Semiconductor resources. \nD&R IP SoC Event Series is fully dedicated to IP (Silicon Intellectual property) and IP based Electronic systems. The goal is to promote IP knowledge worldwide sharing as the seed of Electronic Industry permanent innovation. \nDue to the sanitary situation IP SoC China 22 will be a virtual event with a broad first day program open on September 7th. \nAny question? Please contact us
URL:https://marketingeda.com/event/ip-soc-china-22/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SOC-China-22.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20220905T080000
DTEND;TZID=Asia/Karachi:20220906T170000
DTSTAMP:20220819T165004Z
CREATED:20220808T175544Z
LAST-MODIFIED:20220819T165004Z
UID:5028-1662364800-1662483600@marketingeda.com
SUMMARY:DVCon India
DESCRIPTION:On behalf of the DVCon India 2022 steering committee\, it is my pleasure to welcome you all to the 7th edition of the Design and Verification Conference in India planned from 5-6th September 2022 as a live conference.   We are bringing DVCon India 2022 as a live\, in person conference which would make it the first live event in the VLSI ecosystem in India. The conference would be following the traditional Indian version of the conference of two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThe IC industry continues to grow thanks to the Systems\, Automotive and Technology unicorns venturing to design their own chips and well-established IC companies and start-ups bringing in new innovations and chip architectures.   While there are a lot of new designs and architectures\, we continue to evolve in how we design\, verify\, and validate theses new architectures\, constantly thriving to shift left to shrink our project schedules while ensuring the designs comply with the various standards for safety and security.   All I can say is that the excitement continues to surge! \nThis year’s edition will have a good mix of Vision and Keynote talks\, lively panel discussions spread across both the days and with tutorials and short workshops on Day 1 and papers and posters on Day 2. \nThis year we have expanded our Steering Committee to ensure we expand our reach to academia and ensure active participation from academia and have also made a conscious effort to expand DVCon to academia and spread to the South East Asia and for that we have members from various companies from the ecosystem and academia in India and Sri Lanka. We have had a very strong Technical Program Committee and we want to make it even stronger and hence expanding our TPC for this year’s edition.  The entire team is working to deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, share their learnings with the rest of the community and take an active part in DVCon India 2022. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling.  This year\, we have added a special topic for New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co-verification. \nWe invite you to join us in this exciting journey and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2022
URL:https://marketingeda.com/event/dvcon-india-2/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India.jpg
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BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220831T100000
DTEND;TZID=Europe/Paris:20220831T110000
DTSTAMP:20220823T021950Z
CREATED:20220823T021950Z
LAST-MODIFIED:20220823T021950Z
UID:5123-1661940000-1661943600@marketingeda.com
SUMMARY:Accelerating Software Development for ASIL-D Processor IP Using Synopsys Virtual Prototyping Solutions
DESCRIPTION:As systemic complexity increases and new markets such as automotive\, AI\, and 5G evolve\, it’s crucial to find the optimal software design much earlier in the development process. Synopsys Virtualizer virtual prototyping solution addresses these systemic complexity challenges\, resulting in faster time-to-market through earlier and faster software development\, and improved collaboration throughout the supply chain. \nNSITEXE\, a Denso subsidiary company\, has successfully developed an advanced ASIL-D ready processor and a virtual model for software development using Synopsys Virtualizer. Join this presentation to hear how NSITEXE utilizes the latest techniques and methodologies using Synopsys Virtualizer virtual prototypes to deliver its IP through the supply chain working with a common virtual platform in various industries\, such as automotive\, embedded\, and factory automation. Learn how the supply chain ecosystem can accelerate development using both solutions. \n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Tim Kogel\n\n\nPrincipal Engineer\nSynopsys \n\n\n\n\n\n\n\n\nDr. Tim Kogel is a Principal Engineer for Virtual Prototyping in the Systems Design Group of Synopsys. He received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH)\, Aachen\, Germany\, in 1999 and 2005. He has authored a book and numerous technical and scientific publications on system-level modeling of SoC platforms. Tim is leading a team of applications engineering specialists\, responsible for the definition\, realization and deployment of Synopsys’ Virtual Prototyping solutions. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Masayuki Ito\n\n\nDirector of Business Promotion\nNSITEXE\, Inc. \n\n\n\n\n\n\n\n\nDr. Masayuki Ito is Director in Business Promotion Unit at NSITEXE\, Inc.\, Denso’s subsidiary\, where he focuses on business promotions for its own IP-products: RISC-V processor\, AI accelerators\, and Security Solutions. He has more than 20 years of experience in the semiconductor industry. He started his career in the Semiconductor Development Center in Hitachi Ltd. in Tokyo\, followed by Renesas Technology Corporation. and Renesas Electronics Corporation. Throughout his career he consistently worked for processor and SoC development for mobile and automobile. He holds a master’s degree in Computer engineering from Kyoto University and a Ph.D.in Science and Engineering from Tokyo Institute of Technology in Japan.
URL:https://marketingeda.com/event/accelerating-software-development-for-asil-d-processor-ip-using-synopsys-virtual-prototyping-solutions/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220824T080000
DTEND;TZID=America/Los_Angeles:20220824T090000
DTSTAMP:20220823T163315Z
CREATED:20220823T163315Z
LAST-MODIFIED:20220823T163315Z
UID:5129-1661328000-1661331600@marketingeda.com
SUMMARY:Arm Immortalis-G715 GPU
DESCRIPTION:Dan Wilson\, Director Product Management\, Arm \n\n\nAbout this talk\nThe new Arm flagship GPU\, Immortalis-G715\, is designed to enable the very best gaming experiences on next-generation flagship smartphones. Join this webinar for a detailed examination of the latest graphics features made possible by Immortalis-G715\, including hardware-based ray tracing support for more realistic and immersive mobile gaming experiences. Also\, learn about key improvements and enhancements across the latest range of Arm GPUs that make them the highest performing\, most energy efficient to date.\n\nAgenda:\n• Introduction – Immortalis-G715: Arm’s new flagship GPU.\n• New graphic and gaming features\, including hardware-based ray tracing support through Immortalis-G715 and variable rating shading across all the new Arm GPUs.\n• Performance\, efficiency\, and ML improvements and graphics enhancements across all new Arm GPUs.\n• The latest developer support and optimizations beyond the IP\, including resources and tools for to enable the best application experiences.\n• Q&A\n\nWho should attend:\n• Consumer device OEMs\, semiconductor manufacturers\, and mobile game developers.
URL:https://marketingeda.com/event/arm-immortalis-g715-gpu/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Arm-August-24-2022.webp
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BEGIN:VEVENT
DTSTART;TZID=America/Sao_Paulo:20220822T080000
DTEND;TZID=America/Sao_Paulo:20220826T170000
DTSTAMP:20220820T233927Z
CREATED:20220820T233927Z
LAST-MODIFIED:20220820T233927Z
UID:5104-1661155200-1661533200@marketingeda.com
SUMMARY:SBCCI 2022
DESCRIPTION:35ᵗʰ Symposium on Integrated Circuits and Systems Design \nSBCCI is an international forum dedicated to integrated circuits and systems design\, held annually in Brazil. The 35th SBCCI will be virtual from the Rio Grande do Sul state\, Brazil. This originates the name Chip in the Minuano – Minuano wind is the cold southwesterly current of air that typically affects the state. The goal of the symposium is to bring together researchers in the areas of EDA\, design\, and test of integrated circuits and systems. The scope of the symposium includes technical sessions\, tutorials\, and panels\, as well as an exhibition and working group meetings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. The best papers presented at the symposium will be invited to resubmit an extended version to be considered for publication at the IEEE Design & Test\, at the Springer Nature ALOG (Analog Integrated Circuits and Signal Processing)\, and at SBMicro/SBC JICS (Journal of Integrated Circuits and Systems). Information about paper submission is available on the conference webpage. \n\n\nThe areas of interest include:\n• System-level modeling and synthesis\n• Hardware-software co-design and co-verification\n• High-level and logic synthesis\n• Physical design of ICs and systems\n• EDA – Electronic Design Automation\n• Testability issues\, design for test techniques\n• Design and modeling languages and applications\n• Analog\, Digital\, and mixed-signal designs\n• Embedded systems and Cyber-physical systems design\n• System-on-chip\, IP reuse\, and platform-based designs\n• Low power tools and designs techniques
URL:https://marketingeda.com/event/sbcci-2022/
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/SBCCI-2022.png
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END:VCALENDAR