BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.2//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20210314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20211107T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Jerusalem
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20210326T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20211030T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20220325T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20221029T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20230324T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20231028T230000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Rome
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20210314T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20211107T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20220313T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20221106T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Karachi
BEGIN:STANDARD
TZOFFSETFROM:+0500
TZOFFSETTO:+0500
TZNAME:PKT
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Sao_Paulo
BEGIN:STANDARD
TZOFFSETFROM:-0300
TZOFFSETTO:-0300
TZNAME:-03
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Australia/Perth
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:AWST
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Brussels
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221018T100000
DTEND;TZID=America/Los_Angeles:20221018T180000
DTSTAMP:20221011T163924Z
CREATED:20220926T195009Z
LAST-MODIFIED:20221011T163924Z
UID:5236-1666087200-1666116000@marketingeda.com
SUMMARY:RISC-V Con
DESCRIPTION:In order to foster stronger collaboration on RISC-V across the computing industry\, RISC-V CON focuses on this disruptive technology\, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON\, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. \nSeventeen years in business and a Founding Premier member of RISC-V International\, Andes Technology is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions\, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP\, FPU\, Vector\, Linux\, superscalar\, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021\, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. \nBy bringing the leading companies in the RISC-V ecosystem together at RISC-V CON\, Andes aims to boost RISC-V adoption by collaborating with partners and customers to quickly bring innovative designs based on the open RISC-V ISA to market.
URL:https://marketingeda.com/event/risc-v-con/
LOCATION:DoubleTree Hotel\, 2050 Gateway Place\, San Jose\, CA\, 95110\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Con.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20221017T080000
DTEND;TZID=Europe/Berlin:20221018T170000
DTSTAMP:20220916T202247Z
CREATED:20220916T202247Z
LAST-MODIFIED:20220916T202247Z
UID:5210-1665993600-1666112400@marketingeda.com
SUMMARY:SNUG Europe
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. Join your fellow engineers at SNUG to hear practical information you can use on your current projects and spark the inspiration to create Smart Everything. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \nWhy Attend? \n\n\n\n\n\n\nLearn from Synopsys keynote by Alessandra Costa\, Senior Vice President\, Applications Engineering\, Customer Success Group:\n“A Renaissance Era of Innovation – Then and Now”\nAttend tutorials for the latest advancements in Synopsys technology\nGain practical knowledge you can apply today\nHear users showcase best practices for design & verification challenges\nTechnical tracks include: Artificial Intelligence\, Automotive\, Cloud\, Custom Implementation & AMS\, Digital Implementation\, IP\, Low Power\, Signoff\, Test\, and Verification Continuum.\nNetwork with User & Synopsys experts in over 40+ Technical presentations\n\nKeynote Spotlight \nChip Design: Prerequisite for Europe’s Economic Sovereignty\nMonday\, October 17th at 13:15\nProfessor Dr.-Ing Wolfgang Nebel\nUniversität Oldenburg and Chairman of the Board\, edacentrum e.V. \nA Renaissance Era of Innovation – Then and Now\nTuesday\, October 18th at 9:15\nAlessandra Costa\nSVP\, Applications Engineering\, Customer Success Group\, Synopsys \nVirtual Development in Automotive E/E\nTuesday\, October 18th at 13:25\nRalph Schleifer\nHead of HW/SW CoDesign & Virtual Platforms\, CARIAD SE
URL:https://marketingeda.com/event/snug-europe/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221006T080000
DTEND;TZID=America/Los_Angeles:20221007T170000
DTSTAMP:20220920T032644Z
CREATED:20220920T032644Z
LAST-MODIFIED:20220920T032644Z
UID:5217-1665043200-1665162000@marketingeda.com
SUMMARY:2022 IEEE Electronic Design Process Symposium (EDPS)
DESCRIPTION:We are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. \n\n\nAbout this event\n\n\n\n2022 IEEE EDPS will be held on Oct 6 and Oct 7 2022 in Milpitas\, CA. \nWe have invited industry practitioners and leaders from academia to present their work in following areas: \n\nInnovative Designs and Design Techniques including Design Co-optimization\nDesign for Trust/Design for Security\nAdvanced Packaging\, 3DIC\nDesign Technology Co-optimization/Systems Technology Co-optimization\nMachine Learning/Artificial Intelligence in System Design and EDA\nSystem Reliability\n5G Infrastructure\nSilicon Photonics\nSmart Manufacturing\n\nCheck out 2022 IEEE EDPS website for additional program details. \nPlease join us at SEMI facility in Milpitas\, CA this fall! The registration includes refreshments\, breakfast\, and lunch on both days\, as well as dinner on Thursday!
URL:https://marketingeda.com/event/2022-ieee-electronic-design-process-symposium-edps/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20220928T080000
DTEND;TZID=Europe/Berlin:20220929T170000
DTSTAMP:20220914T220520Z
CREATED:20220914T220520Z
LAST-MODIFIED:20220914T220520Z
UID:5202-1664352000-1664470800@marketingeda.com
SUMMARY:Global Foundries Technology Summit - EMEA
DESCRIPTION:DAY 1 \nWednesday\, September 28\, 2022\nDoors Open 3:00pm CET \n  \nDINNER \nRestaurant KULTURWIRTSCHAFT\, 7pm – 10pm \n  \nDAY 2 \nThursday\, September 29\, 2022\nDoors Open 8:30am CET \n  \nEVENT LOCATION\nGlobalFoundries FAB 1\nWilschdorfer Landstrasse 101\n01109 Dresden\, Germany \n  \nWe are thrilled to welcome you to GF Technology Summit 2022. \nThis exclusive\, invitation-only event is in-person again\, located in GF’s FAB 1 facility! \n\n(RE)CONNECT Join CEO Tom Caulfield\, the GF team\, partners and industry experts for lively\, interactive discussions\nLEARN See how GF’s differentiated solutions and technology roadmap is delivering a new era of more\nDELIVER Collaborate\, partner and invest with GF to drive transformation in your industry\n\nWe look forward to seeing you (in-person!) at GTS 2022 EMEA. \n  \n\nYour Host  \n\n\n\n\n\n\n\n\n\n\nRuth Hernandez\nPartnerships & Business Development\, EMEA\nGlobalFoundries \n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n“We look forward to seeing you at GF Technology Summit 2022 EMEA\, in-person in Dresden\, on September 28 and 29. Join us to connect\, build relationships and discover new ways of collaborating and innovating.” \n 
URL:https://marketingeda.com/event/global-foundries-technology-summit-emea/
LOCATION:GlobalFoundries Fab 1\, Wilschdorfer Landstrasse 101\, Dresden\, 01109\, Germany
CATEGORIES:EDA,Foundry,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GF-September-28-29-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220927T080000
DTEND;TZID=America/Los_Angeles:20220927T170000
DTSTAMP:20220705T205605Z
CREATED:20220705T205605Z
LAST-MODIFIED:20220705T205605Z
UID:4906-1664265600-1664298000@marketingeda.com
SUMMARY:U.S. Executive Forum
DESCRIPTION:The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park\, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it’s too late. \nIn this unique and exclusive gathering\, thought leaders\, visionaries and innovators will shed light on the leadership role that the semiconductor industry must embrace to lead the world to a brighter future. Our program features some of the biggest names in semis fostering discussions on the industry’s most pressing issues. We hope you’ll join us at USEF 2022 for a day of leadership\, networking and enrichment. \nTraditionally\, even as semiconductors have been at the core of technological innovation and have changed the world beyond any other technology\, they have often been seen as a commodity and rarely in the spotlight or getting noticed. \nThis has all changed with the acceleration of digital transformation across industries and digitalization of work and life styles. Semiconductors are enabling new technologies and applications\, such as AI and IoT\, that have sparked a new wave of innovation for the industry. \nIn addition\, the implementation of 5G networks coincides with the growing demand for faster high-performance computing devices in the cloud and at the edge. \nIt is time for the industry to step up and show leadership in not only the technology field but also as a responsible global industry in areas of social impact. Climate change\, digital inequality\, diversity\, are all areas that the industry impacts and can show leadership in change. \nIn this unique and exclusive gathering\, thought leaders\, visionaries\, and innovators will shed light on the leadership role that the semiconductor industry needs to embrace and lead the world for a brighter future.
URL:https://marketingeda.com/event/u-s-executive-forum/
CATEGORIES:EDA,Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA.-September-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220921T080000
DTEND;TZID=America/Los_Angeles:20220921T090000
DTSTAMP:20220826T190645Z
CREATED:20220826T190645Z
LAST-MODIFIED:20220826T190645Z
UID:5148-1663747200-1663750800@marketingeda.com
SUMMARY:Protocol and Memory Interface Verification in the Shrinking World of 3DIC
DESCRIPTION:Emerging 2.5D and 3DIC packaging technologies enable more design complexity\, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. \nPackaging technologies for 2.5D and 3DIC are becoming more available and more accessible\, with solutions addressing both the economics problem and the technical scalability challenge of building ever more complex SoCs. Standards are competing and emerging for interconnect protocols\, memory interfaces\, backplane-like and motherboard-like solutions within the IC package. \nIn this session\, we take a look at how to scale your verification capability to match those designs\, divide and conquer\, and use the right abstractions to equip projects with high quality and faster time-to-market\, and to equip design/verification engineers with scalable tools and solutions for verification. We will dive into the interface and memory protocols driving High Performance Compute innovation – PCIe Gen6\, CXL\, HBM3\, and future UCIe\, as well as important aspects of enabling scalability such as IDE security. \nWhat You Will Learn: \n\nThe challenges of verifying today’s advanced die-to-die interface and memory protocols\nThe broad portfolio of Siemens EDA Verification IP solutions available today\nHow our automated approach and flexible VIP can enable your productivity\n\nWho Should Attend: \n\nDesign & Verification Engineers & Managers and those interested in Protocol or Memory Interface verification\n\nProduct Covered: \n\nQuesta Verification IP solutions for protocols and memories including PCIe\, CXL\, IDE\, HBM\n\n\n\n\nSpeakers\n\n\n\n\nGordon Allan\nVerification IP Product Manager\nSiemens EDA\n\n\nGordon Allan is Product Manager for Verification IP at Siemens EDA. Gordon was one of the authors of Accellera UVM\, and he published the online UVM Cookbook on our Verification Academy site where it is appreciated by over 65\,000 engineers today. Prior to joining the EDA industry he gained over 18 years of Design/Verification experience leading & developing SoC and complex protocol IP/VIP projects in several semiconductor companies\, fabless startups\, EDA and system houses. Gordon is based in Silicon Valley. \n\n\n\n\n\nJoe Hupcey III\nVerification Product Technologist\nSiemens EDA\n\n\nJoe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley\, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens\, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies\, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing\, Joe worked as an electrical engineer in FPGA design\, EDA tools for FPGAs and ASICs\, and ASIC verification. Joe’s educational background includes BSEE\, MSEE\, and MBA degrees from Cornell University in Ithaca\, NY.
URL:https://marketingeda.com/event/protocol-and-memory-interface-verification-in-the-shrinking-world-of-3dic/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/004B10F7-2E47-47CD-9F94-8AD8C4D98D58.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220920T080000
DTEND;TZID=America/Los_Angeles:20220921T170000
DTSTAMP:20220822T190157Z
CREATED:20220822T190157Z
LAST-MODIFIED:20220822T190157Z
UID:5119-1663660800-1663779600@marketingeda.com
SUMMARY:MIPI DevCon 2022
DESCRIPTION:MIPI DevCon 2022 will be held 20-21 September\, offering developers and implementers of MIPI specifications a forum for training\, education and networking. The virtual event will feature conference presentations by MIPI experts and working group leaders sharing use cases\, implementation experiences and application examples – all from a technical perspective. \nOpen to all Alliance members and industry representatives\, MIPI DevCon is targeted towards developers\, system architects and engineering managers\, including design\, test\, application\, system\, hardware\, firmware and other engineers. \n\nPrevious MIPI DevCon Sessions\nInterested in learning more about MIPI specifiations and their implementations in mobile and beyond? Presentations from past MIPI DevCons are available in the MIPI Knowledge Library. \nVisit the MIPI DevCon 2021 Agenda page to learn more about last year’s sessions\, access the recordings and download all presentations (including Japanese\, Korean and Chinese translations of the Asia track sessions)\, or visit our YouTube page for access to all DevCon session and demo recordings\, along with other MIPI Alliance educational videos.
URL:https://marketingeda.com/event/mipi-devcon-2022/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MIPI-DevCon-2022-Learn-More-1024x576-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220920T080000
DTEND;TZID=Asia/Jerusalem:20220920T170000
DTSTAMP:20220817T222547Z
CREATED:20220817T222547Z
LAST-MODIFIED:20220817T222547Z
UID:5092-1663660800-1663693200@marketingeda.com
SUMMARY:SNUG Israel 2022
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. By attending SNUG Israel\, you gain knowledge to use on current projects and discover ideas to spark future innovations. \nSNUG is offered at no charge to Synopsys customers. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nLearn from Keynote\, Shankar Krishnamoorthy – GM\, Silicon Realization Group\, Synopsys \n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\nGain practical knowledge you can apply today \n\n\n\n\n\nHear users showcase best practices for design & verification challenges \n\n\n\n\n\n\n\n\n\n\nStay connected and inspired by industry keynotes \n\n\n\n\n\n\n\n\n\n\nNetwork with User & Synopsys experts in over 30+ Technical presentations
URL:https://marketingeda.com/event/snug-israel-2022/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/1C26AE4C-66F9-4EB4-934D-F1F55430B1A0-e1660774735313.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20220919T080000
DTEND;TZID=Europe/Rome:20220922T170000
DTSTAMP:20220919T015335Z
CREATED:20220919T015335Z
LAST-MODIFIED:20220919T015335Z
UID:5213-1663574400-1663866000@marketingeda.com
SUMMARY:ESSCIRC 2022
DESCRIPTION:The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore\, more than ever before\, a deeper interaction among technologists\, device experts\, IC designers and system designers is necessary. \nWhile keeping separate Technical Program Committees\, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions\, regardless to which conference they belong. \n\n​ \nCONFERENCE HIGHLIGHTS \n\n\n4 joint keynote presentations \n\n\n3 ESSDERC keynote presentations \n\n\n3 ESSCIRC keynote presentations \n\n\nInvited papers with overall coverage of all aspects of advanced devices and circuits \n\n\nPresentation of IEEE and ESSDERC/ESSCIRC Awards \n\n\nESSDERC/ESSCIRC Welcome Reception on Tuesday\, September 20\, 2022 \n\n\nESSDERC/ESSCIRC Gala Dinner on Wednesday\, September 21\, 2022 \n\n\nTutorials and workshops \n\n\n\nThe venue of the conference events\, including workshops and tutorials\, will be at the University of Milan-Bicocca (Milan\, IT)\, that is well connected (metro\, bus\, train with Milan downtown). \nThe working language of the conference is English. \n​ \n​ \nBEST PAPER AWARDS \nPapers presented at the conference will be considered for the ”Best Paper Award” and ”Best Young Scientist Paper Award”. \nThe selection will be based on the results of the paper selection process and the judgment of the conference participants. \nThe 2022 Award Ceremony will take place during ESSDERC/ESSCIRC 2023. \n\n​ \nCONFERENCE TARGET AND EVOLUTION \nESSDERC and ESSCIRC have evolved over the last years to follow recent R&D device\, circuit and system fast-growing topics. Besides the traditional ESSDERC and ESSCIRC tracks\, a number of JOINT tracks have been introduced\, to encourage and facilitate interactions between circuit\, system and device researchers. \n\nESSDERC/ESSCIRC encourages submissions in all areas of solid-state devices\, circuits and systems\, with special emphasis on: \n\n\nAnalog\, Power and RF Devices \n\n\nElectron Device Simulation and Modeling \n\n\nAdvanced Technology\, Processes and Materials \n\n\nNeuromorphic Computing\, Advanced Memories\, Al Accelerators\, in-Memory-Computing\, Security \n\n\nAdvanced Computing Devices and Circuits: Advanced CMOS\, Post-CMOS\, Quantum Computing \n\n\nSensors\, MEMS\, Bioelectronics\, Biomedical Electronics\, Optoelectronics\, Display and Imaging \n\n\nAnalog Circuits \n\n\nData Converters \n\n\nRF and mm-Wave Circuits \n\n\nFrequency Generation \n\n\nWireless and Wireline Interfaces \n\n\nIntegrated Power Electronics and Power Management \n\n\nDigital Circuits & Systems \n\n\n\nStudent papers are welcome and encouraged. \n\n​ \nPAPERS SUBMISSION \nPapers submitted for review must clearly state: \n\n\nThe purpose of the work \n\n\nHow and to what extent it advances the state-of-the art \n\n\nSpecific results and their impact \n\n\nOnly material that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. \nManuscript guidelines\, as well as instructions on how to electronically submit papers will be available in the 1st Call for Papers and on this website. \nPapers must not exceed four A4 pages with all illustrations and references included. \n\nPapers submission deadline: April\, 12\, 2022
URL:https://marketingeda.com/event/esscirc-2022/
LOCATION:Università degli Studi di MILANO – BICOCCA\, Viale Piero e Alberto Pirelli\, 22\, Milano\, 20126\, Italy
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESSCIRC-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220914T080000
DTEND;TZID=America/New_York:20220914T183000
DTSTAMP:20220817T161455Z
CREATED:20220817T161455Z
LAST-MODIFIED:20220817T161455Z
UID:5072-1663142400-1663180200@marketingeda.com
SUMMARY:CadenceLIVE Boston 2022
DESCRIPTION:CadenceLIVE Boston 2022 is back\, this time in person and will be held on September 14 at the Boston Marriott Burlington. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users\, developers\, and industry experts together to network\, share ideas\, and inspire design creativity. \nAttendees have the opportunity to attend captivating keynotes\, watch interesting user presentations\, and learn new ways to solve your design challenges from industry leaders and Cadence experts. \n\nCadence®  products\, solutions\, flows\, and techniques will be featured at the conference in the following areas: \n\nSystem Design Analysis\nCustom IC / Mixed-Signal RF\nDigital Design and Signoff\n3D-IC\nPCB / Advanced Packaging\nVerification Hardware and Software\n\nThe event is  FREE  of charge for Cadence customers and partners. Please reach out to your Cadence contact for a promo code\, or contact us \n\n\n\n\n\n\n\n\n\n\nCOVID-19 Vaccination Requirement \n\n\n\n\n\n\n\n\n\n\nIn line with its current vaccination policy\, Cadence will require proof of vaccination to attend CadenceLIVE Boston 2022\, a Cadence-sponsored event. We accept verification your vaccination status by one of the following options: \n\nCOVID-19 Vaccination Record Card (issued by the Department of Health and Human Services Centers for Disease Control & Prevention or WHO Yellow Card1) which includes the name of the person vaccinated\, type of vaccine provided and date doses administered); OR\nA photo of a vaccination card as a separate document; OR\nA photo of the attendee’s vaccine card stored on a phone or electronic device; OR\nDocumentation of vaccination from a healthcare provider;\n\nYou can find more information regarding vaccine records and types of vaccines accepted HERE. \nCadence continues to follow local\, state\, and federal regulations and CDC guidelines and recommendations\, and will make adjustments to our protocols accordingly. \n\nKeynote Speakers \nTom Beckley\nVice President and General Manager\, Custom IC & PCB Group \nVern Boyle\nVice President\, Northrop Grumman
URL:https://marketingeda.com/event/cadencelive-boston-2022/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-14-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220913T080000
DTEND;TZID=America/Los_Angeles:20220913T170000
DTSTAMP:20220831T195020Z
CREATED:20220804T155555Z
LAST-MODIFIED:20220831T195020Z
UID:5007-1663056000-1663088400@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Stay Tuned… \nAdvanced RISC-V processor verification and methodologies\nThis talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications\, including the innovations in processor designs with features such as: out-of-order pipelines\, hardware multi-threading\, multi-hart\, custom extensions and advanced privileged modes\, plus vector accelerators. Key updates will focus on functional coverage\, Verification IP (VIP) and testbenches for asynchronous events\, with examples from customers\, partners and users at the forefront of RISC-V adoption. \nSpeaker:    Larry Lapides\, Imperas Software Ltd\nWhen:        September 13\, 2022 – TBD (Tel Aviv\, Israel)
URL:https://marketingeda.com/event/semisrael-tech-webinar-3/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-September-13-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220908T110000
DTEND;TZID=America/Los_Angeles:20220908T120000
DTSTAMP:20220908T010855Z
CREATED:20220908T010855Z
LAST-MODIFIED:20220908T010855Z
UID:5168-1662634800-1662638400@marketingeda.com
SUMMARY:CDC Verification with Hard IP Blocks
DESCRIPTION:Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code\, and therefore are excluded from advanced linting. In fact\, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic verification. However\, clock domain crossing verification still requires hard IP block constraining. These block-level constraints serve the following purposes: \n\nIdentify clock and reset ports\, as well as required reset polarity and synchronization\nIdentify required clock phases for I/O ports\nDescribe hard IP as one of valid CDC synchronizer circuits\n\nDuring automated conversion of FPGA vendor projects\, hard IPs were automatically constrained by the tool. These constraints are extracted from hard IP instance connectivity. In most cases\, these IP-level constraints are not complete and require special attention from designers\, as the top-level CDC analysis relies on the quality and completeness of hard IP constraints.\n\nIn this webinar\, we will present a robust hard IP design constraints development methodology. This methodology is illustrated for different IP block types and on the number of FPGA designs.\n\nAgenda:\n\nShort CDC Analysis Overview\nAldec Design Constraints for block-level constraining\nConstraining Single-Clock hard IP blocks\nConstraining Multiple-Clock hard IP blocks\nCDC Analysis of design with Hard IP blocks\nLive Demo\nConclusion\nQ&A\n\n\nWebinar Duration:\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nAlexander Gnusin\, Design Verification Technologist.\nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/cdc-verification-with-hard-ip-blocks/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-September-8-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220908T093000
DTEND;TZID=America/Los_Angeles:20220908T170000
DTSTAMP:20220726T205633Z
CREATED:20220726T205620Z
LAST-MODIFIED:20220726T205633Z
UID:4968-1662629400-1662656400@marketingeda.com
SUMMARY:ARC Processor Summit 2022
DESCRIPTION:Attend this free one-day event to get in-depth information from industry leaders on the latest ARC processor IP and related hardware/software technologies that enable you to achieve differentiation in your chip or system design. You will hear Synopsys experts\, partners\, and the ARC user community discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, security\, software development for embedded systems and much\, much more.\nWhether you are a developer of chips\, systems or software\, the ARC Processor Summit will give you practical information to help you create more differentiated products in the shortest amount of time.\nWe look forward to seeing you in person this year!
URL:https://marketingeda.com/event/arc-processor-summit-2022/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-8-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220907T080000
DTEND;TZID=America/Los_Angeles:20220907T170000
DTSTAMP:20220823T024532Z
CREATED:20220823T024532Z
LAST-MODIFIED:20220823T024532Z
UID:5126-1662537600-1662570000@marketingeda.com
SUMMARY:IP-SOC China 22
DESCRIPTION:The semiconductor world has to face a worldwide accelerated evolution\, never seen before\, both in terms of technology evolution (3D Packaging\, advanced nodes) as well as new applications (IoT\, Artificial Intelligence\, Automotive\, Security\, etc) triggering an increasing demand of Semiconductor resources. \nD&R IP SoC Event Series is fully dedicated to IP (Silicon Intellectual property) and IP based Electronic systems. The goal is to promote IP knowledge worldwide sharing as the seed of Electronic Industry permanent innovation. \nDue to the sanitary situation IP SoC China 22 will be a virtual event with a broad first day program open on September 7th. \nAny question? Please contact us
URL:https://marketingeda.com/event/ip-soc-china-22/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SOC-China-22.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20220905T080000
DTEND;TZID=Asia/Karachi:20220906T170000
DTSTAMP:20220819T165004Z
CREATED:20220808T175544Z
LAST-MODIFIED:20220819T165004Z
UID:5028-1662364800-1662483600@marketingeda.com
SUMMARY:DVCon India
DESCRIPTION:On behalf of the DVCon India 2022 steering committee\, it is my pleasure to welcome you all to the 7th edition of the Design and Verification Conference in India planned from 5-6th September 2022 as a live conference.   We are bringing DVCon India 2022 as a live\, in person conference which would make it the first live event in the VLSI ecosystem in India. The conference would be following the traditional Indian version of the conference of two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThe IC industry continues to grow thanks to the Systems\, Automotive and Technology unicorns venturing to design their own chips and well-established IC companies and start-ups bringing in new innovations and chip architectures.   While there are a lot of new designs and architectures\, we continue to evolve in how we design\, verify\, and validate theses new architectures\, constantly thriving to shift left to shrink our project schedules while ensuring the designs comply with the various standards for safety and security.   All I can say is that the excitement continues to surge! \nThis year’s edition will have a good mix of Vision and Keynote talks\, lively panel discussions spread across both the days and with tutorials and short workshops on Day 1 and papers and posters on Day 2. \nThis year we have expanded our Steering Committee to ensure we expand our reach to academia and ensure active participation from academia and have also made a conscious effort to expand DVCon to academia and spread to the South East Asia and for that we have members from various companies from the ecosystem and academia in India and Sri Lanka. We have had a very strong Technical Program Committee and we want to make it even stronger and hence expanding our TPC for this year’s edition.  The entire team is working to deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, share their learnings with the rest of the community and take an active part in DVCon India 2022. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling.  This year\, we have added a special topic for New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co-verification. \nWe invite you to join us in this exciting journey and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2022
URL:https://marketingeda.com/event/dvcon-india-2/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220831T100000
DTEND;TZID=Europe/Paris:20220831T110000
DTSTAMP:20220823T021950Z
CREATED:20220823T021950Z
LAST-MODIFIED:20220823T021950Z
UID:5123-1661940000-1661943600@marketingeda.com
SUMMARY:Accelerating Software Development for ASIL-D Processor IP Using Synopsys Virtual Prototyping Solutions
DESCRIPTION:As systemic complexity increases and new markets such as automotive\, AI\, and 5G evolve\, it’s crucial to find the optimal software design much earlier in the development process. Synopsys Virtualizer virtual prototyping solution addresses these systemic complexity challenges\, resulting in faster time-to-market through earlier and faster software development\, and improved collaboration throughout the supply chain. \nNSITEXE\, a Denso subsidiary company\, has successfully developed an advanced ASIL-D ready processor and a virtual model for software development using Synopsys Virtualizer. Join this presentation to hear how NSITEXE utilizes the latest techniques and methodologies using Synopsys Virtualizer virtual prototypes to deliver its IP through the supply chain working with a common virtual platform in various industries\, such as automotive\, embedded\, and factory automation. Learn how the supply chain ecosystem can accelerate development using both solutions. \n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Tim Kogel\n\n\nPrincipal Engineer\nSynopsys \n\n\n\n\n\n\n\n\nDr. Tim Kogel is a Principal Engineer for Virtual Prototyping in the Systems Design Group of Synopsys. He received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH)\, Aachen\, Germany\, in 1999 and 2005. He has authored a book and numerous technical and scientific publications on system-level modeling of SoC platforms. Tim is leading a team of applications engineering specialists\, responsible for the definition\, realization and deployment of Synopsys’ Virtual Prototyping solutions. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Masayuki Ito\n\n\nDirector of Business Promotion\nNSITEXE\, Inc. \n\n\n\n\n\n\n\n\nDr. Masayuki Ito is Director in Business Promotion Unit at NSITEXE\, Inc.\, Denso’s subsidiary\, where he focuses on business promotions for its own IP-products: RISC-V processor\, AI accelerators\, and Security Solutions. He has more than 20 years of experience in the semiconductor industry. He started his career in the Semiconductor Development Center in Hitachi Ltd. in Tokyo\, followed by Renesas Technology Corporation. and Renesas Electronics Corporation. Throughout his career he consistently worked for processor and SoC development for mobile and automobile. He holds a master’s degree in Computer engineering from Kyoto University and a Ph.D.in Science and Engineering from Tokyo Institute of Technology in Japan.
URL:https://marketingeda.com/event/accelerating-software-development-for-asil-d-processor-ip-using-synopsys-virtual-prototyping-solutions/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220824T080000
DTEND;TZID=America/Los_Angeles:20220824T090000
DTSTAMP:20220823T163315Z
CREATED:20220823T163315Z
LAST-MODIFIED:20220823T163315Z
UID:5129-1661328000-1661331600@marketingeda.com
SUMMARY:Arm Immortalis-G715 GPU
DESCRIPTION:Dan Wilson\, Director Product Management\, Arm \n\n\nAbout this talk\nThe new Arm flagship GPU\, Immortalis-G715\, is designed to enable the very best gaming experiences on next-generation flagship smartphones. Join this webinar for a detailed examination of the latest graphics features made possible by Immortalis-G715\, including hardware-based ray tracing support for more realistic and immersive mobile gaming experiences. Also\, learn about key improvements and enhancements across the latest range of Arm GPUs that make them the highest performing\, most energy efficient to date.\n\nAgenda:\n• Introduction – Immortalis-G715: Arm’s new flagship GPU.\n• New graphic and gaming features\, including hardware-based ray tracing support through Immortalis-G715 and variable rating shading across all the new Arm GPUs.\n• Performance\, efficiency\, and ML improvements and graphics enhancements across all new Arm GPUs.\n• The latest developer support and optimizations beyond the IP\, including resources and tools for to enable the best application experiences.\n• Q&A\n\nWho should attend:\n• Consumer device OEMs\, semiconductor manufacturers\, and mobile game developers.
URL:https://marketingeda.com/event/arm-immortalis-g715-gpu/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Arm-August-24-2022.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Sao_Paulo:20220822T080000
DTEND;TZID=America/Sao_Paulo:20220826T170000
DTSTAMP:20220820T233927Z
CREATED:20220820T233927Z
LAST-MODIFIED:20220820T233927Z
UID:5104-1661155200-1661533200@marketingeda.com
SUMMARY:SBCCI 2022
DESCRIPTION:35ᵗʰ Symposium on Integrated Circuits and Systems Design \nSBCCI is an international forum dedicated to integrated circuits and systems design\, held annually in Brazil. The 35th SBCCI will be virtual from the Rio Grande do Sul state\, Brazil. This originates the name Chip in the Minuano – Minuano wind is the cold southwesterly current of air that typically affects the state. The goal of the symposium is to bring together researchers in the areas of EDA\, design\, and test of integrated circuits and systems. The scope of the symposium includes technical sessions\, tutorials\, and panels\, as well as an exhibition and working group meetings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. The best papers presented at the symposium will be invited to resubmit an extended version to be considered for publication at the IEEE Design & Test\, at the Springer Nature ALOG (Analog Integrated Circuits and Signal Processing)\, and at SBMicro/SBC JICS (Journal of Integrated Circuits and Systems). Information about paper submission is available on the conference webpage. \n\n\nThe areas of interest include:\n• System-level modeling and synthesis\n• Hardware-software co-design and co-verification\n• High-level and logic synthesis\n• Physical design of ICs and systems\n• EDA – Electronic Design Automation\n• Testability issues\, design for test techniques\n• Design and modeling languages and applications\n• Analog\, Digital\, and mixed-signal designs\n• Embedded systems and Cyber-physical systems design\n• System-on-chip\, IP reuse\, and platform-based designs\n• Low power tools and designs techniques
URL:https://marketingeda.com/event/sbcci-2022/
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/SBCCI-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220821T080000
DTEND;TZID=America/Los_Angeles:20220823T170000
DTSTAMP:20220615T165130Z
CREATED:20220615T165130Z
LAST-MODIFIED:20220615T165130Z
UID:4843-1661068800-1661274000@marketingeda.com
SUMMARY:Hot Chips 2022
DESCRIPTION:HC34(2022) (advance program) will take place virtually from Sunday\, August 21 – Tuesday\, August 23\, 2022. \nAll HC33(2021) conference content open to public. Visit https://hc33.hotchips.org. \nSince it started in 1989\, HOT CHIPS has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity\, Silicon Valley. \nThe HOT CHIPS conference typically attracts more than 500 attendees from all over the world. It provides an opportunity for chip designers\, computer architects\, system engineers\, press and analysts\, as well as attendees from national laboratories and academia to mix\, mingle and see presentations on the latest technologies and products. The three days of the conference typically feature two tutorials\, two keynotes\, a panel discussion and around 25 presentations on a variety of subjects related to microprocessors and integrated circuits. It is widely covered by the media; last year\, we had about 25 members of the industry and national press covering the conference. \nPresentations at HOT CHIPS are in the form of 30-minute talks. Presentation slides are published in the HOT CHIPS proceedings and online in the archives section of the HOT CHIPS website. Participants are not required to submit written papers\, but a select group are invited to submit a paper for inclusion in a special issue of IEEE Micro. \nThe conference emphasis this year\, as in previous years\, is on real products and realizable technology. Submissions are invited from a variety of “hot” topics\, including embedded and reconfigurable processors\, quantum computing\, nano structures\, wireless chips\, network/security processors\, advanced packaging technology etc. For a complete list of topics\, refer to the official call for papers. \nThe program committee consisting of members from academia and industry\, is busy sorting through a record number of paper submissions this year. As usual\, the passionate and highly dedicated members of the program and organizing committees are working together to provide high quality content and experience to the HOT CHIPS conference attendees. \nThank you for your interest in HOT CHIPS. We hope to see you at the conference! \nVirtual Conference: The conference will take place live in an all digital format: \n\nAll tutorials\, keynotes\, and sessions will be broadcast in a live video stream that all registered conference attendees will be able to access with a password protected login. Conference credentials will be emailed to you starting Monday\, August 15 at 3:00 PM PDT. If you are not in the Pacific Time Zone\, you will be able to watch a recording of the video stream when it is convenient for you.\nAlong with the video stream login\, registered attendees will have access to the Hot Chips Slack workspace.  This workspace will be where questions can be submitted for presenters to answer live following their talks\, or answer in the channel assigned to the talk throughout the conference.  Presenters will answer your questions live during the last 5 minutes of their presentation. You won’t have to scramble to the microphone\, just post your question in the Slack channel\, one channel per presentation.\nAttendees will have access in the Slack workspace to this year’s selected posters.  The posters can be viewed at any time once the conference starts and poster presenters will be available during set times via Slack to answer your questions.\nMany of our sponsors will be hosting virtual tables which can be accessed from this website and through the Slack workspace.  You can connect with sponsors\, view product demos\, and talk to their representatives.
URL:https://marketingeda.com/event/hot-chips-2022/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/HotChips34.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220817T100000
DTEND;TZID=America/Los_Angeles:20220817T110000
DTSTAMP:20220805T173528Z
CREATED:20220805T173528Z
LAST-MODIFIED:20220805T173528Z
UID:5018-1660730400-1660734000@marketingeda.com
SUMMARY:FPGAs for AI and AI for FPGAs
DESCRIPTION:Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications\, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism\, while being flexible and easily configurable\, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use cases. \nThe emergence of Deep Learning as an omnipresent workload has driven FPGA architecture evolution as well. Academic researchers have proposed optimizing the architecture of FPGAs to better fit the needs of DL workloads and FPGA companies now have AI-optimized FPGAs in their product portfolios. \nFPGAs are very well-suited for prototyping and accelerating the rapidly changing algorithms and novel network architectures in the field of DL. In addition\, DL is being used to assist in chip design processes such as power prediction\, floorplanning\, etc. including for FPGAs. \nWhat you will learn:\nIn this webinar\, we will discuss recent innovations in DL-optimized FPGA architecture\, using AI to estimate things such as power consumption on (new or existing) FPGAs and new types of neural network accelerators using existing FPGAs. \nPresenter: \nDr. Lizy Kurian John holds the Cullen Trust for Higher Education Endowed Professorship in Electrical Engineering in the Department of Electrical & Computer Engineering at The University of Texas at Austin. She received her Ph.D. in computer engineering from The Pennsylvania State University. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture\, multicore processors\, memory systems\, performance evaluation and benchmarking\, workload characterization\, and reconfigurable computing. \nProfessor John holds 15 U. S. patents\, has coauthored 4 books\, 16 book chapters\, and approximately 300 journal/ conferences/workshop papers. She is a Fellow of IEEE\, Fellow of ACM and a Fellow of the National Academy of Inventors (NAI).
URL:https://marketingeda.com/event/fpgas-for-ai-and-ai-for-fpgas/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSFPGA-August-17-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220804T100000
DTEND;TZID=America/Los_Angeles:20220804T110000
DTSTAMP:20220730T003409Z
CREATED:20220730T003409Z
LAST-MODIFIED:20220730T003409Z
UID:4973-1659607200-1659610800@marketingeda.com
SUMMARY:A Smart and Automatic Assembly and Connections for SoCs
DESCRIPTION:Learn how to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators\, bridges\, channels\, bus fabrics\, muxes\, etc. wherever needed.
URL:https://marketingeda.com/event/a-smart-and-automatic-assembly-and-connections-for-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2BA08003-45F1-463F-88DC-BAE1A46EDDED.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220714T100000
DTEND;TZID=America/Los_Angeles:20220714T110000
DTSTAMP:20220610T050529Z
CREATED:20220610T050529Z
LAST-MODIFIED:20220610T050529Z
UID:4827-1657792800-1657796400@marketingeda.com
SUMMARY:Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges
DESCRIPTION:PCIe\, the most popular interconnect in compute\, AI and storage systems\, is now offering faster data rate\, higher performance\, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling\, challenges such as signal integrity\, power integrity\, implementation\, IP integration and more must be considered when designing 64GT/s systems. This Synopsys webinar explains how designers can overcome these challenges by accounting for PCIe 6.0 system-level co-design in pre-silicon. In addition\, the Synopsys webinar highlights the importance of pre-silicon validation for overall system integration\, performance and compliance. \n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMadhumita Sanyal\n\n\nSr. Staff Technical Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nMadhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products\, logic libraries\, embedded memories\, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNarasimha Babu GVL\n\n\nSynopsys Scientist\nSynopsys \n\n\n\n\n\n\n\n\nNarasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including PCIe and CXL. Babu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India 2022 steering committee. He is also actively involved in writing and editing technical blog publications on PCIe and CXL verification.
URL:https://marketingeda.com/event/overcoming-pcie-6-0-system-integration-and-pre-silicon-validation-challenges/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-July-14-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220710T080000
DTEND;TZID=America/Los_Angeles:20220714T170000
DTSTAMP:20220429T201931Z
CREATED:20220429T201907Z
LAST-MODIFIED:20220429T201931Z
UID:4613-1657440000-1657818000@marketingeda.com
SUMMARY:Design Automation Conference\, 2022
DESCRIPTION:The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems.  DAC offers outstanding training\, education\, exhibits and superb networking opportunities for designers\, researchers\, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA). \nMembers are from a diverse worldwide community of more than 1\,000 organizations that attend each year\, represented by system designers and architects\, logic and circuit designers\, validation engineers\, CAD managers\, senior managers and executives\, and researchers and academicians from leading universities. \nOver five days\, DAC provides over 300 technical presentations and sessions that are selected by a committee of electronic design and university research experts offering information on recent developments and trends\, management practices and new products\, methodologies\, and technologies in the electronics industry. \nA highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging companies in: \n\nArtificial Intelligence/ Machine Learning (AI/ ML)\nAutomotive\nDesign Services\nDesign on Cloud\nElectronic Design Automation (EDA)\nEmbedded Systems and Software (ESS)\nIntellectual Property (IP)\nSecurity/Privacy
URL:https://marketingeda.com/event/design-automation-conference-2022/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220710T080000
DTEND;TZID=America/Los_Angeles:20220714T170000
DTSTAMP:20220119T035414Z
CREATED:20220119T035414Z
LAST-MODIFIED:20220119T035414Z
UID:4200-1657440000-1657818000@marketingeda.com
SUMMARY:59th DAC
DESCRIPTION:The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits.\nDAC focuses on the latest methodologies and technology advancements in electronic design. Get ready for 59th DAC returning to San Francisco\, California this July 10-14 at the Moscone West Center. Join researchers\, designers\, practitioners\, tool developers\, students\, vendors and more at DAC 2022.
URL:https://marketingeda.com/event/59th-dac/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/dac59.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Australia/Perth:20220701T083000
DTEND;TZID=Australia/Perth:20220701T170000
DTSTAMP:20220629T200819Z
CREATED:20220629T200539Z
LAST-MODIFIED:20220629T200819Z
UID:4898-1656664200-1656694800@marketingeda.com
SUMMARY:RIOS Open-source Hardware IP Licensing and Policy Workshop
DESCRIPTION:IOS Lab is excited to announce that the first international legal conference on open tech and IP will be held on July 1st\, 2022 (GMT+8). The main themes of the 2022 conference are open hardware licensing\, litigation protections and open source policies. Some of the most prominent and high-profile speakers and representatives from a wide range of entities will deliver presentations and panel discussions on the themes from different angles. Some featured talks are as follows: \n  \n\nAlternative microprocessor patent classifications to IPC and CPC\nObservations on open EDA\, open PDK\, and IPs and their development\nOpen Source RISC-V Cores Commercial Adoption lessons learned (Solderpad Hardware license)\nFormulation of open source technology IP rules—from bottlenecks of open source technology\nIntroduction of OIN Licenses for open source hardware\n\n  \nEveryone is welcome to attend to learn about the latest on the open source community and its legal protections and prospects from global industry giants such as Google\, top community institute leaders such as OIN\, Chip Alliance\, and OpenHW Group\, professional law firms such as King and Wood Mallesons. Register now by emailing to chen.g@rioslab.org for workshop agenda and programs.
URL:https://marketingeda.com/event/rios-open-source-hardware-ip-licensing-and-policy-workshop/
CATEGORIES:IP,Workshop
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RIOS-workshop.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20220630T080000
DTEND;TZID=Asia/Shanghai:20220630T170000
DTSTAMP:20220519T155249Z
CREATED:20220519T155249Z
LAST-MODIFIED:20220519T155249Z
UID:4746-1656576000-1656608400@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - China\, Virtual
DESCRIPTION:Date\nJune 30\, 2022 (Thursday)\nTime\nStarts at 9:00 a.m.\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-china-virtual/
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220628T103000
DTEND;TZID=Europe/Paris:20220628T113000
DTSTAMP:20220623T163054Z
CREATED:20220623T161813Z
LAST-MODIFIED:20220623T163054Z
UID:4888-1656412200-1656415800@marketingeda.com
SUMMARY:SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
DESCRIPTION:A Physically Unclonable Function or PUF is a function used to generate secret information on-chip. Information such as a secret key / public key pair may be generated on-chip each time it is needed\, while the secret key never needs to be output from the chip. \nThus the attack surface is reduced\, since only the public key needs to be extracted from the chip. This enables Zero-Trust Onboarding. \nThe intrinsic properties of the PUF and its operation make it impervious to tampering: security may not be compromised. \nMoreover\, it is possible to enroll chips late in the manufacturing process (Zero-Touch Onboarding). \nThanks to these features\, the PUF allows to enhance the security in many different applications based on cryptographic keys\, such authentication protocols\, data confidentiality and integrity\, or Secure Boot. \nBy leveraging end points integrated security\, the PUF advantages make it the perfect fit for connected devices life cycle management solutions such as Secure-IC iSSP\, which maintains over time the right level of security for fleets of devices\, during their full life-time\, by mitigating the growing threats and vulnerabilities in the field and protecting end-user devices from cyberattacks at both the network and device levels\, filtering attacks in real time and implementing a centralized protection mechanism for all connected modules. \nThis webinar will help you understand: \n\nWhy we need PUF security and how does it work?\nWhat is lifecycle security?\nHow we can leverage end points integrated security for lifecycle management?\n\n\nSylvain GUILLEY\nCTO at Secure-IC\n \nSylvain Guilley is co-founder and CTO at Secure-IC. Sylvain is also professor at “Télécom ParisTech”\, associate research at “École Normale Supérieure” (ENS)\, and adjunct professor at the Chinese Academy of Sciences (CAS). His research interests are trusted computing\, cyber-physical security\, secure prototyping in FPGA and ASIC\, and formal / mathematical methods. \nSince 2012\, he organizes the PROOFS workshop\, which brings together researchers whose objective is to increase the trust in the security of embedded systems. Sylvain is also lead editor of international standards\, such as ISO/IEC 20897 (Physically Unclonable Functions) and ISO/IEC 20085 (Calibration of non-invasive testing tools). \nSylvain has co-authored 200+ research papers and filed 30+ patents. He is member of the IACR\, and senior member of the IEEE and the CryptArchi club. He is alumni from “École Polytechnique” and “Télécom ParisTech”.
URL:https://marketingeda.com/event/securyzrtm-issp-simplifying-security-lifecycle-management-with-puf/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-June-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220628T080000
DTEND;TZID=Asia/Jerusalem:20220628T170000
DTSTAMP:20220519T155026Z
CREATED:20220519T155026Z
LAST-MODIFIED:20220519T155026Z
UID:4743-1656403200-1656435600@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - Israel
DESCRIPTION:Israel Technology Workshop (In-Person Event)\n\nDate\nJune 28\, 2022 (Tuesday)\nTime\n9:30a.m. – 4:30p.m.\nVenue\nDaniel Herzliya Hotel\nRamat Yam St 60\, Herzliya\, Israel\n\nEurope Technology Symposium (Online VOD Event)\n\nDate\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-israel/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Brussels:20220622T090000
DTEND;TZID=Europe/Brussels:20220622T110000
DTSTAMP:20220525T163320Z
CREATED:20220525T163134Z
LAST-MODIFIED:20220525T163320Z
UID:4762-1655888400-1655895600@marketingeda.com
SUMMARY:Extending Processors into Flexible Accelerators for 5G
DESCRIPTION:The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the end product.\nJoin us at Synopsys’ ASIP Designer™ Virtual Seminar 2022 to learn why ASIPs are getting so much attention these days\, and why Synopsys’ ASIP Designer is the industry’s leading tool to design\, implement\, program and verify such specialized processors.\nThis event focuses on ASIPs for 5G wireless applications and will cover the following topics:\n\n\n\nAn introduction to the ASIP Designer tool suite\nCase study: An Application Specific Vector Processor for CNN-based Massive MIMO Positioning\nCase study: 5G NR MMSE Channel Equalization using Cholesky Decomposition\n\n\n\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.\n\n\nPresenters: \n\n\n\n\n\nPatrick Verbist\n\n\nProduct Marketing Manager\n\n\nSynopsys Belgium\n\n\n\n\nPatrick Verbist is the Product Marketing Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\n\nFalco Munsche\n\n\nTechnical Marketing Manager\n\n\nSynopsys Germany\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\n\nMohammad Attari\n\n\nDigital ASIC Research Group\n\n\nEIT at Lund University\n\n\n\n\nMohammad Attari is currently a PhD student in the Digital ASIC research group in the Electrical and Information Technology (EIT) department at Lund University. His research focuses on developing Massive MIMO and next generation baseband communications processors. His interests include (but are not limited to) computer architecture\, domain specific architectures\, accelerator-level parallelism\, application specific instruction set processors (ASIP)\, neural networks\, and cross-level hardware-software (-algorithm) codesign and implementation.
URL:https://marketingeda.com/event/extending-processors-flexible-accelerators-5g/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-June-22-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220622T080000
DTEND;TZID=America/Los_Angeles:20220622T090000
DTSTAMP:20220606T145048Z
CREATED:20220606T145048Z
LAST-MODIFIED:20220606T145048Z
UID:4802-1655884800-1655888400@marketingeda.com
SUMMARY:Cost effective 5G for the IoT
DESCRIPTION:5G RedCap is an exciting new 3GPP feature\, soon to be introduced in Rel. 17 of the standard\, targeting reduced capability use cases for industrial\, wearables\, and IoT in general. We will discuss the new standard\, the market potential\, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. \nJoin CEVA to learn about: \n\nIntroduction to the 5G RedCap standard\n5G RedCap use cases and market potential\nCEVA PentaG2-Lite architecture\n\n  \nTarget Audience \nCellular system engineers and product managers targeting 5G SoCs and devices\, that are interested in the new RedCap standard for emerging applications. \nSpeakers: \n\n\n\n\nNir Shapira\nDirector for Strategic Technologies\, Mobile Broadband BU\, CEVA Inc
URL:https://marketingeda.com/event/cost-effective-5g-for-the-iot/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CEVA-June-22-2022.png
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END:VCALENDAR