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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220908T093000
DTEND;TZID=America/Los_Angeles:20220908T170000
DTSTAMP:20220726T205633Z
CREATED:20220726T205620Z
LAST-MODIFIED:20220726T205633Z
UID:4968-1662629400-1662656400@marketingeda.com
SUMMARY:ARC Processor Summit 2022
DESCRIPTION:Attend this free one-day event to get in-depth information from industry leaders on the latest ARC processor IP and related hardware/software technologies that enable you to achieve differentiation in your chip or system design. You will hear Synopsys experts\, partners\, and the ARC user community discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, security\, software development for embedded systems and much\, much more.\nWhether you are a developer of chips\, systems or software\, the ARC Processor Summit will give you practical information to help you create more differentiated products in the shortest amount of time.\nWe look forward to seeing you in person this year!
URL:https://marketingeda.com/event/arc-processor-summit-2022/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-8-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220907T080000
DTEND;TZID=America/Los_Angeles:20220907T170000
DTSTAMP:20220823T024532Z
CREATED:20220823T024532Z
LAST-MODIFIED:20220823T024532Z
UID:5126-1662537600-1662570000@marketingeda.com
SUMMARY:IP-SOC China 22
DESCRIPTION:The semiconductor world has to face a worldwide accelerated evolution\, never seen before\, both in terms of technology evolution (3D Packaging\, advanced nodes) as well as new applications (IoT\, Artificial Intelligence\, Automotive\, Security\, etc) triggering an increasing demand of Semiconductor resources. \nD&R IP SoC Event Series is fully dedicated to IP (Silicon Intellectual property) and IP based Electronic systems. The goal is to promote IP knowledge worldwide sharing as the seed of Electronic Industry permanent innovation. \nDue to the sanitary situation IP SoC China 22 will be a virtual event with a broad first day program open on September 7th. \nAny question? Please contact us
URL:https://marketingeda.com/event/ip-soc-china-22/
LOCATION:MA
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SOC-China-22.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Karachi:20220905T080000
DTEND;TZID=Asia/Karachi:20220906T170000
DTSTAMP:20220819T165004Z
CREATED:20220808T175544Z
LAST-MODIFIED:20220819T165004Z
UID:5028-1662364800-1662483600@marketingeda.com
SUMMARY:DVCon India
DESCRIPTION:On behalf of the DVCon India 2022 steering committee\, it is my pleasure to welcome you all to the 7th edition of the Design and Verification Conference in India planned from 5-6th September 2022 as a live conference.   We are bringing DVCon India 2022 as a live\, in person conference which would make it the first live event in the VLSI ecosystem in India. The conference would be following the traditional Indian version of the conference of two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey. \nThe IC industry continues to grow thanks to the Systems\, Automotive and Technology unicorns venturing to design their own chips and well-established IC companies and start-ups bringing in new innovations and chip architectures.   While there are a lot of new designs and architectures\, we continue to evolve in how we design\, verify\, and validate theses new architectures\, constantly thriving to shift left to shrink our project schedules while ensuring the designs comply with the various standards for safety and security.   All I can say is that the excitement continues to surge! \nThis year’s edition will have a good mix of Vision and Keynote talks\, lively panel discussions spread across both the days and with tutorials and short workshops on Day 1 and papers and posters on Day 2. \nThis year we have expanded our Steering Committee to ensure we expand our reach to academia and ensure active participation from academia and have also made a conscious effort to expand DVCon to academia and spread to the South East Asia and for that we have members from various companies from the ecosystem and academia in India and Sri Lanka. We have had a very strong Technical Program Committee and we want to make it even stronger and hence expanding our TPC for this year’s edition.  The entire team is working to deliver a world class technical conference and am sure you will participate to elevate the conference experience. \nWe invite the entire technical fraternity from the ecosystem to actively participate\, share their learnings with the rest of the community and take an active part in DVCon India 2022. \nThis conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation\, Methodology & Automation\, Functional Safety & Security\, Low Power and Mixed Signal Design\, Static and Formal methods and Digital Twins and SystemC Modelling.  This year\, we have added a special topic for New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation\, Big Data analysis and new algorithms in HW/SW co-design and co-verification. \nWe invite you to join us in this exciting journey and make it a grand success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2022
URL:https://marketingeda.com/event/dvcon-india-2/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220831T100000
DTEND;TZID=Europe/Paris:20220831T110000
DTSTAMP:20220823T021950Z
CREATED:20220823T021950Z
LAST-MODIFIED:20220823T021950Z
UID:5123-1661940000-1661943600@marketingeda.com
SUMMARY:Accelerating Software Development for ASIL-D Processor IP Using Synopsys Virtual Prototyping Solutions
DESCRIPTION:As systemic complexity increases and new markets such as automotive\, AI\, and 5G evolve\, it’s crucial to find the optimal software design much earlier in the development process. Synopsys Virtualizer virtual prototyping solution addresses these systemic complexity challenges\, resulting in faster time-to-market through earlier and faster software development\, and improved collaboration throughout the supply chain. \nNSITEXE\, a Denso subsidiary company\, has successfully developed an advanced ASIL-D ready processor and a virtual model for software development using Synopsys Virtualizer. Join this presentation to hear how NSITEXE utilizes the latest techniques and methodologies using Synopsys Virtualizer virtual prototypes to deliver its IP through the supply chain working with a common virtual platform in various industries\, such as automotive\, embedded\, and factory automation. Learn how the supply chain ecosystem can accelerate development using both solutions. \n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Tim Kogel\n\n\nPrincipal Engineer\nSynopsys \n\n\n\n\n\n\n\n\nDr. Tim Kogel is a Principal Engineer for Virtual Prototyping in the Systems Design Group of Synopsys. He received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH)\, Aachen\, Germany\, in 1999 and 2005. He has authored a book and numerous technical and scientific publications on system-level modeling of SoC platforms. Tim is leading a team of applications engineering specialists\, responsible for the definition\, realization and deployment of Synopsys’ Virtual Prototyping solutions. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Masayuki Ito\n\n\nDirector of Business Promotion\nNSITEXE\, Inc. \n\n\n\n\n\n\n\n\nDr. Masayuki Ito is Director in Business Promotion Unit at NSITEXE\, Inc.\, Denso’s subsidiary\, where he focuses on business promotions for its own IP-products: RISC-V processor\, AI accelerators\, and Security Solutions. He has more than 20 years of experience in the semiconductor industry. He started his career in the Semiconductor Development Center in Hitachi Ltd. in Tokyo\, followed by Renesas Technology Corporation. and Renesas Electronics Corporation. Throughout his career he consistently worked for processor and SoC development for mobile and automobile. He holds a master’s degree in Computer engineering from Kyoto University and a Ph.D.in Science and Engineering from Tokyo Institute of Technology in Japan.
URL:https://marketingeda.com/event/accelerating-software-development-for-asil-d-processor-ip-using-synopsys-virtual-prototyping-solutions/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220824T080000
DTEND;TZID=America/Los_Angeles:20220824T090000
DTSTAMP:20220823T163315Z
CREATED:20220823T163315Z
LAST-MODIFIED:20220823T163315Z
UID:5129-1661328000-1661331600@marketingeda.com
SUMMARY:Arm Immortalis-G715 GPU
DESCRIPTION:Dan Wilson\, Director Product Management\, Arm \n\n\nAbout this talk\nThe new Arm flagship GPU\, Immortalis-G715\, is designed to enable the very best gaming experiences on next-generation flagship smartphones. Join this webinar for a detailed examination of the latest graphics features made possible by Immortalis-G715\, including hardware-based ray tracing support for more realistic and immersive mobile gaming experiences. Also\, learn about key improvements and enhancements across the latest range of Arm GPUs that make them the highest performing\, most energy efficient to date.\n\nAgenda:\n• Introduction – Immortalis-G715: Arm’s new flagship GPU.\n• New graphic and gaming features\, including hardware-based ray tracing support through Immortalis-G715 and variable rating shading across all the new Arm GPUs.\n• Performance\, efficiency\, and ML improvements and graphics enhancements across all new Arm GPUs.\n• The latest developer support and optimizations beyond the IP\, including resources and tools for to enable the best application experiences.\n• Q&A\n\nWho should attend:\n• Consumer device OEMs\, semiconductor manufacturers\, and mobile game developers.
URL:https://marketingeda.com/event/arm-immortalis-g715-gpu/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Arm-August-24-2022.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Sao_Paulo:20220822T080000
DTEND;TZID=America/Sao_Paulo:20220826T170000
DTSTAMP:20220820T233927Z
CREATED:20220820T233927Z
LAST-MODIFIED:20220820T233927Z
UID:5104-1661155200-1661533200@marketingeda.com
SUMMARY:SBCCI 2022
DESCRIPTION:35ᵗʰ Symposium on Integrated Circuits and Systems Design \nSBCCI is an international forum dedicated to integrated circuits and systems design\, held annually in Brazil. The 35th SBCCI will be virtual from the Rio Grande do Sul state\, Brazil. This originates the name Chip in the Minuano – Minuano wind is the cold southwesterly current of air that typically affects the state. The goal of the symposium is to bring together researchers in the areas of EDA\, design\, and test of integrated circuits and systems. The scope of the symposium includes technical sessions\, tutorials\, and panels\, as well as an exhibition and working group meetings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. The best papers presented at the symposium will be invited to resubmit an extended version to be considered for publication at the IEEE Design & Test\, at the Springer Nature ALOG (Analog Integrated Circuits and Signal Processing)\, and at SBMicro/SBC JICS (Journal of Integrated Circuits and Systems). Information about paper submission is available on the conference webpage. \n\n\nThe areas of interest include:\n• System-level modeling and synthesis\n• Hardware-software co-design and co-verification\n• High-level and logic synthesis\n• Physical design of ICs and systems\n• EDA – Electronic Design Automation\n• Testability issues\, design for test techniques\n• Design and modeling languages and applications\n• Analog\, Digital\, and mixed-signal designs\n• Embedded systems and Cyber-physical systems design\n• System-on-chip\, IP reuse\, and platform-based designs\n• Low power tools and designs techniques
URL:https://marketingeda.com/event/sbcci-2022/
LOCATION:MA
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/SBCCI-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220821T080000
DTEND;TZID=America/Los_Angeles:20220823T170000
DTSTAMP:20220615T165130Z
CREATED:20220615T165130Z
LAST-MODIFIED:20220615T165130Z
UID:4843-1661068800-1661274000@marketingeda.com
SUMMARY:Hot Chips 2022
DESCRIPTION:HC34(2022) (advance program) will take place virtually from Sunday\, August 21 – Tuesday\, August 23\, 2022. \nAll HC33(2021) conference content open to public. Visit https://hc33.hotchips.org. \nSince it started in 1989\, HOT CHIPS has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity\, Silicon Valley. \nThe HOT CHIPS conference typically attracts more than 500 attendees from all over the world. It provides an opportunity for chip designers\, computer architects\, system engineers\, press and analysts\, as well as attendees from national laboratories and academia to mix\, mingle and see presentations on the latest technologies and products. The three days of the conference typically feature two tutorials\, two keynotes\, a panel discussion and around 25 presentations on a variety of subjects related to microprocessors and integrated circuits. It is widely covered by the media; last year\, we had about 25 members of the industry and national press covering the conference. \nPresentations at HOT CHIPS are in the form of 30-minute talks. Presentation slides are published in the HOT CHIPS proceedings and online in the archives section of the HOT CHIPS website. Participants are not required to submit written papers\, but a select group are invited to submit a paper for inclusion in a special issue of IEEE Micro. \nThe conference emphasis this year\, as in previous years\, is on real products and realizable technology. Submissions are invited from a variety of “hot” topics\, including embedded and reconfigurable processors\, quantum computing\, nano structures\, wireless chips\, network/security processors\, advanced packaging technology etc. For a complete list of topics\, refer to the official call for papers. \nThe program committee consisting of members from academia and industry\, is busy sorting through a record number of paper submissions this year. As usual\, the passionate and highly dedicated members of the program and organizing committees are working together to provide high quality content and experience to the HOT CHIPS conference attendees. \nThank you for your interest in HOT CHIPS. We hope to see you at the conference! \nVirtual Conference: The conference will take place live in an all digital format: \n\nAll tutorials\, keynotes\, and sessions will be broadcast in a live video stream that all registered conference attendees will be able to access with a password protected login. Conference credentials will be emailed to you starting Monday\, August 15 at 3:00 PM PDT. If you are not in the Pacific Time Zone\, you will be able to watch a recording of the video stream when it is convenient for you.\nAlong with the video stream login\, registered attendees will have access to the Hot Chips Slack workspace.  This workspace will be where questions can be submitted for presenters to answer live following their talks\, or answer in the channel assigned to the talk throughout the conference.  Presenters will answer your questions live during the last 5 minutes of their presentation. You won’t have to scramble to the microphone\, just post your question in the Slack channel\, one channel per presentation.\nAttendees will have access in the Slack workspace to this year’s selected posters.  The posters can be viewed at any time once the conference starts and poster presenters will be available during set times via Slack to answer your questions.\nMany of our sponsors will be hosting virtual tables which can be accessed from this website and through the Slack workspace.  You can connect with sponsors\, view product demos\, and talk to their representatives.
URL:https://marketingeda.com/event/hot-chips-2022/
LOCATION:MA
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/HotChips34.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220817T100000
DTEND;TZID=America/Los_Angeles:20220817T110000
DTSTAMP:20220805T173528Z
CREATED:20220805T173528Z
LAST-MODIFIED:20220805T173528Z
UID:5018-1660730400-1660734000@marketingeda.com
SUMMARY:FPGAs for AI and AI for FPGAs
DESCRIPTION:Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications\, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism\, while being flexible and easily configurable\, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use cases. \nThe emergence of Deep Learning as an omnipresent workload has driven FPGA architecture evolution as well. Academic researchers have proposed optimizing the architecture of FPGAs to better fit the needs of DL workloads and FPGA companies now have AI-optimized FPGAs in their product portfolios. \nFPGAs are very well-suited for prototyping and accelerating the rapidly changing algorithms and novel network architectures in the field of DL. In addition\, DL is being used to assist in chip design processes such as power prediction\, floorplanning\, etc. including for FPGAs. \nWhat you will learn:\nIn this webinar\, we will discuss recent innovations in DL-optimized FPGA architecture\, using AI to estimate things such as power consumption on (new or existing) FPGAs and new types of neural network accelerators using existing FPGAs. \nPresenter: \nDr. Lizy Kurian John holds the Cullen Trust for Higher Education Endowed Professorship in Electrical Engineering in the Department of Electrical & Computer Engineering at The University of Texas at Austin. She received her Ph.D. in computer engineering from The Pennsylvania State University. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture\, multicore processors\, memory systems\, performance evaluation and benchmarking\, workload characterization\, and reconfigurable computing. \nProfessor John holds 15 U. S. patents\, has coauthored 4 books\, 16 book chapters\, and approximately 300 journal/ conferences/workshop papers. She is a Fellow of IEEE\, Fellow of ACM and a Fellow of the National Academy of Inventors (NAI).
URL:https://marketingeda.com/event/fpgas-for-ai-and-ai-for-fpgas/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSFPGA-August-17-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220804T100000
DTEND;TZID=America/Los_Angeles:20220804T110000
DTSTAMP:20220730T003409Z
CREATED:20220730T003409Z
LAST-MODIFIED:20220730T003409Z
UID:4973-1659607200-1659610800@marketingeda.com
SUMMARY:A Smart and Automatic Assembly and Connections for SoCs
DESCRIPTION:Learn how to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators\, bridges\, channels\, bus fabrics\, muxes\, etc. wherever needed.
URL:https://marketingeda.com/event/a-smart-and-automatic-assembly-and-connections-for-socs/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2BA08003-45F1-463F-88DC-BAE1A46EDDED.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220714T100000
DTEND;TZID=America/Los_Angeles:20220714T110000
DTSTAMP:20220610T050529Z
CREATED:20220610T050529Z
LAST-MODIFIED:20220610T050529Z
UID:4827-1657792800-1657796400@marketingeda.com
SUMMARY:Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges
DESCRIPTION:PCIe\, the most popular interconnect in compute\, AI and storage systems\, is now offering faster data rate\, higher performance\, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling\, challenges such as signal integrity\, power integrity\, implementation\, IP integration and more must be considered when designing 64GT/s systems. This Synopsys webinar explains how designers can overcome these challenges by accounting for PCIe 6.0 system-level co-design in pre-silicon. In addition\, the Synopsys webinar highlights the importance of pre-silicon validation for overall system integration\, performance and compliance. \n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMadhumita Sanyal\n\n\nSr. Staff Technical Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nMadhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products\, logic libraries\, embedded memories\, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNarasimha Babu GVL\n\n\nSynopsys Scientist\nSynopsys \n\n\n\n\n\n\n\n\nNarasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including PCIe and CXL. Babu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India 2022 steering committee. He is also actively involved in writing and editing technical blog publications on PCIe and CXL verification.
URL:https://marketingeda.com/event/overcoming-pcie-6-0-system-integration-and-pre-silicon-validation-challenges/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-July-14-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220710T080000
DTEND;TZID=America/Los_Angeles:20220714T170000
DTSTAMP:20220429T201931Z
CREATED:20220429T201907Z
LAST-MODIFIED:20220429T201931Z
UID:4613-1657440000-1657818000@marketingeda.com
SUMMARY:Design Automation Conference\, 2022
DESCRIPTION:The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems.  DAC offers outstanding training\, education\, exhibits and superb networking opportunities for designers\, researchers\, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA). \nMembers are from a diverse worldwide community of more than 1\,000 organizations that attend each year\, represented by system designers and architects\, logic and circuit designers\, validation engineers\, CAD managers\, senior managers and executives\, and researchers and academicians from leading universities. \nOver five days\, DAC provides over 300 technical presentations and sessions that are selected by a committee of electronic design and university research experts offering information on recent developments and trends\, management practices and new products\, methodologies\, and technologies in the electronics industry. \nA highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging companies in: \n\nArtificial Intelligence/ Machine Learning (AI/ ML)\nAutomotive\nDesign Services\nDesign on Cloud\nElectronic Design Automation (EDA)\nEmbedded Systems and Software (ESS)\nIntellectual Property (IP)\nSecurity/Privacy
URL:https://marketingeda.com/event/design-automation-conference-2022/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220710T080000
DTEND;TZID=America/Los_Angeles:20220714T170000
DTSTAMP:20220119T035414Z
CREATED:20220119T035414Z
LAST-MODIFIED:20220119T035414Z
UID:4200-1657440000-1657818000@marketingeda.com
SUMMARY:59th DAC
DESCRIPTION:The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits.\nDAC focuses on the latest methodologies and technology advancements in electronic design. Get ready for 59th DAC returning to San Francisco\, California this July 10-14 at the Moscone West Center. Join researchers\, designers\, practitioners\, tool developers\, students\, vendors and more at DAC 2022.
URL:https://marketingeda.com/event/59th-dac/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/dac59.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Australia/Perth:20220701T083000
DTEND;TZID=Australia/Perth:20220701T170000
DTSTAMP:20220629T200819Z
CREATED:20220629T200539Z
LAST-MODIFIED:20220629T200819Z
UID:4898-1656664200-1656694800@marketingeda.com
SUMMARY:RIOS Open-source Hardware IP Licensing and Policy Workshop
DESCRIPTION:IOS Lab is excited to announce that the first international legal conference on open tech and IP will be held on July 1st\, 2022 (GMT+8). The main themes of the 2022 conference are open hardware licensing\, litigation protections and open source policies. Some of the most prominent and high-profile speakers and representatives from a wide range of entities will deliver presentations and panel discussions on the themes from different angles. Some featured talks are as follows: \n  \n\nAlternative microprocessor patent classifications to IPC and CPC\nObservations on open EDA\, open PDK\, and IPs and their development\nOpen Source RISC-V Cores Commercial Adoption lessons learned (Solderpad Hardware license)\nFormulation of open source technology IP rules—from bottlenecks of open source technology\nIntroduction of OIN Licenses for open source hardware\n\n  \nEveryone is welcome to attend to learn about the latest on the open source community and its legal protections and prospects from global industry giants such as Google\, top community institute leaders such as OIN\, Chip Alliance\, and OpenHW Group\, professional law firms such as King and Wood Mallesons. Register now by emailing to chen.g@rioslab.org for workshop agenda and programs.
URL:https://marketingeda.com/event/rios-open-source-hardware-ip-licensing-and-policy-workshop/
LOCATION:MA
CATEGORIES:IP,Workshop
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RIOS-workshop.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20220630T080000
DTEND;TZID=Asia/Shanghai:20220630T170000
DTSTAMP:20220519T155249Z
CREATED:20220519T155249Z
LAST-MODIFIED:20220519T155249Z
UID:4746-1656576000-1656608400@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - China\, Virtual
DESCRIPTION:Date\nJune 30\, 2022 (Thursday)\nTime\nStarts at 9:00 a.m.\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-china-virtual/
LOCATION:MA
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220628T103000
DTEND;TZID=Europe/Paris:20220628T113000
DTSTAMP:20220623T163054Z
CREATED:20220623T161813Z
LAST-MODIFIED:20220623T163054Z
UID:4888-1656412200-1656415800@marketingeda.com
SUMMARY:SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
DESCRIPTION:A Physically Unclonable Function or PUF is a function used to generate secret information on-chip. Information such as a secret key / public key pair may be generated on-chip each time it is needed\, while the secret key never needs to be output from the chip. \nThus the attack surface is reduced\, since only the public key needs to be extracted from the chip. This enables Zero-Trust Onboarding. \nThe intrinsic properties of the PUF and its operation make it impervious to tampering: security may not be compromised. \nMoreover\, it is possible to enroll chips late in the manufacturing process (Zero-Touch Onboarding). \nThanks to these features\, the PUF allows to enhance the security in many different applications based on cryptographic keys\, such authentication protocols\, data confidentiality and integrity\, or Secure Boot. \nBy leveraging end points integrated security\, the PUF advantages make it the perfect fit for connected devices life cycle management solutions such as Secure-IC iSSP\, which maintains over time the right level of security for fleets of devices\, during their full life-time\, by mitigating the growing threats and vulnerabilities in the field and protecting end-user devices from cyberattacks at both the network and device levels\, filtering attacks in real time and implementing a centralized protection mechanism for all connected modules. \nThis webinar will help you understand: \n\nWhy we need PUF security and how does it work?\nWhat is lifecycle security?\nHow we can leverage end points integrated security for lifecycle management?\n\n\nSylvain GUILLEY\nCTO at Secure-IC\n \nSylvain Guilley is co-founder and CTO at Secure-IC. Sylvain is also professor at “Télécom ParisTech”\, associate research at “École Normale Supérieure” (ENS)\, and adjunct professor at the Chinese Academy of Sciences (CAS). His research interests are trusted computing\, cyber-physical security\, secure prototyping in FPGA and ASIC\, and formal / mathematical methods. \nSince 2012\, he organizes the PROOFS workshop\, which brings together researchers whose objective is to increase the trust in the security of embedded systems. Sylvain is also lead editor of international standards\, such as ISO/IEC 20897 (Physically Unclonable Functions) and ISO/IEC 20085 (Calibration of non-invasive testing tools). \nSylvain has co-authored 200+ research papers and filed 30+ patents. He is member of the IACR\, and senior member of the IEEE and the CryptArchi club. He is alumni from “École Polytechnique” and “Télécom ParisTech”.
URL:https://marketingeda.com/event/securyzrtm-issp-simplifying-security-lifecycle-management-with-puf/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-June-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220628T080000
DTEND;TZID=Asia/Jerusalem:20220628T170000
DTSTAMP:20220519T155026Z
CREATED:20220519T155026Z
LAST-MODIFIED:20220519T155026Z
UID:4743-1656403200-1656435600@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - Israel
DESCRIPTION:Israel Technology Workshop (In-Person Event)\n\nDate\nJune 28\, 2022 (Tuesday)\nTime\n9:30a.m. – 4:30p.m.\nVenue\nDaniel Herzliya Hotel\nRamat Yam St 60\, Herzliya\, Israel\n\nEurope Technology Symposium (Online VOD Event)\n\nDate\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-israel/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Brussels:20220622T090000
DTEND;TZID=Europe/Brussels:20220622T110000
DTSTAMP:20220525T163320Z
CREATED:20220525T163134Z
LAST-MODIFIED:20220525T163320Z
UID:4762-1655888400-1655895600@marketingeda.com
SUMMARY:Extending Processors into Flexible Accelerators for 5G
DESCRIPTION:The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the end product.\nJoin us at Synopsys’ ASIP Designer™ Virtual Seminar 2022 to learn why ASIPs are getting so much attention these days\, and why Synopsys’ ASIP Designer is the industry’s leading tool to design\, implement\, program and verify such specialized processors.\nThis event focuses on ASIPs for 5G wireless applications and will cover the following topics:\n\n\n\nAn introduction to the ASIP Designer tool suite\nCase study: An Application Specific Vector Processor for CNN-based Massive MIMO Positioning\nCase study: 5G NR MMSE Channel Equalization using Cholesky Decomposition\n\n\n\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.\n\n\nPresenters: \n\n\n\n\n\nPatrick Verbist\n\n\nProduct Marketing Manager\n\n\nSynopsys Belgium\n\n\n\n\nPatrick Verbist is the Product Marketing Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\n\nFalco Munsche\n\n\nTechnical Marketing Manager\n\n\nSynopsys Germany\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\n\nMohammad Attari\n\n\nDigital ASIC Research Group\n\n\nEIT at Lund University\n\n\n\n\nMohammad Attari is currently a PhD student in the Digital ASIC research group in the Electrical and Information Technology (EIT) department at Lund University. His research focuses on developing Massive MIMO and next generation baseband communications processors. His interests include (but are not limited to) computer architecture\, domain specific architectures\, accelerator-level parallelism\, application specific instruction set processors (ASIP)\, neural networks\, and cross-level hardware-software (-algorithm) codesign and implementation.
URL:https://marketingeda.com/event/extending-processors-flexible-accelerators-5g/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-June-22-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220622T080000
DTEND;TZID=America/Los_Angeles:20220622T090000
DTSTAMP:20220606T145048Z
CREATED:20220606T145048Z
LAST-MODIFIED:20220606T145048Z
UID:4802-1655884800-1655888400@marketingeda.com
SUMMARY:Cost effective 5G for the IoT
DESCRIPTION:5G RedCap is an exciting new 3GPP feature\, soon to be introduced in Rel. 17 of the standard\, targeting reduced capability use cases for industrial\, wearables\, and IoT in general. We will discuss the new standard\, the market potential\, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. \nJoin CEVA to learn about: \n\nIntroduction to the 5G RedCap standard\n5G RedCap use cases and market potential\nCEVA PentaG2-Lite architecture\n\n  \nTarget Audience \nCellular system engineers and product managers targeting 5G SoCs and devices\, that are interested in the new RedCap standard for emerging applications. \nSpeakers: \n\n\n\n\nNir Shapira\nDirector for Strategic Technologies\, Mobile Broadband BU\, CEVA Inc
URL:https://marketingeda.com/event/cost-effective-5g-for-the-iot/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CEVA-June-22-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220622T020000
DTEND;TZID=America/New_York:20220622T150000
DTSTAMP:20220613T211131Z
CREATED:20220613T211131Z
LAST-MODIFIED:20220613T211131Z
UID:4834-1655863200-1655910000@marketingeda.com
SUMMARY:Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
DESCRIPTION:Standards such as ISO 26262 define strict requirements\, processes\, and methods that all stakeholders – IP vendors\, sub-system developers\, and semiconductor SoC and system developers – must abide by when designing safety-critical automotive products. One such requirement is the Development Interface Agreement (DIA)\, which defines the interactions\, interfaces\, responsibilities\, dependencies\, and work products exchanged between customers and suppliers for all distributed safety-related activities.\n\nThis 60-minute Webinar explains the details of distributed development based on DIA and outlines the different activities for which DIAs must be signed during a distributed development process. In the second part of the presentation\, an engineer from Infineon discusses their approach to meeting SoC-level functional safety objectives while closely collaborating with Synopsys.\n\n\nSpeakers:\nDietmar Koenig\, Lead Principal Engineer\, Infineon\nDietmar Koenig is a Lead Principal Engineer at Infineon with technical responsibility for the execution of safety-related work products in the Infineon Automotive Microcontroller division. He has 23 years of experience in microcontroller concept development at Siemens and Infineon and more than 18 years of experience on safety concepts for microcontrollers. \nVladimir Litovtchenko\, Director\, Functional Safety and Quality Engineering\, Synopsys  \nVladimir Litovtchenko is a Director for the functional safety team at Synopsys. He has more than 19 years of experience in the semiconductor industry focusing on automotive functional safety products and development flows. He spent 12 years as Senior Systems and SoC Design Engineer at Freescale/NXP and nearly three years at Infineon as a Senior MCU Concept and Functional Safety Expert. As a Senior Staff Concept Engineer at Infineon\, Vladimir worked on functional safety architectures and concepts for automotive MCU SoCs. He holds more than 23 EU and US patents and has published several papers and presentations. \nModerator: Amanda Hosey\, Editor\, SAE Media Group
URL:https://marketingeda.com/event/simplify-streamline-development-of-iso-26262-compliant-automotive-socs/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAE-Media-Group-June-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220620T080000
DTEND;TZID=Europe/Paris:20220621T170000
DTSTAMP:20220620T144134Z
CREATED:20220620T144134Z
LAST-MODIFIED:20220620T144134Z
UID:4871-1655712000-1655830800@marketingeda.com
SUMMARY:Leti Innovation Days
DESCRIPTION:The chip shortage has brought with it an extraordinary boost to Moore’s Law. \n Discover policy maker and tech leader strategic decisions on downscaling\, “More than Moore electronics” and other future technologies for components.\n Identify key emerging technologies to grow your business.\n\n\nPlenary Session\n\n\nA plenary session will gather high-level keynote speakers to discuss novel tech strategies to foster out performance. As our world continues to change rapidly and we reach a key turning point in the electronics industry\, hear from CEOs\, executives and decision makers in order to better understand and meet the challenges of exponential demand for smart electronics in our daily lives. Join us to innovate and participate as a game changer.\n\n\n\n​​6 Workshops: choose yours!\n\n\n\nNew Paradigms for Computing Workshop\nSatellite Communication Workshop\nSMEs & the International Market Workshop\nMore than Moore Workshop\nSustainability Workshop\nHealthcare Workshop\n\nExhibition & Networking\n\n\n\nLive demos: Discover more than 40 live demos and network with potential partners.\n\n\nStartup Corner: Don’t miss out on the startup corner to learn about the latest tech offers.\n\n\nBusiness Meetings: Book meetings with experts to discuss your innovation project.\n\n\nForum Area: Listen 15 minute sales-oriented pitches. Discover the latest developments offered by CEA-Leti startups and local SMEs specializing in microelectronics.\n\n\nNetworking: Join us for two evening receptions.
URL:https://marketingeda.com/event/leti-innovation-days/
LOCATION:Minalogic\, 3 PARV Louis Neel\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Leti-Innovation-Days-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Amsterdam:20220620T080000
DTEND;TZID=Europe/Amsterdam:20220620T170000
DTSTAMP:20220519T154700Z
CREATED:20220519T154638Z
LAST-MODIFIED:20220519T154700Z
UID:4739-1655712000-1655744400@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - Europe
DESCRIPTION:Europe Technology Symposium (In-Person Event)\n\nDate\nJune 20\, 2022 (Monday)\nTime\n8:30a.m. – 4:50p.m.\nVenue\nHilton Amsterdam Airport Schiphol\nSchiphol Boulevard 701Amsterdam\,1118BN Netherlands\n\nIsrael Technology Workshop (In-Person Event)\n\nDate\nJune 28\, 2022 (Tuesday)\nTime\n9:30a.m. – 4:30p.m.\nVenue\nDaniel Herzliya Hotel\nRamat Yam St 60\, Herzliya\, Israel\n\nEurope Technology Symposium (Online VOD Event)\n\nDate\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-europe/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220616T080000
DTEND;TZID=America/Los_Angeles:20220616T170000
DTSTAMP:20220519T154250Z
CREATED:20220519T154250Z
LAST-MODIFIED:20220519T154250Z
UID:4736-1655366400-1655398800@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - North America
DESCRIPTION:A Technology Symposium (In-Person Event)\nDate:\nJune 16\, 2022 (Thursday)\nTime:\n8:30a.m. – 5:05p.m.\nVenue:\nSanta Clara Convention Center\n5001 Great America Parkway\,\nSanta Clara\, CA 95054\n\n\nNA Technology Symposium (Online VOD Event)\nDate:\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220608T080000
DTEND;TZID=America/Los_Angeles:20220609T170000
DTSTAMP:20220601T175752Z
CREATED:20220303T004334Z
LAST-MODIFIED:20220601T175752Z
UID:4407-1654675200-1654794000@marketingeda.com
SUMMARY:CadenceLIVE 2022 - Silicon Valley
DESCRIPTION:Are you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer tips to address the complexities and challenges that engineers face today. CadenceLIVE Silicon Valley features peer presentations that highlight solutions\, using Cadence® products\, for today’s design challenges. \nCurrently\, we are expecting CadenceLIVE Silicon Valley 2022 to be an in-person conference with digital\, on-demand access available two to three weeks after the event. Please note\, we always follow local\, state\, and federal orders and CDC guidelines\, and will make adjustments to the event format as needed. \nShould you have any questions about abstract submissions\, please email cadencelive@cadence.com \n 
URL:https://marketingeda.com/event/cadencelive-2022-silicon-valley/
LOCATION:Cadence\, San Jose\, CA\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-8-9-2022-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220607T100000
DTEND;TZID=America/Los_Angeles:20220607T110000
DTSTAMP:20220601T174855Z
CREATED:20220601T174855Z
LAST-MODIFIED:20220601T174855Z
UID:4785-1654596000-1654599600@marketingeda.com
SUMMARY:Embedded Applications Get a Helping Hand: Extensible Processor Architectures
DESCRIPTION:Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today\, many embedded applications such as those found in artificial intelligence (AI)\, automotive and storage segments require increased bandwidth and memory address space expansion. As Moore’s law slows\, design teams seek different ways to deliver unique solutions for these applications while maintaining power\, performance\, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools\, and software ecosystem\, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how highly extensible processor architectures can enable designers to meet their application requirements and provide SoC differentiation. \nAttend this Synopsys webinar to learn about: \n\nTypical ISA trade-offs designers must make for high-end application development\nHow to achieve design flexibility through configurable\, scalable processor architectures\nHow leveraging extensibility options of Synopsys ARC® Processors can provide SoC differentiation\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\n\n\n\n\n\n\n\n\nDirector of Product Marketing\nSynopsys \n\n\n\n\n\n\n\n\nRich Collins is director of product marketing for ARC Processors and Subsystems at Synopsys. Rich has over 25 years of experience in embedded semiconductor R&D\, product marketing and business development\, including 17 years at Motorola/Freescale before joining Synopsys. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.
URL:https://marketingeda.com/event/embedded-applications-get-a-helping-hand-extensible-processor-architectures/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-June-7-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220531T080000
DTEND;TZID=Asia/Tokyo:20220602T170000
DTSTAMP:20220510T154735Z
CREATED:20220510T154735Z
LAST-MODIFIED:20220510T154735Z
UID:4668-1653984000-1654189200@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2022 Spring
DESCRIPTION:RISC-V Days Tokyo is Japan’s largest online RISC-V event.  Live online presentations are hosted on May 31st (Tue)\, June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products\, key persons and engineers\, and to provide business opportunities for product recognition\, collaboration among companies\, technology exchange and information gathering. We look forward to your participation in this opportunity! \n \n\nGoogle\nSiemens\nefabless\nImperas\nSHC\nDTS\n\n\n\nSiFive\nCodaSip\neFinix\neSol Trinity\nGigaDevice\nIAR Systems\n\n\n\nImagination\nMIPS\nSIgnate\nRISC-V\nKeio University\nRed Hat\nThe University of Tokyo\nUEC Tokyo\n\n\n 
URL:https://marketingeda.com/event/risc-v-days-tokyo-2022-spring/
LOCATION:MA
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Day-Tokyo-2022-Spring-Logo.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T100000
DTEND;TZID=America/Los_Angeles:20220524T110000
DTSTAMP:20220511T045624Z
CREATED:20220511T045624Z
LAST-MODIFIED:20220511T045624Z
UID:4674-1653386400-1653390000@marketingeda.com
SUMMARY:DSP IP for High Performance Sensor Fusion on an Embedded Budget
DESCRIPTION:The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition\, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput. \nIn this webinar we will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing\, often combining classical filtering operations and AI-based decision making. Featuring the Synopsys ARC® VPX DSP family\, we will explain key functions that can be optimized to handle a spectrum of sensor fusion workloads\, while adhering to a single programming environment. \nSpeaker\n\n\n\n\nPieter van der Wolf\n\n\nPrincipal R&D Engineer\nSynopsys \n\n\n\n\n\n\n\n\nPieter van der Wolf is a Principal R&D Engineer at Synopsys. He received his MSc and PhD degrees in Electrical Engineering from the Delft University of Technology. He was an Associate Professor at the Delft University of Technology before joining Philips Research in 1996. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. In 2009 he joined Virage Logic\, which was subsequently acquired by Synopsys. He has worked on a broad range of topics including multi-processor architectures and system design methodologies.
URL:https://marketingeda.com/event/dsp-ip-for-high-performance-sensor-fusion-on-an-embedded-budget/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T080000
DTEND;TZID=America/Los_Angeles:20220524T093000
DTSTAMP:20220516T163304Z
CREATED:20220516T163304Z
LAST-MODIFIED:20220516T163304Z
UID:4710-1653379200-1653384600@marketingeda.com
SUMMARY:Automotive Cyber-Security: Off-board and On-board\, standards and technologies
DESCRIPTION:This webinar will help you understand:\n• The different standards that exist and why is compliance so important?\n• How to protect against tampering attacks?\n• What is lifecycle security and how can it benefit the automotive industry?\n• Why is it important to protect the whole lifecycle of a device?
URL:https://marketingeda.com/event/automotive-cyber-security-off-board-and-on-board-standards-and-technologies/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Secure-IC-May-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220517T080000
DTEND;TZID=America/Los_Angeles:20220518T170000
DTSTAMP:20220511T162123Z
CREATED:20220511T162123Z
LAST-MODIFIED:20220511T162123Z
UID:4677-1652774400-1652893200@marketingeda.com
SUMMARY:Embedded Vision Summit
DESCRIPTION:The premier event for practical\, deployable computer vision and visual AI\, for product creators who want to bring visual intelligence to products. \n\n\n\n\nThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy attend? It’s a First-Rate Program with Powerful Insights into Practical Visual AI. \n\n\n\n\n\nJoin us for four days of learning—from tutorials to deep-dive days\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\n\n4 Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\nWe’ve been doing this for 11 years.\n\n\nA whopping 97% of our attendees would recommend the Summit to a colleague.
URL:https://marketingeda.com/event/embedded-vision-summit/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summit-May-16-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220512T100000
DTEND;TZID=America/Los_Angeles:20220512T110000
DTSTAMP:20220505T180841Z
CREATED:20220505T180841Z
LAST-MODIFIED:20220505T180841Z
UID:4631-1652349600-1652353200@marketingeda.com
SUMMARY:AMBA AHB Subsystems and How to Customize\, Secure\, and Verify
DESCRIPTION:AMBA is a set of interconnect specifications that standardizes on chip communication mechanisms between various functional blocks (or IP) for building SOC designs. Silvaco’s AMBA AHB subsystems provide the basic interconnect and functional subsystems enabling SOC designers to target products such as IoT Devices\, Medical Devices\, Industrial Controllers\, Wireless Gateways\, and many more applications.  These designs typically have one or more micro controllers or microprocessors along with several other subsystem components. \nThis webinar will provide an overview of the AMBA AHB subsystems and products offered by Silvaco. Some topics of discussion include Channel vs. Fabric architecture\, low power\, customization\, hardware- and software-based security\, and co-verification of the hardware and software. \nWhat You Will Learn \n\nOverview of Silvaco’s portfolio of AMBA AHB subsystems\, features\, and capabilities\nWhich architecture to use for a given application: Channel vs. Fabric\nCustomization of subsystems\nSecurity Issues with traditional Cortex-M architecture\nOverview of Secure Subsystem Security features\nSoftware as a component of hardware simulation\nSecurity improvements\, software security\, and secure boot\n\nBio\nJim Avant\, Senior Hardware and Software Engineer\,\nIP Division\, Silvaco\, Inc.\nJim Avant is a senior hardware and software engineer in Silvaco’s IP Division. He is the primary designer for several digital soft IP designs including the Secure AHB Subsystem. Prior to joining Silvaco in 2017\, Jim was a senior design engineer at SoC Solutions. He has an extensive background in RTL digital logic design\, digital signal processing\, and embedded C programming.\nJim Avant holds a bachelor’s degree in Electrical Engineering (BEE) from Georgia Tech in Atlanta\, Georgia.
URL:https://marketingeda.com/event/amba-ahb-subsystems-and-how-to-customize-secure-and-verify/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-May-12-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220511T100000
DTEND;TZID=America/Los_Angeles:20220511T130000
DTSTAMP:20220419T200653Z
CREATED:20220419T200653Z
LAST-MODIFIED:20220419T200653Z
UID:4569-1652263200-1652274000@marketingeda.com
SUMMARY:Arm and Cadence: Achieving Best Silicon Power\, Performance\, and Area
DESCRIPTION:How do you deal with design requirements that span high performance\, energy-efficient computing\, and high-reliability implementation? To realize these goals\, you need optimal design flows to deliver the best power\, performance\, and reliability. \nJoin Cadence and Arm virtually for CadenceCONNECT: Arm and Cadence – Achieving Best Silicon Power\, Performance\, and Area. Learn about: \n\nHigh-performance design for the Arm® Cortex®-A710 and other Arm processors\nEnergy-efficient CPU implementation flows\nHigh-reliability design using Arm library IP\nAging-aware static timing analysis (STA)\n\nExplore how you can efficiently implement your Arm-based SoCs with the Cadence® digital full-flow solution and get the best power\, performance\, and area (PPA). \nRegister now and join us on May 11. \nEvent times per region. Each event is 3 hours long. \nAsia-Pacific\n9:00am CST | 10:00am JST\, KST \nEurope\, Israel\, India\n9:00am BST | 10:00am CEST | 11:00am Israel | 1:30pm India​ \nNorth America\n1:00pm EDT I 10:00am PDT \n  \n\n\n\nSessions\nSpeaker\n\n\nDelivering Best-in-Class PA and TAT for Arm Total Compute\nUsing Cadence Digital Full Flow\nPierre-Alexandre Bou-Ach\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nAchieving Outstanding Performance for Arm Cortex-A710 Processor\nUsing Samsung Foundry 4LPP and the Cadence Digital Flow\nChinthamani Jagannath\, Cadence\n\n\nEnergy-Efficient 5nm High-Performance Arm Core Implementation\nUsing Cadence Digital Full Flow\nOlivier Rizzo\, Arm\n\n\nAchieving 3.6GHz+ for New Client Markets Through Implementation\nUsing Cadence Digital Full Flow\nRahoul Varma and Haroon Gauhar\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nGain PA Advantage with New Aging-Aware STA Solution for\nHigh-Performance Semiconductor Designs\nSatheesh Balasubramanian\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nHigh-Reliability Soft-Error Resilience Design Implementation\nUsing Arm IP and Cadence Digital Full Flow\nRobert Christy\, Arm\, and\nDesmond Cicero\, Cadence\n\n\n\n 
URL:https://marketingeda.com/event/arm-and-cadence-achieving-best-silicon-power-performance-and-area/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-11-2022.jpg
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END:VCALENDAR