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BEGIN:VEVENT
DTSTART;TZID=Australia/Perth:20220701T083000
DTEND;TZID=Australia/Perth:20220701T170000
DTSTAMP:20220629T200819Z
CREATED:20220629T200539Z
LAST-MODIFIED:20220629T200819Z
UID:4898-1656664200-1656694800@marketingeda.com
SUMMARY:RIOS Open-source Hardware IP Licensing and Policy Workshop
DESCRIPTION:IOS Lab is excited to announce that the first international legal conference on open tech and IP will be held on July 1st\, 2022 (GMT+8). The main themes of the 2022 conference are open hardware licensing\, litigation protections and open source policies. Some of the most prominent and high-profile speakers and representatives from a wide range of entities will deliver presentations and panel discussions on the themes from different angles. Some featured talks are as follows: \n  \n\nAlternative microprocessor patent classifications to IPC and CPC\nObservations on open EDA\, open PDK\, and IPs and their development\nOpen Source RISC-V Cores Commercial Adoption lessons learned (Solderpad Hardware license)\nFormulation of open source technology IP rules—from bottlenecks of open source technology\nIntroduction of OIN Licenses for open source hardware\n\n  \nEveryone is welcome to attend to learn about the latest on the open source community and its legal protections and prospects from global industry giants such as Google\, top community institute leaders such as OIN\, Chip Alliance\, and OpenHW Group\, professional law firms such as King and Wood Mallesons. Register now by emailing to chen.g@rioslab.org for workshop agenda and programs.
URL:https://marketingeda.com/event/rios-open-source-hardware-ip-licensing-and-policy-workshop/
CATEGORIES:IP,Workshop
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RIOS-workshop.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20220630T080000
DTEND;TZID=Asia/Shanghai:20220630T170000
DTSTAMP:20220519T155249Z
CREATED:20220519T155249Z
LAST-MODIFIED:20220519T155249Z
UID:4746-1656576000-1656608400@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - China\, Virtual
DESCRIPTION:Date\nJune 30\, 2022 (Thursday)\nTime\nStarts at 9:00 a.m.\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-china-virtual/
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220628T103000
DTEND;TZID=Europe/Paris:20220628T113000
DTSTAMP:20220623T163054Z
CREATED:20220623T161813Z
LAST-MODIFIED:20220623T163054Z
UID:4888-1656412200-1656415800@marketingeda.com
SUMMARY:SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
DESCRIPTION:A Physically Unclonable Function or PUF is a function used to generate secret information on-chip. Information such as a secret key / public key pair may be generated on-chip each time it is needed\, while the secret key never needs to be output from the chip. \nThus the attack surface is reduced\, since only the public key needs to be extracted from the chip. This enables Zero-Trust Onboarding. \nThe intrinsic properties of the PUF and its operation make it impervious to tampering: security may not be compromised. \nMoreover\, it is possible to enroll chips late in the manufacturing process (Zero-Touch Onboarding). \nThanks to these features\, the PUF allows to enhance the security in many different applications based on cryptographic keys\, such authentication protocols\, data confidentiality and integrity\, or Secure Boot. \nBy leveraging end points integrated security\, the PUF advantages make it the perfect fit for connected devices life cycle management solutions such as Secure-IC iSSP\, which maintains over time the right level of security for fleets of devices\, during their full life-time\, by mitigating the growing threats and vulnerabilities in the field and protecting end-user devices from cyberattacks at both the network and device levels\, filtering attacks in real time and implementing a centralized protection mechanism for all connected modules. \nThis webinar will help you understand: \n\nWhy we need PUF security and how does it work?\nWhat is lifecycle security?\nHow we can leverage end points integrated security for lifecycle management?\n\n\nSylvain GUILLEY\nCTO at Secure-IC\n \nSylvain Guilley is co-founder and CTO at Secure-IC. Sylvain is also professor at “Télécom ParisTech”\, associate research at “École Normale Supérieure” (ENS)\, and adjunct professor at the Chinese Academy of Sciences (CAS). His research interests are trusted computing\, cyber-physical security\, secure prototyping in FPGA and ASIC\, and formal / mathematical methods. \nSince 2012\, he organizes the PROOFS workshop\, which brings together researchers whose objective is to increase the trust in the security of embedded systems. Sylvain is also lead editor of international standards\, such as ISO/IEC 20897 (Physically Unclonable Functions) and ISO/IEC 20085 (Calibration of non-invasive testing tools). \nSylvain has co-authored 200+ research papers and filed 30+ patents. He is member of the IACR\, and senior member of the IEEE and the CryptArchi club. He is alumni from “École Polytechnique” and “Télécom ParisTech”.
URL:https://marketingeda.com/event/securyzrtm-issp-simplifying-security-lifecycle-management-with-puf/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-June-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220628T080000
DTEND;TZID=Asia/Jerusalem:20220628T170000
DTSTAMP:20220519T155026Z
CREATED:20220519T155026Z
LAST-MODIFIED:20220519T155026Z
UID:4743-1656403200-1656435600@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - Israel
DESCRIPTION:Israel Technology Workshop (In-Person Event)\n\nDate\nJune 28\, 2022 (Tuesday)\nTime\n9:30a.m. – 4:30p.m.\nVenue\nDaniel Herzliya Hotel\nRamat Yam St 60\, Herzliya\, Israel\n\nEurope Technology Symposium (Online VOD Event)\n\nDate\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-israel/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Brussels:20220622T090000
DTEND;TZID=Europe/Brussels:20220622T110000
DTSTAMP:20220525T163320Z
CREATED:20220525T163134Z
LAST-MODIFIED:20220525T163320Z
UID:4762-1655888400-1655895600@marketingeda.com
SUMMARY:Extending Processors into Flexible Accelerators for 5G
DESCRIPTION:The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the end product.\nJoin us at Synopsys’ ASIP Designer™ Virtual Seminar 2022 to learn why ASIPs are getting so much attention these days\, and why Synopsys’ ASIP Designer is the industry’s leading tool to design\, implement\, program and verify such specialized processors.\nThis event focuses on ASIPs for 5G wireless applications and will cover the following topics:\n\n\n\nAn introduction to the ASIP Designer tool suite\nCase study: An Application Specific Vector Processor for CNN-based Massive MIMO Positioning\nCase study: 5G NR MMSE Channel Equalization using Cholesky Decomposition\n\n\n\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.\n\n\nPresenters: \n\n\n\n\n\nPatrick Verbist\n\n\nProduct Marketing Manager\n\n\nSynopsys Belgium\n\n\n\n\nPatrick Verbist is the Product Marketing Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\n\nFalco Munsche\n\n\nTechnical Marketing Manager\n\n\nSynopsys Germany\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\n\nMohammad Attari\n\n\nDigital ASIC Research Group\n\n\nEIT at Lund University\n\n\n\n\nMohammad Attari is currently a PhD student in the Digital ASIC research group in the Electrical and Information Technology (EIT) department at Lund University. His research focuses on developing Massive MIMO and next generation baseband communications processors. His interests include (but are not limited to) computer architecture\, domain specific architectures\, accelerator-level parallelism\, application specific instruction set processors (ASIP)\, neural networks\, and cross-level hardware-software (-algorithm) codesign and implementation.
URL:https://marketingeda.com/event/extending-processors-flexible-accelerators-5g/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-June-22-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220622T080000
DTEND;TZID=America/Los_Angeles:20220622T090000
DTSTAMP:20220606T145048Z
CREATED:20220606T145048Z
LAST-MODIFIED:20220606T145048Z
UID:4802-1655884800-1655888400@marketingeda.com
SUMMARY:Cost effective 5G for the IoT
DESCRIPTION:5G RedCap is an exciting new 3GPP feature\, soon to be introduced in Rel. 17 of the standard\, targeting reduced capability use cases for industrial\, wearables\, and IoT in general. We will discuss the new standard\, the market potential\, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. \nJoin CEVA to learn about: \n\nIntroduction to the 5G RedCap standard\n5G RedCap use cases and market potential\nCEVA PentaG2-Lite architecture\n\n  \nTarget Audience \nCellular system engineers and product managers targeting 5G SoCs and devices\, that are interested in the new RedCap standard for emerging applications. \nSpeakers: \n\n\n\n\nNir Shapira\nDirector for Strategic Technologies\, Mobile Broadband BU\, CEVA Inc
URL:https://marketingeda.com/event/cost-effective-5g-for-the-iot/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CEVA-June-22-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220622T020000
DTEND;TZID=America/New_York:20220622T150000
DTSTAMP:20220613T211131Z
CREATED:20220613T211131Z
LAST-MODIFIED:20220613T211131Z
UID:4834-1655863200-1655910000@marketingeda.com
SUMMARY:Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
DESCRIPTION:Standards such as ISO 26262 define strict requirements\, processes\, and methods that all stakeholders – IP vendors\, sub-system developers\, and semiconductor SoC and system developers – must abide by when designing safety-critical automotive products. One such requirement is the Development Interface Agreement (DIA)\, which defines the interactions\, interfaces\, responsibilities\, dependencies\, and work products exchanged between customers and suppliers for all distributed safety-related activities.\n\nThis 60-minute Webinar explains the details of distributed development based on DIA and outlines the different activities for which DIAs must be signed during a distributed development process. In the second part of the presentation\, an engineer from Infineon discusses their approach to meeting SoC-level functional safety objectives while closely collaborating with Synopsys.\n\n\nSpeakers:\nDietmar Koenig\, Lead Principal Engineer\, Infineon\nDietmar Koenig is a Lead Principal Engineer at Infineon with technical responsibility for the execution of safety-related work products in the Infineon Automotive Microcontroller division. He has 23 years of experience in microcontroller concept development at Siemens and Infineon and more than 18 years of experience on safety concepts for microcontrollers. \nVladimir Litovtchenko\, Director\, Functional Safety and Quality Engineering\, Synopsys  \nVladimir Litovtchenko is a Director for the functional safety team at Synopsys. He has more than 19 years of experience in the semiconductor industry focusing on automotive functional safety products and development flows. He spent 12 years as Senior Systems and SoC Design Engineer at Freescale/NXP and nearly three years at Infineon as a Senior MCU Concept and Functional Safety Expert. As a Senior Staff Concept Engineer at Infineon\, Vladimir worked on functional safety architectures and concepts for automotive MCU SoCs. He holds more than 23 EU and US patents and has published several papers and presentations. \nModerator: Amanda Hosey\, Editor\, SAE Media Group
URL:https://marketingeda.com/event/simplify-streamline-development-of-iso-26262-compliant-automotive-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAE-Media-Group-June-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20220620T080000
DTEND;TZID=Europe/Paris:20220621T170000
DTSTAMP:20220620T144134Z
CREATED:20220620T144134Z
LAST-MODIFIED:20220620T144134Z
UID:4871-1655712000-1655830800@marketingeda.com
SUMMARY:Leti Innovation Days
DESCRIPTION:The chip shortage has brought with it an extraordinary boost to Moore’s Law. \n Discover policy maker and tech leader strategic decisions on downscaling\, “More than Moore electronics” and other future technologies for components.\n Identify key emerging technologies to grow your business.\n\n\nPlenary Session\n\n\nA plenary session will gather high-level keynote speakers to discuss novel tech strategies to foster out performance. As our world continues to change rapidly and we reach a key turning point in the electronics industry\, hear from CEOs\, executives and decision makers in order to better understand and meet the challenges of exponential demand for smart electronics in our daily lives. Join us to innovate and participate as a game changer.\n\n\n\n​​6 Workshops: choose yours!\n\n\n\nNew Paradigms for Computing Workshop\nSatellite Communication Workshop\nSMEs & the International Market Workshop\nMore than Moore Workshop\nSustainability Workshop\nHealthcare Workshop\n\nExhibition & Networking\n\n\n\nLive demos: Discover more than 40 live demos and network with potential partners.\n\n\nStartup Corner: Don’t miss out on the startup corner to learn about the latest tech offers.\n\n\nBusiness Meetings: Book meetings with experts to discuss your innovation project.\n\n\nForum Area: Listen 15 minute sales-oriented pitches. Discover the latest developments offered by CEA-Leti startups and local SMEs specializing in microelectronics.\n\n\nNetworking: Join us for two evening receptions.
URL:https://marketingeda.com/event/leti-innovation-days/
LOCATION:Minalogic\, 3 PARV Louis Neel\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Leti-Innovation-Days-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Amsterdam:20220620T080000
DTEND;TZID=Europe/Amsterdam:20220620T170000
DTSTAMP:20220519T154700Z
CREATED:20220519T154638Z
LAST-MODIFIED:20220519T154700Z
UID:4739-1655712000-1655744400@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - Europe
DESCRIPTION:Europe Technology Symposium (In-Person Event)\n\nDate\nJune 20\, 2022 (Monday)\nTime\n8:30a.m. – 4:50p.m.\nVenue\nHilton Amsterdam Airport Schiphol\nSchiphol Boulevard 701Amsterdam\,1118BN Netherlands\n\nIsrael Technology Workshop (In-Person Event)\n\nDate\nJune 28\, 2022 (Tuesday)\nTime\n9:30a.m. – 4:30p.m.\nVenue\nDaniel Herzliya Hotel\nRamat Yam St 60\, Herzliya\, Israel\n\nEurope Technology Symposium (Online VOD Event)\n\nDate\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric® advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-europe/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220616T080000
DTEND;TZID=America/Los_Angeles:20220616T170000
DTSTAMP:20220519T154250Z
CREATED:20220519T154250Z
LAST-MODIFIED:20220519T154250Z
UID:4736-1655366400-1655398800@marketingeda.com
SUMMARY:TSMC 2022 Technology Symposium - North America
DESCRIPTION:A Technology Symposium (In-Person Event)\nDate:\nJune 16\, 2022 (Thursday)\nTime:\n8:30a.m. – 5:05p.m.\nVenue:\nSanta Clara Convention Center\n5001 Great America Parkway\,\nSanta Clara\, CA 95054\n\n\nNA Technology Symposium (Online VOD Event)\nDate:\nJune 30\, 2022 (Thursday)\n\nWebsite link to be announced in June \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at symposium@tsmc.com. \nWe look forward to seeing you at the 2022 TSMC Technology Symposium!
URL:https://marketingeda.com/event/tsmc-2022-technology-symposium-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/TSMC-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220608T080000
DTEND;TZID=America/Los_Angeles:20220609T170000
DTSTAMP:20220601T175752Z
CREATED:20220303T004334Z
LAST-MODIFIED:20220601T175752Z
UID:4407-1654675200-1654794000@marketingeda.com
SUMMARY:CadenceLIVE 2022 - Silicon Valley
DESCRIPTION:Are you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer tips to address the complexities and challenges that engineers face today. CadenceLIVE Silicon Valley features peer presentations that highlight solutions\, using Cadence® products\, for today’s design challenges. \nCurrently\, we are expecting CadenceLIVE Silicon Valley 2022 to be an in-person conference with digital\, on-demand access available two to three weeks after the event. Please note\, we always follow local\, state\, and federal orders and CDC guidelines\, and will make adjustments to the event format as needed. \nShould you have any questions about abstract submissions\, please email cadencelive@cadence.com \n 
URL:https://marketingeda.com/event/cadencelive-2022-silicon-valley/
LOCATION:Cadence\, San Jose\, CA\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-8-9-2022-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220607T100000
DTEND;TZID=America/Los_Angeles:20220607T110000
DTSTAMP:20220601T174855Z
CREATED:20220601T174855Z
LAST-MODIFIED:20220601T174855Z
UID:4785-1654596000-1654599600@marketingeda.com
SUMMARY:Embedded Applications Get a Helping Hand: Extensible Processor Architectures
DESCRIPTION:Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today\, many embedded applications such as those found in artificial intelligence (AI)\, automotive and storage segments require increased bandwidth and memory address space expansion. As Moore’s law slows\, design teams seek different ways to deliver unique solutions for these applications while maintaining power\, performance\, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools\, and software ecosystem\, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how highly extensible processor architectures can enable designers to meet their application requirements and provide SoC differentiation. \nAttend this Synopsys webinar to learn about: \n\nTypical ISA trade-offs designers must make for high-end application development\nHow to achieve design flexibility through configurable\, scalable processor architectures\nHow leveraging extensibility options of Synopsys ARC® Processors can provide SoC differentiation\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\n\n\n\n\n\n\n\n\nDirector of Product Marketing\nSynopsys \n\n\n\n\n\n\n\n\nRich Collins is director of product marketing for ARC Processors and Subsystems at Synopsys. Rich has over 25 years of experience in embedded semiconductor R&D\, product marketing and business development\, including 17 years at Motorola/Freescale before joining Synopsys. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.
URL:https://marketingeda.com/event/embedded-applications-get-a-helping-hand-extensible-processor-architectures/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-June-7-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220531T080000
DTEND;TZID=Asia/Tokyo:20220602T170000
DTSTAMP:20220510T154735Z
CREATED:20220510T154735Z
LAST-MODIFIED:20220510T154735Z
UID:4668-1653984000-1654189200@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2022 Spring
DESCRIPTION:RISC-V Days Tokyo is Japan’s largest online RISC-V event.  Live online presentations are hosted on May 31st (Tue)\, June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products\, key persons and engineers\, and to provide business opportunities for product recognition\, collaboration among companies\, technology exchange and information gathering. We look forward to your participation in this opportunity! \n \n\nGoogle\nSiemens\nefabless\nImperas\nSHC\nDTS\n\n\n\nSiFive\nCodaSip\neFinix\neSol Trinity\nGigaDevice\nIAR Systems\n\n\n\nImagination\nMIPS\nSIgnate\nRISC-V\nKeio University\nRed Hat\nThe University of Tokyo\nUEC Tokyo\n\n\n 
URL:https://marketingeda.com/event/risc-v-days-tokyo-2022-spring/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Day-Tokyo-2022-Spring-Logo.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T100000
DTEND;TZID=America/Los_Angeles:20220524T110000
DTSTAMP:20220511T045624Z
CREATED:20220511T045624Z
LAST-MODIFIED:20220511T045624Z
UID:4674-1653386400-1653390000@marketingeda.com
SUMMARY:DSP IP for High Performance Sensor Fusion on an Embedded Budget
DESCRIPTION:The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition\, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput. \nIn this webinar we will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing\, often combining classical filtering operations and AI-based decision making. Featuring the Synopsys ARC® VPX DSP family\, we will explain key functions that can be optimized to handle a spectrum of sensor fusion workloads\, while adhering to a single programming environment. \nSpeaker\n\n\n\n\nPieter van der Wolf\n\n\nPrincipal R&D Engineer\nSynopsys \n\n\n\n\n\n\n\n\nPieter van der Wolf is a Principal R&D Engineer at Synopsys. He received his MSc and PhD degrees in Electrical Engineering from the Delft University of Technology. He was an Associate Professor at the Delft University of Technology before joining Philips Research in 1996. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. In 2009 he joined Virage Logic\, which was subsequently acquired by Synopsys. He has worked on a broad range of topics including multi-processor architectures and system design methodologies.
URL:https://marketingeda.com/event/dsp-ip-for-high-performance-sensor-fusion-on-an-embedded-budget/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T080000
DTEND;TZID=America/Los_Angeles:20220524T093000
DTSTAMP:20220516T163304Z
CREATED:20220516T163304Z
LAST-MODIFIED:20220516T163304Z
UID:4710-1653379200-1653384600@marketingeda.com
SUMMARY:Automotive Cyber-Security: Off-board and On-board\, standards and technologies
DESCRIPTION:This webinar will help you understand:\n• The different standards that exist and why is compliance so important?\n• How to protect against tampering attacks?\n• What is lifecycle security and how can it benefit the automotive industry?\n• Why is it important to protect the whole lifecycle of a device?
URL:https://marketingeda.com/event/automotive-cyber-security-off-board-and-on-board-standards-and-technologies/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Secure-IC-May-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220517T080000
DTEND;TZID=America/Los_Angeles:20220518T170000
DTSTAMP:20220511T162123Z
CREATED:20220511T162123Z
LAST-MODIFIED:20220511T162123Z
UID:4677-1652774400-1652893200@marketingeda.com
SUMMARY:Embedded Vision Summit
DESCRIPTION:The premier event for practical\, deployable computer vision and visual AI\, for product creators who want to bring visual intelligence to products. \n\n\n\n\nThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy attend? It’s a First-Rate Program with Powerful Insights into Practical Visual AI. \n\n\n\n\n\nJoin us for four days of learning—from tutorials to deep-dive days\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\n\n4 Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\nWe’ve been doing this for 11 years.\n\n\nA whopping 97% of our attendees would recommend the Summit to a colleague.
URL:https://marketingeda.com/event/embedded-vision-summit/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summit-May-16-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220512T100000
DTEND;TZID=America/Los_Angeles:20220512T110000
DTSTAMP:20220505T180841Z
CREATED:20220505T180841Z
LAST-MODIFIED:20220505T180841Z
UID:4631-1652349600-1652353200@marketingeda.com
SUMMARY:AMBA AHB Subsystems and How to Customize\, Secure\, and Verify
DESCRIPTION:AMBA is a set of interconnect specifications that standardizes on chip communication mechanisms between various functional blocks (or IP) for building SOC designs. Silvaco’s AMBA AHB subsystems provide the basic interconnect and functional subsystems enabling SOC designers to target products such as IoT Devices\, Medical Devices\, Industrial Controllers\, Wireless Gateways\, and many more applications.  These designs typically have one or more micro controllers or microprocessors along with several other subsystem components. \nThis webinar will provide an overview of the AMBA AHB subsystems and products offered by Silvaco. Some topics of discussion include Channel vs. Fabric architecture\, low power\, customization\, hardware- and software-based security\, and co-verification of the hardware and software. \nWhat You Will Learn \n\nOverview of Silvaco’s portfolio of AMBA AHB subsystems\, features\, and capabilities\nWhich architecture to use for a given application: Channel vs. Fabric\nCustomization of subsystems\nSecurity Issues with traditional Cortex-M architecture\nOverview of Secure Subsystem Security features\nSoftware as a component of hardware simulation\nSecurity improvements\, software security\, and secure boot\n\nBio\nJim Avant\, Senior Hardware and Software Engineer\,\nIP Division\, Silvaco\, Inc.\nJim Avant is a senior hardware and software engineer in Silvaco’s IP Division. He is the primary designer for several digital soft IP designs including the Secure AHB Subsystem. Prior to joining Silvaco in 2017\, Jim was a senior design engineer at SoC Solutions. He has an extensive background in RTL digital logic design\, digital signal processing\, and embedded C programming.\nJim Avant holds a bachelor’s degree in Electrical Engineering (BEE) from Georgia Tech in Atlanta\, Georgia.
URL:https://marketingeda.com/event/amba-ahb-subsystems-and-how-to-customize-secure-and-verify/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-May-12-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220511T100000
DTEND;TZID=America/Los_Angeles:20220511T130000
DTSTAMP:20220419T200653Z
CREATED:20220419T200653Z
LAST-MODIFIED:20220419T200653Z
UID:4569-1652263200-1652274000@marketingeda.com
SUMMARY:Arm and Cadence: Achieving Best Silicon Power\, Performance\, and Area
DESCRIPTION:How do you deal with design requirements that span high performance\, energy-efficient computing\, and high-reliability implementation? To realize these goals\, you need optimal design flows to deliver the best power\, performance\, and reliability. \nJoin Cadence and Arm virtually for CadenceCONNECT: Arm and Cadence – Achieving Best Silicon Power\, Performance\, and Area. Learn about: \n\nHigh-performance design for the Arm® Cortex®-A710 and other Arm processors\nEnergy-efficient CPU implementation flows\nHigh-reliability design using Arm library IP\nAging-aware static timing analysis (STA)\n\nExplore how you can efficiently implement your Arm-based SoCs with the Cadence® digital full-flow solution and get the best power\, performance\, and area (PPA). \nRegister now and join us on May 11. \nEvent times per region. Each event is 3 hours long. \nAsia-Pacific\n9:00am CST | 10:00am JST\, KST \nEurope\, Israel\, India\n9:00am BST | 10:00am CEST | 11:00am Israel | 1:30pm India​ \nNorth America\n1:00pm EDT I 10:00am PDT \n  \n\n\n\nSessions\nSpeaker\n\n\nDelivering Best-in-Class PA and TAT for Arm Total Compute\nUsing Cadence Digital Full Flow\nPierre-Alexandre Bou-Ach\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nAchieving Outstanding Performance for Arm Cortex-A710 Processor\nUsing Samsung Foundry 4LPP and the Cadence Digital Flow\nChinthamani Jagannath\, Cadence\n\n\nEnergy-Efficient 5nm High-Performance Arm Core Implementation\nUsing Cadence Digital Full Flow\nOlivier Rizzo\, Arm\n\n\nAchieving 3.6GHz+ for New Client Markets Through Implementation\nUsing Cadence Digital Full Flow\nRahoul Varma and Haroon Gauhar\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nGain PA Advantage with New Aging-Aware STA Solution for\nHigh-Performance Semiconductor Designs\nSatheesh Balasubramanian\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nHigh-Reliability Soft-Error Resilience Design Implementation\nUsing Arm IP and Cadence Digital Full Flow\nRobert Christy\, Arm\, and\nDesmond Cicero\, Cadence\n\n\n\n 
URL:https://marketingeda.com/event/arm-and-cadence-achieving-best-silicon-power-performance-and-area/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-11-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220510T080000
DTEND;TZID=America/Los_Angeles:20220512T170000
DTSTAMP:20220429T015316Z
CREATED:20220421T220326Z
LAST-MODIFIED:20220429T015316Z
UID:4583-1652169600-1652374800@marketingeda.com
SUMMARY:AutoSense Detroit 2022
DESCRIPTION:We can’t wait to bring our community back together at the Michigan Science Center in Detroit. Join us 10-12 May to hear from over 50 speakers from companies across the autonomous vehicle perception supply chain\, including  AMD\, BrainChip\, Indie Semiconductor\, ON Semiconductor\, Siemens\, STMicroelectronics\, Cadence\, Valeo\, MOBIS\, Synopsys\, Veoneer\, General Motors and Baraja. \nWith a full exhibition of over 30 key industry players\, a range of round table sessions and two drinks receptions\, you can maximise the opportunity to network with expert engineers\, academics\, and professionals. \nKey topics include developments in RADAR and LiDAR\, image quality\, data\, safe system design\, advances in camera technology\, in-cabin monitoring\, supply chain outlook and more.
URL:https://marketingeda.com/event/autosense-detroit-2022/
LOCATION:Michigan Science Center\, 5020 John R St\, Detroit\, MI\, 48202\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/AutoSens-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220428T090000
DTEND;TZID=America/Los_Angeles:20220428T100000
DTSTAMP:20220411T214937Z
CREATED:20220411T214937Z
LAST-MODIFIED:20220411T214937Z
UID:4534-1651136400-1651140000@marketingeda.com
SUMMARY:Adding Intelligence to Electronic Product Lifecycle using Requirements management
DESCRIPTION:This Webinar will cover a methodology that can be easily integrated into the system design and systems engineering process. VisualSim Insight Engine provides an intelligent way to connect the Requirements to system specification by running Monte Carlo simulation to detect the quality\, efficiency\, reliability and compliance to the Requirements. You can identify areas of improvement\, detect bottlenecks and also determine the expected behavior when the system is integrated. Unlike current solutions that treat Requirements as a document\, this dynamic solution tracks the system behavior through the design process and ensure the results are adhering to the Requirements. \nDuring this Webinar\, we will cover the translation of Requirements into system logic for use in systems engineering simulation\, setup the Requirements for a system\, semiconductor or network\, visualize the comparison and reports\, and make decisions. We will use an automotive\, processor and a radar signal processing system as examples to illustrate the benefits. \n1. Do you have formal Requirements program? \n2. Would you like to integrate Requirements into the product design flow? \n3. Do you want to optimize the system specification to meet and not over/under design? \n4. Are you trying to simulate your SysML specification to meet performance and power goals? \nHost\nDeepak Shankar is the Founder of Mirabilis Design and has been involved in the Requirements simulation\, systems engineering and architecture exploration of processors\, avionics\, network gateways\,. Mr. Shankar started Mirabilis Design because of a vacuum in the integration of requirements into systems engineering and modeling. Deepak has published over 50 articles and presented at over 30 conferences in EDA\, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley\, MS in from Clemson University and BS from Coimbatore Institute of Technology\, both in Electronics and Communication.
URL:https://marketingeda.com/event/adding-intelligence-to-electronic-product-lifecycle-using-requirements-management/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220428T083000
DTEND;TZID=America/Los_Angeles:20220428T093000
DTSTAMP:20220331T170239Z
CREATED:20220331T170239Z
LAST-MODIFIED:20220331T170239Z
UID:4487-1651134600-1651138200@marketingeda.com
SUMMARY:Protecting Connected IoT devices against Quantum computing threats: Post Quantum Cryptography
DESCRIPTION:With Sofiane Takarabt\, Program Manager of Applied Cryptography at Secure-IC\nThursday\, April 28\, 2022 – 10:00 AM (CET) & 17:30 (CET) – 11:30 AM (EST) \nIn a world of ubiquitous connected devices\, massive exchange of sensitive data must be protected with cryptographic functions. It is also necessary to prepare for the advent of quantum computers which will make classic asymmetric cryptography obsolete. The recent trend of standardization pushes indeed a safe quantum cryptography. Thus\, a wide variety of communication systems and public key infrastructures must be updated with post-quantum cryptography solutions. In this presentation\, we discuss the three main functions; signature verification\, key encapsulation and secure boot\, and how to provide these services in different contexts and constraints of performance. \nThis webinar will help you understand: \n\nThe main applications for PQC algorithms\, giving an accurate understanding of the subject\nHow classic asymmetric cryptography algorithms may be replaced\nHow PQC can be implemented in all kinds of applications\, to answer a variety of use cases\n\nInsights will also be given on the way to best choose and implement the algorithms to answer various performance constraints. \n 
URL:https://marketingeda.com/event/protecting-connected-iot-devices-against-quantum-computing-threats-post-quantum-cryptography/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-APril-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220426T080000
DTEND;TZID=America/Los_Angeles:20220427T170000
DTSTAMP:20220427T064316Z
CREATED:20220127T174859Z
LAST-MODIFIED:20220427T064316Z
UID:4228-1650960000-1651078800@marketingeda.com
SUMMARY:D&R IP SoC Silicon Valley 2022
DESCRIPTION:When : April 26th 2022 \nWhere : Computer History Museum\n1401 N. Shoreline Blvd\nMountain View\, CA 94043\, USA \nD&R IP-SoC Silicon Valley 2022 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nPhysical meeting between vendors and consumers is the unique and non replaceable vehicle to engage business discussions between vendors and clients.\nNevertheless this event will also be “replicated” on line after the event aiming at triggering more business opportunities.\nPosting their talk and recording their presentations on easily accessible platforms will extend innovation sharing among the worldwide IP-SoC Community. \nAny question? Please contact us \n\nImportant Dates \n\nSubmission Deadline : March 1st 2022\nSlides and presentation records available on April 1st 2022\nPanel proposal to be submitted before February 25th 2022\nto gabriele.saucier@design-reuse.com\n\nAreas of interest (not limited to) : \nInnovation in technology \n• New technology for new applications\n• Foundries Ecosystem\n• IP and SoC on Advanced node\n• 3D packaging\, D2D\, C2C connectivity\n• Quantum computing and Qubit technology \nInnovative IP SoC \n• Low power Analog IP and Memory\n• Advanced Interface IP\n• IP SoC for Artificial Intelligence\n• IP/SoC for Automotive\, Avionics\, Defense…\n• RISC-V\, GPU\, Dedicated processor…\n• Security Solutions \nIP Best Practice \n• Business models\n• IP Management Platform\n• Market Analysis \nIP/SoC Design Methodology \n• Low Power\, and area optimized design\n• IP Integration & Design Flows\n• Verification and Emulation
URL:https://marketingeda.com/event/dr-ip-soc-silicon-valley-2022/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Design-and-Reuse-April-26-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220421T080000
DTEND;TZID=America/Los_Angeles:20220421T090000
DTSTAMP:20220419T005257Z
CREATED:20220419T004804Z
LAST-MODIFIED:20220419T005257Z
UID:4558-1650528000-1650531600@marketingeda.com
SUMMARY:What's Behind the Infrastructure of the CORE-V Family
DESCRIPTION:Automated code validation\, continuous integration and test regression are cornerstones of OpenHW Group’s community-based engineering process to develop and verify high-quality processor cores. OpenHW Group is deploying a state-of-the-art Test Automation and Continuous Integration environment to achieve these objectives across our diverse projects\, resulting in faster development cycles with increased quality. In this webinar\, Florian Zaruba and Massimiliano (Max) Giacometti of the OpenHW Group staff will review OpenHW’s CI requirements and approaches. \nA critical component to highlight is the robust design equivalence checking solution\, which ensures that only the expected changes have been implemented at check-in points and no downstream functional bugs are introduced across logical Boolean\, low power intent\, and clock/reset domain contexts. David Stratman\, Product Management Director at Cadence Design Systems\, will discuss the Cadence Conformal suite of tools anchored by their Logical Equivalence Checking (LEC) solution. \nRick O’Connor of OpenHW Group will be moderating the discussion.
URL:https://marketingeda.com/event/whats-behind-the-infrastructure-of-the-core-v-family/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/OpenHW-April-21-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220420T080000
DTEND;TZID=America/Los_Angeles:20220421T170000
DTSTAMP:20220406T202613Z
CREATED:20220406T202537Z
LAST-MODIFIED:20220406T202613Z
UID:4513-1650441600-1650560400@marketingeda.com
SUMMARY:Linley Spring Processor Conference 2022
DESCRIPTION:TechInsights is pleased to continue the semi-annual Linley Processor Conferences\, established more than a decade ago. This year\, the Linley Spring Processor Conference will return to Santa Clara on April 20-21\, 2022 with a new hybrid format; if you can’t attend in person\, you can tune in to our virtual livestream. \nPresentations will address processors and IP cores for AI applications\, embedded\, data-center\, automotive\, and server designs. In-person attendees will be able to hear presentations and interact with the speakers during Q&A\, lunch\, and the networking reception. \nAnalyst and Industry Keynotes \nLinley Gwennap\, principal analyst\, TechInsights\, will open the conference with an overview of the latest market\, technologies\, equipment-design\, and silicon trends. We’ll also feature a keynote from another industry leader. \nIn-Depth Technical Sessions \nUnlike many conferences\, we ensure that the presentations deliver real technical content\, not marketing hype. We’re the conference of choice for many companies who announce new products or make technology disclosures. TechInsights analysts carefully select session topics and choose leading speakers who are experts in their fields. In addition\, the analysts ensure that the content of the presentations are full of insightful\, technical information that will help attendees select the right components and systems for their next project. \nThe program will feature talks and panel discussions covering a broad range of topics: \nAgenda Day 1\nAgenda Day 2 \nWhy Attend \nThe Linley Processor Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear\, question\, and network with key providers of advanced technology products. \nThe conferences analyze products and design strategies in a particular technology segment\, providing information that engineers can immediately use to improve their designs. The events feature in-depth technical presentations from our own analysts as well as leading technologists from the industry. \nFree Admission \nWe offer free admission to qualified registrants\, making it easy to participate. The conference is intended for chip designers\, system designers\, equipment vendors\, OEM/ODMs\, service providers\, press\, and the financial community. \nCOVID-19 Policies and Precautions \nWe are working closely with the Hyatt Regency to reduce the risk of attending our in-person event. Individuals and their employers\, however\, must decide what level of risk is acceptable. For those unable to attend in person\, we offer our virtual livestream. \nAttendees will be required to provide proof of vaccination before receiving their conference badge. Consistent with local health orders\, masks are now recommended but not required. Policies are subject to change; we will update this page as needed.
URL:https://marketingeda.com/event/linley-spring-processor-conference-2022/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Linley-April-20-21-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220419T080000
DTEND;TZID=America/Los_Angeles:20220419T170000
DTSTAMP:20220404T192418Z
CREATED:20220404T192418Z
LAST-MODIFIED:20220404T192418Z
UID:4499-1650355200-1650387600@marketingeda.com
SUMMARY:CHIPS Alliance Spring Event
DESCRIPTION:The CHIPS Alliance holds workshops in various locations throughout the year\, based upon the needs of our project and members.  Members of the CHIPS Alliance receive a number of complementary passes each year\, based upon their membership level. \nDate: April 19\, 2022 at 8 a.m. PT \nSchedule: \n\nWelcome / Opening Remarks: Rob Mains\, CHIPS Alliance\nChisel/FIRRTL Ecosystem Updates: Jack Koenig\, SiFive\nF4PGA Group Kickoff\, Interchange Format: Karol Gugala\, Antmicro\nChiplet Protocol IP: David Kehlet\, Intel\nNIST (Cryo Test Structures): Mehdi Saligane\, UMICH\nNVMe FPGA IP for Edge Applications: Anand Kulkarni\, Western Digital\nUpdate on Shuttle Programs: Tim Ansell\, Google
URL:https://marketingeda.com/event/chips-alliance-spring-event/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CHIPS-Alliance-April-19-2022.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220412T090000
DTEND;TZID=America/Los_Angeles:20220412T100000
DTSTAMP:20220411T185919Z
CREATED:20220411T185919Z
LAST-MODIFIED:20220411T185919Z
UID:4531-1649754000-1649757600@marketingeda.com
SUMMARY:The Changing Landscape of Automotive Electronics
DESCRIPTION:The automotive industry is undergoing a seismic shift. Supply chain constraints\, software defined architectures\, functional safety requirements\, and the changing dynamics between OEMs\, Tier 1s and semiconductor companies\, are driving the industry to seek innovative ways to approach new challenges.\nJoin us on Tuesday\, April 12th\, 2022\, for a special panel discussion as we review the changing landscape of automotive electronics. \n\nThe webinar will examine:\n\n\n\nBeyond the current supply demand problem\nThe changing relationships between OEMs\, Tier 1s\, and Semiconductors\nHow can the industry develop a standardization of language?\nHow software defined architecture is changing automotive electronics?\nWhat is the next generation of vehicle architecture?\nAdvanced electronics as a driver for safety profiles\n\nModerator\nGrayson Brulte\nCo-Founder\nBrulte & Company \nPanelists \nDr. Peter Mertens\nAutomotive Industry Veteran and Tech-Investor \nDr. Dean Bushey\nVice President and Head of Environment Business Division (Americas)\nHitachi \nStephen Kosonocky\nSenior Fellow\nUhnder \nGal Carmel\nGM Automotive\nproteanTecs
URL:https://marketingeda.com/event/the-changing-landscape-of-automotive-electronics/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-April-12-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220411T100000
DTEND;TZID=America/New_York:20220412T112000
DTSTAMP:20220401T201126Z
CREATED:20220401T201105Z
LAST-MODIFIED:20220401T201126Z
UID:4492-1649671200-1649762400@marketingeda.com
SUMMARY:Design Automation WebiNar (DAWN)
DESCRIPTION:We are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nDue to the outbreak of coronavirus (COVID-19)\, almost all conferences/symposiums in design automation community are canceled/postponed. People are not able to meet each other\, learn recent advances\, and discuss research ideas. The whole community is quarantined\, just like shrouded in darkness made by COVID-19. Thus\, it is about time to bring the light from inspired scholars in our community and therefore we are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote- and sole-speaker-style webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nApril 11\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – Hardware/Software Co-Exploration of Neural Architectures\n10:20 AM-10:40 AM – BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework\n10:40 AM-11:00 AM – APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors\n11:00 AM-11:20 AM – Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration\n\nApril 12\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement\n10:20 AM-10:40 AM – TreeNet: Deep Point Cloud Embedding for Routing Tree Construction\n10:40 AM-11:00 AM – Intermittent-Aware Neural Architecture Search\n11:00 AM-11:20 AM – A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
URL:https://marketingeda.com/event/design-automation-webinar-dawn/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/IEEE-April-11-12-2022.png
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BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220405T110000
DTEND;TZID=Asia/Jerusalem:20220405T170000
DTSTAMP:20220324T164026Z
CREATED:20220324T164026Z
LAST-MODIFIED:20220324T164026Z
UID:4461-1649156400-1649178000@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:11:00 – 11:30 | ASIC Verification\nVeloce proFPGA: The Perfect Complement for Your System Verification Flow \n11:30 – 12:00 | Emulation Queuing\nEmulation – Getting a Better Return on Your Investment \n12:00 – 12:30 | DFT For Automotive\nDesign-For-Test Design (DFT) Consideration for Automotive Designs \n12:30 – 13:00 | Low-power Vector AI Processing\nIntroducing SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA \n13:00 – 15:00 | Break \n15:00 – 15:30\nTessent Streaming Scan Network (SSN): No-compromise DFT \n15:30 – 16:00 | RISC-V Software Development\nWhy Wait For Hardware to Start RISC-V Software Development? \n16:00 – 16:30 | Design & Verification IP\nMaking MIPI Your Ally \n16:30 – 17:00 | Physical Planning and Timing Closure\nExcellicon Product Portfolio
URL:https://marketingeda.com/event/semisrael-tech-webinar-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-April-5-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220405T080000
DTEND;TZID=America/Los_Angeles:20220407T170000
DTSTAMP:20220301T023630Z
CREATED:20210903T205459Z
LAST-MODIFIED:20220301T023630Z
UID:3257-1649145600-1649350800@marketingeda.com
SUMMARY:DesignCon 2022
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers \nDesignCon is the premier high-speed communications and system design conference\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
URL:https://marketingeda.com/event/designcon-2022/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220330T140000
DTEND;TZID=Asia/Tokyo:20220330T143000
DTSTAMP:20220324T162830Z
CREATED:20220324T162830Z
LAST-MODIFIED:20220324T162830Z
UID:4457-1648648800-1648650600@marketingeda.com
SUMMARY:Imperas RISC-V simulation technology with eSol Trinity and NSITEXE
DESCRIPTION:Imperas Software Ltd.\, the leader in RISC-V simulation solutions\, today announced with eSol Trinity the webinar event on RISC-V reference models and simulation technology for the growing adoption of RISC-V in Japan. This webinar will feature a guest speaker – Mr. Marume of NSITEXE Co.\, Ltd.\, a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs\, will introduce an example of using the Imperas RISC-V reference model and simulator. \nRISC-V is an open ISA (Instruction Set Architecture)\, which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra\, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles. \nVirtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors\, as well as user defined custom instructions\, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow. As the project develops to the next phase\, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early software compatibility with the growing ecosystem supporting RISC-V vector extensions. \n  \nWebinar:    ‘Imperas RISC-V reference model and high speed simulation technology’\nWhen:         March 30th 2022\nWhere:        2:00-2:30pm (JST) Live streaming (Zoom) \nFor more information including registration please visit this link.\nAbout Imperas \nFor more information about Imperas\, please see www.imperas.com. Follow Imperas on LinkedIn\, twitter @ImperasSoftware and YouTube. \nAll trademarks or registered trademarks are the property of their respective holders.
URL:https://marketingeda.com/event/imperas-risc-v-simulation-technology-with-esol-trinity-and-nsitexe/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Imperas-March-30-2022.jpg
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END:VCALENDAR