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BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220531T080000
DTEND;TZID=Asia/Tokyo:20220602T170000
DTSTAMP:20220510T154735Z
CREATED:20220510T154735Z
LAST-MODIFIED:20220510T154735Z
UID:4668-1653984000-1654189200@marketingeda.com
SUMMARY:RISC-V Days Tokyo 2022 Spring
DESCRIPTION:RISC-V Days Tokyo is Japan’s largest online RISC-V event.  Live online presentations are hosted on May 31st (Tue)\, June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products\, key persons and engineers\, and to provide business opportunities for product recognition\, collaboration among companies\, technology exchange and information gathering. We look forward to your participation in this opportunity! \n \n\nGoogle\nSiemens\nefabless\nImperas\nSHC\nDTS\n\n\n\nSiFive\nCodaSip\neFinix\neSol Trinity\nGigaDevice\nIAR Systems\n\n\n\nImagination\nMIPS\nSIgnate\nRISC-V\nKeio University\nRed Hat\nThe University of Tokyo\nUEC Tokyo\n\n\n 
URL:https://marketingeda.com/event/risc-v-days-tokyo-2022-spring/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Day-Tokyo-2022-Spring-Logo.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T100000
DTEND;TZID=America/Los_Angeles:20220524T110000
DTSTAMP:20220511T045624Z
CREATED:20220511T045624Z
LAST-MODIFIED:20220511T045624Z
UID:4674-1653386400-1653390000@marketingeda.com
SUMMARY:DSP IP for High Performance Sensor Fusion on an Embedded Budget
DESCRIPTION:The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition\, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput. \nIn this webinar we will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing\, often combining classical filtering operations and AI-based decision making. Featuring the Synopsys ARC® VPX DSP family\, we will explain key functions that can be optimized to handle a spectrum of sensor fusion workloads\, while adhering to a single programming environment. \nSpeaker\n\n\n\n\nPieter van der Wolf\n\n\nPrincipal R&D Engineer\nSynopsys \n\n\n\n\n\n\n\n\nPieter van der Wolf is a Principal R&D Engineer at Synopsys. He received his MSc and PhD degrees in Electrical Engineering from the Delft University of Technology. He was an Associate Professor at the Delft University of Technology before joining Philips Research in 1996. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. In 2009 he joined Virage Logic\, which was subsequently acquired by Synopsys. He has worked on a broad range of topics including multi-processor architectures and system design methodologies.
URL:https://marketingeda.com/event/dsp-ip-for-high-performance-sensor-fusion-on-an-embedded-budget/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220524T080000
DTEND;TZID=America/Los_Angeles:20220524T093000
DTSTAMP:20220516T163304Z
CREATED:20220516T163304Z
LAST-MODIFIED:20220516T163304Z
UID:4710-1653379200-1653384600@marketingeda.com
SUMMARY:Automotive Cyber-Security: Off-board and On-board\, standards and technologies
DESCRIPTION:This webinar will help you understand:\n• The different standards that exist and why is compliance so important?\n• How to protect against tampering attacks?\n• What is lifecycle security and how can it benefit the automotive industry?\n• Why is it important to protect the whole lifecycle of a device?
URL:https://marketingeda.com/event/automotive-cyber-security-off-board-and-on-board-standards-and-technologies/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Secure-IC-May-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220517T080000
DTEND;TZID=America/Los_Angeles:20220518T170000
DTSTAMP:20220511T162123Z
CREATED:20220511T162123Z
LAST-MODIFIED:20220511T162123Z
UID:4677-1652774400-1652893200@marketingeda.com
SUMMARY:Embedded Vision Summit
DESCRIPTION:The premier event for practical\, deployable computer vision and visual AI\, for product creators who want to bring visual intelligence to products. \n\n\n\n\nThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy attend? It’s a First-Rate Program with Powerful Insights into Practical Visual AI. \n\n\n\n\n\nJoin us for four days of learning—from tutorials to deep-dive days\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\n\n4 Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\nWe’ve been doing this for 11 years.\n\n\nA whopping 97% of our attendees would recommend the Summit to a colleague.
URL:https://marketingeda.com/event/embedded-vision-summit/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summit-May-16-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220512T100000
DTEND;TZID=America/Los_Angeles:20220512T110000
DTSTAMP:20220505T180841Z
CREATED:20220505T180841Z
LAST-MODIFIED:20220505T180841Z
UID:4631-1652349600-1652353200@marketingeda.com
SUMMARY:AMBA AHB Subsystems and How to Customize\, Secure\, and Verify
DESCRIPTION:AMBA is a set of interconnect specifications that standardizes on chip communication mechanisms between various functional blocks (or IP) for building SOC designs. Silvaco’s AMBA AHB subsystems provide the basic interconnect and functional subsystems enabling SOC designers to target products such as IoT Devices\, Medical Devices\, Industrial Controllers\, Wireless Gateways\, and many more applications.  These designs typically have one or more micro controllers or microprocessors along with several other subsystem components. \nThis webinar will provide an overview of the AMBA AHB subsystems and products offered by Silvaco. Some topics of discussion include Channel vs. Fabric architecture\, low power\, customization\, hardware- and software-based security\, and co-verification of the hardware and software. \nWhat You Will Learn \n\nOverview of Silvaco’s portfolio of AMBA AHB subsystems\, features\, and capabilities\nWhich architecture to use for a given application: Channel vs. Fabric\nCustomization of subsystems\nSecurity Issues with traditional Cortex-M architecture\nOverview of Secure Subsystem Security features\nSoftware as a component of hardware simulation\nSecurity improvements\, software security\, and secure boot\n\nBio\nJim Avant\, Senior Hardware and Software Engineer\,\nIP Division\, Silvaco\, Inc.\nJim Avant is a senior hardware and software engineer in Silvaco’s IP Division. He is the primary designer for several digital soft IP designs including the Secure AHB Subsystem. Prior to joining Silvaco in 2017\, Jim was a senior design engineer at SoC Solutions. He has an extensive background in RTL digital logic design\, digital signal processing\, and embedded C programming.\nJim Avant holds a bachelor’s degree in Electrical Engineering (BEE) from Georgia Tech in Atlanta\, Georgia.
URL:https://marketingeda.com/event/amba-ahb-subsystems-and-how-to-customize-secure-and-verify/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-May-12-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220511T100000
DTEND;TZID=America/Los_Angeles:20220511T130000
DTSTAMP:20220419T200653Z
CREATED:20220419T200653Z
LAST-MODIFIED:20220419T200653Z
UID:4569-1652263200-1652274000@marketingeda.com
SUMMARY:Arm and Cadence: Achieving Best Silicon Power\, Performance\, and Area
DESCRIPTION:How do you deal with design requirements that span high performance\, energy-efficient computing\, and high-reliability implementation? To realize these goals\, you need optimal design flows to deliver the best power\, performance\, and reliability. \nJoin Cadence and Arm virtually for CadenceCONNECT: Arm and Cadence – Achieving Best Silicon Power\, Performance\, and Area. Learn about: \n\nHigh-performance design for the Arm® Cortex®-A710 and other Arm processors\nEnergy-efficient CPU implementation flows\nHigh-reliability design using Arm library IP\nAging-aware static timing analysis (STA)\n\nExplore how you can efficiently implement your Arm-based SoCs with the Cadence® digital full-flow solution and get the best power\, performance\, and area (PPA). \nRegister now and join us on May 11. \nEvent times per region. Each event is 3 hours long. \nAsia-Pacific\n9:00am CST | 10:00am JST\, KST \nEurope\, Israel\, India\n9:00am BST | 10:00am CEST | 11:00am Israel | 1:30pm India​ \nNorth America\n1:00pm EDT I 10:00am PDT \n  \n\n\n\nSessions\nSpeaker\n\n\nDelivering Best-in-Class PA and TAT for Arm Total Compute\nUsing Cadence Digital Full Flow\nPierre-Alexandre Bou-Ach\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nAchieving Outstanding Performance for Arm Cortex-A710 Processor\nUsing Samsung Foundry 4LPP and the Cadence Digital Flow\nChinthamani Jagannath\, Cadence\n\n\nEnergy-Efficient 5nm High-Performance Arm Core Implementation\nUsing Cadence Digital Full Flow\nOlivier Rizzo\, Arm\n\n\nAchieving 3.6GHz+ for New Client Markets Through Implementation\nUsing Cadence Digital Full Flow\nRahoul Varma and Haroon Gauhar\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nGain PA Advantage with New Aging-Aware STA Solution for\nHigh-Performance Semiconductor Designs\nSatheesh Balasubramanian\, Arm\, and\nPaddy Mamtora\, Cadence\n\n\nHigh-Reliability Soft-Error Resilience Design Implementation\nUsing Arm IP and Cadence Digital Full Flow\nRobert Christy\, Arm\, and\nDesmond Cicero\, Cadence\n\n\n\n 
URL:https://marketingeda.com/event/arm-and-cadence-achieving-best-silicon-power-performance-and-area/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-11-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220510T080000
DTEND;TZID=America/Los_Angeles:20220512T170000
DTSTAMP:20220429T015316Z
CREATED:20220421T220326Z
LAST-MODIFIED:20220429T015316Z
UID:4583-1652169600-1652374800@marketingeda.com
SUMMARY:AutoSense Detroit 2022
DESCRIPTION:We can’t wait to bring our community back together at the Michigan Science Center in Detroit. Join us 10-12 May to hear from over 50 speakers from companies across the autonomous vehicle perception supply chain\, including  AMD\, BrainChip\, Indie Semiconductor\, ON Semiconductor\, Siemens\, STMicroelectronics\, Cadence\, Valeo\, MOBIS\, Synopsys\, Veoneer\, General Motors and Baraja. \nWith a full exhibition of over 30 key industry players\, a range of round table sessions and two drinks receptions\, you can maximise the opportunity to network with expert engineers\, academics\, and professionals. \nKey topics include developments in RADAR and LiDAR\, image quality\, data\, safe system design\, advances in camera technology\, in-cabin monitoring\, supply chain outlook and more.
URL:https://marketingeda.com/event/autosense-detroit-2022/
LOCATION:Michigan Science Center\, 5020 John R St\, Detroit\, MI\, 48202\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/AutoSens-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220428T090000
DTEND;TZID=America/Los_Angeles:20220428T100000
DTSTAMP:20220411T214937Z
CREATED:20220411T214937Z
LAST-MODIFIED:20220411T214937Z
UID:4534-1651136400-1651140000@marketingeda.com
SUMMARY:Adding Intelligence to Electronic Product Lifecycle using Requirements management
DESCRIPTION:This Webinar will cover a methodology that can be easily integrated into the system design and systems engineering process. VisualSim Insight Engine provides an intelligent way to connect the Requirements to system specification by running Monte Carlo simulation to detect the quality\, efficiency\, reliability and compliance to the Requirements. You can identify areas of improvement\, detect bottlenecks and also determine the expected behavior when the system is integrated. Unlike current solutions that treat Requirements as a document\, this dynamic solution tracks the system behavior through the design process and ensure the results are adhering to the Requirements. \nDuring this Webinar\, we will cover the translation of Requirements into system logic for use in systems engineering simulation\, setup the Requirements for a system\, semiconductor or network\, visualize the comparison and reports\, and make decisions. We will use an automotive\, processor and a radar signal processing system as examples to illustrate the benefits. \n1. Do you have formal Requirements program? \n2. Would you like to integrate Requirements into the product design flow? \n3. Do you want to optimize the system specification to meet and not over/under design? \n4. Are you trying to simulate your SysML specification to meet performance and power goals? \nHost\nDeepak Shankar is the Founder of Mirabilis Design and has been involved in the Requirements simulation\, systems engineering and architecture exploration of processors\, avionics\, network gateways\,. Mr. Shankar started Mirabilis Design because of a vacuum in the integration of requirements into systems engineering and modeling. Deepak has published over 50 articles and presented at over 30 conferences in EDA\, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley\, MS in from Clemson University and BS from Coimbatore Institute of Technology\, both in Electronics and Communication.
URL:https://marketingeda.com/event/adding-intelligence-to-electronic-product-lifecycle-using-requirements-management/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220428T083000
DTEND;TZID=America/Los_Angeles:20220428T093000
DTSTAMP:20220331T170239Z
CREATED:20220331T170239Z
LAST-MODIFIED:20220331T170239Z
UID:4487-1651134600-1651138200@marketingeda.com
SUMMARY:Protecting Connected IoT devices against Quantum computing threats: Post Quantum Cryptography
DESCRIPTION:With Sofiane Takarabt\, Program Manager of Applied Cryptography at Secure-IC\nThursday\, April 28\, 2022 – 10:00 AM (CET) & 17:30 (CET) – 11:30 AM (EST) \nIn a world of ubiquitous connected devices\, massive exchange of sensitive data must be protected with cryptographic functions. It is also necessary to prepare for the advent of quantum computers which will make classic asymmetric cryptography obsolete. The recent trend of standardization pushes indeed a safe quantum cryptography. Thus\, a wide variety of communication systems and public key infrastructures must be updated with post-quantum cryptography solutions. In this presentation\, we discuss the three main functions; signature verification\, key encapsulation and secure boot\, and how to provide these services in different contexts and constraints of performance. \nThis webinar will help you understand: \n\nThe main applications for PQC algorithms\, giving an accurate understanding of the subject\nHow classic asymmetric cryptography algorithms may be replaced\nHow PQC can be implemented in all kinds of applications\, to answer a variety of use cases\n\nInsights will also be given on the way to best choose and implement the algorithms to answer various performance constraints. \n 
URL:https://marketingeda.com/event/protecting-connected-iot-devices-against-quantum-computing-threats-post-quantum-cryptography/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-APril-28-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220426T080000
DTEND;TZID=America/Los_Angeles:20220427T170000
DTSTAMP:20220427T064316Z
CREATED:20220127T174859Z
LAST-MODIFIED:20220427T064316Z
UID:4228-1650960000-1651078800@marketingeda.com
SUMMARY:D&R IP SoC Silicon Valley 2022
DESCRIPTION:When : April 26th 2022 \nWhere : Computer History Museum\n1401 N. Shoreline Blvd\nMountain View\, CA 94043\, USA \nD&R IP-SoC Silicon Valley 2022 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nPhysical meeting between vendors and consumers is the unique and non replaceable vehicle to engage business discussions between vendors and clients.\nNevertheless this event will also be “replicated” on line after the event aiming at triggering more business opportunities.\nPosting their talk and recording their presentations on easily accessible platforms will extend innovation sharing among the worldwide IP-SoC Community. \nAny question? Please contact us \n\nImportant Dates \n\nSubmission Deadline : March 1st 2022\nSlides and presentation records available on April 1st 2022\nPanel proposal to be submitted before February 25th 2022\nto gabriele.saucier@design-reuse.com\n\nAreas of interest (not limited to) : \nInnovation in technology \n• New technology for new applications\n• Foundries Ecosystem\n• IP and SoC on Advanced node\n• 3D packaging\, D2D\, C2C connectivity\n• Quantum computing and Qubit technology \nInnovative IP SoC \n• Low power Analog IP and Memory\n• Advanced Interface IP\n• IP SoC for Artificial Intelligence\n• IP/SoC for Automotive\, Avionics\, Defense…\n• RISC-V\, GPU\, Dedicated processor…\n• Security Solutions \nIP Best Practice \n• Business models\n• IP Management Platform\n• Market Analysis \nIP/SoC Design Methodology \n• Low Power\, and area optimized design\n• IP Integration & Design Flows\n• Verification and Emulation
URL:https://marketingeda.com/event/dr-ip-soc-silicon-valley-2022/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Design-and-Reuse-April-26-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220421T080000
DTEND;TZID=America/Los_Angeles:20220421T090000
DTSTAMP:20220419T005257Z
CREATED:20220419T004804Z
LAST-MODIFIED:20220419T005257Z
UID:4558-1650528000-1650531600@marketingeda.com
SUMMARY:What's Behind the Infrastructure of the CORE-V Family
DESCRIPTION:Automated code validation\, continuous integration and test regression are cornerstones of OpenHW Group’s community-based engineering process to develop and verify high-quality processor cores. OpenHW Group is deploying a state-of-the-art Test Automation and Continuous Integration environment to achieve these objectives across our diverse projects\, resulting in faster development cycles with increased quality. In this webinar\, Florian Zaruba and Massimiliano (Max) Giacometti of the OpenHW Group staff will review OpenHW’s CI requirements and approaches. \nA critical component to highlight is the robust design equivalence checking solution\, which ensures that only the expected changes have been implemented at check-in points and no downstream functional bugs are introduced across logical Boolean\, low power intent\, and clock/reset domain contexts. David Stratman\, Product Management Director at Cadence Design Systems\, will discuss the Cadence Conformal suite of tools anchored by their Logical Equivalence Checking (LEC) solution. \nRick O’Connor of OpenHW Group will be moderating the discussion.
URL:https://marketingeda.com/event/whats-behind-the-infrastructure-of-the-core-v-family/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/OpenHW-April-21-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220420T080000
DTEND;TZID=America/Los_Angeles:20220421T170000
DTSTAMP:20220406T202613Z
CREATED:20220406T202537Z
LAST-MODIFIED:20220406T202613Z
UID:4513-1650441600-1650560400@marketingeda.com
SUMMARY:Linley Spring Processor Conference 2022
DESCRIPTION:TechInsights is pleased to continue the semi-annual Linley Processor Conferences\, established more than a decade ago. This year\, the Linley Spring Processor Conference will return to Santa Clara on April 20-21\, 2022 with a new hybrid format; if you can’t attend in person\, you can tune in to our virtual livestream. \nPresentations will address processors and IP cores for AI applications\, embedded\, data-center\, automotive\, and server designs. In-person attendees will be able to hear presentations and interact with the speakers during Q&A\, lunch\, and the networking reception. \nAnalyst and Industry Keynotes \nLinley Gwennap\, principal analyst\, TechInsights\, will open the conference with an overview of the latest market\, technologies\, equipment-design\, and silicon trends. We’ll also feature a keynote from another industry leader. \nIn-Depth Technical Sessions \nUnlike many conferences\, we ensure that the presentations deliver real technical content\, not marketing hype. We’re the conference of choice for many companies who announce new products or make technology disclosures. TechInsights analysts carefully select session topics and choose leading speakers who are experts in their fields. In addition\, the analysts ensure that the content of the presentations are full of insightful\, technical information that will help attendees select the right components and systems for their next project. \nThe program will feature talks and panel discussions covering a broad range of topics: \nAgenda Day 1\nAgenda Day 2 \nWhy Attend \nThe Linley Processor Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear\, question\, and network with key providers of advanced technology products. \nThe conferences analyze products and design strategies in a particular technology segment\, providing information that engineers can immediately use to improve their designs. The events feature in-depth technical presentations from our own analysts as well as leading technologists from the industry. \nFree Admission \nWe offer free admission to qualified registrants\, making it easy to participate. The conference is intended for chip designers\, system designers\, equipment vendors\, OEM/ODMs\, service providers\, press\, and the financial community. \nCOVID-19 Policies and Precautions \nWe are working closely with the Hyatt Regency to reduce the risk of attending our in-person event. Individuals and their employers\, however\, must decide what level of risk is acceptable. For those unable to attend in person\, we offer our virtual livestream. \nAttendees will be required to provide proof of vaccination before receiving their conference badge. Consistent with local health orders\, masks are now recommended but not required. Policies are subject to change; we will update this page as needed.
URL:https://marketingeda.com/event/linley-spring-processor-conference-2022/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Linley-April-20-21-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220419T080000
DTEND;TZID=America/Los_Angeles:20220419T170000
DTSTAMP:20220404T192418Z
CREATED:20220404T192418Z
LAST-MODIFIED:20220404T192418Z
UID:4499-1650355200-1650387600@marketingeda.com
SUMMARY:CHIPS Alliance Spring Event
DESCRIPTION:The CHIPS Alliance holds workshops in various locations throughout the year\, based upon the needs of our project and members.  Members of the CHIPS Alliance receive a number of complementary passes each year\, based upon their membership level. \nDate: April 19\, 2022 at 8 a.m. PT \nSchedule: \n\nWelcome / Opening Remarks: Rob Mains\, CHIPS Alliance\nChisel/FIRRTL Ecosystem Updates: Jack Koenig\, SiFive\nF4PGA Group Kickoff\, Interchange Format: Karol Gugala\, Antmicro\nChiplet Protocol IP: David Kehlet\, Intel\nNIST (Cryo Test Structures): Mehdi Saligane\, UMICH\nNVMe FPGA IP for Edge Applications: Anand Kulkarni\, Western Digital\nUpdate on Shuttle Programs: Tim Ansell\, Google
URL:https://marketingeda.com/event/chips-alliance-spring-event/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CHIPS-Alliance-April-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220412T090000
DTEND;TZID=America/Los_Angeles:20220412T100000
DTSTAMP:20220411T185919Z
CREATED:20220411T185919Z
LAST-MODIFIED:20220411T185919Z
UID:4531-1649754000-1649757600@marketingeda.com
SUMMARY:The Changing Landscape of Automotive Electronics
DESCRIPTION:The automotive industry is undergoing a seismic shift. Supply chain constraints\, software defined architectures\, functional safety requirements\, and the changing dynamics between OEMs\, Tier 1s and semiconductor companies\, are driving the industry to seek innovative ways to approach new challenges.\nJoin us on Tuesday\, April 12th\, 2022\, for a special panel discussion as we review the changing landscape of automotive electronics. \n\nThe webinar will examine:\n\n\n\nBeyond the current supply demand problem\nThe changing relationships between OEMs\, Tier 1s\, and Semiconductors\nHow can the industry develop a standardization of language?\nHow software defined architecture is changing automotive electronics?\nWhat is the next generation of vehicle architecture?\nAdvanced electronics as a driver for safety profiles\n\nModerator\nGrayson Brulte\nCo-Founder\nBrulte & Company \nPanelists \nDr. Peter Mertens\nAutomotive Industry Veteran and Tech-Investor \nDr. Dean Bushey\nVice President and Head of Environment Business Division (Americas)\nHitachi \nStephen Kosonocky\nSenior Fellow\nUhnder \nGal Carmel\nGM Automotive\nproteanTecs
URL:https://marketingeda.com/event/the-changing-landscape-of-automotive-electronics/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-April-12-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220411T100000
DTEND;TZID=America/New_York:20220412T112000
DTSTAMP:20220401T201126Z
CREATED:20220401T201105Z
LAST-MODIFIED:20220401T201126Z
UID:4492-1649671200-1649762400@marketingeda.com
SUMMARY:Design Automation WebiNar (DAWN)
DESCRIPTION:We are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nDue to the outbreak of coronavirus (COVID-19)\, almost all conferences/symposiums in design automation community are canceled/postponed. People are not able to meet each other\, learn recent advances\, and discuss research ideas. The whole community is quarantined\, just like shrouded in darkness made by COVID-19. Thus\, it is about time to bring the light from inspired scholars in our community and therefore we are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote- and sole-speaker-style webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nApril 11\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – Hardware/Software Co-Exploration of Neural Architectures\n10:20 AM-10:40 AM – BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework\n10:40 AM-11:00 AM – APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors\n11:00 AM-11:20 AM – Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration\n\nApril 12\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement\n10:20 AM-10:40 AM – TreeNet: Deep Point Cloud Embedding for Routing Tree Construction\n10:40 AM-11:00 AM – Intermittent-Aware Neural Architecture Search\n11:00 AM-11:20 AM – A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
URL:https://marketingeda.com/event/design-automation-webinar-dawn/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/IEEE-April-11-12-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220405T110000
DTEND;TZID=Asia/Jerusalem:20220405T170000
DTSTAMP:20220324T164026Z
CREATED:20220324T164026Z
LAST-MODIFIED:20220324T164026Z
UID:4461-1649156400-1649178000@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:11:00 – 11:30 | ASIC Verification\nVeloce proFPGA: The Perfect Complement for Your System Verification Flow \n11:30 – 12:00 | Emulation Queuing\nEmulation – Getting a Better Return on Your Investment \n12:00 – 12:30 | DFT For Automotive\nDesign-For-Test Design (DFT) Consideration for Automotive Designs \n12:30 – 13:00 | Low-power Vector AI Processing\nIntroducing SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA \n13:00 – 15:00 | Break \n15:00 – 15:30\nTessent Streaming Scan Network (SSN): No-compromise DFT \n15:30 – 16:00 | RISC-V Software Development\nWhy Wait For Hardware to Start RISC-V Software Development? \n16:00 – 16:30 | Design & Verification IP\nMaking MIPI Your Ally \n16:30 – 17:00 | Physical Planning and Timing Closure\nExcellicon Product Portfolio
URL:https://marketingeda.com/event/semisrael-tech-webinar-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-April-5-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220405T080000
DTEND;TZID=America/Los_Angeles:20220407T170000
DTSTAMP:20220301T023630Z
CREATED:20210903T205459Z
LAST-MODIFIED:20220301T023630Z
UID:3257-1649145600-1649350800@marketingeda.com
SUMMARY:DesignCon 2022
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers \nDesignCon is the premier high-speed communications and system design conference\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
URL:https://marketingeda.com/event/designcon-2022/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220330T140000
DTEND;TZID=Asia/Tokyo:20220330T143000
DTSTAMP:20220324T162830Z
CREATED:20220324T162830Z
LAST-MODIFIED:20220324T162830Z
UID:4457-1648648800-1648650600@marketingeda.com
SUMMARY:Imperas RISC-V simulation technology with eSol Trinity and NSITEXE
DESCRIPTION:Imperas Software Ltd.\, the leader in RISC-V simulation solutions\, today announced with eSol Trinity the webinar event on RISC-V reference models and simulation technology for the growing adoption of RISC-V in Japan. This webinar will feature a guest speaker – Mr. Marume of NSITEXE Co.\, Ltd.\, a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs\, will introduce an example of using the Imperas RISC-V reference model and simulator. \nRISC-V is an open ISA (Instruction Set Architecture)\, which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra\, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles. \nVirtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors\, as well as user defined custom instructions\, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow. As the project develops to the next phase\, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early software compatibility with the growing ecosystem supporting RISC-V vector extensions. \n  \nWebinar:    ‘Imperas RISC-V reference model and high speed simulation technology’\nWhen:         March 30th 2022\nWhere:        2:00-2:30pm (JST) Live streaming (Zoom) \nFor more information including registration please visit this link.\nAbout Imperas \nFor more information about Imperas\, please see www.imperas.com. Follow Imperas on LinkedIn\, twitter @ImperasSoftware and YouTube. \nAll trademarks or registered trademarks are the property of their respective holders.
URL:https://marketingeda.com/event/imperas-risc-v-simulation-technology-with-esol-trinity-and-nsitexe/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Imperas-March-30-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220330T080000
DTEND;TZID=America/Los_Angeles:20220331T170000
DTSTAMP:20220203T000634Z
CREATED:20220203T000634Z
LAST-MODIFIED:20220203T000634Z
UID:4274-1648627200-1648746000@marketingeda.com
SUMMARY:SNUG - Silicon Valley
DESCRIPTION:SNUG brings together users and technical experts to network and share best practices for tackling design and verification challenges. By attending SNUG\, attendees gain knowledge to use on current projects and discover ideas to spark future innovations. SNUG Silicon Valley will be conducted in a virtual format due to recent COVID-19 developments that have raised concerns among attendees and presenters about assembling in a large group\, and about traveling for conferences. SNUG will still be taking place on March 30-31\, 2022\, and will offer user presentations\, keynote addresses\, panels\, tutorials\, and more. The SNUG team remains committed to delivering an exciting conference\, driven by the always innovative Synopsys community.
URL:https://marketingeda.com/event/snug-silicon-valley/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220330T080000
DTEND;TZID=America/Los_Angeles:20220330T170000
DTSTAMP:20220315T164242Z
CREATED:20220315T164242Z
LAST-MODIFIED:20220315T164242Z
UID:4445-1648627200-1648659600@marketingeda.com
SUMMARY:Secure Your Devices with PUF Plus Hardware Root of Trust
DESCRIPTION:Technology experts from Rambus and Intrinsic ID will discuss how combining PUF technology with a hardware Root of Trust can provide robust security for data and devices. The session will start with the fundamentals of PUFs and example use cases. Then we will discuss how the characteristics of PUFs and a hardware Root of Trust can provide protection against would-be attackers as well as ongoing security over the life of a device. \nFEATURED PRESENTERS\n\n\n\n\n\n\n\n\nDr. Ir. Roel Maes\n\nPrincipal Security Architect\, Intrinsic ID\n\n\n\n\nRoel Maes is the Principal Security Architect at Intrinsic ID where he works on the research\, development and specification of security architectures and solutions for Intrinsic ID’s products and innovations. His technical expertise is focused on…\nFull Profile\n\n\n\n\n\n\n\n\n\n\n\nScott Best\n\nTechnical Director Product Management\, Rambus\n\n\n\n\nScott Best joined Rambus in October 1998 who\, while serving in many and varied technical roles\, has become one of the most prolific inventors in the company’s history. Over the course of his career at Rambus\, he is a named inventor on over 200…\nFull Profile\n\n\n\n\n\n\n\n\n\n\n\nBrandon Lewis\n\nEditor-in-Chief\, Embedded Computing Design\n\n\n\n\nBrandon is a tech journalist and electronics marketer with more than a decade of experience covering the embedded sector. In his current role as Editor-in-Chief of Embedded Computing Design\, he guides the publication’s content strategy\, editorial…\nFull Profile
URL:https://marketingeda.com/event/secure-your-devices-with-puf-plus-hardware-root-of-trust/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-March-30-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220328T080000
DTEND;TZID=America/Los_Angeles:20220330T170000
DTSTAMP:20220128T183820Z
CREATED:20220128T183820Z
LAST-MODIFIED:20220128T183820Z
UID:4241-1648454400-1648659600@marketingeda.com
SUMMARY:tinyML Summit 2022
DESCRIPTION:Registration will open by January 31 \nWhat seemed like a dream a few years ago is quickly turning into reality. Problems which used to require Gigabytes to solve\, became Megabytes and then Kilobytes. Join us at the tinyML Summit 2022 to take part in the sharing\, learning\, and celebrating tinyML. \nWith ever more pervasive advances in technology and algorithms\, tinyML is rapidly becoming a reality. In the tinyML community\, we stand on the shoulders of giants. It is the incredibly open and collaborative nature of ML technology which allows this field to advance so quickly. From its inception in 2019\, the tinyML community has grown tremendously and has benefited greatly by supporting one another. We all hold unique pieces of the puzzle\, but it is through leveraging the collective knowledge of the community that we can move together more quickly. \nIn conjunction with the Summit\, the tinyML Research Symposium 2022 will be held on Monday\, March 28. \n\n\n\n\n\nVenue\n\n\nHyatt Regency San Francisco Airport\n\n1333 Bayshore Highway\, Burlingame\, CA 94010. \n\nRoom Booking\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVENUE & ACCOMMODATIONS \nHyatt Regency San Francisco Airport \nRoom Booking \nThe cut-off date is Monday\, March 7th\, 2022.  After March 7 rooms may still be available but may have a higher prevailing rate. \nPROGRAM PREVIEW\n \nFive sessions have been planned focusing on several different areas related to tinyML. You will be hearing from selectively invited speakers from each area: \nTalk to Me! TinyML opportunities in smart audio\nSession Leader: Chris Rowen\, Cisco \nAudio is a uniquely attractive target for Tiny machine learning. On one hand\, audio\, especially speech\, hosts richly layered information on communication intent\, identity\, location\, emotion and events. On the other hand\, it is densely encoded so this rich diversity of information is surprisingly hard to extract and interpret. Machine Learning methods prove remarkably effective\, opening up countless applications in speech recognition\, event detection\, voice trigger\, speech transformation and generation. The relatively low bit-rates for audio make it possible to capture and process audio in small power budgets\, and the privacy and latency concerns often make it necessary to concentrate audio processing at the edge – a perfect storm for tinyML audio opportunity. \ntinyML Vision: Efficient design of tiny vision models for IoT devices\nSession Leader: Song Han\, MIT \nComputer vision is popular application for tiny machine learning. Many vision applications require real-time\, low-latency processing\, and privacy is a big priority\, thus recognizing the images/videos locally on tiny edge devices has a lot of opportunity. However\, the large computation and memory footprint poses a challenge on these low-power devices\, which goes worse as the resolution requirement gets larger. Opportunities including model compression and neural network and accelerator co-design opens up a larger design space for tiny machine learning for vision\, which has a large market in smart home\, smart factory\, smart driving\, smart healthcare\, and more. \n\n\n\n\ntinySensing: Scaling tinyML solutions with optimized edge sensing capabilities\nSession Leader: Steve Whalley\, tinyML Board of Directors member \nAs more is done on the edge with less power\, code and real estate\, what does this mean for sensor requirements to stay aligned with the explosive tinyML growth? Going beyond popular tinyML applications in camera sensing for vision and MEMS microphones for audio\, will traditional inertial\, environmental\, medical sensing\, etc. capabilities suffice? What new innovations and ‘smart capabilities’ be required to squeeze more performance\, bandwidth\, lower power\, memory\, analog and ASIC capability into edge sensing solutions? Will changes in Machine Learning methods and tools be needed? Will printed sensing\, with the promise of tiny footprints and power\, be the future darling of tinyML? This session will delve into some of the opportunities\, challenges and trends in the tinySensing world and provide a rigorous dialog on what is needed. \ntinyHardware – there’s plenty of room at the bottom\nSession Leader: Francesco Conti\, University of Bologna \ntinyHardware stands at the crossroads between algorithm\, technology\, and architecture. Aggressive algorithmic optimizations such as quantization\, pruning\, and analog computation do not destroy Machine Learning’s capability to decode and interpret information – rather\, they introduce smooth degradations that can often be tolerated. On the other hand\, these optimizations offer a large “attack surface” for emerging technology such as non-volatile memory\, analog in-memory computing\, and innovative chip-to-chip links – as well as for novel architecture in terms of dataflow choices\, sparsity support\, core/memory coupling and caching schemes. Altogether\, these opportunities define a huge design space spanning from low-bitwidth ISA extensions to multi-chip systolic arrays to System-on-Chips with core-coupled in-memory accelerators – a space that we have just started to navigate in the quest to raise system-level energy efficiency of tinyML applications while enabling more complex Tiny applications. \ntinySW/Tools: Enabling tiny experiences for the real-world\nSession Leader: Alessandro Grande\, Edge Impulse \nSoftware and tools specifically designed for tiny machine learning (tinyML) are empowering researchers\, data scientists and embedded engineers to pave the way for a whole new class of experiences. Whereas the focus was initially on creating software and tools to make each step of the process possible — on one hand enabling data scientists to create datasets\, train and optimize models able to run on resource-constrained devices\, on the other hand helping embedded engineers use the models to develop applications capable of efficiently performing inference on the microcontrollers themselves — we are now starting to see a shift towards software and tools that allow scientists and engineers to leverage tinyML in real-world use cases. Opportunities lie in tightly integrated end-to-end platforms\, new data augmentation methods\, performance analysis tools\, as well as optimization tool techniques. This tinySW/Tools session will explore some of the recent advancements in the field\, while uncovering some of the challenges we are facing as an industry. \nAutoTinyML design\nSession Leader: Danilo Pau\, STMicroelectronics \nLatest generation microcontrollers\, sensors\, digital signal processors\, and ultra-low power accelerometers are opening numerous possibilities in compact machine learning (ML) applications with limited storage and power consumption. Now\, the over 10 million C developers of the embedded community are calling for useful productivity tools to support ML pipeline design from the earliest concept and design phases. The tools should automate ML topology design and optimize configuration without requiring developers to craft new solutions for each issue. \nThis session will focus on tools for Automated Tiny ML design and Hyper Parameter Search. Industrial and university experts will discuss the current and next-generation tools for embedding ML in small\, everyday applications. This is an excellent opportunity for attendees to learn how to deploy their models in tiny devices and ramp up ML design productivity.
URL:https://marketingeda.com/event/tinyml-summit-2022/
LOCATION:Hyatt Regecy San Francisco Airport\, 1333 Bayshore Highway\, Burlingame\, CA\, 94010\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/tinyML-Summit-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220322T083000
DTEND;TZID=America/Los_Angeles:20220322T093000
DTSTAMP:20220301T180600Z
CREATED:20220301T180600Z
LAST-MODIFIED:20220301T180600Z
UID:4399-1647937800-1647941400@marketingeda.com
SUMMARY:SecuryzrTM integrated Security Services Platform (iSSP): Services for lifecycle security management
DESCRIPTION:Nowadays\, fleets of connected devices have operational needs to maintain over time a relevant level of security. To mitigate the growing threats and vulnerabilities in the field and protect end-user devices from cyberattacks at both the network and device levels\, a new strategy is needed to filter attacks in real time and implement a centralized protection mechanism for all connected modules. While device-to-device communication remains operational\, a secure cloud-based device manager\, capable of ensuring secure operation throughout the devices’ lifecycle is needed. \nSecuryzrTM integrated Security Services Platform (iSSP) enables the secure provisioning\, deployment and management of a fleet of devices from the cloud. The solution manages heterogeneous fleets of devices with different services: \n\nKey provisioning to securely provision the chip devices with secret key across the supply chain\,\nFirmware Update (FOTA/FUOTA) to securely provide chips with their software and then update them physically or over the air\, to maintain their security level\,\nDevices Monitoring and cyber intelligence to provide a proactive security service\, retrieving cyber security logs from the chips\, analyzing them and sending instructions back to the chip fleet if necessary\,\nDevices Identity to guarantee trust from the chip to the cloud\, to the devices\, users and data through devices multi-factor authentication that allows resistance against impersonation\, replay\, and in the event of an initial compromise.\n\nThis webinar will present Secure-IC’s new solution and associated added-value security services. \nMichel Le Rolland\nProduct Marketing Manager of Secure-IC\nMichel Le Rolland has a master of engineering degree in electronics and computer science from the French “Telecom Bretagne”.\nHe joined Secure-IC in 2016 as R&D engineer in charge of the design of anti-tampering solution. After 3 years of designing HW Secure-IC’s solution\, he is now in charge of the Product Marketing activity for Secure-IC.
URL:https://marketingeda.com/event/securyzrtm-integrated-security-services-platform-issp-services-for-lifecycle-security-management/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-March-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220321T080000
DTEND;TZID=America/Los_Angeles:20220324T170000
DTSTAMP:20220128T182927Z
CREATED:20220128T182521Z
LAST-MODIFIED:20220128T182927Z
UID:4235-1647849600-1648141200@marketingeda.com
SUMMARY:GOMACTech 2022
DESCRIPTION:WELCOME TO GOMACTech 2022\nEnabling Distributed Capabilities: Microelectronics Thriving in the Face of Change\n\n\nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \nSECURITY PROCEDURES\nThe GOMACTech Conference is an Unclassified\, Export-Controlled event that requires participants to be U.S. Citizens or legal U.S. Permanent Residents. All registrants\, including presenters and exhibitors\, must provide proof of U.S. Citizenship or Permanent Resident status prior to being permitted entry into the conference. Additionally\, a signed Non-Disclosure Statement will be required. Note that all NDAs must be completed and signed on site.\nYou may prove U.S. citizenship with any of the following:\n• U.S. Passport\n• Birth certificate AND valid government-issued photo ID\n• Naturalization certificate AND valid government-issued photo ID \nThe following are NOT proof of citizenship:\n• Voter registration card\n• Driver’s license
URL:https://marketingeda.com/event/gomactech-2022/
LOCATION:Hyatt Regecy Miami\, 400 South East Second Avenue\, Miami\, FL\, 33131-2197\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220316T080000
DTEND;TZID=America/Los_Angeles:20220316T090000
DTSTAMP:20220308T015931Z
CREATED:20220308T015931Z
LAST-MODIFIED:20220308T015931Z
UID:4430-1647417600-1647421200@marketingeda.com
SUMMARY:Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
DESCRIPTION:Automotive microcontrollers for next-generation software-defined vehicles need to deliver higher software capabilities. ST Stellar Integration MCUs offer safe\, secure\, and deterministic solutions for new vehicle architectures. The use of virtual prototypes is a key enabler to solving the emerging\, complex software development challenges throughout the automotive design and test supply chain\, such as feature integration\, functional safety\, and secure communications. \nThis 30-minute Webinar provides an overview of ST Stellar Integration MCU architectures and application domains\, explores how virtual prototypes enable the supply chain\, and includes a discussion on their benefits. Real case studies based on the ST Stellar virtual platform are examined to show how it’s integrated with the automotive tool ecosystem\, such as software debuggers\, plant models\, and network simulators. \nAn audience Q&A follows the technical presentation. \nSpeakers \nKevin Brand\, Senior Manager\, Applications Engineering\, Synopsys \nKevin Brand is a Senior Manager of Applications Engineering at Synopsys. He has been in the field of virtual prototyping for 17 years. With a strong focus on automotive\, Kevin has been working in R&D and\, in more recent years\, directly enabling and deploying virtual prototyping solutions at semiconductor\, Tier 1\, and OEM companies. \nPaul Kinowski\, Product Marketing Manager\, MCUs\, STMicroelectronics \nPaul Kinowski is the Marketing Manager for 32-bit automotive MCUs at STMicroelectronics. He has been working in the field of automotive MCUs for more than 20 years\, as an application engineer and in product marketing\, leading the introduction of popular MCUs for body and gateway applications. Since 2019\, Paul has been responsible for the automotive MCUs product marketing team\, having special focus on STELLAR products.
URL:https://marketingeda.com/event/using-st-stellar-mcu-virtual-prototypes-to-deliver-next-generation-software-defined-vehicles/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-March-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220315T110000
DTEND;TZID=America/Los_Angeles:20220315T120000
DTSTAMP:20220217T015416Z
CREATED:20220217T015403Z
LAST-MODIFIED:20220217T015416Z
UID:4332-1647342000-1647345600@marketingeda.com
SUMMARY:Memory Bandwidth Races Higher with HBM3
DESCRIPTION:With the formal release of the HBM3 specification\, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM\, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIn this webinar\, you will learn:\n\nCapabilities of HBM3 memory\nDesign considerations for HBM3 2D/3D implementations\nFeatures of the Rambus HBM3 Memory Interface Subsystem
URL:https://marketingeda.com/event/memory-bandwidth-races-higher-with-hbm3/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-March-15-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T100000
DTEND;TZID=America/Los_Angeles:20220310T110000
DTSTAMP:20220310T025826Z
CREATED:20220310T025826Z
LAST-MODIFIED:20220310T025826Z
UID:4435-1646906400-1646910000@marketingeda.com
SUMMARY:Power Intent Management for Large SoCs
DESCRIPTION:The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area)\, it’s challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. \nDuring this webinar\, we’ll talk about power. Beyond an automated generation of the power intent files before synthesis\, recently Defacto has released key capabilities at the front-end to better manage the power intent. \n• First capability is the promotion of the UPF; Given power intent files for different IPs\, designers have today the ability to assemble UPF files and promote the power intent automatically to the top. \n• The second feature is the other way around called UPF demotion; Given an existing SoC or subsystem\, a designer can extract the power intent file. \nMore precisely\, during this webinar our experts will cover a complete power intent management methodology with a particular focus on integration needs pre-synthesis: how to generate UPF from scratch\, update the UPF after design changes\, demote UPF for reuse purpose and promote the UPF based on the integration. \nAUDIENCE:\nCAD Manager\, Architects\, CAD Engineer\, Designers\, Integration teams\, Verification teams and UPF experts! S \nPEAKERS:\n• Chouki Aktouf: CTO at Defacto • Arthur Kalsing: Senior R&D engineer at Defacto & UPF Expert
URL:https://marketingeda.com/event/power-intent-management-for-large-socs/
LOCATION:Defacto Techologie\, 2 rue Emile Augier\, Grenoble\, France
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-March-10-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T090000
DTEND;TZID=America/Los_Angeles:20220310T100000
DTSTAMP:20220223T170626Z
CREATED:20220223T170626Z
LAST-MODIFIED:20220223T170626Z
UID:4356-1646902800-1646906400@marketingeda.com
SUMMARY:Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
DESCRIPTION:• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?\n• Do you need to size the AI accelerator for existing and future AI requirements?\n• Would it be beneficial if you knew the latency advantage between ARM\, RISC\, DSP and Accelerator in deploying AI tasks? \nThis webinar focuses on design teams transitioning to an AI accelerator in their next-generation SoC processor. In the webinar\, we will use VisualSim system-level modeling and hardware-software partitioning technology in migrating an algorithm to an AI accelerator. The SoC architecture will be tested for a variety of workloads and use-cases. The new VisualSim Insight methodology will be deployed to track the requirements through SoC planning\, design\, validation and testing. The generated diagnostics and metrics will be used to make decisions on the right AI accelerator configuration. \nAI accelerators can be built with a variety of configurations- single vs. multi-core\, 2 or 3 level caches\, Network-on-Chip (NoC) vs. AMBA AXI bus\, or LPDDR vs. DDR5. At the same time\, the task partitioning can be based on lowest power\, latency\, memory throughput\, or smallest size of each IP block. Join this webinar to understand the power\, sizing and latency advantages obtained through AI Accelerators. \nSpeaker:\nTom Jose is a Research & Development Engineer at Mirabilis Design. A System Design Architect & Trainer\, he supports companies and universities to build their own design. He has published three papers – RISC-V & ARM processor comparison at the RISC-V international conference\, Using AI for optimal Time Sensitive Networking in Avionics & Functional Safety for Braking System through ISO 26262\, and Operating System Security and DO 254. He has worked with the micro architecture design of processor pipeline stages\, instruction implementation\, verification and workload partitioning. \nThis webinar is in partnership with SemiWiki and Mirabilis Design.
URL:https://marketingeda.com/event/balancing-performance-and-power-in-adding-ai-accelerators-to-system-on-chip-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/MIrabilis-March-10-2022.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T080000
DTEND;TZID=America/Los_Angeles:20220310T090000
DTSTAMP:20220222T173510Z
CREATED:20220222T173510Z
LAST-MODIFIED:20220222T173510Z
UID:4349-1646899200-1646902800@marketingeda.com
SUMMARY:Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
DESCRIPTION:Audiovisual experiences in XR\, gaming\, movies\, and concerts can all be enhanced with spatial audio experience immersive technology. A superior spatial audio experience occurs when you combine headphones\, with wearable head tracking\, and on-device processing. Believe it or not\, despite the recent wide adoption of Spatial/3D Audio\, the concept and technology have been around for a while. However\, the technology behind it has advanced significantly as the industry continues to make strides in computing and cost. \nIn this webinar\, we begin by discussing the fundamental concepts of binaural spatial audio and their core principles of operation. We expose the key spatial audio processing and head tracking challenges to creating an effective system. We will offer solutions to these challenges on the way to creating a robust\, complete Spatial Audio experience. Finally\, we will close by introducing an available reference design that combines these\, as well as some upcoming improvements. \nJoin CEVA and VisiSonics experts to learn about: \n\nWhat is Spatial/3D Audio\nHow does Spatial/3D Audio work\nWhat are the technical challenges to implementing an effective Spatial/3D Audio system\nWhy is head tracking so important to Spatial/3D Audio\nHow can the technical challenges be addressed to provide a robust\, complete solution\n\n\nTarget Audience\nAudio system engineers and product managers targeting audio enabled devices\, that are looking to add 3D Audio capabilities to Hearables\, Smart Home\, Mobile\, and Automotive products.\n\nSpeakers\n\nBryan Cook\nSenior Team Leader\, Algorithm Software\, CEVA Inc.\n\n\n\nRamani Duraiswami\nCEO and Founder\, VisiSonics
URL:https://marketingeda.com/event/spatial-audio-what-it-is-and-how-to-overcome-its-unique-challenges-to-provide-a-complete-solution/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA.-March-10-2022.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220224T170000
DTEND;TZID=America/Los_Angeles:20220224T180000
DTSTAMP:20220221T220207Z
CREATED:20220221T220124Z
LAST-MODIFIED:20220221T220207Z
UID:4345-1645722000-1645725600@marketingeda.com
SUMMARY:Securing the Future with RISC-V
DESCRIPTION:While the metaverse took the spotlight at the recent CES\, it is made possible with advancement in computation and connectivity\, which also empower many other aspects of people’s lives from IoT\, Automotive\, and to all kinds of applications around us. \nWhile Andes RISC-V has continued to enable innovations in all emerging applications\, security in modern SoC design is becoming much more essential. \nIn this joint webinar\, PUFsecurity and Andes will discuss how to best address security design with Andes RISC-V architecture and share some common pitfalls to avoid.
URL:https://marketingeda.com/event/securing-the-future-with-risc-v/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Andes-February-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220223T090000
DTEND;TZID=America/Los_Angeles:20220223T100000
DTSTAMP:20220217T172213Z
CREATED:20220217T172213Z
LAST-MODIFIED:20220217T172213Z
UID:4336-1645606800-1645610400@marketingeda.com
SUMMARY:The Role of PUFs in a Trusted Supply Chain
DESCRIPTION:Trusted supply chain provenance and traceability is becoming increasingly important for the quality\, reliability\, and security of electronic products. It can help reduce costs for tracking and fixing field issues\, minimize liability risks and enable higher value in connected IoT applications. In addition\, there are significant efficiencies and cost reductions that could be enabled in the procurement process for many integrators. In this PUF Cafe Episode\, Tom will explain what the roles of trusted identities and PUF technology are in a trusted supply chain.
URL:https://marketingeda.com/event/the-role-of-pufs-in-a-trusted-supply-chain/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Itrinsic-ID-February-23-2022.png
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