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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220419T080000
DTEND;TZID=America/Los_Angeles:20220419T170000
DTSTAMP:20220404T192418Z
CREATED:20220404T192418Z
LAST-MODIFIED:20220404T192418Z
UID:4499-1650355200-1650387600@marketingeda.com
SUMMARY:CHIPS Alliance Spring Event
DESCRIPTION:The CHIPS Alliance holds workshops in various locations throughout the year\, based upon the needs of our project and members.  Members of the CHIPS Alliance receive a number of complementary passes each year\, based upon their membership level. \nDate: April 19\, 2022 at 8 a.m. PT \nSchedule: \n\nWelcome / Opening Remarks: Rob Mains\, CHIPS Alliance\nChisel/FIRRTL Ecosystem Updates: Jack Koenig\, SiFive\nF4PGA Group Kickoff\, Interchange Format: Karol Gugala\, Antmicro\nChiplet Protocol IP: David Kehlet\, Intel\nNIST (Cryo Test Structures): Mehdi Saligane\, UMICH\nNVMe FPGA IP for Edge Applications: Anand Kulkarni\, Western Digital\nUpdate on Shuttle Programs: Tim Ansell\, Google
URL:https://marketingeda.com/event/chips-alliance-spring-event/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/CHIPS-Alliance-April-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220412T090000
DTEND;TZID=America/Los_Angeles:20220412T100000
DTSTAMP:20220411T185919Z
CREATED:20220411T185919Z
LAST-MODIFIED:20220411T185919Z
UID:4531-1649754000-1649757600@marketingeda.com
SUMMARY:The Changing Landscape of Automotive Electronics
DESCRIPTION:The automotive industry is undergoing a seismic shift. Supply chain constraints\, software defined architectures\, functional safety requirements\, and the changing dynamics between OEMs\, Tier 1s and semiconductor companies\, are driving the industry to seek innovative ways to approach new challenges.\nJoin us on Tuesday\, April 12th\, 2022\, for a special panel discussion as we review the changing landscape of automotive electronics. \n\nThe webinar will examine:\n\n\n\nBeyond the current supply demand problem\nThe changing relationships between OEMs\, Tier 1s\, and Semiconductors\nHow can the industry develop a standardization of language?\nHow software defined architecture is changing automotive electronics?\nWhat is the next generation of vehicle architecture?\nAdvanced electronics as a driver for safety profiles\n\nModerator\nGrayson Brulte\nCo-Founder\nBrulte & Company \nPanelists \nDr. Peter Mertens\nAutomotive Industry Veteran and Tech-Investor \nDr. Dean Bushey\nVice President and Head of Environment Business Division (Americas)\nHitachi \nStephen Kosonocky\nSenior Fellow\nUhnder \nGal Carmel\nGM Automotive\nproteanTecs
URL:https://marketingeda.com/event/the-changing-landscape-of-automotive-electronics/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-April-12-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220411T100000
DTEND;TZID=America/New_York:20220412T112000
DTSTAMP:20220401T201126Z
CREATED:20220401T201105Z
LAST-MODIFIED:20220401T201126Z
UID:4492-1649671200-1649762400@marketingeda.com
SUMMARY:Design Automation WebiNar (DAWN)
DESCRIPTION:We are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nDue to the outbreak of coronavirus (COVID-19)\, almost all conferences/symposiums in design automation community are canceled/postponed. People are not able to meet each other\, learn recent advances\, and discuss research ideas. The whole community is quarantined\, just like shrouded in darkness made by COVID-19. Thus\, it is about time to bring the light from inspired scholars in our community and therefore we are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote- and sole-speaker-style webinars\, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. \nApril 11\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – Hardware/Software Co-Exploration of Neural Architectures\n10:20 AM-10:40 AM – BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework\n10:40 AM-11:00 AM – APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors\n11:00 AM-11:20 AM – Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration\n\nApril 12\, 2022 (UTC-4)\n\n10:00 AM-10:20 AM – DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement\n10:20 AM-10:40 AM – TreeNet: Deep Point Cloud Embedding for Routing Tree Construction\n10:40 AM-11:00 AM – Intermittent-Aware Neural Architecture Search\n11:00 AM-11:20 AM – A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
URL:https://marketingeda.com/event/design-automation-webinar-dawn/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/IEEE-April-11-12-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220405T110000
DTEND;TZID=Asia/Jerusalem:20220405T170000
DTSTAMP:20220324T164026Z
CREATED:20220324T164026Z
LAST-MODIFIED:20220324T164026Z
UID:4461-1649156400-1649178000@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:11:00 – 11:30 | ASIC Verification\nVeloce proFPGA: The Perfect Complement for Your System Verification Flow \n11:30 – 12:00 | Emulation Queuing\nEmulation – Getting a Better Return on Your Investment \n12:00 – 12:30 | DFT For Automotive\nDesign-For-Test Design (DFT) Consideration for Automotive Designs \n12:30 – 13:00 | Low-power Vector AI Processing\nIntroducing SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA \n13:00 – 15:00 | Break \n15:00 – 15:30\nTessent Streaming Scan Network (SSN): No-compromise DFT \n15:30 – 16:00 | RISC-V Software Development\nWhy Wait For Hardware to Start RISC-V Software Development? \n16:00 – 16:30 | Design & Verification IP\nMaking MIPI Your Ally \n16:30 – 17:00 | Physical Planning and Timing Closure\nExcellicon Product Portfolio
URL:https://marketingeda.com/event/semisrael-tech-webinar-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-April-5-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220405T080000
DTEND;TZID=America/Los_Angeles:20220407T170000
DTSTAMP:20220301T023630Z
CREATED:20210903T205459Z
LAST-MODIFIED:20220301T023630Z
UID:3257-1649145600-1649350800@marketingeda.com
SUMMARY:DesignCon 2022
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers \nDesignCon is the premier high-speed communications and system design conference\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
URL:https://marketingeda.com/event/designcon-2022/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DesignCon-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20220330T140000
DTEND;TZID=Asia/Tokyo:20220330T143000
DTSTAMP:20220324T162830Z
CREATED:20220324T162830Z
LAST-MODIFIED:20220324T162830Z
UID:4457-1648648800-1648650600@marketingeda.com
SUMMARY:Imperas RISC-V simulation technology with eSol Trinity and NSITEXE
DESCRIPTION:Imperas Software Ltd.\, the leader in RISC-V simulation solutions\, today announced with eSol Trinity the webinar event on RISC-V reference models and simulation technology for the growing adoption of RISC-V in Japan. This webinar will feature a guest speaker – Mr. Marume of NSITEXE Co.\, Ltd.\, a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs\, will introduce an example of using the Imperas RISC-V reference model and simulator. \nRISC-V is an open ISA (Instruction Set Architecture)\, which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra\, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles. \nVirtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors\, as well as user defined custom instructions\, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow. As the project develops to the next phase\, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early software compatibility with the growing ecosystem supporting RISC-V vector extensions. \n  \nWebinar:    ‘Imperas RISC-V reference model and high speed simulation technology’\nWhen:         March 30th 2022\nWhere:        2:00-2:30pm (JST) Live streaming (Zoom) \nFor more information including registration please visit this link.\nAbout Imperas \nFor more information about Imperas\, please see www.imperas.com. Follow Imperas on LinkedIn\, twitter @ImperasSoftware and YouTube. \nAll trademarks or registered trademarks are the property of their respective holders.
URL:https://marketingeda.com/event/imperas-risc-v-simulation-technology-with-esol-trinity-and-nsitexe/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Imperas-March-30-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220330T080000
DTEND;TZID=America/Los_Angeles:20220331T170000
DTSTAMP:20220203T000634Z
CREATED:20220203T000634Z
LAST-MODIFIED:20220203T000634Z
UID:4274-1648627200-1648746000@marketingeda.com
SUMMARY:SNUG - Silicon Valley
DESCRIPTION:SNUG brings together users and technical experts to network and share best practices for tackling design and verification challenges. By attending SNUG\, attendees gain knowledge to use on current projects and discover ideas to spark future innovations. SNUG Silicon Valley will be conducted in a virtual format due to recent COVID-19 developments that have raised concerns among attendees and presenters about assembling in a large group\, and about traveling for conferences. SNUG will still be taking place on March 30-31\, 2022\, and will offer user presentations\, keynote addresses\, panels\, tutorials\, and more. The SNUG team remains committed to delivering an exciting conference\, driven by the always innovative Synopsys community.
URL:https://marketingeda.com/event/snug-silicon-valley/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220330T080000
DTEND;TZID=America/Los_Angeles:20220330T170000
DTSTAMP:20220315T164242Z
CREATED:20220315T164242Z
LAST-MODIFIED:20220315T164242Z
UID:4445-1648627200-1648659600@marketingeda.com
SUMMARY:Secure Your Devices with PUF Plus Hardware Root of Trust
DESCRIPTION:Technology experts from Rambus and Intrinsic ID will discuss how combining PUF technology with a hardware Root of Trust can provide robust security for data and devices. The session will start with the fundamentals of PUFs and example use cases. Then we will discuss how the characteristics of PUFs and a hardware Root of Trust can provide protection against would-be attackers as well as ongoing security over the life of a device. \nFEATURED PRESENTERS\n\n\n\n\n\n\n\n\nDr. Ir. Roel Maes\n\nPrincipal Security Architect\, Intrinsic ID\n\n\n\n\nRoel Maes is the Principal Security Architect at Intrinsic ID where he works on the research\, development and specification of security architectures and solutions for Intrinsic ID’s products and innovations. His technical expertise is focused on…\nFull Profile\n\n\n\n\n\n\n\n\n\n\n\nScott Best\n\nTechnical Director Product Management\, Rambus\n\n\n\n\nScott Best joined Rambus in October 1998 who\, while serving in many and varied technical roles\, has become one of the most prolific inventors in the company’s history. Over the course of his career at Rambus\, he is a named inventor on over 200…\nFull Profile\n\n\n\n\n\n\n\n\n\n\n\nBrandon Lewis\n\nEditor-in-Chief\, Embedded Computing Design\n\n\n\n\nBrandon is a tech journalist and electronics marketer with more than a decade of experience covering the embedded sector. In his current role as Editor-in-Chief of Embedded Computing Design\, he guides the publication’s content strategy\, editorial…\nFull Profile
URL:https://marketingeda.com/event/secure-your-devices-with-puf-plus-hardware-root-of-trust/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-March-30-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220328T080000
DTEND;TZID=America/Los_Angeles:20220330T170000
DTSTAMP:20220128T183820Z
CREATED:20220128T183820Z
LAST-MODIFIED:20220128T183820Z
UID:4241-1648454400-1648659600@marketingeda.com
SUMMARY:tinyML Summit 2022
DESCRIPTION:Registration will open by January 31 \nWhat seemed like a dream a few years ago is quickly turning into reality. Problems which used to require Gigabytes to solve\, became Megabytes and then Kilobytes. Join us at the tinyML Summit 2022 to take part in the sharing\, learning\, and celebrating tinyML. \nWith ever more pervasive advances in technology and algorithms\, tinyML is rapidly becoming a reality. In the tinyML community\, we stand on the shoulders of giants. It is the incredibly open and collaborative nature of ML technology which allows this field to advance so quickly. From its inception in 2019\, the tinyML community has grown tremendously and has benefited greatly by supporting one another. We all hold unique pieces of the puzzle\, but it is through leveraging the collective knowledge of the community that we can move together more quickly. \nIn conjunction with the Summit\, the tinyML Research Symposium 2022 will be held on Monday\, March 28. \n\n\n\n\n\nVenue\n\n\nHyatt Regency San Francisco Airport\n\n1333 Bayshore Highway\, Burlingame\, CA 94010. \n\nRoom Booking\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVENUE & ACCOMMODATIONS \nHyatt Regency San Francisco Airport \nRoom Booking \nThe cut-off date is Monday\, March 7th\, 2022.  After March 7 rooms may still be available but may have a higher prevailing rate. \nPROGRAM PREVIEW\n \nFive sessions have been planned focusing on several different areas related to tinyML. You will be hearing from selectively invited speakers from each area: \nTalk to Me! TinyML opportunities in smart audio\nSession Leader: Chris Rowen\, Cisco \nAudio is a uniquely attractive target for Tiny machine learning. On one hand\, audio\, especially speech\, hosts richly layered information on communication intent\, identity\, location\, emotion and events. On the other hand\, it is densely encoded so this rich diversity of information is surprisingly hard to extract and interpret. Machine Learning methods prove remarkably effective\, opening up countless applications in speech recognition\, event detection\, voice trigger\, speech transformation and generation. The relatively low bit-rates for audio make it possible to capture and process audio in small power budgets\, and the privacy and latency concerns often make it necessary to concentrate audio processing at the edge – a perfect storm for tinyML audio opportunity. \ntinyML Vision: Efficient design of tiny vision models for IoT devices\nSession Leader: Song Han\, MIT \nComputer vision is popular application for tiny machine learning. Many vision applications require real-time\, low-latency processing\, and privacy is a big priority\, thus recognizing the images/videos locally on tiny edge devices has a lot of opportunity. However\, the large computation and memory footprint poses a challenge on these low-power devices\, which goes worse as the resolution requirement gets larger. Opportunities including model compression and neural network and accelerator co-design opens up a larger design space for tiny machine learning for vision\, which has a large market in smart home\, smart factory\, smart driving\, smart healthcare\, and more. \n\n\n\n\ntinySensing: Scaling tinyML solutions with optimized edge sensing capabilities\nSession Leader: Steve Whalley\, tinyML Board of Directors member \nAs more is done on the edge with less power\, code and real estate\, what does this mean for sensor requirements to stay aligned with the explosive tinyML growth? Going beyond popular tinyML applications in camera sensing for vision and MEMS microphones for audio\, will traditional inertial\, environmental\, medical sensing\, etc. capabilities suffice? What new innovations and ‘smart capabilities’ be required to squeeze more performance\, bandwidth\, lower power\, memory\, analog and ASIC capability into edge sensing solutions? Will changes in Machine Learning methods and tools be needed? Will printed sensing\, with the promise of tiny footprints and power\, be the future darling of tinyML? This session will delve into some of the opportunities\, challenges and trends in the tinySensing world and provide a rigorous dialog on what is needed. \ntinyHardware – there’s plenty of room at the bottom\nSession Leader: Francesco Conti\, University of Bologna \ntinyHardware stands at the crossroads between algorithm\, technology\, and architecture. Aggressive algorithmic optimizations such as quantization\, pruning\, and analog computation do not destroy Machine Learning’s capability to decode and interpret information – rather\, they introduce smooth degradations that can often be tolerated. On the other hand\, these optimizations offer a large “attack surface” for emerging technology such as non-volatile memory\, analog in-memory computing\, and innovative chip-to-chip links – as well as for novel architecture in terms of dataflow choices\, sparsity support\, core/memory coupling and caching schemes. Altogether\, these opportunities define a huge design space spanning from low-bitwidth ISA extensions to multi-chip systolic arrays to System-on-Chips with core-coupled in-memory accelerators – a space that we have just started to navigate in the quest to raise system-level energy efficiency of tinyML applications while enabling more complex Tiny applications. \ntinySW/Tools: Enabling tiny experiences for the real-world\nSession Leader: Alessandro Grande\, Edge Impulse \nSoftware and tools specifically designed for tiny machine learning (tinyML) are empowering researchers\, data scientists and embedded engineers to pave the way for a whole new class of experiences. Whereas the focus was initially on creating software and tools to make each step of the process possible — on one hand enabling data scientists to create datasets\, train and optimize models able to run on resource-constrained devices\, on the other hand helping embedded engineers use the models to develop applications capable of efficiently performing inference on the microcontrollers themselves — we are now starting to see a shift towards software and tools that allow scientists and engineers to leverage tinyML in real-world use cases. Opportunities lie in tightly integrated end-to-end platforms\, new data augmentation methods\, performance analysis tools\, as well as optimization tool techniques. This tinySW/Tools session will explore some of the recent advancements in the field\, while uncovering some of the challenges we are facing as an industry. \nAutoTinyML design\nSession Leader: Danilo Pau\, STMicroelectronics \nLatest generation microcontrollers\, sensors\, digital signal processors\, and ultra-low power accelerometers are opening numerous possibilities in compact machine learning (ML) applications with limited storage and power consumption. Now\, the over 10 million C developers of the embedded community are calling for useful productivity tools to support ML pipeline design from the earliest concept and design phases. The tools should automate ML topology design and optimize configuration without requiring developers to craft new solutions for each issue. \nThis session will focus on tools for Automated Tiny ML design and Hyper Parameter Search. Industrial and university experts will discuss the current and next-generation tools for embedding ML in small\, everyday applications. This is an excellent opportunity for attendees to learn how to deploy their models in tiny devices and ramp up ML design productivity.
URL:https://marketingeda.com/event/tinyml-summit-2022/
LOCATION:Hyatt Regecy San Francisco Airport\, 1333 Bayshore Highway\, Burlingame\, CA\, 94010\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/tinyML-Summit-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220322T083000
DTEND;TZID=America/Los_Angeles:20220322T093000
DTSTAMP:20220301T180600Z
CREATED:20220301T180600Z
LAST-MODIFIED:20220301T180600Z
UID:4399-1647937800-1647941400@marketingeda.com
SUMMARY:SecuryzrTM integrated Security Services Platform (iSSP): Services for lifecycle security management
DESCRIPTION:Nowadays\, fleets of connected devices have operational needs to maintain over time a relevant level of security. To mitigate the growing threats and vulnerabilities in the field and protect end-user devices from cyberattacks at both the network and device levels\, a new strategy is needed to filter attacks in real time and implement a centralized protection mechanism for all connected modules. While device-to-device communication remains operational\, a secure cloud-based device manager\, capable of ensuring secure operation throughout the devices’ lifecycle is needed. \nSecuryzrTM integrated Security Services Platform (iSSP) enables the secure provisioning\, deployment and management of a fleet of devices from the cloud. The solution manages heterogeneous fleets of devices with different services: \n\nKey provisioning to securely provision the chip devices with secret key across the supply chain\,\nFirmware Update (FOTA/FUOTA) to securely provide chips with their software and then update them physically or over the air\, to maintain their security level\,\nDevices Monitoring and cyber intelligence to provide a proactive security service\, retrieving cyber security logs from the chips\, analyzing them and sending instructions back to the chip fleet if necessary\,\nDevices Identity to guarantee trust from the chip to the cloud\, to the devices\, users and data through devices multi-factor authentication that allows resistance against impersonation\, replay\, and in the event of an initial compromise.\n\nThis webinar will present Secure-IC’s new solution and associated added-value security services. \nMichel Le Rolland\nProduct Marketing Manager of Secure-IC\nMichel Le Rolland has a master of engineering degree in electronics and computer science from the French “Telecom Bretagne”.\nHe joined Secure-IC in 2016 as R&D engineer in charge of the design of anti-tampering solution. After 3 years of designing HW Secure-IC’s solution\, he is now in charge of the Product Marketing activity for Secure-IC.
URL:https://marketingeda.com/event/securyzrtm-integrated-security-services-platform-issp-services-for-lifecycle-security-management/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Secure-IC-March-22-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220321T080000
DTEND;TZID=America/Los_Angeles:20220324T170000
DTSTAMP:20220128T182927Z
CREATED:20220128T182521Z
LAST-MODIFIED:20220128T182927Z
UID:4235-1647849600-1648141200@marketingeda.com
SUMMARY:GOMACTech 2022
DESCRIPTION:WELCOME TO GOMACTech 2022\nEnabling Distributed Capabilities: Microelectronics Thriving in the Face of Change\n\n\nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \nSECURITY PROCEDURES\nThe GOMACTech Conference is an Unclassified\, Export-Controlled event that requires participants to be U.S. Citizens or legal U.S. Permanent Residents. All registrants\, including presenters and exhibitors\, must provide proof of U.S. Citizenship or Permanent Resident status prior to being permitted entry into the conference. Additionally\, a signed Non-Disclosure Statement will be required. Note that all NDAs must be completed and signed on site.\nYou may prove U.S. citizenship with any of the following:\n• U.S. Passport\n• Birth certificate AND valid government-issued photo ID\n• Naturalization certificate AND valid government-issued photo ID \nThe following are NOT proof of citizenship:\n• Voter registration card\n• Driver’s license
URL:https://marketingeda.com/event/gomactech-2022/
LOCATION:Hyatt Regecy Miami\, 400 South East Second Avenue\, Miami\, FL\, 33131-2197\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GOMACTech-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220316T080000
DTEND;TZID=America/Los_Angeles:20220316T090000
DTSTAMP:20220308T015931Z
CREATED:20220308T015931Z
LAST-MODIFIED:20220308T015931Z
UID:4430-1647417600-1647421200@marketingeda.com
SUMMARY:Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
DESCRIPTION:Automotive microcontrollers for next-generation software-defined vehicles need to deliver higher software capabilities. ST Stellar Integration MCUs offer safe\, secure\, and deterministic solutions for new vehicle architectures. The use of virtual prototypes is a key enabler to solving the emerging\, complex software development challenges throughout the automotive design and test supply chain\, such as feature integration\, functional safety\, and secure communications. \nThis 30-minute Webinar provides an overview of ST Stellar Integration MCU architectures and application domains\, explores how virtual prototypes enable the supply chain\, and includes a discussion on their benefits. Real case studies based on the ST Stellar virtual platform are examined to show how it’s integrated with the automotive tool ecosystem\, such as software debuggers\, plant models\, and network simulators. \nAn audience Q&A follows the technical presentation. \nSpeakers \nKevin Brand\, Senior Manager\, Applications Engineering\, Synopsys \nKevin Brand is a Senior Manager of Applications Engineering at Synopsys. He has been in the field of virtual prototyping for 17 years. With a strong focus on automotive\, Kevin has been working in R&D and\, in more recent years\, directly enabling and deploying virtual prototyping solutions at semiconductor\, Tier 1\, and OEM companies. \nPaul Kinowski\, Product Marketing Manager\, MCUs\, STMicroelectronics \nPaul Kinowski is the Marketing Manager for 32-bit automotive MCUs at STMicroelectronics. He has been working in the field of automotive MCUs for more than 20 years\, as an application engineer and in product marketing\, leading the introduction of popular MCUs for body and gateway applications. Since 2019\, Paul has been responsible for the automotive MCUs product marketing team\, having special focus on STELLAR products.
URL:https://marketingeda.com/event/using-st-stellar-mcu-virtual-prototypes-to-deliver-next-generation-software-defined-vehicles/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-March-16-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220315T110000
DTEND;TZID=America/Los_Angeles:20220315T120000
DTSTAMP:20220217T015416Z
CREATED:20220217T015403Z
LAST-MODIFIED:20220217T015416Z
UID:4332-1647342000-1647345600@marketingeda.com
SUMMARY:Memory Bandwidth Races Higher with HBM3
DESCRIPTION:With the formal release of the HBM3 specification\, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM\, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIn this webinar\, you will learn:\n\nCapabilities of HBM3 memory\nDesign considerations for HBM3 2D/3D implementations\nFeatures of the Rambus HBM3 Memory Interface Subsystem
URL:https://marketingeda.com/event/memory-bandwidth-races-higher-with-hbm3/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-March-15-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T100000
DTEND;TZID=America/Los_Angeles:20220310T110000
DTSTAMP:20220310T025826Z
CREATED:20220310T025826Z
LAST-MODIFIED:20220310T025826Z
UID:4435-1646906400-1646910000@marketingeda.com
SUMMARY:Power Intent Management for Large SoCs
DESCRIPTION:The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area)\, it’s challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. \nDuring this webinar\, we’ll talk about power. Beyond an automated generation of the power intent files before synthesis\, recently Defacto has released key capabilities at the front-end to better manage the power intent. \n• First capability is the promotion of the UPF; Given power intent files for different IPs\, designers have today the ability to assemble UPF files and promote the power intent automatically to the top. \n• The second feature is the other way around called UPF demotion; Given an existing SoC or subsystem\, a designer can extract the power intent file. \nMore precisely\, during this webinar our experts will cover a complete power intent management methodology with a particular focus on integration needs pre-synthesis: how to generate UPF from scratch\, update the UPF after design changes\, demote UPF for reuse purpose and promote the UPF based on the integration. \nAUDIENCE:\nCAD Manager\, Architects\, CAD Engineer\, Designers\, Integration teams\, Verification teams and UPF experts! S \nPEAKERS:\n• Chouki Aktouf: CTO at Defacto • Arthur Kalsing: Senior R&D engineer at Defacto & UPF Expert
URL:https://marketingeda.com/event/power-intent-management-for-large-socs/
LOCATION:Defacto Techologie\, 2 rue Emile Augier\, Grenoble\, France
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-March-10-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T090000
DTEND;TZID=America/Los_Angeles:20220310T100000
DTSTAMP:20220223T170626Z
CREATED:20220223T170626Z
LAST-MODIFIED:20220223T170626Z
UID:4356-1646902800-1646906400@marketingeda.com
SUMMARY:Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
DESCRIPTION:• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?\n• Do you need to size the AI accelerator for existing and future AI requirements?\n• Would it be beneficial if you knew the latency advantage between ARM\, RISC\, DSP and Accelerator in deploying AI tasks? \nThis webinar focuses on design teams transitioning to an AI accelerator in their next-generation SoC processor. In the webinar\, we will use VisualSim system-level modeling and hardware-software partitioning technology in migrating an algorithm to an AI accelerator. The SoC architecture will be tested for a variety of workloads and use-cases. The new VisualSim Insight methodology will be deployed to track the requirements through SoC planning\, design\, validation and testing. The generated diagnostics and metrics will be used to make decisions on the right AI accelerator configuration. \nAI accelerators can be built with a variety of configurations- single vs. multi-core\, 2 or 3 level caches\, Network-on-Chip (NoC) vs. AMBA AXI bus\, or LPDDR vs. DDR5. At the same time\, the task partitioning can be based on lowest power\, latency\, memory throughput\, or smallest size of each IP block. Join this webinar to understand the power\, sizing and latency advantages obtained through AI Accelerators. \nSpeaker:\nTom Jose is a Research & Development Engineer at Mirabilis Design. A System Design Architect & Trainer\, he supports companies and universities to build their own design. He has published three papers – RISC-V & ARM processor comparison at the RISC-V international conference\, Using AI for optimal Time Sensitive Networking in Avionics & Functional Safety for Braking System through ISO 26262\, and Operating System Security and DO 254. He has worked with the micro architecture design of processor pipeline stages\, instruction implementation\, verification and workload partitioning. \nThis webinar is in partnership with SemiWiki and Mirabilis Design.
URL:https://marketingeda.com/event/balancing-performance-and-power-in-adding-ai-accelerators-to-system-on-chip-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/MIrabilis-March-10-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T080000
DTEND;TZID=America/Los_Angeles:20220310T090000
DTSTAMP:20220222T173510Z
CREATED:20220222T173510Z
LAST-MODIFIED:20220222T173510Z
UID:4349-1646899200-1646902800@marketingeda.com
SUMMARY:Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
DESCRIPTION:Audiovisual experiences in XR\, gaming\, movies\, and concerts can all be enhanced with spatial audio experience immersive technology. A superior spatial audio experience occurs when you combine headphones\, with wearable head tracking\, and on-device processing. Believe it or not\, despite the recent wide adoption of Spatial/3D Audio\, the concept and technology have been around for a while. However\, the technology behind it has advanced significantly as the industry continues to make strides in computing and cost. \nIn this webinar\, we begin by discussing the fundamental concepts of binaural spatial audio and their core principles of operation. We expose the key spatial audio processing and head tracking challenges to creating an effective system. We will offer solutions to these challenges on the way to creating a robust\, complete Spatial Audio experience. Finally\, we will close by introducing an available reference design that combines these\, as well as some upcoming improvements. \nJoin CEVA and VisiSonics experts to learn about: \n\nWhat is Spatial/3D Audio\nHow does Spatial/3D Audio work\nWhat are the technical challenges to implementing an effective Spatial/3D Audio system\nWhy is head tracking so important to Spatial/3D Audio\nHow can the technical challenges be addressed to provide a robust\, complete solution\n\n\nTarget Audience\nAudio system engineers and product managers targeting audio enabled devices\, that are looking to add 3D Audio capabilities to Hearables\, Smart Home\, Mobile\, and Automotive products.\n\nSpeakers\n\nBryan Cook\nSenior Team Leader\, Algorithm Software\, CEVA Inc.\n\n\n\nRamani Duraiswami\nCEO and Founder\, VisiSonics
URL:https://marketingeda.com/event/spatial-audio-what-it-is-and-how-to-overcome-its-unique-challenges-to-provide-a-complete-solution/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA.-March-10-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220224T170000
DTEND;TZID=America/Los_Angeles:20220224T180000
DTSTAMP:20220221T220207Z
CREATED:20220221T220124Z
LAST-MODIFIED:20220221T220207Z
UID:4345-1645722000-1645725600@marketingeda.com
SUMMARY:Securing the Future with RISC-V
DESCRIPTION:While the metaverse took the spotlight at the recent CES\, it is made possible with advancement in computation and connectivity\, which also empower many other aspects of people’s lives from IoT\, Automotive\, and to all kinds of applications around us. \nWhile Andes RISC-V has continued to enable innovations in all emerging applications\, security in modern SoC design is becoming much more essential. \nIn this joint webinar\, PUFsecurity and Andes will discuss how to best address security design with Andes RISC-V architecture and share some common pitfalls to avoid.
URL:https://marketingeda.com/event/securing-the-future-with-risc-v/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Andes-February-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220223T090000
DTEND;TZID=America/Los_Angeles:20220223T100000
DTSTAMP:20220217T172213Z
CREATED:20220217T172213Z
LAST-MODIFIED:20220217T172213Z
UID:4336-1645606800-1645610400@marketingeda.com
SUMMARY:The Role of PUFs in a Trusted Supply Chain
DESCRIPTION:Trusted supply chain provenance and traceability is becoming increasingly important for the quality\, reliability\, and security of electronic products. It can help reduce costs for tracking and fixing field issues\, minimize liability risks and enable higher value in connected IoT applications. In addition\, there are significant efficiencies and cost reductions that could be enabled in the procurement process for many integrators. In this PUF Cafe Episode\, Tom will explain what the roles of trusted identities and PUF technology are in a trusted supply chain.
URL:https://marketingeda.com/event/the-role-of-pufs-in-a-trusted-supply-chain/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Itrinsic-ID-February-23-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220222T090000
DTEND;TZID=Asia/Jerusalem:20220222T180000
DTSTAMP:20220210T171059Z
CREATED:20220210T171059Z
LAST-MODIFIED:20220210T171059Z
UID:4310-1645520400-1645552800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:SemIsrael Expo is the premier professional semiconductor event in Israel.\nThe event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry.\nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities. \n\nThe event will be hosted at Avenue Convention and Events Center on December 13\, 2021. \nSemIsrael Expo events are produced by SemIsrael – The Israeli Semiconductor Portal.
URL:https://marketingeda.com/event/semisrael-tech-webinar/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220215T100000
DTEND;TZID=America/Los_Angeles:20220215T110000
DTSTAMP:20220211T225528Z
CREATED:20220211T225528Z
LAST-MODIFIED:20220211T225528Z
UID:4321-1644919200-1644922800@marketingeda.com
SUMMARY:Optimized Chip Design with Main Processors and AI Accelerators
DESCRIPTION:Presented by\nPaul Karazuba\, VP of Marketing\, Expedera & John Min\, Director of Field Application Engineering\, Andes Technology \n\n\nAbout this talk\nAs AI capability is beginning large-scale deployment into edge devices\, many wonder about the decision to use a specialized AI accelerator\, rather than simply using the systems main processor. In this first of two webinars on the topic\, Paul Karazuba\, VP of Marketing at Expedera\, and John Min\, Director of Field Application Engineering at Andes Technology\, will explore the state of the art of CPUs and AI processing\, and examine why leading semiconductor companies are adopting hybrid core architecture that combines a main processor with a specialized AI processor.
URL:https://marketingeda.com/event/optimized-chip-design-with-main-processors-and-ai-accelerators/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Andes-Feb-15-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220210T100000
DTEND;TZID=America/Los_Angeles:20220210T103000
DTSTAMP:20220127T184724Z
CREATED:20220127T184724Z
LAST-MODIFIED:20220127T184724Z
UID:4232-1644487200-1644489000@marketingeda.com
SUMMARY:Managing the Complexity of FinFET Standard Cell Layout with Cello
DESCRIPTION:FinFET technologies have enabled designs with increased density and performance while reducing power\, when compared to MOSFET. However\, this comes at a cost of increased design complexity. Not only are some undesirable layout dependent effects more pronounced\, but design rules have become much more complex. Many design rules violations can no longer be fixed within a local scope\, since they may span a large region of a standard-cell and involve several polygons. \nIn this webinar we are going to review some of the most challenging aspects of FinFET standard-cell layout design\, and how Silvaco’s Cello tool can be used to address these issues. \nWhat You Will Learn\n\nFinFET overview and application\nFinFET layout design\nUsing Cello for FinFET design and implementation\n\n\n\n\n\n\nPresenter\n\n\n\n\nOsvaldo Martinello is the Sr. R&D Director for the Foundation IP group at Silvaco\, in Santa Clara\, California\, where he leads the development of tools for IP design and optimization. He holds a Computer Engineering degree and a Computer Science MSc\, both received from UFRGS\, in Porto Alegre\, Brazil. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nIP\, Circuit\, CAD\, SoC and System design engineers\, product managers and engineering management.
URL:https://marketingeda.com/event/managing-the-complexity-of-finfet-standard-cell-layout-with-cello/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Silvaco-February-10-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220202T090000
DTEND;TZID=America/Los_Angeles:20220202T110000
DTSTAMP:20220113T183152Z
CREATED:20220113T183152Z
LAST-MODIFIED:20220113T183152Z
UID:4186-1643792400-1643799600@marketingeda.com
SUMMARY:ASIP Virtual Seminar 2022
DESCRIPTION:Extending RISC Processors into Flexible Accelerators using ASIP Designer\n\n\nCase Studies in Artificial Intelligence and Image Signal Processing \n\n\n\n\n\n\n\n\n\n\n\nThe slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  Maintaining a RISC-V ISA baseline facilitates compatibility with and reuse of existing processor ecosystem elements. \nSynopsys’ ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop and synthesis-in-the-loop methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study\, by the University of Virginia\, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms\, combining TVM and ASIP Designer.  Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.  The second case study\, by Synopsys\, shows an accelerator for image signal processing.  A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.
URL:https://marketingeda.com/event/asip-virtual-seminar-2022/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-February-2-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220127T100000
DTEND;TZID=America/Los_Angeles:20220127T110000
DTSTAMP:20220105T173206Z
CREATED:20220105T173206Z
LAST-MODIFIED:20220105T173206Z
UID:4150-1643277600-1643281200@marketingeda.com
SUMMARY:Boost Your CXL Verification from IP to System Level
DESCRIPTION:Register now for this CadenceTECHTALK\, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using the Cadence® Verification IP (VIP) solution for advanced verification methodologies. \nSpecifically\, this webinar will cover following topics: \n\nGrowing market needs for CXL\nVerification challenges of CXL designs\nSolution for IP-level verification\nSystem-level verification in simulation and emulation\n\nSessions \nEMEA and India\nThursday\, January 27\, 2022\n9:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST \nNorth America\nThursday\, January 27\, 2022\n10:00am PT / 1:00pm ET
URL:https://marketingeda.com/event/boost-your-cxl-verification-from-ip-to-system-level/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-CXL-January-27-2002.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211216T100000
DTEND;TZID=America/Los_Angeles:20211216T110000
DTSTAMP:20211210T212305Z
CREATED:20211210T212305Z
LAST-MODIFIED:20211210T212305Z
UID:3804-1639648800-1639652400@marketingeda.com
SUMMARY:How to Overcome the Pain Points of AI/ML Hardware Design
DESCRIPTION:Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event\nAI/ML hardware faces three common pain points: memory bandwidth\, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip\, GDDR6 memory interfaces and high performance machine learning processors\, which present new capabilities to alleviate these pain points and offer a balance of speed\, power and cost. \nIn this webinar\, you will learn: \n\nTop trends in data generation\nThree challenges in processing data with AI/ML hardware solutions\nHow FPGA architectures can overcome data processing challenges\nFeatured example: How to achieve 60 TOPS in Speedster®7t FPGAs\n\nJoin the webinar to find out why FPGAs and embedded FPGA (eFPGA) IP are ideal platforms for AI/ML inferencing solutions that provide the flexibility of a GPU while performing at ASIC-like speeds.
URL:https://marketingeda.com/event/how-to-overcome-the-pain-points-of-ai-ml-hardware-design/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/November___Achronix_Posts.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211208T100000
DTEND;TZID=America/Los_Angeles:20211208T110000
DTSTAMP:20211130T072046Z
CREATED:20211129T233007Z
LAST-MODIFIED:20211130T072046Z
UID:3773-1638957600-1638961200@marketingeda.com
SUMMARY:PCIe 6.0 From IP to Interconnect in High-Performance Computing
DESCRIPTION:ABSTRACT: \nPCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center\, cloud and AI edge continue to increase in speed and density. System architects\, SoC designers\, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. \nIn this webinar\, technical experts from Synopsys and Samtec will discuss the latest developments in next-generation PCIe 6.0 solutions and demonstrate interoperable technology from IP to interconnect in HPC. Additionally\, practical signal channel design techniques and connectivity options will be highlighted. \nPRESENTERS: \nMadhumita Sanyal \nSynopsys\, Sr. Staff Technical Marketing Manager Madhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products\, logic libraries\, embedded memories\, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business. \nMatthew Burns \nSamtec\, Technical Marketing Manager Matthew Burns develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years\, he has been a leader in design\, technical sales and marketing in the telecommunications\, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University. *This webinar is in partnership with SemiWiki\, Samtec\, and Synopsys
URL:https://marketingeda.com/event/pcie-6-0-from-ip-to-interconnect-in-high-performance-computing/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/synopsys-december-8-2021.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211205T080000
DTEND;TZID=America/Los_Angeles:20211210T170000
DTSTAMP:20210903T183636Z
CREATED:20210903T183636Z
LAST-MODIFIED:20210903T183636Z
UID:3194-1638691200-1639155600@marketingeda.com
SUMMARY:58th Design Automation Conference
DESCRIPTION:The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits.\nDAC focuses on the latest methodologies and technology advancements in electronic design.\nThe 58th DAC will bring together researchers\, designers\, practitioners\, tool developers\, students and vendors.
URL:https://marketingeda.com/event/58th-design-automation-conference/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP,Workshop
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/58dac.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211202T090000
DTEND;TZID=America/Los_Angeles:20211202T100000
DTSTAMP:20211112T052726Z
CREATED:20211112T052726Z
LAST-MODIFIED:20211112T052726Z
UID:3718-1638435600-1638439200@marketingeda.com
SUMMARY:How to Sign Off a 10 Billion+ Transistor Design in the Cloud
DESCRIPTION:Advanced semiconductor applications such as artificial intelligence / machine learning (AI/ML) and graphic processing units (GPUs) fully leverage dense\, advanced-node technology to push the extreme limits of design size. To signoff such large designs\, engineers are increasingly relying on distributed compute methods to accelerate the signoff analysis. Furthermore\, given lack of scalability of on-premises compute resources\, designers are migrating towards cloud-based solutions to solve their peak compute demand and meet their aggressive tapeout schedules. \nIn this CadenceTECHTALK\, TSMC + Microsoft + Cadence will present a signoff methodology optimized for giga-scale class (10 billion+ transistor) designs and tailored for execution on cloud-based infrastructure. The talk will feature the Cadence® Tempus™ Timing Signoff Solution’s STA signoff tool and CloudBurst™ platform\, as well as Microsoft Azure’s latest offerings suited for EDA workloads. \n\n\n\n\n\nFeatured Speakers \n\n\n\n\n\n\n\n\n\n\nVivian Jiang & Kurt Chiang\,\nTechnical Managers\,\nTSMC \n\n\n\n\n\n\n\n\nBrandon Bautz\, Sr. Group Director Product Management\, Cadence \n\n\n\n\n\n\n\n\nPrashant Varshney\, Sr. Director Product Management\, Microsoft \n\n\n\n\n\n\n\n\nKetan Joshi\, Group Director\, Cloud Business Development\, Cadence
URL:https://marketingeda.com/event/how-to-sign-off-a-10-billion-transistor-design-in-the-cloud/
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211201T080000
DTEND;TZID=America/Los_Angeles:20211202T170000
DTSTAMP:20211130T072557Z
CREATED:20211130T072557Z
LAST-MODIFIED:20211130T072557Z
UID:3776-1638345600-1638464400@marketingeda.com
SUMMARY:IP-SoC Conference 21
DESCRIPTION:IP-SoC 2021 will be the 24th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts in all the design track from Foundry\, technology\, design methodology to EDA tools share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nWarning: \n– To enter the physical or virtual event\, you need:\n• to be registered.\n– To enter the physical\, you need:\n• to show your proof of vaccination or “pass sanitaire”. Masks are mandatory except at the lunch table.
URL:https://marketingeda.com/event/ip-soc-conference-21/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Design-Reuse.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211117T100000
DTEND;TZID=America/Los_Angeles:20211117T170000
DTSTAMP:20211112T184020Z
CREATED:20211112T184020Z
LAST-MODIFIED:20211112T184020Z
UID:3735-1637143200-1637168400@marketingeda.com
SUMMARY:Samsung SAFE Forum 2021
DESCRIPTION:Join us for Samsung Foundry’s annual SAFE™ Forum. \nWhat will you take away from Samsung Foundry’s ecosystem event? Bump your SoC PPA knowledge with the latest information on: \nHigh speed interconnect IPs for HPC and Data Center applications and foundational IPs\nHigh bandwidth memory subsystems\nKey IP trends for automotive and mobile applications\nFoundational Analog Mixed Signal IP for a variety of applications\nThere will also be an opportunity to network with experts in IP\, EDA\, Cloud\, Design Services and Packaging during the virtual partner pavilion. \nRegister today! Participate to join the raffle for exciting prizes! \n– SAFE Forum Team
URL:https://marketingeda.com/event/samsung-safe-forum-2021/
CATEGORIES:Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAFE-2021.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211117T100000
DTEND;TZID=America/Los_Angeles:20211117T110000
DTSTAMP:20211104T190551Z
CREATED:20211104T190551Z
LAST-MODIFIED:20211104T190551Z
UID:3608-1637143200-1637146800@marketingeda.com
SUMMARY:CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
DESCRIPTION:Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power\, energy\, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. \nIn this CadenceTECHTALK\, you will learn how to: \n\nAddress the challenges of accelerating power and system-level verification in a pre-silicon emulated design flow using Cadence® Tensilica® IP\nExplore architecture usability with Tensilica IP with actual hardware and software implementation\nCreate an efficient environment to make energy-aware tradeoffs with accurate implementation characterization data\n\nDate and Time\nWednesday\, November 17\, 2021\n10:00am PST / 1:00pm EST
URL:https://marketingeda.com/event/cadencetechtalk-power-and-energy-optimization-using-tensilica-ip/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-17.jpg
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