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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220315T110000
DTEND;TZID=America/Los_Angeles:20220315T120000
DTSTAMP:20220217T015416Z
CREATED:20220217T015403Z
LAST-MODIFIED:20220217T015416Z
UID:4332-1647342000-1647345600@marketingeda.com
SUMMARY:Memory Bandwidth Races Higher with HBM3
DESCRIPTION:With the formal release of the HBM3 specification\, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM\, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIn this webinar\, you will learn:\n\nCapabilities of HBM3 memory\nDesign considerations for HBM3 2D/3D implementations\nFeatures of the Rambus HBM3 Memory Interface Subsystem
URL:https://marketingeda.com/event/memory-bandwidth-races-higher-with-hbm3/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-March-15-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T100000
DTEND;TZID=America/Los_Angeles:20220310T110000
DTSTAMP:20220310T025826Z
CREATED:20220310T025826Z
LAST-MODIFIED:20220310T025826Z
UID:4435-1646906400-1646910000@marketingeda.com
SUMMARY:Power Intent Management for Large SoCs
DESCRIPTION:The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area)\, it’s challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. \nDuring this webinar\, we’ll talk about power. Beyond an automated generation of the power intent files before synthesis\, recently Defacto has released key capabilities at the front-end to better manage the power intent. \n• First capability is the promotion of the UPF; Given power intent files for different IPs\, designers have today the ability to assemble UPF files and promote the power intent automatically to the top. \n• The second feature is the other way around called UPF demotion; Given an existing SoC or subsystem\, a designer can extract the power intent file. \nMore precisely\, during this webinar our experts will cover a complete power intent management methodology with a particular focus on integration needs pre-synthesis: how to generate UPF from scratch\, update the UPF after design changes\, demote UPF for reuse purpose and promote the UPF based on the integration. \nAUDIENCE:\nCAD Manager\, Architects\, CAD Engineer\, Designers\, Integration teams\, Verification teams and UPF experts! S \nPEAKERS:\n• Chouki Aktouf: CTO at Defacto • Arthur Kalsing: Senior R&D engineer at Defacto & UPF Expert
URL:https://marketingeda.com/event/power-intent-management-for-large-socs/
LOCATION:Defacto Techologie\, 2 rue Emile Augier\, Grenoble\, France
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-March-10-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T090000
DTEND;TZID=America/Los_Angeles:20220310T100000
DTSTAMP:20220223T170626Z
CREATED:20220223T170626Z
LAST-MODIFIED:20220223T170626Z
UID:4356-1646902800-1646906400@marketingeda.com
SUMMARY:Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
DESCRIPTION:• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?\n• Do you need to size the AI accelerator for existing and future AI requirements?\n• Would it be beneficial if you knew the latency advantage between ARM\, RISC\, DSP and Accelerator in deploying AI tasks? \nThis webinar focuses on design teams transitioning to an AI accelerator in their next-generation SoC processor. In the webinar\, we will use VisualSim system-level modeling and hardware-software partitioning technology in migrating an algorithm to an AI accelerator. The SoC architecture will be tested for a variety of workloads and use-cases. The new VisualSim Insight methodology will be deployed to track the requirements through SoC planning\, design\, validation and testing. The generated diagnostics and metrics will be used to make decisions on the right AI accelerator configuration. \nAI accelerators can be built with a variety of configurations- single vs. multi-core\, 2 or 3 level caches\, Network-on-Chip (NoC) vs. AMBA AXI bus\, or LPDDR vs. DDR5. At the same time\, the task partitioning can be based on lowest power\, latency\, memory throughput\, or smallest size of each IP block. Join this webinar to understand the power\, sizing and latency advantages obtained through AI Accelerators. \nSpeaker:\nTom Jose is a Research & Development Engineer at Mirabilis Design. A System Design Architect & Trainer\, he supports companies and universities to build their own design. He has published three papers – RISC-V & ARM processor comparison at the RISC-V international conference\, Using AI for optimal Time Sensitive Networking in Avionics & Functional Safety for Braking System through ISO 26262\, and Operating System Security and DO 254. He has worked with the micro architecture design of processor pipeline stages\, instruction implementation\, verification and workload partitioning. \nThis webinar is in partnership with SemiWiki and Mirabilis Design.
URL:https://marketingeda.com/event/balancing-performance-and-power-in-adding-ai-accelerators-to-system-on-chip-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/MIrabilis-March-10-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220310T080000
DTEND;TZID=America/Los_Angeles:20220310T090000
DTSTAMP:20220222T173510Z
CREATED:20220222T173510Z
LAST-MODIFIED:20220222T173510Z
UID:4349-1646899200-1646902800@marketingeda.com
SUMMARY:Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
DESCRIPTION:Audiovisual experiences in XR\, gaming\, movies\, and concerts can all be enhanced with spatial audio experience immersive technology. A superior spatial audio experience occurs when you combine headphones\, with wearable head tracking\, and on-device processing. Believe it or not\, despite the recent wide adoption of Spatial/3D Audio\, the concept and technology have been around for a while. However\, the technology behind it has advanced significantly as the industry continues to make strides in computing and cost. \nIn this webinar\, we begin by discussing the fundamental concepts of binaural spatial audio and their core principles of operation. We expose the key spatial audio processing and head tracking challenges to creating an effective system. We will offer solutions to these challenges on the way to creating a robust\, complete Spatial Audio experience. Finally\, we will close by introducing an available reference design that combines these\, as well as some upcoming improvements. \nJoin CEVA and VisiSonics experts to learn about: \n\nWhat is Spatial/3D Audio\nHow does Spatial/3D Audio work\nWhat are the technical challenges to implementing an effective Spatial/3D Audio system\nWhy is head tracking so important to Spatial/3D Audio\nHow can the technical challenges be addressed to provide a robust\, complete solution\n\n\nTarget Audience\nAudio system engineers and product managers targeting audio enabled devices\, that are looking to add 3D Audio capabilities to Hearables\, Smart Home\, Mobile\, and Automotive products.\n\nSpeakers\n\nBryan Cook\nSenior Team Leader\, Algorithm Software\, CEVA Inc.\n\n\n\nRamani Duraiswami\nCEO and Founder\, VisiSonics
URL:https://marketingeda.com/event/spatial-audio-what-it-is-and-how-to-overcome-its-unique-challenges-to-provide-a-complete-solution/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA.-March-10-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220224T170000
DTEND;TZID=America/Los_Angeles:20220224T180000
DTSTAMP:20220221T220207Z
CREATED:20220221T220124Z
LAST-MODIFIED:20220221T220207Z
UID:4345-1645722000-1645725600@marketingeda.com
SUMMARY:Securing the Future with RISC-V
DESCRIPTION:While the metaverse took the spotlight at the recent CES\, it is made possible with advancement in computation and connectivity\, which also empower many other aspects of people’s lives from IoT\, Automotive\, and to all kinds of applications around us. \nWhile Andes RISC-V has continued to enable innovations in all emerging applications\, security in modern SoC design is becoming much more essential. \nIn this joint webinar\, PUFsecurity and Andes will discuss how to best address security design with Andes RISC-V architecture and share some common pitfalls to avoid.
URL:https://marketingeda.com/event/securing-the-future-with-risc-v/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Andes-February-24-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220223T090000
DTEND;TZID=America/Los_Angeles:20220223T100000
DTSTAMP:20220217T172213Z
CREATED:20220217T172213Z
LAST-MODIFIED:20220217T172213Z
UID:4336-1645606800-1645610400@marketingeda.com
SUMMARY:The Role of PUFs in a Trusted Supply Chain
DESCRIPTION:Trusted supply chain provenance and traceability is becoming increasingly important for the quality\, reliability\, and security of electronic products. It can help reduce costs for tracking and fixing field issues\, minimize liability risks and enable higher value in connected IoT applications. In addition\, there are significant efficiencies and cost reductions that could be enabled in the procurement process for many integrators. In this PUF Cafe Episode\, Tom will explain what the roles of trusted identities and PUF technology are in a trusted supply chain.
URL:https://marketingeda.com/event/the-role-of-pufs-in-a-trusted-supply-chain/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Itrinsic-ID-February-23-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20220222T090000
DTEND;TZID=Asia/Jerusalem:20220222T180000
DTSTAMP:20220210T171059Z
CREATED:20220210T171059Z
LAST-MODIFIED:20220210T171059Z
UID:4310-1645520400-1645552800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:SemIsrael Expo is the premier professional semiconductor event in Israel.\nThe event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry.\nThe Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups\, local R&D offices of multinationals and IDMs\, foundries\, design houses\, labs and universities. \n\nThe event will be hosted at Avenue Convention and Events Center on December 13\, 2021. \nSemIsrael Expo events are produced by SemIsrael – The Israeli Semiconductor Portal.
URL:https://marketingeda.com/event/semisrael-tech-webinar/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220215T100000
DTEND;TZID=America/Los_Angeles:20220215T110000
DTSTAMP:20220211T225528Z
CREATED:20220211T225528Z
LAST-MODIFIED:20220211T225528Z
UID:4321-1644919200-1644922800@marketingeda.com
SUMMARY:Optimized Chip Design with Main Processors and AI Accelerators
DESCRIPTION:Presented by\nPaul Karazuba\, VP of Marketing\, Expedera & John Min\, Director of Field Application Engineering\, Andes Technology \n\n\nAbout this talk\nAs AI capability is beginning large-scale deployment into edge devices\, many wonder about the decision to use a specialized AI accelerator\, rather than simply using the systems main processor. In this first of two webinars on the topic\, Paul Karazuba\, VP of Marketing at Expedera\, and John Min\, Director of Field Application Engineering at Andes Technology\, will explore the state of the art of CPUs and AI processing\, and examine why leading semiconductor companies are adopting hybrid core architecture that combines a main processor with a specialized AI processor.
URL:https://marketingeda.com/event/optimized-chip-design-with-main-processors-and-ai-accelerators/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Andes-Feb-15-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220210T100000
DTEND;TZID=America/Los_Angeles:20220210T103000
DTSTAMP:20220127T184724Z
CREATED:20220127T184724Z
LAST-MODIFIED:20220127T184724Z
UID:4232-1644487200-1644489000@marketingeda.com
SUMMARY:Managing the Complexity of FinFET Standard Cell Layout with Cello
DESCRIPTION:FinFET technologies have enabled designs with increased density and performance while reducing power\, when compared to MOSFET. However\, this comes at a cost of increased design complexity. Not only are some undesirable layout dependent effects more pronounced\, but design rules have become much more complex. Many design rules violations can no longer be fixed within a local scope\, since they may span a large region of a standard-cell and involve several polygons. \nIn this webinar we are going to review some of the most challenging aspects of FinFET standard-cell layout design\, and how Silvaco’s Cello tool can be used to address these issues. \nWhat You Will Learn\n\nFinFET overview and application\nFinFET layout design\nUsing Cello for FinFET design and implementation\n\n\n\n\n\n\nPresenter\n\n\n\n\nOsvaldo Martinello is the Sr. R&D Director for the Foundation IP group at Silvaco\, in Santa Clara\, California\, where he leads the development of tools for IP design and optimization. He holds a Computer Engineering degree and a Computer Science MSc\, both received from UFRGS\, in Porto Alegre\, Brazil. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nIP\, Circuit\, CAD\, SoC and System design engineers\, product managers and engineering management.
URL:https://marketingeda.com/event/managing-the-complexity-of-finfet-standard-cell-layout-with-cello/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Silvaco-February-10-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220202T090000
DTEND;TZID=America/Los_Angeles:20220202T110000
DTSTAMP:20220113T183152Z
CREATED:20220113T183152Z
LAST-MODIFIED:20220113T183152Z
UID:4186-1643792400-1643799600@marketingeda.com
SUMMARY:ASIP Virtual Seminar 2022
DESCRIPTION:Extending RISC Processors into Flexible Accelerators using ASIP Designer\n\n\nCase Studies in Artificial Intelligence and Image Signal Processing \n\n\n\n\n\n\n\n\n\n\n\nThe slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  Maintaining a RISC-V ISA baseline facilitates compatibility with and reuse of existing processor ecosystem elements. \nSynopsys’ ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop and synthesis-in-the-loop methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study\, by the University of Virginia\, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms\, combining TVM and ASIP Designer.  Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.  The second case study\, by Synopsys\, shows an accelerator for image signal processing.  A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.
URL:https://marketingeda.com/event/asip-virtual-seminar-2022/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-February-2-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220127T100000
DTEND;TZID=America/Los_Angeles:20220127T110000
DTSTAMP:20220105T173206Z
CREATED:20220105T173206Z
LAST-MODIFIED:20220105T173206Z
UID:4150-1643277600-1643281200@marketingeda.com
SUMMARY:Boost Your CXL Verification from IP to System Level
DESCRIPTION:Register now for this CadenceTECHTALK\, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using the Cadence® Verification IP (VIP) solution for advanced verification methodologies. \nSpecifically\, this webinar will cover following topics: \n\nGrowing market needs for CXL\nVerification challenges of CXL designs\nSolution for IP-level verification\nSystem-level verification in simulation and emulation\n\nSessions \nEMEA and India\nThursday\, January 27\, 2022\n9:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST \nNorth America\nThursday\, January 27\, 2022\n10:00am PT / 1:00pm ET
URL:https://marketingeda.com/event/boost-your-cxl-verification-from-ip-to-system-level/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-CXL-January-27-2002.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211216T100000
DTEND;TZID=America/Los_Angeles:20211216T110000
DTSTAMP:20211210T212305Z
CREATED:20211210T212305Z
LAST-MODIFIED:20211210T212305Z
UID:3804-1639648800-1639652400@marketingeda.com
SUMMARY:How to Overcome the Pain Points of AI/ML Hardware Design
DESCRIPTION:Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event\nAI/ML hardware faces three common pain points: memory bandwidth\, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip\, GDDR6 memory interfaces and high performance machine learning processors\, which present new capabilities to alleviate these pain points and offer a balance of speed\, power and cost. \nIn this webinar\, you will learn: \n\nTop trends in data generation\nThree challenges in processing data with AI/ML hardware solutions\nHow FPGA architectures can overcome data processing challenges\nFeatured example: How to achieve 60 TOPS in Speedster®7t FPGAs\n\nJoin the webinar to find out why FPGAs and embedded FPGA (eFPGA) IP are ideal platforms for AI/ML inferencing solutions that provide the flexibility of a GPU while performing at ASIC-like speeds.
URL:https://marketingeda.com/event/how-to-overcome-the-pain-points-of-ai-ml-hardware-design/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/November___Achronix_Posts.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211208T100000
DTEND;TZID=America/Los_Angeles:20211208T110000
DTSTAMP:20211130T072046Z
CREATED:20211129T233007Z
LAST-MODIFIED:20211130T072046Z
UID:3773-1638957600-1638961200@marketingeda.com
SUMMARY:PCIe 6.0 From IP to Interconnect in High-Performance Computing
DESCRIPTION:ABSTRACT: \nPCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center\, cloud and AI edge continue to increase in speed and density. System architects\, SoC designers\, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. \nIn this webinar\, technical experts from Synopsys and Samtec will discuss the latest developments in next-generation PCIe 6.0 solutions and demonstrate interoperable technology from IP to interconnect in HPC. Additionally\, practical signal channel design techniques and connectivity options will be highlighted. \nPRESENTERS: \nMadhumita Sanyal \nSynopsys\, Sr. Staff Technical Marketing Manager Madhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products\, logic libraries\, embedded memories\, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business. \nMatthew Burns \nSamtec\, Technical Marketing Manager Matthew Burns develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years\, he has been a leader in design\, technical sales and marketing in the telecommunications\, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University. *This webinar is in partnership with SemiWiki\, Samtec\, and Synopsys
URL:https://marketingeda.com/event/pcie-6-0-from-ip-to-interconnect-in-high-performance-computing/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/synopsys-december-8-2021.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211205T080000
DTEND;TZID=America/Los_Angeles:20211210T170000
DTSTAMP:20210903T183636Z
CREATED:20210903T183636Z
LAST-MODIFIED:20210903T183636Z
UID:3194-1638691200-1639155600@marketingeda.com
SUMMARY:58th Design Automation Conference
DESCRIPTION:The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits.\nDAC focuses on the latest methodologies and technology advancements in electronic design.\nThe 58th DAC will bring together researchers\, designers\, practitioners\, tool developers\, students and vendors.
URL:https://marketingeda.com/event/58th-design-automation-conference/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP,Workshop
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/58dac.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211202T090000
DTEND;TZID=America/Los_Angeles:20211202T100000
DTSTAMP:20211112T052726Z
CREATED:20211112T052726Z
LAST-MODIFIED:20211112T052726Z
UID:3718-1638435600-1638439200@marketingeda.com
SUMMARY:How to Sign Off a 10 Billion+ Transistor Design in the Cloud
DESCRIPTION:Advanced semiconductor applications such as artificial intelligence / machine learning (AI/ML) and graphic processing units (GPUs) fully leverage dense\, advanced-node technology to push the extreme limits of design size. To signoff such large designs\, engineers are increasingly relying on distributed compute methods to accelerate the signoff analysis. Furthermore\, given lack of scalability of on-premises compute resources\, designers are migrating towards cloud-based solutions to solve their peak compute demand and meet their aggressive tapeout schedules. \nIn this CadenceTECHTALK\, TSMC + Microsoft + Cadence will present a signoff methodology optimized for giga-scale class (10 billion+ transistor) designs and tailored for execution on cloud-based infrastructure. The talk will feature the Cadence® Tempus™ Timing Signoff Solution’s STA signoff tool and CloudBurst™ platform\, as well as Microsoft Azure’s latest offerings suited for EDA workloads. \n\n\n\n\n\nFeatured Speakers \n\n\n\n\n\n\n\n\n\n\nVivian Jiang & Kurt Chiang\,\nTechnical Managers\,\nTSMC \n\n\n\n\n\n\n\n\nBrandon Bautz\, Sr. Group Director Product Management\, Cadence \n\n\n\n\n\n\n\n\nPrashant Varshney\, Sr. Director Product Management\, Microsoft \n\n\n\n\n\n\n\n\nKetan Joshi\, Group Director\, Cloud Business Development\, Cadence
URL:https://marketingeda.com/event/how-to-sign-off-a-10-billion-transistor-design-in-the-cloud/
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211201T080000
DTEND;TZID=America/Los_Angeles:20211202T170000
DTSTAMP:20211130T072557Z
CREATED:20211130T072557Z
LAST-MODIFIED:20211130T072557Z
UID:3776-1638345600-1638464400@marketingeda.com
SUMMARY:IP-SoC Conference 21
DESCRIPTION:IP-SoC 2021 will be the 24th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts in all the design track from Foundry\, technology\, design methodology to EDA tools share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nWarning: \n– To enter the physical or virtual event\, you need:\n• to be registered.\n– To enter the physical\, you need:\n• to show your proof of vaccination or “pass sanitaire”. Masks are mandatory except at the lunch table.
URL:https://marketingeda.com/event/ip-soc-conference-21/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Design-Reuse.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211117T100000
DTEND;TZID=America/Los_Angeles:20211117T170000
DTSTAMP:20211112T184020Z
CREATED:20211112T184020Z
LAST-MODIFIED:20211112T184020Z
UID:3735-1637143200-1637168400@marketingeda.com
SUMMARY:Samsung SAFE Forum 2021
DESCRIPTION:Join us for Samsung Foundry’s annual SAFE™ Forum. \nWhat will you take away from Samsung Foundry’s ecosystem event? Bump your SoC PPA knowledge with the latest information on: \nHigh speed interconnect IPs for HPC and Data Center applications and foundational IPs\nHigh bandwidth memory subsystems\nKey IP trends for automotive and mobile applications\nFoundational Analog Mixed Signal IP for a variety of applications\nThere will also be an opportunity to network with experts in IP\, EDA\, Cloud\, Design Services and Packaging during the virtual partner pavilion. \nRegister today! Participate to join the raffle for exciting prizes! \n– SAFE Forum Team
URL:https://marketingeda.com/event/samsung-safe-forum-2021/
CATEGORIES:Forum,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SAFE-2021.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211117T100000
DTEND;TZID=America/Los_Angeles:20211117T110000
DTSTAMP:20211104T190551Z
CREATED:20211104T190551Z
LAST-MODIFIED:20211104T190551Z
UID:3608-1637143200-1637146800@marketingeda.com
SUMMARY:CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
DESCRIPTION:Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power\, energy\, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. \nIn this CadenceTECHTALK\, you will learn how to: \n\nAddress the challenges of accelerating power and system-level verification in a pre-silicon emulated design flow using Cadence® Tensilica® IP\nExplore architecture usability with Tensilica IP with actual hardware and software implementation\nCreate an efficient environment to make energy-aware tradeoffs with accurate implementation characterization data\n\nDate and Time\nWednesday\, November 17\, 2021\n10:00am PST / 1:00pm EST
URL:https://marketingeda.com/event/cadencetechtalk-power-and-energy-optimization-using-tensilica-ip/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-17.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20211117T080000
DTEND;TZID=Asia/Tokyo:20211119T170000
DTSTAMP:20211029T175327Z
CREATED:20211029T175327Z
LAST-MODIFIED:20211029T175327Z
UID:3574-1637136000-1637341200@marketingeda.com
SUMMARY:RISC-V Days Tokyo Autumn 2021
DESCRIPTION:RISC-V Days Tokyo is Japan’s largest RISC-V event. We will hold live and online presentations\, live exhibition booths\, and press conferences. RISC-V Days Tokyo brings together excellent RISC-V-related technologies and products\, as well as key persons and engineers\, and provides business opportunities such as raising product awareness\, realizing collaboration between companies\, technology exchange\, and information gathering. Is intended to provide. Last year’s Day Tokyo 2020 was held online with a total of 1\,053 participants from 11 countries (Japan\, Sweden\, USA\, Taiwan\, France\, China\, Russia\, United Kingdom\, Switzerland\, Vietnam and Denmark). \nEvent is being held in-person and virtual.
URL:https://marketingeda.com/event/risc-v-days-tokyo-autumn-2021/
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/RISC-V-Days-Tokyo-Autumn-2021.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211109T100000
DTEND;TZID=America/Los_Angeles:20211109T110000
DTSTAMP:20211021T172343Z
CREATED:20211021T172343Z
LAST-MODIFIED:20211021T172343Z
UID:3558-1636452000-1636455600@marketingeda.com
SUMMARY:CXL and IDE: Important Considerations of Protecting High Speed Interconnects
DESCRIPTION:In a few short years\, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers\, high performance computing\, and cloud computing. However\, as the adoption has increased\, so has the security threat model users face. To address this\, the CXL 2.0 standard has included an optional IDE (Integrity and Data Encryption). While IDE is optional today\, given ever-increasing security threats\, it won’t be forever so understanding IDE will become essential. \nIn this webinar\, Rambus and Siemens will discuss the background of IDE\, the threat models it addresses\, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs. \nSpeakers \nAllan Gordan\, Siemens EDA\nProduct Manager for Verification IP \nArjun Bangre\, Rabus\nDirector of Product Management for PCIe and CXL controllers
URL:https://marketingeda.com/event/cxl-and-ide-important-considerations-of-protecting-high-speed-interconnects/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/rambus-siemens.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211109T100000
DTEND;TZID=America/Los_Angeles:20211109T110000
DTSTAMP:20211004T163653Z
CREATED:20211004T163653Z
LAST-MODIFIED:20211004T163653Z
UID:3462-1636452000-1636455600@marketingeda.com
SUMMARY:Boost LPDDR5 Verification   from IP to System Level
DESCRIPTION:Overview \nLow power DRAM is being adopted in a wide array of markets\, including automotive\, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth\, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall System on Chip (SoC) requirements are fully met makes verification extremely challenging. \nJoin us to learn about LPDDR5 verification challenges from IP-level to system-level and demonstrate how these challenges can be significantly mitigated using advanced verification methodologies and tools. \nThis webinar will cover the following topics: \n· Verification challenges of LPDDR5 designs \n· IP-level verification for specification’s compliancy \n· System-level verification in simulation and emulation \n\nDate \nTuesday\, November 9\, 2021 \nTime \nEMEA and APJ Sessions: 09:00 BST / 10:00 CEST / 11:00 EEST and IDT / 13:30 IST/ 16:00 CST/17:00 JST \nNorth America Session: 10:00 PDT / 13:00 EDT
URL:https://marketingeda.com/event/boost-lpddr5-verification-from-ip-to-system-level/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-9.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20211102T130000
DTEND;TZID=Asia/Tokyo:20211102T170000
DTSTAMP:20211004T164336Z
CREATED:20211004T164336Z
LAST-MODIFIED:20211004T164336Z
UID:3465-1635858000-1635872400@marketingeda.com
SUMMARY:Silvaco UseRs Global Event - Japan
DESCRIPTION:開催日時：2021/11/02 13:00\nSURGE (Silvaco UseRs Global Event)とは、シルバコが開催するワールドワイドのイベントです。\nSURGEは、TCAD、EDA、IPの各分野において、新しい技術について議論し、ユーザの経験を共有し、先進的な半導体設計のための革新的な技術を発見するためのイベントです。\n本年は、オンラインでの開催となります。 \n当日ご参加いただき、アンケートにご回答いただいたお客様の中から抽選で50名の方にAmazonギフト券1000円分(Eメールタイプ)を進呈させていただきます。\nこの機会に是非ともSURGE Japanにご登録ください。
URL:https://marketingeda.com/event/silvaco-users-global-event-japan/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-Japan.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211026T080000
DTEND;TZID=America/Los_Angeles:20211027T170000
DTSTAMP:20210915T165013Z
CREATED:20210915T165013Z
LAST-MODIFIED:20210915T165013Z
UID:3330-1635235200-1635354000@marketingeda.com
SUMMARY:DVCon Europe 2021
DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications and demonstrations for the practical use of EDA solutions for electronic design. \nDue to health and safety concerns\, DVCon Europe 2021 will be held as a fully virtual conference. \nhttps://dvcon-europe.org/ \nCheck to see if your company is an Accellera member at: https://accellera.org/about/members
URL:https://marketingeda.com/event/dvcon-europe-2021/
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2021.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211021T090000
DTEND;TZID=America/Los_Angeles:20211021T100000
DTSTAMP:20210930T162644Z
CREATED:20210930T162644Z
LAST-MODIFIED:20210930T162644Z
UID:3455-1634806800-1634810400@marketingeda.com
SUMMARY:Compare Performance-power of Arm Cortex vs RISC-V for AI applications
DESCRIPTION:In the Webinar\, we will show you how to construct\, simulate\, analyze\, validate\, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1\, SiFive u74\, and other vendor cores. Aside from the processor resources such as cache and memory\, the system will contain custom switches\, Ingress/Egress buffers\, credit flow control\, DMA AI accelerators\, NoC and AMBA AXI buses. The evaluation and optimization criteria will be task latency\, dCache hit-ratio\, power consumed/task and memory bandwidth. The parameters to be modified are bus topology\, cache size\, processor clock speed\, custom arbiters\, task thread allocation and changing the processor pipeline. \nKey Takeaways:  \n1. Validating architecture models using mathematical calculus and hardware traces \n2. Construct custom policies\, arbitrations and configure processor cores \n3. Select the right combination of statistics to detect bottlenecks and optimize the architecture \n4. Identify the right use of stochastic\, transaction\, cycle-accurate and traces to construct the model \nSpeaker Bios:  \nAlex Su is a FPGA solution architect at E-Elements Technology\, Hsinchu\, Taiwan. Prior to that\, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP. \nDeepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Deepak has published over 50 articles and presented at over 30 conferences in EDA\, semiconductors\, and embedded computing. This webinar is in partnership with SemiWIki.com and Mirabillis.
URL:https://marketingeda.com/event/compare-performance-power-of-arm-cortex-vs-risc-v-for-ai-applications/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211020T100000
DTEND;TZID=America/Los_Angeles:20211020T110000
DTSTAMP:20211011T161713Z
CREATED:20211011T161657Z
LAST-MODIFIED:20211011T161713Z
UID:3502-1634724000-1634727600@marketingeda.com
SUMMARY:Role of MIPI IP in New Automotive SoC Architectures
DESCRIPTION:SoCs for Automotive applications such as ADAS\, Infotainment\, and connected vehicles are shifting to a more domain-based architecture. As a result\, the car’s electronics for such applications are requiring a major redesign for a more efficient connectivity with the utmost reliability\, security\, and safety. This shift along with the increasing use of sensors and displays in the car are highlighting the value and technical advantages of interfaces such as MIPI CSI-2\, DSI/DSI-2 and C-PHY/D-PHY. \nAttend to learn about: \n\nThe transition from distributed ECU system to domain-based architecture and ultimately to zonal architecture\nSoC requirements for new automotive electronics that now leverage more sensors and displays\nHow to address automotive IP and SoC requirements for functional safety\, reliability\, and quality\nTypical use cases and architectures for MIPI interfaces\n\n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nLicinio Sousa\n\n\nSr. Staff Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nLicinio Sousa is currently a Senior Staff Product Marketing Manager responsible for DesignWare® MIPI and Mobile Storage IP Solutions. Mr. Sousa brings more than 18 years of experience in Semiconductor\, IP and EDA companies focusing on software and hardware design. He has also held various R&D\, Field Applications Engineering and Marketing positions at Synopsys. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRon DiGiuseppe\n\n\nAutomotive IP Segment Manager\nSynopsys \n\n\n\n\n\n\n\n\nRon DiGiuseppe is currently a Senior Strategic Marketing Manager responsible for automotive segment marketing for ADAS\, Functional Safety\, Infotainment and MCU applications. Ron brings more than 18 years of semiconductor experience to Synopsys. Prior to joining Synopsys\, Ron held a range of management positions at Xilinx for automotive connectivity IP products as well as engineering development and management roles for companies including Oki Semiconductor\, NEC\, and Raytheon Corporation.
URL:https://marketingeda.com/event/role-of-mipi-ip-in-new-automotive-soc-architectures/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNPS-Oct-20.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211020T080000
DTEND;TZID=America/Los_Angeles:20211023T170000
DTSTAMP:20210915T060448Z
CREATED:20210915T060448Z
LAST-MODIFIED:20210915T060448Z
UID:3315-1634716800-1635008400@marketingeda.com
SUMMARY:VSDOpen 2021 Online Conference
DESCRIPTION:What is VSDOpen 2021 Agenda?\nKey strategy – Provide High Tech Experience of developing analog designs using Open-Source Tools\, PDKs and Cloud Platform 3 days of Conference Tutorials\nKey Focus – Analog Products\, Open-source FPGA and Semiconductor IP’s\nKeynote Speaker – Industry leaders focused on Developing IoT\, 5G and AI products\, Professor from open-source Research and Organization supporting Talent pool development in Semiconductor field. \nSpeakers \nKunal Ghosh\, VLSI System Design \nSteve Hoover\, Redwood EDA
URL:https://marketingeda.com/event/vsdopen-2021-online-conference/
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/VSDopen21banner.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211020T080000
DTEND;TZID=America/Los_Angeles:20211021T170000
DTSTAMP:20210921T162439Z
CREATED:20210921T162131Z
LAST-MODIFIED:20210921T162439Z
UID:3386-1634716800-1634835600@marketingeda.com
SUMMARY:Linley Fall Processor Conference 2021
DESCRIPTION:For more than a decade\, The Linley Group has delivered the industry’s premier processor conferences. This year\, the Linley Fall Processor Conference will return to Santa Clara on October 20-21\, 2021. If you can’t attend in person\, attend the virtual event on October 27-29 and November 3-5 with live Q&A and breakout sessions. \nPlease stay tuned for virtual-program details coming soon!!! Virtual dates are mornings (Pacific time) on October 27-29 and November 3-5. \nPresentations will address processors and IP cores for AI applications\, embedded\, data center\, automotive\, and server designs. Attendees will be able to hear presentations and interact with the speakers during Q&A\, lunch\, and the networking reception. \nAnalyst and Industry Keynotes \nLinley Gwennap\, principal analyst\, The Linley Group\, will open the conference with an overview of the latest market\, technologies\, equipment-design\, and silicon trends. We’ll also feature a keynote from an industry leader. \nIn-Depth Technical Sessions \nUnlike many conferences\, we ensure that the presentations deliver real technical content\, not marketing hype. We’re the conference of choice for many companies who announce new products or make technology disclosures. \nThe Linley Group analysts carefully select session topics and choose leading speakers who are experts in their fields. In addition\, the analysts ensure that the content of the presentations are full of insightful\, technical information that will help attendees select the right components and systems for their next project. \nAgenda Day 1 \nAgenda Day 2 \nWhy Attend \nThe Linley Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear\, question\, and network with key providers of advanced technology products. \nThe Linley Conferences analyze products and design strategies in a particular technology segment\, providing information that engineers can immediately use to improve their designs. The events feature in-depth technical presentations from our own analysts as well as leading technologists from the industry. \nFree Admission \nWe offer free admission to qualified registrants making it easy to participate. The conference is intended for chip designers\, system designers\, equipment vendors\, OEM/ODMs\, service providers\, press\, and the financial community. \nCOVID-19 Policies and Precautions \nWe are working closely with the Hyatt Regency to reduce the risk of attending our in-person event. Individuals and their employers\, however\, must decide what level of risk is acceptable. For those unable to attend in person\, we offer our subsequent virtual event. \nCurrent policies and precautions: \n• Verification of fully vaccinated status or negative test result is required of all attendees\n• All attendees are required to wear well-fitting masks except when actively eating or drinking (in accordance with the County of Santa Clara 8/2/21 Order)\n• Hyatt staff will serve food\, no open buffets will be offered\n• Many additional safety measures as a part of Hyatt’s Global Care & Cleanliness Commitment \nPolicies are subject to change. We will update this page as needed. \nTo keep informed about this and other upcoming events\, subscribe to the free Linley Newsletter\, for weekly news and updates.
URL:https://marketingeda.com/event/linley-fall-processor-conference-2021/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/The-Linley-Group.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211019T090000
DTEND;TZID=America/Los_Angeles:20211019T100000
DTSTAMP:20211011T160945Z
CREATED:20211011T160945Z
LAST-MODIFIED:20211011T160945Z
UID:3499-1634634000-1634637600@marketingeda.com
SUMMARY:Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
DESCRIPTION:Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data\, high-performance computing (HPC)\, and analytics. In-house data centers are increasingly going off-premise\, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability and reduce IT costs. This huge\, and growing\, amount of data with confidential and critical information must be protected. In addition\, new laws and regulations to comply with data privacy rules\, along with standards updates for PCI Express (PCIe) and CXL for Integrity and Data Encryption (IDE)\, put more pressure on solution providers to secure their systems and data starting with the SoC. \nIn this presentation\, attendees will: \n\nLearn about today’s known threats for cloud and edge computing systems\nUnderstand new developments in PCIe and CXL security solutions\, including IDEs\nWalk through a cloud computing use case that addresses the applications’ security\, performance\, and latency requirements with DesignWare® Security IP\n\nBy the end of the presentation\, attendees will understand the importance of securing data moving through PCIe and CXL interfaces\, market point of view\, and get a reference example for how security can be addressed with DesignWare IP.
URL:https://marketingeda.com/event/defending-the-cloud-pcie-and-cxl-data-security-for-high-performance-computing/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNPS-Oct-19.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211019T080000
DTEND;TZID=America/Los_Angeles:20211021T170000
DTSTAMP:20210919T014256Z
CREATED:20210919T014256Z
LAST-MODIFIED:20210919T014256Z
UID:3379-1634630400-1634835600@marketingeda.com
SUMMARY:arm DevSummit 2021
DESCRIPTION:Engineers\, developers\, and tech enthusiasts: Arm DevSummit 2021 is coming to your screens October 19-21. This three-day virtual conference serves up insights into the latest technology trends\, gives you an opportunity to up-level your skills in technical sessions and hands-on workshops\, and offers the chance to network with like-minded software developers and hardware designers. \nJoin us online to learn how Arm combines the power of specialized processing with the design freedom and accessibility of general-purpose compute to help you unlock the power of technology for any device\, from edge to cloud. \nCome and join the millions of active developers in our community and help us spark the world’s technology potential. Together\, we can create positive impact at scale through building energy-efficient high-performance computing solutions. \n\nFind Out More
URL:https://marketingeda.com/event/arm-devsummit-2021/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/arm-DevSummit-2021.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20211014T090000
DTEND;TZID=America/Los_Angeles:20211014T150000
DTSTAMP:20210903T194614Z
CREATED:20210903T194614Z
LAST-MODIFIED:20210903T194614Z
UID:3226-1634202000-1634223600@marketingeda.com
SUMMARY:SURGE Virtual Event North America 2021
DESCRIPTION:Silvaco is pleased to invite you to join its annual SURGE users event\, taking place virtually\, on October 14\, 2021. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. This year we have a virtual event that includes cool prizes and giveaways for attendees.
URL:https://marketingeda.com/event/surge-virtual-event-north-america-2021/
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SURGE-North-America.jpg
END:VEVENT
END:VCALENDAR