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DTSTART;TZID=America/Los_Angeles:20210921T080000
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UID:3234-1632211200-1632330000@marketingeda.com
SUMMARY:ARC Processor Virtual Summit 2021
DESCRIPTION:Why Attend?\nJoin us for the ARC® Processor Virtual Summit to hear our experts\, users and ecosystem partners discuss the most recent trends and solutions that impact the development of SoCs for embedded applications.  This multi-day event will provide you with in-depth information from industry leaders on the latest ARC processor IP and related hardware/software technologies that enable you to achieve differentiation in your chip or system design. \nWho Should Attend?\nWhether you are a developer of chips\, systems or software\, the ARC Processor Virtual Summit will give you practical information to help you meet your unique performance\, power and area requirements in the shortest amount of time.
URL:https://marketingeda.com/event/arc-processor-virtual-summit-2021/
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ARC-Processor-Virtual-Summit-2021.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20210915T180000
DTEND;TZID=America/Los_Angeles:20210915T190000
DTSTAMP:20210915T161315Z
CREATED:20210915T161007Z
LAST-MODIFIED:20210915T161315Z
UID:3319-1631728800-1631732400@marketingeda.com
SUMMARY:Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
DESCRIPTION:When verifying large SoC designs\, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow\, such as UVM. This talk addresses ways to extract those models automatically from circuits. \nThe first approach is called structural modeling\, mapping each device in the circuit to an equivalent model in SystemVerilog and connecting them up as they are in the original circuit. While this guarantees correct-by-construction models\, the improvement in the simulation speed is limited due to the low abstraction level of the models. \nThe second approach is called functional modeling\, aiming to raise the abstraction level of the models. One can select a part of the circuit and map it to one of the predefined model templates to generate its functional model. Although it requires some manual inputs\, the resulting models can deliver significantly faster and even more accurate simulations than the structural models. \nQuestion is\, how many model templates would be necessary to model analog circuits? This talk shares my journey to answer this. I will use a pipelined analog-to-digital converter (ADC) example to demonstrate these different approaches.
URL:https://marketingeda.com/event/automatic-generation-of-systemverilog-models-from-analog-mixed-signal-circuits-a-pipelined-adc-example/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Scientific-Analog.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20210915T110000
DTEND;TZID=America/New_York:20210915T153000
DTSTAMP:20210907T164632Z
CREATED:20210907T164541Z
LAST-MODIFIED:20210907T164632Z
UID:3282-1631703600-1631719800@marketingeda.com
SUMMARY:GF Technology Summit 2021
DESCRIPTION:DELIVERING A NEW ERA OF MORE  \n\n\n\nSemiconductor chips are pervasive—inside everything from appliances to thermostats\, smartphones to automobiles\, and industrial equipment to medical devices. These incredibly complex feats of human ingenuity power our world\, fuel the global economy and enrich our lives. \n  \nThe GF Technology Summit offers an opportunity to discuss the challenges and opportunities in semiconductor design and manufacturing\, learn about new technologies and solutions\, and discover new ways to collaborate\, partner and invest so that together we can deliver more innovation\, more capabilities\, more intuitive interaction\, more intelligence\, and more feature-rich solutions. \n\n\n\n\n\n\n\nMORE INNOVATION  \nGain insight from industry experts about the latest innovations in smart mobile devices\, automotive\, personal computing\, communications infrastructure and datacenter\, home and industrial IoT and more. \n  \n\n\n\n\n\n\n\nMORE COLLABORATION   \nEnter a virtual lounge\, schedule a breakout room and visit the partner pavilion. There are lots of ways to network\, explore partnership opportunities and collaborate on your next IC design project. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMORE GROWTH \nEngage with the GF team and ecosystem partners to learn how GF platforms and solutions\, design enablement and turnkey services\, coupled with industry leading IP offerings and EDA tools\, can help you accelerate your design cycle and speed your time-to-market. \n\n\n\n\n\n\n\n\n\n\n“I’m looking forward to welcoming you to our GF Technology Summit 2021 North America\, which will be delivered in a new live interactive\, virtual format. Join us to connect\, build relationships and discover new ways of collaborating and innovating together. I look forward to spending time with you on September 15th.”
URL:https://marketingeda.com/event/gf-technology-summit-2021/
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GF-Technology-Summit-2021.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20210915T100000
DTEND;TZID=America/Los_Angeles:20210915T110000
DTSTAMP:20210907T202849Z
CREATED:20210907T202849Z
LAST-MODIFIED:20210907T202849Z
UID:3293-1631700000-1631703600@marketingeda.com
SUMMARY:How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
DESCRIPTION:In this webinar\, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration\, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols such as PCIe\, CXL\, DDR5 and Die-to-Die has been enhanced with specific capabilities for the Arm Neoverse platform. \nAttendees will learn about \n\nThe companies’ collaboration to eliminate design bottlenecks so SoC designers can focus on their core competencies\nHow the Synopsys and Arm IP collaboration maximizes system performance for HPC and data center SoCs\nTechnical enhancements to Synopsys Interface IP to improve Arm-based SoC performance\nThe details of Arm-validated interoperability testing of Synopsys DesignWare Interface IP portfolio\nNeed for pre-Silicon Server Base System Architecture (SBSA) testing to meet SystemReady certification
URL:https://marketingeda.com/event/how-synopsys-interface-ip-and-arm-interoperate-to-accelerate-system-io-and-memory-performance/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-15.jpg
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DTSTART;TZID=America/Los_Angeles:20210913T080000
DTEND;TZID=America/Los_Angeles:20210916T170000
DTSTAMP:20210903T185159Z
CREATED:20210903T185159Z
LAST-MODIFIED:20210903T185159Z
UID:3204-1631520000-1631811600@marketingeda.com
SUMMARY:AI Hardware Summit
DESCRIPTION:AI Hardware is evolving – and so are we! As machine learning models continue to grow in size and complexity\, and more and more models enter production in enterprises worldwide\, the way we approach accelerating these workloads is changing. \nAt the front end\, data-centricity is taking precedence over model-centricity. At the back end\, AI practitioners want systems that are performant and efficient\, but also sustainable\, explainable and accountable. \n\nFrom massive research models like GPT-3\, to day-to-day models deployed by enterprises around the world\, we are lifting the hood on how to make AI fast\, efficient and affordable. \nAI Hardware Summit is evolving\, we continue our mission to help those who are accelerating AI workloads in the cloud and at the edge\, and this year is all about systems level AI acceleration. \nEvent Overview \nSept 13: Virtual Day \nSept 14-15: In-Person Summit\, Streamed Globally \nSept 16: Virtual Roundtables
URL:https://marketingeda.com/event/ai-hardware-summit/
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-HW-Summit.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20210909T100000
DTEND;TZID=America/Los_Angeles:20210909T103000
DTSTAMP:20210903T191530Z
CREATED:20210903T191530Z
LAST-MODIFIED:20210903T191530Z
UID:3216-1631181600-1631183400@marketingeda.com
SUMMARY:Designing with Silvaco's Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
DESCRIPTION:Abstract \nOne commonality across semiconductor market segments is the need for memory.  However\, memory characteristics and interfaces vary greatly depending on the market segment and application. This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling. \nSPI was developed by Motorola in 1979 for short-distance communication within embedded systems. Its popularity grew quickly\, and SPI soon spawned many variants but lacked a unifying standard. Almost 30 years after its inception\, SPI was adopted by FLASH memory manufacturers to satisfy growing demand in the emerging IoT space. As edge devices became more complex\, a push for greater memory performance resulted\, and the SPI interface evolved to meet these new challenges: Dual\, Quad\, Octal and Octal DDR (Double Data Rate) SPI variants ensued. With Octal DDR\, the performance of the interface was sufficient to support RAM devices in addition to FLASH devices\, some much-needed standardization was realized in the form of several similar\, overlapping specifications. \nToday’s IoT systems need a solution for interfacing with these memories: the Octal SPI Memory Controller.  This product from Silvaco contains powerful features such as XIP (Execute In Place) and supports FLASH and PSRAM memories. \nWhat You Will Learn: \n\nOctal SPI Controller architecture and key features\nImplementation of a typical Octal SPI integration in an embedded system\nOperating modes will be defined and explained\nSeamless memory access\, support for a range of memory devices\, and flexibility to accommodate various clocking and integration scenarios\nXIP (Execute in Place) and PSRAM support
URL:https://marketingeda.com/event/designing-with-silvacos-octal-spi-memory-controller-with-advanced-memory-support-for-iot-systems/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-IP.jpg
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