BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Europe/Paris BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20240618T080000 DTEND;TZID=Europe/Paris:20240618T170000 DTSTAMP:20240528T182135Z CREATED:20240528T182135Z LAST-MODIFIED:20240528T182135Z UID:8066-1718697600-1718730000@marketingeda.com SUMMARY:Open-source silicon and EDA workshop 2024 DESCRIPTION:The chip design ecosystem in Europe is challenged by expensive development tools\, legal constraints\, lock-in threats and dependency on external supply chains. \nOpen-source Electronic Design Automation (EDA) tools and open-source silicon chips are emerging as possible solutions to these problems. It is increasingly recognised that open-source development offers not only faster and cheaper development but also better products. The open-source model moreover resonates well with the core aims of the European Chips Act of reinforcing the Union’s semiconductor ecosystem by reducing dependencies\, enhancing digital sovereignty\, stimulating investment\, increasing design capacity and the resilience of the Union’s semiconductor supply chain. \nEven though some IP building blocks\, such as those based on the RISC-V open instruction set\, are already witnessing overwhelming success and industrial adoption\, the open-source EDA and chip ecosystems are still in their infancy. Their development is further hindered by the high costs of manufacturing silicon chips and by the complexity of the ecosystem which involves heterogeneous participants (from designers to EDA developers\, to foundries). \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/open-source-silicon-and-eda-workshop-2024/ LOCATION:Sorbonne Université\, 15-21 Rue de l'École de Médecine\, Paris\, France CATEGORIES:EDA,IP,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240616T080000 DTEND;TZID=America/Los_Angeles:20240620T170000 DTSTAMP:20240226T234257Z CREATED:20240226T234257Z LAST-MODIFIED:20240226T234257Z UID:7693-1718524800-1718902800@marketingeda.com SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/ LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240612T080000 DTEND;TZID=America/Los_Angeles:20240613T170000 DTSTAMP:20240522T150924Z CREATED:20240522T150924Z LAST-MODIFIED:20240522T150924Z UID:8019-1718179200-1718298000@marketingeda.com SUMMARY:PCI-SIG 2024 DESCRIPTION:The PCI-SIG Developers Conference 2024 returned to Santa Clara on June 12-13\, 2024! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers attended this event. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nThe presentations were captured on video and are available to all members. These recordings provide a valuable opportunity to those who were unable to attend the event and for those who want to re-experience the presentations for more in-depth learning. \nAttendee Registration – Open Now!\nOnline attendee registration is open. All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting\nThe PCI-SIG Annual Meeting will be held on June 12th\, 2024. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nPCI Board Panel \nFollowing a positive response from last year’s panel\, we will be holding another Board Panel at this year’s US DevCon. We are currently accepting questions from members for the Board of Directors to address during the panel discussion. If you have a question you would like to submit\, please email them to pcidevcon@pcisig.com. \nCall for Papers – Closed\nYou will not want to miss this series of presentations as PCI-SIG members present unique tips\, tricks\, and pitfalls learned during their implementation of PCI technology. \nIf you are interested in submitting an abstract for consideration\, we encourage you to review the online Call for Papers instructions and milestones.  \n*Note that registering and submitting materials does not guarantee you will be selected as a speaker at this event. We will follow up with those selected following the associated deadlines and provide notice to those not chosen.  \nSponsorship Registration – Closed\nPCI-SIG member companies will have the opportunity to demonstrate their company’s industry leadership in advancing the PCI landscape by participating as a Sponsor of the PCI-SIG DevCon 2024. Sponsor opportunities offer a variety of benefits including onsite presence and logo promotion. \nTo review sponsor opportunities\, please visit the PCI-SIG Sponsor Opportunities web page. \nConnect with us on LinkedIn and Twitter @pci_sig #PCISIGDevCon24 \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/pci-sig-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCI-SIG-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240611T090000 DTEND;TZID=America/Los_Angeles:20240611T170000 DTSTAMP:20240508T184358Z CREATED:20240508T183624Z LAST-MODIFIED:20240508T184358Z UID:7972-1718096400-1718125200@marketingeda.com SUMMARY:2024 ANDES RISC-V CON DESCRIPTION:Recently\, RISC-V\, with its open\, streamlined\, and scalable configuration\, has become the mainstream solution adopted by leading market players\, paving the way for widespread technological innovation. In the RISC-V application field\, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention\, and the need for product information security has also increased. \nAs a Premier member and a leading brand in 32/64-bit embedded CPU cores\, Andes\, a member of RISC-V International\, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends.” The event aims to introduce the market dynamics and development trends of RISC-V\, discuss Andes’ comprehensive product portfolio recently launched\, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities. \nThe seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners\, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts\, paving the way for a diverse application vision! \nHere is our event schedule \n09:00 – 09:25 Registration\n09:25 – 09:30 Opening-Market Watch\, Frankwell Lin\, Chairman & CEO\, Andes Technology\n09:30 – 09:50 Customer Use Case Presentation\n09:50 – 10:25 Unlocking RISC-V’s potential on Intelligence Application Processing\, Dr. Charlie Su\, President & CTO\, Andes Technology\n10:25 – 10:45 Safe and Secure Software Solutions for Andes RISC-V\, Robert Redfield\, Director of Business Development\, Green Hills Software\nGreen Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture\, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills Software’s offering features real-time operating systems\, powerful compilers and advanced C/C++ development tools that leverage the company’s 40-years of microprocessor experience. \n10:45 – 11:05 Lauterbach Debug and Trace of Andes RISC-V Processors\, Dennis Griffiths\, Field Applications Engineer\, Lauterbach\nLauterbach\, the leader in RISC-V debug and trace\, will be discussing and demonstrating the TRACE32 tools for the Andes N27 on the Big Orca reference hardware.Using our TRACE32® tools you can debug and control any RISC-V core (along with all of the other cores) in any SoC via a single debug interface\, all at the same time. TRACE32® tools support real-time on- and off-chip tracing for all major RISC-V trace systems. \n11:05 – 11:35 Break\n11:35 – 11:55 Customer Use Case Presentation\n11:55 – 12:15 Ecosystem Partners Showcase – Siemens EDA\n12:15 – 13:15 Lunch\n13:15 – 14:05 RISC-V Ecosystem Panel: Open-Source is Transforming AI and Hardware\nModerator: Dylan Patel\, Chief Analyst\, SemiAnalysis\nPanelist: Charlie Cheng\, CEO\, Cucina\, Inc.\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\n14:05 – 14:35 Driving Safe and Secure Innovations with Andes RISC-V Solutions\, Andes Technology\n14:35 – 15:05 Break\n15:05 – 15:25 Synopsys Solutions Empower Software Development on Andes Processors\, Larry Lapides\, Business Development Director\, Synopsys\nAndes processor IP is increasingly being used in high performance applications such as AI/ML\, and in use cases where there are reliability\, safety and security requirements. For these and other advanced applications software development is critical. Starting software development early\, before RTL is ready\, can accelerate software tasks by months. Other key pieces of the software task include hardware-software co-verification\, building prototypes and enabling CI/CD software methodology in production. Synopsys tools\, including ImperasFPM fast processor models of the Andes cores\, Virtualizer for virtual prototypes\, and the HAPS and ZeBu hardware-assisted verification tools\, have been supporting and enabling Andes customers for more than 5 years. This talk will discuss software methodology in general\, and provide case studies of Andes-Synopsys joint customers. \n15:25 – 15:45 Are you a professional developer? Then why use amateur tools? Shawn Prestridge\, US FAE Manager\, IAR\nWhat can professional tools bring to a professional developer? Many features that optimize your time\, such as live instruction tracing\, complex and conditional breakpoint types\, functional safety certification\, comprehensive live technical support\, and much more. The optional code analysis tools can also help you quickly spot code issues while you are desk-checking your code to make your code fast and accurate. This session will quickly cover the benefits that each of these features brings in terms of time (and ultimately\, money) savings. Your time isn’t free – optimize it by using tools commensurate with your talent that allow you to deliver your product to market as quickly as possible! \n5:45 – 16:35 RISC-V Ecosystem Panel: Unlocking the RISC-V Application Processor Potential\nThe Application Processor market presents a tens-of-billions annual value opportunity\, which expands by an order of magnitude at the device scope\, and is similarly scaled\, if not more\, at the software application level. The target segments are diverse\, ranging from consumer electronics and industrial computing to automotive\, networking\, and communications. The incumbent compute ISAs for application processors are either Arm or x86\, but RISC-V has emerged as a fast-evolving and maturing alternative\, gaining strong traction across the value chain. This growth is fueled by the advent of AI\, whose support is becoming ubiquitous across all compute platforms\, with RISC-V offering significant value for AI computing. Initiatives like defining and ratifying an iterative set of extensions for the RISC-V application (RVA) profile have established a standard architecture base\, enabling hardware and software vendors to develop interoperable solutions. Efforts by organizations like RISE and major Linux-based and Android-based operating system providers have accelerated the software-based infrastructure support for RISC-V. Despite these advancements\, challenges remain in areas such as ecosystem maturity\, hardware performance and availability\, software compatibility\, and general public perception. This panel discussion will delve into these exciting topics to explore the opportunities\, the progress made\, and how to overcome these challenges to unlock the potential of RISC-V application processors. \nModerator: Mark Himelstein\, Heavenstone\, Inc.\nPanelist: Dr. Charlie Su\, President & CTO\, Andes Technology\nLars Bergstrom\, Director of Engineering\, Android team\, Google\nBarna Ibrahim\, Vice-Chair\, RISE\nDr. Sandro Pinto\, Co-founder\, OSYX Technologies\n16:35 – 17:00 Lucky Draw & Evening Reception \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/2024-andes-risc-v-con/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240610T080000 DTEND;TZID=Europe/Berlin:20240611T170000 DTSTAMP:20240503T162031Z CREATED:20240503T162031Z LAST-MODIFIED:20240503T162031Z UID:7940-1718006400-1718125200@marketingeda.com SUMMARY:SNUG Europe 2024 DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas \n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/snug-europe-2024/ LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240530T100000 DTEND;TZID=America/Los_Angeles:20240530T110000 DTSTAMP:20240521T001952Z CREATED:20240521T001952Z LAST-MODIFIED:20240521T001952Z UID:8004-1717063200-1717066800@marketingeda.com SUMMARY:Addressing Real-Time Workloads in Automotive Applications with Efficient ARC-V Processors DESCRIPTION:Many automotive applications require processing workloads with minimum latency and precise timing budgets.  This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking\, where human life may be jeopardized.  These systems require processing elements that can respond to events within specific (predictable) time constraints. System reliability and availability depend on the effectiveness of this real-time processing. \nIn this webinar\, we will outline examples of safety-critical applications and why real-time processing is required to maintain the highest levels of safety and reliability.  We will also discuss Synopsys’ ARC-V™ RHX processor series and how these power/performance efficient processors address the real-time requirements of these applications. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\nSr. Product Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRich Collins is senior product managemet director for the ARC-V  RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D\, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University. \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/addressing-real-time-workloads-in-automotive-applications-with-efficient-arc-v-processors/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240529T100000 DTEND;TZID=America/Los_Angeles:20240529T110000 DTSTAMP:20240521T001409Z CREATED:20240521T001409Z LAST-MODIFIED:20240521T001409Z UID:8001-1716976800-1716980400@marketingeda.com SUMMARY:Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process DESCRIPTION:Synopsys’ SLM PVT Monitor (process detector\, voltage monitor\, temperature sensor) IP can collect voltage\, temperature\, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on how the monitors need to move from analog to digital sensing paradigm due to the design constraints introduced by GAA nodes. \nIn this webinar\, you will learn: \n\nSilicon Lifecycle Management (SLM) overview and the crucial role of PVT IP\nOverview of each component in the PVT IP portfolio – rearchitecting from analog to digital sensing\nPVT IP use cases in data centers\, 5G\, consumer electronics\, and automotive applications\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar\n\n\nProduct Manager\, Senior Staff\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar is a Product Manager\, Senior Staff at Synopsys in the Silicon Lifecycle Management business group and manages the PVT Monitor IP products. He is responsible for total product management including market research and strategy for new product roadmap definition\, go-to-market planning\, product collateral generation for customer engagements and sales trainings. He has more than a decade and a half of experience in the Electronic Design Automation (EDA) industry focusing on the analog and mixed-signal design space. Rohan holds a Master’s degree in Electrical Engineering from The University of Texas. \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/reimagining-synopsys-slm-pvt-monitoring-ip-for-advanced-node-gaa-process/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-29-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20240528T090000 DTEND;TZID=Asia/Shanghai:20240528T160000 DTSTAMP:20240522T200534Z CREATED:20240522T194800Z LAST-MODIFIED:20240522T200534Z UID:8030-1716886800-1716912000@marketingeda.com SUMMARY:TSMC 2024 China Technology Symposium DESCRIPTION:Get the latest on:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC Technology Symposium! \n\n\n\n09:00 – 10:00\nRegistration & Ecosystem Pavilion\n\n\n10:00 – 10:10\nWelcome & Opening Remarks\n\n\n10:10 – 10:30\nMarket Update and Outlook\n\n\n10:30 – 11:00\nTechnology Leadership\n\n\n11:00 – 11:25\nCoffee Break & Ecosystem Pavilion\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 12:15\nAdvanced Technology Design Solutions\n\n\n12:15 – 13:25\nLunch & Ecosystem Pavilion\n\n\n13:25 – 13:45\nAdvanced Technology\n\n\n13:45 – 14:05\n3DFabric Technology\n\n\n14:05 – 14:40\nCoffee Break & Ecosystem Pavilion\n\n\n14:40 – 15:00\nAutomotive & eNVM Technology\n\n\n15:00 – 15:20\nIoT Technology\n\n\n15:20 – 15:40\nAdvanced RF and Analog Technology\n\n\n15:40 – 16:00\nLucky Draw\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2024-china-technology-symposium/ LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China CATEGORIES:EDA,Foundry,IP,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240522T070000 DTEND;TZID=America/Los_Angeles:20240522T090000 DTSTAMP:20240424T164124Z CREATED:20240424T164124Z LAST-MODIFIED:20240424T164124Z UID:7910-1716361200-1716368400@marketingeda.com SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240521T080000 DTEND;TZID=America/Los_Angeles:20240523T170000 DTSTAMP:20240327T162206Z CREATED:20240327T162206Z LAST-MODIFIED:20240327T162206Z UID:7771-1716278400-1716483600@marketingeda.com SUMMARY:Embedded Vision Summit 2024 DESCRIPTION:The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems\, cloud solutions and mobile applications. \n\n\nWhy Attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.\n\n\n\n\nJoin us for three days of learning—from tutorials to Deep-Dive Day\, covering the latest technical insights\, business trends and vision technologies—all with a focus on practical\, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences\, like CVPR\, to the concrete needs of innovators building real-world products. \n\n\n\n\nFour Reasons the Embedded Vision Summit is Different from Other Conferences\n\n\n\n\n\n\n\nThe Summit is by innovators\, for innovators.\n\n\n\n\nWe have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.\n\n\n\n\nWe’ve been doing this for 13 years.\n\n\n\n\nA whopping 99% of our attendees would recommend the Summit to a colleague.\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/embedded-vision-summit-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-Vision-Summmit-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240515T130000 DTEND;TZID=America/Los_Angeles:20240515T140000 DTSTAMP:20240508T233014Z CREATED:20240508T233014Z LAST-MODIFIED:20240508T233014Z UID:7977-1715778000-1715781600@marketingeda.com SUMMARY:Innovative Technologies\, Tools\, and Methodologies for Space Applications DESCRIPTION:In the world of space applications\, reliability is paramount. As the space sector continues to experience rapid growth and evolution\, new challenges are emerging to meet the demands of various mission types and requirements\, such as robust functional safety protections\, high reliability\, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor\, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development. \nSpeakers \nJim T.\, Business Development\, Lattice Semiconductor\nKhalid Khan\, Directory of Applications Engineer\, Synopsys\nMelanie Berg\, Founder and CEO\, Space R3 \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/innovative-technologies-tools-and-methodologies-for-space-applications/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Lattice-May-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240513T080000 DTEND;TZID=America/Los_Angeles:20240517T170000 DTSTAMP:20240514T181939Z CREATED:20240514T181805Z LAST-MODIFIED:20240514T181939Z UID:7992-1715587200-1715965200@marketingeda.com SUMMARY:SEE\, MAPLD 2024 DESCRIPTION:Our workshop will feature content including\, but not limited to\, the following areas: \n\n\n\n\nArtificial Intelligence & Machine Learning (AI / ML)\n\nContinuing Education & Workforce Development\n\n\n\nDesigning with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices\n\nFPGA & SoC Assurance\n\n\n\nGuidelines and Standards\n\nOn-Orbit Experiments & Model Validation\n\n\n\nRadiation Hardness Assurance (RHA)\n\nSEE Test Facilities\n\n\n\nSEE in Devices & Circuits / Mechanisms & Modeling\n\nSpace Environments\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/see-mapld-2024/ LOCATION:Marriott La Jolla\, 4240 La Jolla Village Drive\, La Jolla\, CA\, United States CATEGORIES:EDA,IP,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEE-MAPLD.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240509T173000 DTEND;TZID=America/Los_Angeles:20240509T203000 DTSTAMP:20240328T160417Z CREATED:20240328T160417Z LAST-MODIFIED:20240328T160417Z UID:7787-1715275800-1715286600@marketingeda.com SUMMARY:ESD Alliance CEO/Executive Outlook DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/ LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240509T150000 DTEND;TZID=Asia/Tokyo:20240509T160000 DTSTAMP:20240429T161300Z CREATED:20240429T161300Z LAST-MODIFIED:20240429T161300Z UID:7922-1715266800-1715270400@marketingeda.com SUMMARY:Innovative Approach to SoC Power Optimization DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240509T083000 DTEND;TZID=America/Los_Angeles:20240509T170000 DTSTAMP:20240415T181329Z CREATED:20240415T181329Z LAST-MODIFIED:20240415T181329Z UID:7853-1715243400-1715274000@marketingeda.com SUMMARY:TSMC Technology Workshop 2024 - Boston DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-technology-workshop-2024-boston/ LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States CATEGORIES:EDA,Foundry,IP,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240507T090000 DTEND;TZID=Europe/Berlin:20240507T220000 DTSTAMP:20240429T170320Z CREATED:20240429T170320Z LAST-MODIFIED:20240429T170320Z UID:7928-1715072400-1715119200@marketingeda.com SUMMARY:User2User Europe 2024 DESCRIPTION:User2User is the perfect opportunity to learn\, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. \nDedicated to end-users of Siemens EDA solutions\, this conference is free to attend and includes innovative keynotes from industry leaders\, enriching technical sessions as well as a chance to network with colleagues and peers. \nThe full programme includes papers on these topics\n\nDesign For Test & Embedded Analytics\nElectronic System Design/PCB Design analysis and manufacturing\nFunctional Design & Verification\nHardware Assisted Verification\nHigh Level Synthesis: Digital design in C++/SystemC\nCustom IC Verification\nIC Backend\nSemiconductor packaging design\, analysis and manufacturing\n\nKeynotes\nEnabling imagination – An integrated approach to system design – Mike Ellow \nMike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America. \nDelivering Silicon at Cloud Scale – Ronen Laviv \nRonen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel. \nTechnical breakouts\n\nIC Backend Track 1\n\nImproving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning\nSignoff with Calibre as platform independent application\nUtilizing Calibre Tools for Chipfinishing within a Markefile\n\n\nIC Backend Track 2\n\nPERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies\nMission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower\n\n\nCustom IC Verification\n\nSymphony Pro enablement in STMicroelectronics SmartPower Technologies\nHow AWS cloud compute helps scale custom IC verification workloads\nPLL Design and Simulation using the Advanced SPICE technology\nAccelerating verification of high frequency PLLs for Wireless Application in a Smarter World\n\n\nDesign for Test & Embedded Analytics\n\nAdvancing DFT with the Power of AI: Grand challenges\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/user2user-europe-2024/ LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240507T080000 DTEND;TZID=America/Los_Angeles:20240508T170000 DTSTAMP:20240503T163652Z CREATED:20240419T171240Z LAST-MODIFIED:20240503T163652Z UID:7877-1715068800-1715187600@marketingeda.com SUMMARY:ChipEx 2024 DESCRIPTION:ChipEx2024\, the largest annual event of the Israeli semiconductor industry\, will be held on May 7-8\, 2024 in Tel Aviv\, Israel. ChipEx2024 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2024 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2024 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2024 exhibition will take place on May 7\, 2024 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2024 technical seminar will take place on May 7\, 2024 at the Tel-Aviv Expo Center. \nChipEx2024 Executive Summit \nThe Closing session of ChipEx2024 will take place on May 8\, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe. \nChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \nWe invite you to take part in ChipEx2024 as an exhibitor\, a speaker and/or as a sponsor. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chipex-2024/ LOCATION:Tel Aviv Convention Center\, Rokach Boulevard 101\, Tel Aviv\, Israel CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240502T083000 DTEND;TZID=America/Los_Angeles:20240502T173000 DTSTAMP:20240415T181052Z CREATED:20240415T181052Z LAST-MODIFIED:20240415T181052Z UID:7850-1714638600-1714671000@marketingeda.com SUMMARY:TSMC 2024 Technology Workshop – Austin DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/tsmc-2024-technology-workshop-austin/ LOCATION:JW Marriott Austin\, 110 E 2nd St\, Austin\, TX\, United States CATEGORIES:EDA,Foundry,IP,Semiconductor,Workshop ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240430T080000 DTEND;TZID=America/Los_Angeles:20240501T170000 DTSTAMP:20240416T193144Z CREATED:20240416T193144Z LAST-MODIFIED:20240416T193144Z UID:7866-1714464000-1714582800@marketingeda.com SUMMARY:CXL DevCon 2024 DESCRIPTION:The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1\, 2024\, in Santa Clara\, California! \nCXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training\, view available products and technology demonstrations\, and network with industry peers. \nRegister for the event HERE. \nIf you are not currently a member of the CXL Consortium\, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information. \n  \nCONFERENCE PROGRAM \n\n\n\n\n\n\n\nDevCon 2024 Day 1 – Compliance & Implementation\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 9:00\nRegistration\n\n\n\n9:00 – 9:15\nWelcome\nJim Pappas\, Intel – CXL Chairman\n\n\n9:15 – 9:45\nKeynote – History of CXL\nLarrie Carr\, Rambus – CXL President\n\n\n9:45 – 10:15\nCXL Specifications Overview\nDebendra Das Sharma\, Intel – TTF Co-Chair\n\n\n10:15 – 10:45\nCoffee Break & Exhibit\n\n\n\n10:45 – 11:30\nTechnical Spec Training (1.0/2.0)\nMahesh Wagh\, AMD – TTF Co-Chair\n\n\n11:30 – 12:00\nCXL Use Case – CXL Native Memory\nBill Gervasi\, Wolley\n\n\n12:00 – 1:00\nLunch & Exhibit\n\n\n\n1:00 – 1:20\nProving CXL scale-out and ROI in the data center\nIra Weiny\, Linux\n\n\n1:20 – 1:40\nCXL Software Ecosystem: The Software Stack for CXL\nSteve Scargall\, MemVerge\n\n\n1:40 – 2:00\nExploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework\nMichael Aguilar\, OpenFabrics Alliance – OFA Secretary\n\n\n2:00 – 2:20\nRAS for Resilient Data Centric Platforms using a CXL Memory Controller\nSandeep Dattaprasad\, Astera Labs\n\n\n2:20 – 2:40\nMember Implementation: CXL Memory Latency Measurement Tutorial\nTam Do\, Microchip\n\n\n2:40 – 3:10\nBreak & Exhibit\n\n\n\n3:10 – 3:30\nUnderstanding the Need for Compliance\nAnil Godbole\, Intel\n\n\n3:30 – 3:50\nTesting CXL links using Exercisers & Analyzers\nYamini Shastry\, Viavi\n\n\n3:50 – 4:10\nCXL Testing – Protocol Layers & Testing Examples\nGordon Getty\, Teledyne LeCroy\n\n\n4:10 – 4:40\nFocusing on the Future of CXL Compliance\nNathan White\, Intel – CWG Co-Chair\n\n\n4:40 – 5:00\nDay 1 Open Q&A\nCWG / TTF Panel\n\n\n5:00 – 6:30\nNetworking Reception & Exhibit\n\n\n\n\n  \n\n\n\n\n\n\n\nDevCon 2024 Day 2 – Emerging & Future\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 8:30\nRegistration and Exhibit\n\n\n\n8:30 – 9:30\nTechnical Spec Training (3.0/3.1)\nRob Blankenship\, Intel – PWG Co-Chair\n\n\n9:30 – 10:00\nMember Implementation: Streamlining CXL Adoption for Hyperscale Efficiency\nNilesh Shah\, ZeroPoint Technologies\n\n\n10:00 – 10:30\nTechnical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL\nZongyao Wen\, Synopsys\n\n\n10:30 – 11:00\nCoffee Break & Exhibit\n\n\n\n11:00 – 11:20\nMember Implementation\nDr. Miryeong Kwon\, Panmnesia\n\n\n11:20 – 11:40\nMember Implementation\nGeof Findley\, Montage Technology\n\n\n11:40 – 12:10\nMember Implementation: Using a CXL 2.0 switch for CXL memory expansion\, pooling and sharing\nJianping (JP) Jiang\, PhD\, Xconn Technologies\n\n\n12:10 – 12:30\nMember Implementation: Building Composable and Disaggregated Systems of the Future with CXL 3.0\nRaju Pudota\, Cadence\n\n\n12:30 – 1:30\nLunch & Exhibit\n\n\n\n1:30 – 1:50\nMember Implementation: Improving system memory bandwidth with CXL software interweaving\nRavi Kiran Gummaluri\, Micron\n\n\n1:50 – 2:10\nMember Implementation: Exploring system memory expansion and memory pooling/tiering\nKapil Sethi\, Samsung\n\n\n2:10 -2:30\nMember Implementation: Enabling CXL Memory Module\, Exploring Memory Expansion Use Cases & Beyond\nThomas Won Ha Choi\, PhD\, SK hynix\n\n\n2:30 – 2:50\nMember Implementation: Optical Applications of CXL\nDavid Kulansky\, Alphawave Semi\n\n\n2:50 – 3:30\nBreak & Exhibit\n\n\n\n3:30 – 4:30\nFireside chat – open discussion + audience Q&A\nLeadership Panel\n\n\n4:30 – 5:00\nClosing comments and Call to Action\nKurtis Bowman\, AMD – MWG Co-Chair\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cxl-devcon-2024/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CXL-DevCon-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240429T100000 DTEND;TZID=Europe/London:20240429T143000 DTSTAMP:20240322T163227Z CREATED:20240322T163227Z LAST-MODIFIED:20240322T163227Z UID:7746-1714384800-1714401000@marketingeda.com SUMMARY:TechNES FPGA Front Runner Event DESCRIPTION:The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. \nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/technes-fpga-front-runner-event/ LOCATION:New Mills\, Wotton-under-Edge\, GL12 8JR\, United Kingdom CATEGORIES:Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-29-April-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240425T090000 DTEND;TZID=America/New_York:20240425T100000 DTSTAMP:20240401T180250Z CREATED:20240401T180042Z LAST-MODIFIED:20240401T180250Z UID:7797-1714035600-1714039200@marketingeda.com SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T080000 DTEND;TZID=America/Los_Angeles:20240425T170000 DTSTAMP:20240410T171939Z CREATED:20240410T171409Z LAST-MODIFIED:20240410T171939Z UID:7830-1714032000-1714064400@marketingeda.com SUMMARY:IP-SoC Silicon Valley 2024 DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ip-soc-silicon-valley-2024/ LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-24.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240421T080000 DTEND;TZID=America/Los_Angeles:20240424T170000 DTSTAMP:20240419T164318Z CREATED:20240419T164152Z LAST-MODIFIED:20240419T164318Z UID:7873-1713686400-1713978000@marketingeda.com SUMMARY:CICC 2024 DESCRIPTION:The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cicc-2024/ LOCATION:DoubleTree by Hilton Denver\, 3203 Quebec Street\, Denver\, CO\, United States CATEGORIES:Conference,EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240419T080000 DTEND;TZID=America/Los_Angeles:20240421T170000 DTSTAMP:20240408T222220Z CREATED:20240212T205659Z LAST-MODIFIED:20240408T222220Z UID:7610-1713513600-1713718800@marketingeda.com SUMMARY:Latch-Up 2024: Boston DESCRIPTION:Friday to Sunday April 19–21\, 2024 in Boston\, MA\, USA \nThe Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It’s an event for the open source digital design community\, much like its European sister conference ORConf\, run by the FOSSi Foundation. \n\n\n\n\n\nYou are all invited!\nThe FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston\, MA\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and submit a presentation or proposal if you have a project or idea on the topic to share! \nQuestions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org. \n\n\n\nSubmit a talk\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nTickets and registration\nAttendance of Latch-Up is free of charge. To help us organizing the event\, you are required to register on Eventbrite. Please register as soon as possible\, as we have to close registrations as soon as the room capacity is reached. \nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nFriday\n\n\n\nWhen\nWhat\n\n\n\n\n9:00\nWelcome\n\n\n9:20\nCaster: An Open-source E-Ink Controller\n\n\n9:40\nTeaching Modern EDA using a Tapeout-Centric University Course\n\n\n10:00\nBreak\n\n\n10:20\nCedarEDA for open source silicon\n\n\n10:40\nCohort: Software-Oriented Acceleration for You\, Me\, and Our Heterogeneous SoCs\n\n\n11:00\nTowards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture\n\n\n11:20\nLunch\n\n\n12:20\nTowards Cycle-accurate Simulation of xBGAS\n\n\n12:40\nArtifact Evaluation for the Field Programmable Gate Array Community\n\n\n13:00\nChisel 6 and beyond\n\n\n13:20\nMRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL\n\n\n13:40\nBreak\n\n\n14:40\nRiding The Wave: Building Wave Pipelines in FPGAs\n\n\n15:00\nGiving Students A Byte of Open-Source: Advancing Hardware Education\n\n\n15:20\nBreak\n\n\n15:40\nOpen-source resources for learning the Bluespec HL-HDLs\n\n\n16:00\nPyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface\n\n\n16:20\nTransition to Draper\n\n\n17:00\nTalks(30-40m) at Draper\n\n\n18:00\nTransition to lightning Talks\n\n\n19:00\nLightning Talks\n\n\n20:00\nGo home\n\n\n\nSaturday\n\n\n\nWhen\nWhat\n\n\n\n\n8:40\nWelcome\n\n\n9:00\nOpen source RTL verification with Verilator\n\n\n9:20\nSonata: A development platform to enable exploring the use of CHERI for embedded applications\n\n\n9:40\nTransparent Checkpointing for Fault Tolerance in RISC-V\n\n\n10:00\nBreak\n\n\n10:20\nHDLAgent\, Enhancing Hardware Language in the age of LLMs\n\n\n10:40\nSpade: An HDL Inspired By Modern Software Languages\n\n\n11:00\nSwitchboard: Calling All Hardware Models\n\n\n11:20\nLunch\n\n\n12:20\nFrom an Open-Source ISA to Open-Source HW to Open-Source Silicon\n\n\n12:40\nOpen Source Hardware: Hacking Silicon for Fun (instead of profit)\n\n\n13:00\nA History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation\n\n\n13:20\nUMI: Universal Memory Interface\n\n\n13:40\nBreak\n\n\n14:20\nABC: The Way It Should Have Been Designed\n\n\n14:40\nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\n\n\n15:00\nBeyond EDA lies Edalize\n\n\n15:20\nBreak\n\n\n15:40\nRF Front-end receiver design for 2.4GH/5GHz WiFi application\n\n\n16:00\nCACE Study: Open source analog and mixed-signal design flow\n\n\n16:20\nIHP Open Source PDK: Announcement\, Setup\, Current State and Experiences\, and look ahead\n\n\n16:40\nTiny Tapeout: custom silicon open to all\n\n\n17:20\nMeet at Flattops\n\n\n\nSunday\nComing soon \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/latch-up-2024-boston/ LOCATION:Massachusetts Institute of Technology\, 77 Massachusetts Avenue\, Boston\, MA\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240418T150000 DTEND;TZID=Asia/Tokyo:20240418T160000 DTSTAMP:20240415T174855Z CREATED:20240415T174855Z LAST-MODIFIED:20240415T174855Z UID:7844-1713452400-1713456000@marketingeda.com SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240418T100000 DTEND;TZID=America/Los_Angeles:20240418T110000 DTSTAMP:20240415T175505Z CREATED:20240415T175505Z LAST-MODIFIED:20240415T175505Z UID:7847-1713434400-1713438000@marketingeda.com SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240417T081500 DTEND;TZID=America/Los_Angeles:20240417T170000 DTSTAMP:20240306T181435Z CREATED:20240306T181435Z LAST-MODIFIED:20240306T181435Z UID:7716-1713341700-1713373200@marketingeda.com SUMMARY:CadenceLIVE Silicon Valley 2024 DESCRIPTION:Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings users\, developers\, and industry experts together to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend engaging user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot. \n\n\nApril 17\, 2024 08:15\n\nRegistration\n\n\n\n\n\n\nApril 17\, 2024 09:00\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 10:15\n\nKeynotes\n\n\n\n\n\n\nApril 17\, 2024 11:45\n\nDesigner Expo and Lunch\n\n\n\n\n\n\nApril 17\, 2024 13:15\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 15:45\n\nClosing Keynote\n\n\n\n\n\n\nApril 17\, 2024 16:30\n\nDesigner Expo / Reception / Awards\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cadencelive-silicon-valley-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240417T080000 DTEND;TZID=America/Los_Angeles:20240417T090000 DTSTAMP:20240327T173831Z CREATED:20240327T173831Z LAST-MODIFIED:20240327T173831Z UID:7774-1713340800-1713344400@marketingeda.com SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240409T080000 DTEND;TZID=Europe/Berlin:20240411T170000 DTSTAMP:20240403T194345Z CREATED:20240119T022657Z LAST-MODIFIED:20240403T194345Z UID:7529-1712649600-1712854800@marketingeda.com SUMMARY:Embedded World 2024 DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nKnowledge platform #ew24\nKnow-how at the highest level\nAt the embedded world Conference and the electronic displays Conference\, top-class speakers from research\, development and practice will share their knowledge with you. They discuss the state of the art and possible future developments in the industry. The exhibitor’s forums and top-class discussion panels in the halls also contribute to the high-quality transfer of knowledge. Current topics will be highlighted in numerous expert lectures and panels. And\, of course\, there will be opportunities for intensive technical discussions. \nGuided tours\, tours for trainees and students and special presentations as well as the networking event for women in the embedded systems industry #women4ew complete the offer. \nThe No. 1 hub for the international embedded community\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts! \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/embedded-world-2024/ LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-World-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240403T080000 DTEND;TZID=America/Los_Angeles:20240404T170000 DTSTAMP:20240212T202640Z CREATED:20240212T202640Z LAST-MODIFIED:20240212T202640Z UID:7607-1712131200-1712250000@marketingeda.com SUMMARY:Siemens EDA User2User Conference DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/siemens-eda-user2user-conference/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg END:VEVENT END:VCALENDAR