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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T173000
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DTSTAMP:20240328T160417Z
CREATED:20240328T160417Z
LAST-MODIFIED:20240328T160417Z
UID:7787-1715275800-1715286600@marketingeda.com
SUMMARY:ESD Alliance CEO/Executive Outlook
DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T083000
DTEND;TZID=America/Los_Angeles:20240509T170000
DTSTAMP:20240415T181329Z
CREATED:20240415T181329Z
LAST-MODIFIED:20240415T181329Z
UID:7853-1715243400-1715274000@marketingeda.com
SUMMARY:TSMC Technology Workshop 2024 - Boston
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/tsmc-technology-workshop-2024-boston/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,Foundry,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240507T090000
DTEND;TZID=Europe/Berlin:20240507T220000
DTSTAMP:20240429T170320Z
CREATED:20240429T170320Z
LAST-MODIFIED:20240429T170320Z
UID:7928-1715072400-1715119200@marketingeda.com
SUMMARY:User2User Europe 2024
DESCRIPTION:User2User is the perfect opportunity to learn\, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. \nDedicated to end-users of Siemens EDA solutions\, this conference is free to attend and includes innovative keynotes from industry leaders\, enriching technical sessions as well as a chance to network with colleagues and peers. \nThe full programme includes papers on these topics\n\nDesign For Test & Embedded Analytics\nElectronic System Design/PCB Design analysis and manufacturing\nFunctional Design & Verification\nHardware Assisted Verification\nHigh Level Synthesis: Digital design in C++/SystemC\nCustom IC Verification\nIC Backend\nSemiconductor packaging design\, analysis and manufacturing\n\nKeynotes\nEnabling imagination – An integrated approach to system design – Mike Ellow \nMike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America. \nDelivering Silicon at Cloud Scale – Ronen Laviv \nRonen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel. \nTechnical breakouts\n\nIC Backend Track 1\n\nImproving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning\nSignoff with Calibre as platform independent application\nUtilizing Calibre Tools for Chipfinishing within a Markefile\n\n\nIC Backend Track 2\n\nPERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies\nMission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower\n\n\nCustom IC Verification\n\nSymphony Pro enablement in STMicroelectronics SmartPower Technologies\nHow AWS cloud compute helps scale custom IC verification workloads\nPLL Design and Simulation using the Advanced SPICE technology\nAccelerating verification of high frequency PLLs for Wireless Application in a Smarter World\n\n\nDesign for Test & Embedded Analytics\n\nAdvancing DFT with the Power of AI: Grand challenges\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/user2user-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240507T080000
DTEND;TZID=America/Los_Angeles:20240508T170000
DTSTAMP:20240503T163652Z
CREATED:20240419T171240Z
LAST-MODIFIED:20240503T163652Z
UID:7877-1715068800-1715187600@marketingeda.com
SUMMARY:ChipEx 2024
DESCRIPTION:ChipEx2024\, the largest annual event of the Israeli semiconductor industry\, will be held on May 7-8\, 2024 in Tel Aviv\, Israel. ChipEx2024 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2024 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2024 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2024 exhibition will take place on May 7\, 2024 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2024 technical seminar will take place on May 7\, 2024 at the Tel-Aviv Expo Center. \nChipEx2024 Executive Summit \nThe Closing session of ChipEx2024 will take place on May 8\, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe. \nChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \nWe invite you to take part in ChipEx2024 as an exhibitor\, a speaker and/or as a sponsor. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/chipex-2024/
LOCATION:Tel Aviv Convention Center\, Rokach Boulevard 101\, Tel Aviv\, Israel
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T083000
DTEND;TZID=America/Los_Angeles:20240502T173000
DTSTAMP:20240415T181052Z
CREATED:20240415T181052Z
LAST-MODIFIED:20240415T181052Z
UID:7850-1714638600-1714671000@marketingeda.com
SUMMARY:TSMC 2024 Technology Workshop – Austin
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/tsmc-2024-technology-workshop-austin/
LOCATION:JW Marriott Austin\, 110 E 2nd St\, Austin\, TX\, United States
CATEGORIES:EDA,Foundry,IP,Semiconductor,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T080000
DTEND;TZID=America/Los_Angeles:20240501T170000
DTSTAMP:20240416T193144Z
CREATED:20240416T193144Z
LAST-MODIFIED:20240416T193144Z
UID:7866-1714464000-1714582800@marketingeda.com
SUMMARY:CXL DevCon 2024
DESCRIPTION:The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1\, 2024\, in Santa Clara\, California! \nCXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training\, view available products and technology demonstrations\, and network with industry peers. \nRegister for the event HERE. \nIf you are not currently a member of the CXL Consortium\, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information. \n  \nCONFERENCE PROGRAM \n\n\n\n\n\n\n\nDevCon 2024 Day 1 – Compliance & Implementation\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 9:00\nRegistration\n\n\n\n9:00 – 9:15\nWelcome\nJim Pappas\, Intel – CXL Chairman\n\n\n9:15 – 9:45\nKeynote – History of CXL\nLarrie Carr\, Rambus – CXL President\n\n\n9:45 – 10:15\nCXL Specifications Overview\nDebendra Das Sharma\, Intel – TTF Co-Chair\n\n\n10:15 – 10:45\nCoffee Break & Exhibit\n\n\n\n10:45 – 11:30\nTechnical Spec Training (1.0/2.0)\nMahesh Wagh\, AMD – TTF Co-Chair\n\n\n11:30 – 12:00\nCXL Use Case – CXL Native Memory\nBill Gervasi\, Wolley\n\n\n12:00 – 1:00\nLunch & Exhibit\n\n\n\n1:00 – 1:20\nProving CXL scale-out and ROI in the data center\nIra Weiny\, Linux\n\n\n1:20 – 1:40\nCXL Software Ecosystem: The Software Stack for CXL\nSteve Scargall\, MemVerge\n\n\n1:40 – 2:00\nExploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework\nMichael Aguilar\, OpenFabrics Alliance – OFA Secretary\n\n\n2:00 – 2:20\nRAS for Resilient Data Centric Platforms using a CXL Memory Controller\nSandeep Dattaprasad\, Astera Labs\n\n\n2:20 – 2:40\nMember Implementation: CXL Memory Latency Measurement Tutorial\nTam Do\, Microchip\n\n\n2:40 – 3:10\nBreak & Exhibit\n\n\n\n3:10 – 3:30\nUnderstanding the Need for Compliance\nAnil Godbole\, Intel\n\n\n3:30 – 3:50\nTesting CXL links using Exercisers & Analyzers\nYamini Shastry\, Viavi\n\n\n3:50 – 4:10\nCXL Testing – Protocol Layers & Testing Examples\nGordon Getty\, Teledyne LeCroy\n\n\n4:10 – 4:40\nFocusing on the Future of CXL Compliance\nNathan White\, Intel – CWG Co-Chair\n\n\n4:40 – 5:00\nDay 1 Open Q&A\nCWG / TTF Panel\n\n\n5:00 – 6:30\nNetworking Reception & Exhibit\n\n\n\n\n  \n\n\n\n\n\n\n\nDevCon 2024 Day 2 – Emerging & Future\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 8:30\nRegistration and Exhibit\n\n\n\n8:30 – 9:30\nTechnical Spec Training (3.0/3.1)\nRob Blankenship\, Intel – PWG Co-Chair\n\n\n9:30 – 10:00\nMember Implementation: Streamlining CXL Adoption for Hyperscale Efficiency\nNilesh Shah\, ZeroPoint Technologies\n\n\n10:00 – 10:30\nTechnical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL\nZongyao Wen\, Synopsys\n\n\n10:30 – 11:00\nCoffee Break & Exhibit\n\n\n\n11:00 – 11:20\nMember Implementation\nDr. Miryeong Kwon\, Panmnesia\n\n\n11:20 – 11:40\nMember Implementation\nGeof Findley\, Montage Technology\n\n\n11:40 – 12:10\nMember Implementation: Using a CXL 2.0 switch for CXL memory expansion\, pooling and sharing\nJianping (JP) Jiang\, PhD\, Xconn Technologies\n\n\n12:10 – 12:30\nMember Implementation: Building Composable and Disaggregated Systems of the Future with CXL 3.0\nRaju Pudota\, Cadence\n\n\n12:30 – 1:30\nLunch & Exhibit\n\n\n\n1:30 – 1:50\nMember Implementation: Improving system memory bandwidth with CXL software interweaving\nRavi Kiran Gummaluri\, Micron\n\n\n1:50 – 2:10\nMember Implementation: Exploring system memory expansion and memory pooling/tiering\nKapil Sethi\, Samsung\n\n\n2:10 -2:30\nMember Implementation: Enabling CXL Memory Module\, Exploring Memory Expansion Use Cases & Beyond\nThomas Won Ha Choi\, PhD\, SK hynix\n\n\n2:30 – 2:50\nMember Implementation: Optical Applications of CXL\nDavid Kulansky\, Alphawave Semi\n\n\n2:50 – 3:30\nBreak & Exhibit\n\n\n\n3:30 – 4:30\nFireside chat – open discussion + audience Q&A\nLeadership Panel\n\n\n4:30 – 5:00\nClosing comments and Call to Action\nKurtis Bowman\, AMD – MWG Co-Chair\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/cxl-devcon-2024/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CXL-DevCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240429T100000
DTEND;TZID=Europe/London:20240429T143000
DTSTAMP:20240322T163227Z
CREATED:20240322T163227Z
LAST-MODIFIED:20240322T163227Z
UID:7746-1714384800-1714401000@marketingeda.com
SUMMARY:TechNES FPGA Front Runner Event
DESCRIPTION:The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. \nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/technes-fpga-front-runner-event/
LOCATION:New Mills\, Wotton-under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-29-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T080000
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240410T171939Z
CREATED:20240410T171409Z
LAST-MODIFIED:20240410T171939Z
UID:7830-1714032000-1714064400@marketingeda.com
SUMMARY:IP-SoC Silicon Valley 2024
DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/ip-soc-silicon-valley-2024/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-24.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240421T080000
DTEND;TZID=America/Los_Angeles:20240424T170000
DTSTAMP:20240419T164318Z
CREATED:20240419T164152Z
LAST-MODIFIED:20240419T164318Z
UID:7873-1713686400-1713978000@marketingeda.com
SUMMARY:CICC 2024
DESCRIPTION:The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/cicc-2024/
LOCATION:DoubleTree by Hilton Denver\, 3203 Quebec Street\, Denver\, CO\, United States
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240419T080000
DTEND;TZID=America/Los_Angeles:20240421T170000
DTSTAMP:20240408T222220Z
CREATED:20240212T205659Z
LAST-MODIFIED:20240408T222220Z
UID:7610-1713513600-1713718800@marketingeda.com
SUMMARY:Latch-Up 2024: Boston
DESCRIPTION:Friday to Sunday April 19–21\, 2024 in Boston\, MA\, USA \nThe Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It’s an event for the open source digital design community\, much like its European sister conference ORConf\, run by the FOSSi Foundation. \n\n\n\n\n\nYou are all invited!\nThe FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston\, MA\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and submit a presentation or proposal if you have a project or idea on the topic to share! \nQuestions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org. \n\n\n\nSubmit a talk\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nTickets and registration\nAttendance of Latch-Up is free of charge. To help us organizing the event\, you are required to register on Eventbrite. Please register as soon as possible\, as we have to close registrations as soon as the room capacity is reached. \nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nFriday\n\n\n\nWhen\nWhat\n\n\n\n\n9:00\nWelcome\n\n\n9:20\nCaster: An Open-source E-Ink Controller\n\n\n9:40\nTeaching Modern EDA using a Tapeout-Centric University Course\n\n\n10:00\nBreak\n\n\n10:20\nCedarEDA for open source silicon\n\n\n10:40\nCohort: Software-Oriented Acceleration for You\, Me\, and Our Heterogeneous SoCs\n\n\n11:00\nTowards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture\n\n\n11:20\nLunch\n\n\n12:20\nTowards Cycle-accurate Simulation of xBGAS\n\n\n12:40\nArtifact Evaluation for the Field Programmable Gate Array Community\n\n\n13:00\nChisel 6 and beyond\n\n\n13:20\nMRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL\n\n\n13:40\nBreak\n\n\n14:40\nRiding The Wave: Building Wave Pipelines in FPGAs\n\n\n15:00\nGiving Students A Byte of Open-Source: Advancing Hardware Education\n\n\n15:20\nBreak\n\n\n15:40\nOpen-source resources for learning the Bluespec HL-HDLs\n\n\n16:00\nPyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface\n\n\n16:20\nTransition to Draper\n\n\n17:00\nTalks(30-40m) at Draper\n\n\n18:00\nTransition to lightning Talks\n\n\n19:00\nLightning Talks\n\n\n20:00\nGo home\n\n\n\nSaturday\n\n\n\nWhen\nWhat\n\n\n\n\n8:40\nWelcome\n\n\n9:00\nOpen source RTL verification with Verilator\n\n\n9:20\nSonata: A development platform to enable exploring the use of CHERI for embedded applications\n\n\n9:40\nTransparent Checkpointing for Fault Tolerance in RISC-V\n\n\n10:00\nBreak\n\n\n10:20\nHDLAgent\, Enhancing Hardware Language in the age of LLMs\n\n\n10:40\nSpade: An HDL Inspired By Modern Software Languages\n\n\n11:00\nSwitchboard: Calling All Hardware Models\n\n\n11:20\nLunch\n\n\n12:20\nFrom an Open-Source ISA to Open-Source HW to Open-Source Silicon\n\n\n12:40\nOpen Source Hardware: Hacking Silicon for Fun (instead of profit)\n\n\n13:00\nA History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation\n\n\n13:20\nUMI: Universal Memory Interface\n\n\n13:40\nBreak\n\n\n14:20\nABC: The Way It Should Have Been Designed\n\n\n14:40\nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\n\n\n15:00\nBeyond EDA lies Edalize\n\n\n15:20\nBreak\n\n\n15:40\nRF Front-end receiver design for 2.4GH/5GHz WiFi application\n\n\n16:00\nCACE Study: Open source analog and mixed-signal design flow\n\n\n16:20\nIHP Open Source PDK: Announcement\, Setup\, Current State and Experiences\, and look ahead\n\n\n16:40\nTiny Tapeout: custom silicon open to all\n\n\n17:20\nMeet at Flattops\n\n\n\nSunday\nComing soon \n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/latch-up-2024-boston/
LOCATION:Massachusetts Institute of Technology\, 77 Massachusetts Avenue\, Boston\, MA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240418T150000
DTEND;TZID=Asia/Tokyo:20240418T160000
DTSTAMP:20240415T174855Z
CREATED:20240415T174855Z
LAST-MODIFIED:20240415T174855Z
UID:7844-1713452400-1713456000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240418T100000
DTEND;TZID=America/Los_Angeles:20240418T110000
DTSTAMP:20240415T175505Z
CREATED:20240415T175505Z
LAST-MODIFIED:20240415T175505Z
UID:7847-1713434400-1713438000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T081500
DTEND;TZID=America/Los_Angeles:20240417T170000
DTSTAMP:20240306T181435Z
CREATED:20240306T181435Z
LAST-MODIFIED:20240306T181435Z
UID:7716-1713341700-1713373200@marketingeda.com
SUMMARY:CadenceLIVE Silicon Valley 2024
DESCRIPTION:Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings users\, developers\, and industry experts together to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend engaging user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot. \n\n\nApril 17\, 2024 08:15\n\nRegistration\n\n\n\n\n\n\nApril 17\, 2024 09:00\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 10:15\n\nKeynotes\n\n\n\n\n\n\nApril 17\, 2024 11:45\n\nDesigner Expo and Lunch\n\n\n\n\n\n\nApril 17\, 2024 13:15\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 15:45\n\nClosing Keynote\n\n\n\n\n\n\nApril 17\, 2024 16:30\n\nDesigner Expo / Reception / Awards\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/cadencelive-silicon-valley-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T080000
DTEND;TZID=America/Los_Angeles:20240417T090000
DTSTAMP:20240327T173831Z
CREATED:20240327T173831Z
LAST-MODIFIED:20240327T173831Z
UID:7774-1713340800-1713344400@marketingeda.com
SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem
DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/
LOCATION:MA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240409T080000
DTEND;TZID=Europe/Berlin:20240411T170000
DTSTAMP:20240403T194345Z
CREATED:20240119T022657Z
LAST-MODIFIED:20240403T194345Z
UID:7529-1712649600-1712854800@marketingeda.com
SUMMARY:Embedded World 2024
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nKnowledge platform #ew24\nKnow-how at the highest level\nAt the embedded world Conference and the electronic displays Conference\, top-class speakers from research\, development and practice will share their knowledge with you. They discuss the state of the art and possible future developments in the industry. The exhibitor’s forums and top-class discussion panels in the halls also contribute to the high-quality transfer of knowledge. Current topics will be highlighted in numerous expert lectures and panels. And\, of course\, there will be opportunities for intensive technical discussions. \nGuided tours\, tours for trainees and students and special presentations as well as the networking event for women in the embedded systems industry #women4ew complete the offer. \nThe No. 1 hub for the international embedded community\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts! \n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/embedded-world-2024/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-World-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240403T080000
DTEND;TZID=America/Los_Angeles:20240404T170000
DTSTAMP:20240212T202640Z
CREATED:20240212T202640Z
LAST-MODIFIED:20240212T202640Z
UID:7607-1712131200-1712250000@marketingeda.com
SUMMARY:Siemens EDA User2User Conference
DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive! \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/siemens-eda-user2user-conference/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240402T100000
DTEND;TZID=America/Los_Angeles:20240402T110000
DTSTAMP:20240327T160224Z
CREATED:20240327T160224Z
LAST-MODIFIED:20240327T160224Z
UID:7768-1712052000-1712055600@marketingeda.com
SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power
DESCRIPTION:*Work email required for registration*  \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp.  \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS  \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS* \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240320T080000
DTEND;TZID=America/Los_Angeles:20240321T170000
DTSTAMP:20240305T220415Z
CREATED:20240305T220415Z
LAST-MODIFIED:20240305T220415Z
UID:7710-1710921600-1711040400@marketingeda.com
SUMMARY:SNUG Silicon Valley 2024
DESCRIPTION:Connecting the Synopsys User Community\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nTechnical Committee\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. \nTechnical Committee Chair: \nDon Mills\, Microchip \nCommittee Members: \nAnand Iyer\, Synopsys \nAndy Copperhall\, Independent \nAnwarul Hasan\, Independent \nBrian Kane\, Northrop Grumman \nBryan Morris\, Ciena \nChris Kiegle\, Marvell Semiconductor \nCliff Cummings\, Paradigm Works \nFirouzeh Nourkhalaj\, Synopsys \nGlen McDonnell\, Broadcom \nHongda Lu\, SARC \nJack Dong\, Intel \nJason Rziha\, Microchip \nJeff Montesano\, Meta \nJing Zhang\, Intel \nJohn Thomson\, NVIDIA \nJohn Wei\, Independent \nJon Colburn\, NVIDIA \nJT Longino\, Tesla \nKarthik Rajan\, Microchip \nLeah Clark\, Synopsys \nMark Sprague\, Intel \nNaveen Mysore\, Intel \nNeel Sonara\, Broadcom \nNitin Navale\, AMD \nOlivia Poon\, Marvell Semiconductor \nPinal Patel\, eInfochips \nRavikishore Gandikota\, NVIDIA \nRonald Goodstein\, Lockheed Martin \nRonald Kalim\, Intel \nSachin Parikh\, Broadcom \nSangeetha Chandran Sarala\, Micron \nSathappan Palaniappan\, Broadcom \nSaurabh Bhadoriya\, NVIDIA \nSavita Banerjee\, Meta \nShaiful Alam\, Intel \nStella Matarrese\, Synopsys \nTom Mahatdejkul\, Arm \nTony Todesco\, AMD \nUpasna Vishnoi\, Marvell Semiconductor \nVictoria Kolesov\, Intel \nZafar Hasan\, NVIDIA \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/snug-silicon-valley-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNG-Silicon-Valley-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240313T080000
DTEND;TZID=Europe/London:20240314T170000
DTSTAMP:20240122T194453Z
CREATED:20240122T194453Z
LAST-MODIFIED:20240122T194453Z
UID:7549-1710316800-1710435600@marketingeda.com
SUMMARY:GSA International Semiconductor Conference
DESCRIPTION:Inaugural GSA event in partnership with the UK Government.  \nMeet senior business leaders\, investors\, and public policy officials from around the world. \nAcross two days\, join us for exciting discussions on semiconductor innovation for a NetZero economy\, with a view on the dramatically changing supply chain\, government interventions and industry outlook. \n  \nSemiconductor Innovation for NetZero (March 13-14) \n\nSupply Chain Resilience and national approaches to Semiconductor Policy\nDifferent government approaches to semiconductor policy\, supply chains and stimulating industry growth\nResource and talent development\, including raising the role of women in the industry\nCapital funding and IP strategies for start-ups and scale-ups\n\nWLI EMEA Kick-Off Event (March 13 morning) \n\nThe first GSA Women Leadership Initiative in Europe\nDiscuss the raising role of women in semiconductors\nHear lessons learned from women who have excelled in navigating a traditionally male-dominated industry\n\n\nTicket will cover both days\, all sections\nVIP Dinner will be held on the evening of March 13th: a separate ticket is required\, very limited seating available!\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/gsa-international-semiconductor-conference/
LOCATION:Here East\, 14 E Bay Lane\, London\, United Kingdom
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-March-13-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T090000
DTEND;TZID=America/Los_Angeles:20240307T100000
DTSTAMP:20240226T233450Z
CREATED:20240226T233450Z
LAST-MODIFIED:20240226T233450Z
UID:7690-1709802000-1709805600@marketingeda.com
SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure
DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240304T080000
DTEND;TZID=America/Los_Angeles:20240307T170000
DTSTAMP:20240216T181350Z
CREATED:20240103T171927Z
LAST-MODIFIED:20240216T181350Z
UID:7493-1709539200-1709830800@marketingeda.com
SUMMARY:DVCon USA 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/dvcon-usa-2024/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240226T123000
DTEND;TZID=America/Los_Angeles:20240226T164500
DTSTAMP:20240125T175450Z
CREATED:20240125T175450Z
LAST-MODIFIED:20240125T175450Z
UID:7556-1708950600-1708965900@marketingeda.com
SUMMARY:Synopsys Technical Forum 2024
DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/synopsys-technical-forum-2024/
LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Madrid:20240226T080000
DTEND;TZID=Europe/Madrid:20240229T170000
DTSTAMP:20240321T221956Z
CREATED:20231228T171623Z
LAST-MODIFIED:20240321T221956Z
UID:7473-1708934400-1709226000@marketingeda.com
SUMMARY:MWC 2024
DESCRIPTION:Where technology\, community and commerce converge\n\nMWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months. \n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/mwc-2024/
LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T090000
DTEND;TZID=America/Los_Angeles:20240221T100000
DTSTAMP:20240212T201810Z
CREATED:20240212T201810Z
LAST-MODIFIED:20240212T201810Z
UID:7604-1708506000-1708509600@marketingeda.com
SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering. \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/
LOCATION:MA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T080000
DTEND;TZID=America/Los_Angeles:20240221T180000
DTSTAMP:20240216T221430Z
CREATED:20240216T221430Z
LAST-MODIFIED:20240216T221430Z
UID:7637-1708502400-1708538400@marketingeda.com
SUMMARY:Intel Foundry Services (IFS) Direct Connect
DESCRIPTION:Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world’s first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick around for a panel discussion\, including industry leaders Rene Haas (Arm)\, Yuan Xing Lee (Broadcom)\, and Eric Fisher (MediaTek). \n\n\n\nWhat to Expect\n\n\n\n\n\n\n\n\n\nAll times in PST\nWednesday\, February 21\, 2024\n\n\n\n\n7:30am – 8:30am\nRegistration\, Breakfast\, and Demo Showcase\n\n\n8:30am – 9:30am\nPat Gelsinger and Stu Pann: A Systems Foundry for the AI Era with special appearances by: \n\nGina M. Raimondo\, United States Secretary of Commerce\nSatya Nadella\, Chairman and CEO\, Microsoft\nRene Haas\, CEO\, Arm\n\n\n\n\n9:30am – 10:00am\nCustomer Fireside Chat featuring: \n\nYuan Xing Lee\, VP of Central Engineering\, Broadcom\nEric Fisher\, President\, MediaTek North America\n\n\n\n\n10:00am – 10:30am\nAM Break and Demo Showcase\n\n\n10:30am – 12:00pm\nEcosystem Spotlight featuring: \n\nAart de Geus\, Executive Chair and Founder\, Synopsys\nMike Ellow\, Executive Vice President\, Siemens Digital Industries Software\nJohn Lee\, General Manager and Vice President for Electronics\, Semiconductors and Optics BU\, Ansys\nAnirudh Devgan\, President and CEO\, Cadence Design System\n\n\n\n\n12:00pm – 1:00pm\nNetworking Lunch and Demo Showcase\n\n\n1:00pm – 2:15pm\nDr. Ann Kelleher and Dr. Gary Patton: Delivering the Present and Inventing the Future: A Look Beyond 5N4Y\n\n\n2:15pm – 3:00pm\nDr. Choon Lee: Advanced Packaging and Test Solutions\n\n\n3:00pm – 3:20pm\nPM Break and Demo Showcase\n\n\n3:20pm – 3:50pm\nKeyvan Esfarjani: Transforming Intel Manufacturing featuring: \n\nJason Wang\, President\, UMC\n\n\n\n\n3:50pm – 4:00pm\nStu Pann: Wrap Up\n\n\n4:00pm – 4:45pm\nFireside Chat featuring: \n\nSam Altman\, Co-founder and CEO\, OpenAI\n\n\n\n\n4:45pm – 6:15pm\nNetworking Reception and Demo Showcase\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/intel-foundry-services-ifs-direct-connect/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IFS-Direct-Connect.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240218T080000
DTEND;TZID=America/Los_Angeles:20240222T170000
DTSTAMP:20231230T004304Z
CREATED:20231230T004304Z
LAST-MODIFIED:20231230T004304Z
UID:7483-1708243200-1708621200@marketingeda.com
SUMMARY:ISSCC 2024
DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/isscc-2024/
LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240215T123000
DTEND;TZID=Asia/Kolkata:20240215T170000
DTSTAMP:20240207T181103Z
CREATED:20240207T181103Z
LAST-MODIFIED:20240207T181103Z
UID:7591-1708000200-1708016400@marketingeda.com
SUMMARY:SiFive RISC-V Day
DESCRIPTION:Leadership in the RISC-V Era: India’s Exciting New Opportunity\nJoin SiFive for an informative afternoon session\, featuring key thought leaders in the fast -growing global RISC-V ecosystem. Krste Asanovic\, inventor of RISC-V and SiFive founder will be joined by academic and business leaders to provide an overview of RISC-V and the latest advances as well as talk about how RISC-V is a great opportunity for India to leap ahead in semiconductor technology leadership. \nIndia’s strengths in software and hardware design are helping it jump ahead as RISC-V takes hold around the world\, but the open standard brings a lot of competition from other regions. Our guests will discuss India’s strengths and talk about advances to date and how the country\, and the companies doing business here should think about the opportunities ahead. \nJoin us for SiFive RISC-V Day India on February 15\, 2024. Attend this free event to meet the pioneers driving RISC-V. A networking lunch will be held before the event. Don’t miss out! \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/sifive-risc-v-day/
LOCATION:Hilton Bangalore Embassy GolfLinks\, Embassy Golf Links Business Park\, Bangalore\, 560071\, India
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SiFive-February-15-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=Europe/Oslo:20240214T080000
DTEND;TZID=Europe/Oslo:20240215T170000
DTSTAMP:20240209T180613Z
CREATED:20240209T180613Z
LAST-MODIFIED:20240209T180613Z
UID:7599-1707897600-1708016400@marketingeda.com
SUMMARY:FPGA Forum 2024 - Norway
DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/fpga-forum-2024-norway/
LOCATION:Royal Garden\, Trondheim\, Norway
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg
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END:VCALENDAR