BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.5//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20220313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20221106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Madrid BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Oslo BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Seoul BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:KST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240418T150000 DTEND;TZID=Asia/Tokyo:20240418T160000 DTSTAMP:20240415T174855Z CREATED:20240415T174855Z LAST-MODIFIED:20240415T174855Z UID:7844-1713452400-1713456000@marketingeda.com SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240418T100000 DTEND;TZID=America/Los_Angeles:20240418T110000 DTSTAMP:20240415T175505Z CREATED:20240415T175505Z LAST-MODIFIED:20240415T175505Z UID:7847-1713434400-1713438000@marketingeda.com SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240417T081500 DTEND;TZID=America/Los_Angeles:20240417T170000 DTSTAMP:20240306T181435Z CREATED:20240306T181435Z LAST-MODIFIED:20240306T181435Z UID:7716-1713341700-1713373200@marketingeda.com SUMMARY:CadenceLIVE Silicon Valley 2024 DESCRIPTION:Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings users\, developers\, and industry experts together to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend engaging user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot. \n\n\nApril 17\, 2024 08:15\n\nRegistration\n\n\n\n\n\n\nApril 17\, 2024 09:00\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 10:15\n\nKeynotes\n\n\n\n\n\n\nApril 17\, 2024 11:45\n\nDesigner Expo and Lunch\n\n\n\n\n\n\nApril 17\, 2024 13:15\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 15:45\n\nClosing Keynote\n\n\n\n\n\n\nApril 17\, 2024 16:30\n\nDesigner Expo / Reception / Awards\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cadencelive-silicon-valley-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240417T080000 DTEND;TZID=America/Los_Angeles:20240417T090000 DTSTAMP:20240327T173831Z CREATED:20240327T173831Z LAST-MODIFIED:20240327T173831Z UID:7774-1713340800-1713344400@marketingeda.com SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240409T080000 DTEND;TZID=Europe/Berlin:20240411T170000 DTSTAMP:20240403T194345Z CREATED:20240119T022657Z LAST-MODIFIED:20240403T194345Z UID:7529-1712649600-1712854800@marketingeda.com SUMMARY:Embedded World 2024 DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nKnowledge platform #ew24\nKnow-how at the highest level\nAt the embedded world Conference and the electronic displays Conference\, top-class speakers from research\, development and practice will share their knowledge with you. They discuss the state of the art and possible future developments in the industry. The exhibitor’s forums and top-class discussion panels in the halls also contribute to the high-quality transfer of knowledge. Current topics will be highlighted in numerous expert lectures and panels. And\, of course\, there will be opportunities for intensive technical discussions. \nGuided tours\, tours for trainees and students and special presentations as well as the networking event for women in the embedded systems industry #women4ew complete the offer. \nThe No. 1 hub for the international embedded community\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts! \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/embedded-world-2024/ LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-World-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240403T080000 DTEND;TZID=America/Los_Angeles:20240404T170000 DTSTAMP:20240212T202640Z CREATED:20240212T202640Z LAST-MODIFIED:20240212T202640Z UID:7607-1712131200-1712250000@marketingeda.com SUMMARY:Siemens EDA User2User Conference DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/siemens-eda-user2user-conference/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240402T100000 DTEND;TZID=America/Los_Angeles:20240402T110000 DTSTAMP:20240327T160224Z CREATED:20240327T160224Z LAST-MODIFIED:20240327T160224Z UID:7768-1712052000-1712055600@marketingeda.com SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power DESCRIPTION:*Work email required for registration* \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp. \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS* \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240320T080000 DTEND;TZID=America/Los_Angeles:20240321T170000 DTSTAMP:20240305T220415Z CREATED:20240305T220415Z LAST-MODIFIED:20240305T220415Z UID:7710-1710921600-1711040400@marketingeda.com SUMMARY:SNUG Silicon Valley 2024 DESCRIPTION:Connecting the Synopsys User Community\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nTechnical Committee\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. \nTechnical Committee Chair: \nDon Mills\, Microchip \nCommittee Members: \nAnand Iyer\, Synopsys \nAndy Copperhall\, Independent \nAnwarul Hasan\, Independent \nBrian Kane\, Northrop Grumman \nBryan Morris\, Ciena \nChris Kiegle\, Marvell Semiconductor \nCliff Cummings\, Paradigm Works \nFirouzeh Nourkhalaj\, Synopsys \nGlen McDonnell\, Broadcom \nHongda Lu\, SARC \nJack Dong\, Intel \nJason Rziha\, Microchip \nJeff Montesano\, Meta \nJing Zhang\, Intel \nJohn Thomson\, NVIDIA \nJohn Wei\, Independent \nJon Colburn\, NVIDIA \nJT Longino\, Tesla \nKarthik Rajan\, Microchip \nLeah Clark\, Synopsys \nMark Sprague\, Intel \nNaveen Mysore\, Intel \nNeel Sonara\, Broadcom \nNitin Navale\, AMD \nOlivia Poon\, Marvell Semiconductor \nPinal Patel\, eInfochips \nRavikishore Gandikota\, NVIDIA \nRonald Goodstein\, Lockheed Martin \nRonald Kalim\, Intel \nSachin Parikh\, Broadcom \nSangeetha Chandran Sarala\, Micron \nSathappan Palaniappan\, Broadcom \nSaurabh Bhadoriya\, NVIDIA \nSavita Banerjee\, Meta \nShaiful Alam\, Intel \nStella Matarrese\, Synopsys \nTom Mahatdejkul\, Arm \nTony Todesco\, AMD \nUpasna Vishnoi\, Marvell Semiconductor \nVictoria Kolesov\, Intel \nZafar Hasan\, NVIDIA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/snug-silicon-valley-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNG-Silicon-Valley-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240313T080000 DTEND;TZID=Europe/London:20240314T170000 DTSTAMP:20240122T194453Z CREATED:20240122T194453Z LAST-MODIFIED:20240122T194453Z UID:7549-1710316800-1710435600@marketingeda.com SUMMARY:GSA International Semiconductor Conference DESCRIPTION:Inaugural GSA event in partnership with the UK Government.  \nMeet senior business leaders\, investors\, and public policy officials from around the world. \nAcross two days\, join us for exciting discussions on semiconductor innovation for a NetZero economy\, with a view on the dramatically changing supply chain\, government interventions and industry outlook. \n  \nSemiconductor Innovation for NetZero (March 13-14) \n\nSupply Chain Resilience and national approaches to Semiconductor Policy\nDifferent government approaches to semiconductor policy\, supply chains and stimulating industry growth\nResource and talent development\, including raising the role of women in the industry\nCapital funding and IP strategies for start-ups and scale-ups\n\nWLI EMEA Kick-Off Event (March 13 morning) \n\nThe first GSA Women Leadership Initiative in Europe\nDiscuss the raising role of women in semiconductors\nHear lessons learned from women who have excelled in navigating a traditionally male-dominated industry\n\n\nTicket will cover both days\, all sections\nVIP Dinner will be held on the evening of March 13th: a separate ticket is required\, very limited seating available!\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/gsa-international-semiconductor-conference/ LOCATION:Here East\, 14 E Bay Lane\, London\, United Kingdom CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-March-13-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240307T090000 DTEND;TZID=America/Los_Angeles:20240307T100000 DTSTAMP:20240226T233450Z CREATED:20240226T233450Z LAST-MODIFIED:20240226T233450Z UID:7690-1709802000-1709805600@marketingeda.com SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240304T080000 DTEND;TZID=America/Los_Angeles:20240307T170000 DTSTAMP:20240216T181350Z CREATED:20240103T171927Z LAST-MODIFIED:20240216T181350Z UID:7493-1709539200-1709830800@marketingeda.com SUMMARY:DVCon USA 2024 DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvcon-usa-2024/ LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240226T123000 DTEND;TZID=America/Los_Angeles:20240226T164500 DTSTAMP:20240125T175450Z CREATED:20240125T175450Z LAST-MODIFIED:20240125T175450Z UID:7556-1708950600-1708965900@marketingeda.com SUMMARY:Synopsys Technical Forum 2024 DESCRIPTION:Please join us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. The Tech Forum is peer-to-peer\, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond. \n\n\n\n\n\n\nJoin us for our in-person Synopsys Technical Forum\, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis\, mask data prep\, and lithography simulation solutions. \nWhy Attend? \nSynopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis\, Mask Data Preparation\, TCAD\, and Yield Management tools provide leading edge performance\, accuracy\, quality\, and cost of ownership for all your production and development needs. \nWho Should Attend? \nThe Synopsys Technical Forum provides OPC\, RET\, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware. \n\n\n\n\n\n\n\n\n\n\nAgenda at a Glance\nHere’s an overview of what’s happening at the event!\n\nMonday\, February 26\, 2024\n\n\n\n\n12:30 PM – 1:00 PM\n\n\nRegistration & Lunch\n\n\n\n\n\n\n1:00 PM – 1:15 PM\n\n\nWelcome & Introduction\nShankar Krishnamoorthy\, GM\, Corp Staff\, Synopsys\n\n\n\n\n\n\n1:15 PM – 1:45 PM\n\n\nDistinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation\nKazunari Ishimaru\, Senior Managing Executive Officer\, Silicon Technology Division\, Rapidus Corp.\n\n\n\n\n\n\n1:45 PM – 2:15 PM\n\n\nKeynote: Data Preparation Evolution and Mask Quality Enhancement\nJerry Chen\, Deputy Director\, TSMC EBO\n\n\n\n\n\n\n2:15 PM – 2:45 PM\n\n\nProgress on Curvilinear OPC at Intel\nHarsha Grunes\, Senior Principal Engineer\, Intel\n\n\n\n\n\n\n2:45 PM – 3:15 PM\n\n\nAdvanced Correction Technologies to Optimize Memory Cell Performance\nMS Chiang\, Principal Engineer\, Winbond\n\n\n\n\n\n\n3:15 PM – 3:45 PM\n\n\nAdvances in Computational Lithography Solutions for High NA EUV Manufacturing\nMichael Lam\, Director R&D\, Synopsys\n\n\n\n\n\n\n3:45 PM – 4:45 PM\n\n\nThank You & Prize Drawing – Dessert Reception\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/synopsys-technical-forum-2024/ LOCATION:San Jose Marriott\, 301 S Market Street\, San Jose\, CA\, United States CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synosys-February-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20240226T080000 DTEND;TZID=Europe/Madrid:20240229T170000 DTSTAMP:20240321T221956Z CREATED:20231228T171623Z LAST-MODIFIED:20240321T221956Z UID:7473-1708934400-1709226000@marketingeda.com SUMMARY:MWC 2024 DESCRIPTION:Where technology\, community and commerce converge\n\nMWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months. \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/mwc-2024/ LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240221T090000 DTEND;TZID=America/Los_Angeles:20240221T100000 DTSTAMP:20240212T201810Z CREATED:20240212T201810Z LAST-MODIFIED:20240212T201810Z UID:7604-1708506000-1708509600@marketingeda.com SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240221T080000 DTEND;TZID=America/Los_Angeles:20240221T180000 DTSTAMP:20240216T221430Z CREATED:20240216T221430Z LAST-MODIFIED:20240216T221430Z UID:7637-1708502400-1708538400@marketingeda.com SUMMARY:Intel Foundry Services (IFS) Direct Connect DESCRIPTION:Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world’s first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick around for a panel discussion\, including industry leaders Rene Haas (Arm)\, Yuan Xing Lee (Broadcom)\, and Eric Fisher (MediaTek). \n\n\n\nWhat to Expect\n\n\n\n\n\n\n\n\n\nAll times in PST\nWednesday\, February 21\, 2024\n\n\n\n\n7:30am – 8:30am\nRegistration\, Breakfast\, and Demo Showcase\n\n\n8:30am – 9:30am\nPat Gelsinger and Stu Pann: A Systems Foundry for the AI Era with special appearances by: \n\nGina M. Raimondo\, United States Secretary of Commerce\nSatya Nadella\, Chairman and CEO\, Microsoft\nRene Haas\, CEO\, Arm\n\n\n\n\n9:30am – 10:00am\nCustomer Fireside Chat featuring: \n\nYuan Xing Lee\, VP of Central Engineering\, Broadcom\nEric Fisher\, President\, MediaTek North America\n\n\n\n\n10:00am – 10:30am\nAM Break and Demo Showcase\n\n\n10:30am – 12:00pm\nEcosystem Spotlight featuring: \n\nAart de Geus\, Executive Chair and Founder\, Synopsys\nMike Ellow\, Executive Vice President\, Siemens Digital Industries Software\nJohn Lee\, General Manager and Vice President for Electronics\, Semiconductors and Optics BU\, Ansys\nAnirudh Devgan\, President and CEO\, Cadence Design System\n\n\n\n\n12:00pm – 1:00pm\nNetworking Lunch and Demo Showcase\n\n\n1:00pm – 2:15pm\nDr. Ann Kelleher and Dr. Gary Patton: Delivering the Present and Inventing the Future: A Look Beyond 5N4Y\n\n\n2:15pm – 3:00pm\nDr. Choon Lee: Advanced Packaging and Test Solutions\n\n\n3:00pm – 3:20pm\nPM Break and Demo Showcase\n\n\n3:20pm – 3:50pm\nKeyvan Esfarjani: Transforming Intel Manufacturing featuring: \n\nJason Wang\, President\, UMC\n\n\n\n\n3:50pm – 4:00pm\nStu Pann: Wrap Up\n\n\n4:00pm – 4:45pm\nFireside Chat featuring: \n\nSam Altman\, Co-founder and CEO\, OpenAI\n\n\n\n\n4:45pm – 6:15pm\nNetworking Reception and Demo Showcase\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/intel-foundry-services-ifs-direct-connect/ LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States CATEGORIES:EDA,Foundry,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IFS-Direct-Connect.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240218T080000 DTEND;TZID=America/Los_Angeles:20240222T170000 DTSTAMP:20231230T004304Z CREATED:20231230T004304Z LAST-MODIFIED:20231230T004304Z UID:7483-1708243200-1708621200@marketingeda.com SUMMARY:ISSCC 2024 DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/isscc-2024/ LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States CATEGORIES:Conference,EDA,IP,Semiconductor ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240215T123000 DTEND;TZID=Asia/Kolkata:20240215T170000 DTSTAMP:20240207T181103Z CREATED:20240207T181103Z LAST-MODIFIED:20240207T181103Z UID:7591-1708000200-1708016400@marketingeda.com SUMMARY:SiFive RISC-V Day DESCRIPTION:Leadership in the RISC-V Era: India’s Exciting New Opportunity\nJoin SiFive for an informative afternoon session\, featuring key thought leaders in the fast -growing global RISC-V ecosystem. Krste Asanovic\, inventor of RISC-V and SiFive founder will be joined by academic and business leaders to provide an overview of RISC-V and the latest advances as well as talk about how RISC-V is a great opportunity for India to leap ahead in semiconductor technology leadership. \nIndia’s strengths in software and hardware design are helping it jump ahead as RISC-V takes hold around the world\, but the open standard brings a lot of competition from other regions. Our guests will discuss India’s strengths and talk about advances to date and how the country\, and the companies doing business here should think about the opportunities ahead. \nJoin us for SiFive RISC-V Day India on February 15\, 2024. Attend this free event to meet the pioneers driving RISC-V. A networking lunch will be held before the event. Don’t miss out! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/sifive-risc-v-day/ LOCATION:Hilton Bangalore Embassy GolfLinks\, Embassy Golf Links Business Park\, Bangalore\, 560071\, India CATEGORIES:IP,Symposium ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SiFive-February-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Oslo:20240214T080000 DTEND;TZID=Europe/Oslo:20240215T170000 DTSTAMP:20240209T180613Z CREATED:20240209T180613Z LAST-MODIFIED:20240209T180613Z UID:7599-1707897600-1708016400@marketingeda.com SUMMARY:FPGA Forum 2024 - Norway DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fpga-forum-2024-norway/ LOCATION:Royal Garden\, Trondheim\, Norway CATEGORIES:EDA,Forum,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240206T080000 DTEND;TZID=America/Los_Angeles:20240208T170000 DTSTAMP:20240103T034734Z CREATED:20240103T034448Z LAST-MODIFIED:20240103T034734Z UID:7490-1707206400-1707411600@marketingeda.com SUMMARY:Chiplet Summit DESCRIPTION:The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. \nThey’ll get the scoop on ways to make their chiplets run faster\, scale better\, use less power\, and be more flexible. \nThis unique event gives attendees a place to network with peers\, ask questions of the experts\, and talk to vendors offering a wide variety of products and services. \n\n\nKeynote Speakers\n\n\n\n\n\n\n\n\nSubi Kengeri – Applied Materials \nNitza Basoco – proteanTecs \nDaniel Armbrust – Silicon Catalyst \nBob Brennan – Intel Foundry Services \nSheng Lu – Corigine \nCliff Grossner – Open Compute Project \nBapi Vinnakota – Open Compute Project \n\n\n\n\n\n\n\n\nKEYNOTE SPEAKER DETAILS \nThought-Provoking Panels Where Attendees Can Ask Questions of Leading Experts: \n\nChoosing the Right Architecture for Your Application\nNext Great Breakthrough in Chiplets\nBest Development Platform for Chiplets\nBest Interface for Chiplets\nWhat Standards Are Needed?\nOptimizing Chiplets\n\nATTENDEES \nEngineers and managers who are looking for ways to help meet performance challenges\, handle the move to smaller dimensions\, provide the modularity and scalability today’s chips require\, and develop solutions focused on the latest applications and interfaces.  Designers of enterprise networks\, telecom systems\, high-performance computing\, financial systems\, IoT\, and mil/aero applications all know that chiplets will play a big role in their future. \nBACKGROUND \nChiplets improve chip yields and costs\, but still provide the performance of a large monolithic chip.  Designers can mix-and-match chiplets\, use the process technologies best suited to particular functions\, take advantage of chiplet IP\, simplify moves to new process nodes\,  and avoid wafer waste and manufacturing defects.  Chiplets are the key to producing the extremely high-density\, high-performance chips required for today’s networking\, storage\, AI/ML\, analytics\, media processing\, HPC\, and virtual reality applications. \n\n\n\n\n\n\nExhibit\nPosition Your Company as a Leader in an Emerging Technology.  Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia).  Share Thoughts with Key Experts and Analysts.  Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. \n\n\nOnly event totally dedicated to the skyrocketing chiplet market \n\n\nTop experts\, major keynotes\, and critical topics will draw big-time customers \n\n\nPractical orientation will attract key designers and specifiers \n\n\nVendor-neutral show offers opportunities to everyone \n\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplet-summit-2/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chiplet-Summit-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240131T183000 DTEND;TZID=America/Los_Angeles:20240131T210000 DTSTAMP:20231212T174026Z CREATED:20231212T173907Z LAST-MODIFIED:20231212T174026Z UID:7163-1706725800-1706734800@marketingeda.com SUMMARY:Signal & Power Integrity Special Interest Group DESCRIPTION:Dear SIPI Engineer\, \nAs a member of the engineering community\, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. \nThis event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will provide the opportunity for networking and interactive discussion with other SIPI engineers to exchange ideas and strategies on signal and power integrity challenges and solutions. \nWe will offer Synopsys and partner product demonstrations during our cocktail hour\, followed by a sit-down dinner with invited guest speakers and conclude with a panel discussion. Stay to the end for a chance to win a raffle prize! \nWe are excited to see you in-person once again. Please be sure to reserve your spot today as seating is limited. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/signal-power-integrity-special-interest-group/ LOCATION:Hilton Santa Clara\, 4949 Great America Parkway\, Santa Clara\, CA\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-January-31-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240125T090000 DTEND;TZID=America/Los_Angeles:20240125T100000 DTSTAMP:20231227T171414Z CREATED:20231227T171414Z LAST-MODIFIED:20231227T171414Z UID:7455-1706173200-1706176800@marketingeda.com SUMMARY:Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series DESCRIPTION:Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing\, powering innovations across diverse applications such as automotive and AI. Our experts will guide you through the features\, advantages\, and real-world applications of the Andes Series\, showcasing its ability to unlock the full potential of RISC-V technology. Whether you’re in the automotive industry or the AI sector\, this webinar is your gateway to understanding how Andes Series Total Solutions can elevate your projects to new heights. Don’t miss this opportunity to stay at the forefront of RISC-V advancements and explore the unlimited possibilities that lie ahead! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/releasing-all-potential-of-risc-v-total-solutions-of-andes-core-processors-series/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-January-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240124T080000 DTEND;TZID=Asia/Tokyo:20240126T170000 DTSTAMP:20231227T195553Z CREATED:20231227T195553Z LAST-MODIFIED:20231227T195553Z UID:7462-1706083200-1706288400@marketingeda.com SUMMARY:Automotive World 2024 DESCRIPTION:Combination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics\, connected car\, autonomous driving\, EV/HV/FCV\, lightweight\, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. \n\n1\,650 Exhibitors\n85\,000 Visitors\n170 Speakers\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/automotive-world-2024/ LOCATION:Tokyo Big Sight\, 3 Choe-11-1 Ariake\, Tokyo\, Japan CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Automotive-World-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240124T080000 DTEND;TZID=America/Los_Angeles:20240124T090000 DTSTAMP:20240103T173109Z CREATED:20240103T173109Z LAST-MODIFIED:20240103T173109Z UID:7496-1706083200-1706086800@marketingeda.com SUMMARY:Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs DESCRIPTION:Applications such as Data Centers\, High-Performance computing (HPC)\, artificial intelligence/machine learning (AI/ML)\, cloud computing\, military\, and aerospace\, automotive\, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising results for compute intensive applications. Every successive generation of PCIe has doubled the bandwidth of the previous generation for e.g. PCIe 6.0\, delivers double the bandwidth (64GT/s) of its predecessor i.e.\, PCIe 5.0 (32GT/s). \nCome join us to learn: \n1. How PCIe 6.0 can deliver such high data transfer rate of up to 64 GT/s per pin \n2. Design considerations for PCIe 5.0 and 6.0 design IPs \n3. Why verifying features such as Integrity and data encryption are critical. \n4. Why industry leading PCIe design IPs companies trust us and how stay ahead of the curve \n5. Reaching coverage closure faster through Compliance  Testsuites \n6. What’s next for PCIe. \nWe will also discuss how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs. \n  \nWhat You Will Learn: \n\nOverview of PCIe Verification\nDesign and verification considerations when planning a new PCIe project specially around PCIe Gen5 or Gen6\nUnique features to Siemens Avery PCIe Verification IP and its Compliance Test Suite:\n\nTestbench Creation and easy bring-up. \nRun time Configurations. \nTraffic Generation \nError Injection \nDebug features \nVarious applications and use-cases \n\nChallenges involved in verifying advanced PCIe Generations\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign & Verification Engineers\, Architects.\nManagers\, Directors\, Key Decision Makers.\n\n  \nWhat/Which Products are Covered:  \n\nVerification IP\, SV/UVM\, PCIe\, PCIe Compliance Test Suite\, QuestaSim & Visualizer\n\n\n\nSpeakers:\n\n\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0.  At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his master’s in computer science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\n\n\nJalaj Gupta\nVerification IP Product Engineer\, Siemens EDA\n\n\n\n\nJalaj Gupta is Verification IP Product Engineer at Siemens EDA. Jalaj is responsible for providing support for PCIe and UCIe Avery Verification IPs. He has 10 years of experience working in simulation and emulation domain\, from developing Verification IPs to transactor library development for Veloce to product engineering for leading edge Avery Verification IPs. He has worked on different protocols like USB\, Ethernet\, AMBA\, I2C and PCIe. He is based in Austin\, Texas. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/comprehensive-pcie-verification-solution-for-bleeding-edge-and-mission-critical-soc-ip-designs/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-24-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Seoul:20240122T080000 DTEND;TZID=Asia/Seoul:20240125T170000 DTSTAMP:20231229T165332Z CREATED:20231229T165332Z LAST-MODIFIED:20231229T165332Z UID:7479-1705910400-1706202000@marketingeda.com SUMMARY:ASP-DAC 2024 DESCRIPTION:ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions\, one of the most active regions of design\, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists\, engineers\, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/asp-dac-2024/ LOCATION:Incheon Songdo Convensia\, 123 Central Street\, Yeonsu-gu\, Incheon\, Korea\, Democratic People's Republic of CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20240116T090000 DTEND;TZID=Asia/Tokyo:20240116T170000 DTSTAMP:20231211T175014Z CREATED:20231211T175014Z LAST-MODIFIED:20231211T175014Z UID:7149-1705395600-1705424400@marketingeda.com SUMMARY:RISC-V Day\, Tokyo 2024 Winter DESCRIPTION:The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday\, January 16\, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center\, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products\, as well as key people and engineers\, and provide business opportunities such as increasing product awareness\, realizing collaboration between companies\, technology exchange\, and information gathering. We look forward to your participation on this occasion! A video of the presentation and information on materials will be posted on the website at a later date. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/risc-v-day-tokyo-2024-winter/ LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240109T080000 DTEND;TZID=America/Los_Angeles:20240112T170000 DTSTAMP:20231230T005013Z CREATED:20231129T225332Z LAST-MODIFIED:20231230T005013Z UID:7133-1704787200-1705078800@marketingeda.com SUMMARY:CES 2024 DESCRIPTION:Registration is now open for CES® 2024 — taking place Jan. 9-12\, in Las Vegas. \nFlip the switch on global business opportunity with CES\, where you can meet with partners\, customers\, media\, investors\, and policymakers from across the industry and the world all in one place. \nDon’t miss your chance to be a part of the most powerful tech event in the world. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ces-2024/ LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States CATEGORIES:Conference,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2023-2.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240106T080000 DTEND;TZID=Asia/Kolkata:20240110T170000 DTSTAMP:20231228T190611Z CREATED:20231227T173925Z LAST-MODIFIED:20231228T190611Z UID:7458-1704528000-1704906000@marketingeda.com SUMMARY:VLSID 2024 DESCRIPTION:The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata\, India\, during January 6-10\, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders\, Indian and international industry bodies\, and academic researchers in a common platform. \nIn the present era of automation and connected things\, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift\, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”. \nBrilliant minds across the VLSI domain will brainstorm during the conference to redefine the future course of VLSI Design and Embedded research and application in India. Kolkata (Known as Calcutta during the British Imperial rule) is surrounded by several premier technical and scientific institutes like IIEST Shibpur (B. E. College\, Shibpur)\, IIT Kharagpur\, ISI Calcutta\, Calcutta University\, Jadavpur University etc. \nEast and north-eastern region of our country is a hub of innovation with a focus on emerging technologies. Over the years the region has generated huge number of ESDM professionals and academicians who are right now fueling the growth of ESDM industry. It is high time to operationalize state level high technology clusters in the field of VLSI design\, embedded systems\, cognitive system design and silicon/display/compound fab. VLSID 2024 provides the unique stage where MNCs\, start-ups\, industry bodies and academicians come together and get synergized with what the states of this region have to offer. \nOver a span of five-days of VLSID2024\, the summit will feed brains and nurture minds with state-of-the-art exhibitors\, presentations\, panel discussions\, innovation forums\, and tutorials by established technologists. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/vlsid-2024/ LOCATION:ITC Royal Bengal\, Kolkata\, India CATEGORIES:Conference,EDA,IP ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231214T100000 DTEND;TZID=America/Los_Angeles:20231214T110000 DTSTAMP:20231120T175241Z CREATED:20231120T175241Z LAST-MODIFIED:20231120T175241Z UID:7114-1702548000-1702551600@marketingeda.com SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231213T100000 DTEND;TZID=America/Los_Angeles:20231213T110000 DTSTAMP:20231211T211948Z CREATED:20231211T211948Z LAST-MODIFIED:20231211T211948Z UID:7152-1702461600-1702465200@marketingeda.com SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents. \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231213T090000 DTEND;TZID=America/Los_Angeles:20231213T100000 DTSTAMP:20231204T224640Z CREATED:20231204T224336Z LAST-MODIFIED:20231204T224640Z UID:7139-1702458000-1702461600@marketingeda.com SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg END:VEVENT END:VCALENDAR