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BEGIN:VEVENT
DTSTART;TZID=Europe/Madrid:20240226T080000
DTEND;TZID=Europe/Madrid:20240229T170000
DTSTAMP:20240321T221956Z
CREATED:20231228T171623Z
LAST-MODIFIED:20240321T221956Z
UID:7473-1708934400-1709226000@marketingeda.com
SUMMARY:MWC 2024
DESCRIPTION:Where technology\, community and commerce converge\n\nMWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator\, device manufacturer\, technology provider\, vendor\, content owner\, or are simply interested in the future of tech\, you need to be here. \nWhy? Because it’s the one time of year where everyone who’s anyone comes together under one roof. Tens of thousands of senior executives from the top global companies\, international governments and trailblazing tech businesses converge at MWC Barcelona to make decisions. \n  \n\nThought leaders become change-makers\nNew ideas turn into business deals\nAnd networking means remarkable connections\n\nIt’s the place to find out where the industry\, your business and your career are headed. Miss out on MWC Barcelona\, miss out on the next 12 months.
URL:https://marketingeda.com/event/mwc-2024/
LOCATION:Fira Gran Via\, 08038\, Barcelona\, Spain
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MWC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T090000
DTEND;TZID=America/Los_Angeles:20240221T100000
DTSTAMP:20240212T201810Z
CREATED:20240212T201810Z
LAST-MODIFIED:20240212T201810Z
UID:7604-1708506000-1708509600@marketingeda.com
SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering.
URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T080000
DTEND;TZID=America/Los_Angeles:20240221T180000
DTSTAMP:20240216T221430Z
CREATED:20240216T221430Z
LAST-MODIFIED:20240216T221430Z
UID:7637-1708502400-1708538400@marketingeda.com
SUMMARY:Intel Foundry Services (IFS) Direct Connect
DESCRIPTION:Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world’s first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick around for a panel discussion\, including industry leaders Rene Haas (Arm)\, Yuan Xing Lee (Broadcom)\, and Eric Fisher (MediaTek). \n\n\n\nWhat to Expect\n\n\n\n\n\n\n\n\n\nAll times in PST\nWednesday\, February 21\, 2024\n\n\n\n\n7:30am – 8:30am\nRegistration\, Breakfast\, and Demo Showcase\n\n\n8:30am – 9:30am\nPat Gelsinger and Stu Pann: A Systems Foundry for the AI Era with special appearances by: \n\nGina M. Raimondo\, United States Secretary of Commerce\nSatya Nadella\, Chairman and CEO\, Microsoft\nRene Haas\, CEO\, Arm\n\n\n\n\n9:30am – 10:00am\nCustomer Fireside Chat featuring: \n\nYuan Xing Lee\, VP of Central Engineering\, Broadcom\nEric Fisher\, President\, MediaTek North America\n\n\n\n\n10:00am – 10:30am\nAM Break and Demo Showcase\n\n\n10:30am – 12:00pm\nEcosystem Spotlight featuring: \n\nAart de Geus\, Executive Chair and Founder\, Synopsys\nMike Ellow\, Executive Vice President\, Siemens Digital Industries Software\nJohn Lee\, General Manager and Vice President for Electronics\, Semiconductors and Optics BU\, Ansys\nAnirudh Devgan\, President and CEO\, Cadence Design System\n\n\n\n\n12:00pm – 1:00pm\nNetworking Lunch and Demo Showcase\n\n\n1:00pm – 2:15pm\nDr. Ann Kelleher and Dr. Gary Patton: Delivering the Present and Inventing the Future: A Look Beyond 5N4Y\n\n\n2:15pm – 3:00pm\nDr. Choon Lee: Advanced Packaging and Test Solutions\n\n\n3:00pm – 3:20pm\nPM Break and Demo Showcase\n\n\n3:20pm – 3:50pm\nKeyvan Esfarjani: Transforming Intel Manufacturing featuring: \n\nJason Wang\, President\, UMC\n\n\n\n\n3:50pm – 4:00pm\nStu Pann: Wrap Up\n\n\n4:00pm – 4:45pm\nFireside Chat featuring: \n\nSam Altman\, Co-founder and CEO\, OpenAI\n\n\n\n\n4:45pm – 6:15pm\nNetworking Reception and Demo Showcase
URL:https://marketingeda.com/event/intel-foundry-services-ifs-direct-connect/
LOCATION:San Jose Convention Center\, 150 W San Carlos Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IFS-Direct-Connect.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240218T080000
DTEND;TZID=America/Los_Angeles:20240222T170000
DTSTAMP:20231230T004304Z
CREATED:20231230T004304Z
LAST-MODIFIED:20231230T004304Z
UID:7483-1708243200-1708621200@marketingeda.com
SUMMARY:ISSCC 2024
DESCRIPTION:The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts.
URL:https://marketingeda.com/event/isscc-2024/
LOCATION:San Francisco Marriot Marquis\, 780 Mission Street\, San Francisco\, CA\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISSCC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240215T123000
DTEND;TZID=Asia/Kolkata:20240215T170000
DTSTAMP:20240207T181103Z
CREATED:20240207T181103Z
LAST-MODIFIED:20240207T181103Z
UID:7591-1708000200-1708016400@marketingeda.com
SUMMARY:SiFive RISC-V Day
DESCRIPTION:Leadership in the RISC-V Era: India’s Exciting New Opportunity\nJoin SiFive for an informative afternoon session\, featuring key thought leaders in the fast -growing global RISC-V ecosystem. Krste Asanovic\, inventor of RISC-V and SiFive founder will be joined by academic and business leaders to provide an overview of RISC-V and the latest advances as well as talk about how RISC-V is a great opportunity for India to leap ahead in semiconductor technology leadership. \nIndia’s strengths in software and hardware design are helping it jump ahead as RISC-V takes hold around the world\, but the open standard brings a lot of competition from other regions. Our guests will discuss India’s strengths and talk about advances to date and how the country\, and the companies doing business here should think about the opportunities ahead. \nJoin us for SiFive RISC-V Day India on February 15\, 2024. Attend this free event to meet the pioneers driving RISC-V. A networking lunch will be held before the event. Don’t miss out!
URL:https://marketingeda.com/event/sifive-risc-v-day/
LOCATION:Hilton Bangalore Embassy GolfLinks\, Embassy Golf Links Business Park\, Bangalore\, 560071\, India
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SiFive-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Oslo:20240214T080000
DTEND;TZID=Europe/Oslo:20240215T170000
DTSTAMP:20240209T180613Z
CREATED:20240209T180613Z
LAST-MODIFIED:20240209T180613Z
UID:7599-1707897600-1708016400@marketingeda.com
SUMMARY:FPGA Forum 2024 - Norway
DESCRIPTION:FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers\, project managers\, technical managers\, researchers\, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience\, – the universities will present new and exciting projects\, and the vendors will have technical presentations with a minimum of marketing. At the exhibition\, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday. (FPGA-forum 2022 was postponed to September due to Covid\, but now we are back to February) \nLanguage \nThe FPGA-forum conference is mixed language\, with some presentations in Norwegian and some in English. See the program for more info here. \nThe FPGA-forum web-site is in English as we want all the information to be available for all interested parties – without the extra overhead of language duplication.
URL:https://marketingeda.com/event/fpga-forum-2024-norway/
LOCATION:Royal Garden\, Trondheim\, Norway
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FPGA-Forum-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240206T080000
DTEND;TZID=America/Los_Angeles:20240208T170000
DTSTAMP:20240103T034734Z
CREATED:20240103T034448Z
LAST-MODIFIED:20240103T034734Z
UID:7490-1707206400-1707411600@marketingeda.com
SUMMARY:Chiplet Summit
DESCRIPTION:The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. \nThey’ll get the scoop on ways to make their chiplets run faster\, scale better\, use less power\, and be more flexible. \nThis unique event gives attendees a place to network with peers\, ask questions of the experts\, and talk to vendors offering a wide variety of products and services. \n\n\nKeynote Speakers\n\n\n\n\n\n\n\n\nSubi Kengeri – Applied Materials \nNitza Basoco – proteanTecs \nDaniel Armbrust – Silicon Catalyst \nBob Brennan – Intel Foundry Services \nSheng Lu – Corigine \nCliff Grossner – Open Compute Project \nBapi Vinnakota – Open Compute Project \n\n\n\n\n\n\n\n\nKEYNOTE SPEAKER DETAILS \nThought-Provoking Panels Where Attendees Can Ask Questions of Leading Experts: \n\nChoosing the Right Architecture for Your Application\nNext Great Breakthrough in Chiplets\nBest Development Platform for Chiplets\nBest Interface for Chiplets\nWhat Standards Are Needed?\nOptimizing Chiplets\n\nATTENDEES \nEngineers and managers who are looking for ways to help meet performance challenges\, handle the move to smaller dimensions\, provide the modularity and scalability today’s chips require\, and develop solutions focused on the latest applications and interfaces.  Designers of enterprise networks\, telecom systems\, high-performance computing\, financial systems\, IoT\, and mil/aero applications all know that chiplets will play a big role in their future. \nBACKGROUND \nChiplets improve chip yields and costs\, but still provide the performance of a large monolithic chip.  Designers can mix-and-match chiplets\, use the process technologies best suited to particular functions\, take advantage of chiplet IP\, simplify moves to new process nodes\,  and avoid wafer waste and manufacturing defects.  Chiplets are the key to producing the extremely high-density\, high-performance chips required for today’s networking\, storage\, AI/ML\, analytics\, media processing\, HPC\, and virtual reality applications. \n\n\n\n\n\n\nExhibit\nPosition Your Company as a Leader in an Emerging Technology.  Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia).  Share Thoughts with Key Experts and Analysts.  Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. \n\n\nOnly event totally dedicated to the skyrocketing chiplet market \n\n\nTop experts\, major keynotes\, and critical topics will draw big-time customers \n\n\nPractical orientation will attract key designers and specifiers \n\n\nVendor-neutral show offers opportunities to everyone \n\n\n 
URL:https://marketingeda.com/event/chiplet-summit-2/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chiplet-Summit-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240131T183000
DTEND;TZID=America/Los_Angeles:20240131T210000
DTSTAMP:20231212T174026Z
CREATED:20231212T173907Z
LAST-MODIFIED:20231212T174026Z
UID:7163-1706725800-1706734800@marketingeda.com
SUMMARY:Signal & Power Integrity Special Interest Group
DESCRIPTION:Dear SIPI Engineer\, \nAs a member of the engineering community\, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. \nThis event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will provide the opportunity for networking and interactive discussion with other SIPI engineers to exchange ideas and strategies on signal and power integrity challenges and solutions. \nWe will offer Synopsys and partner product demonstrations during our cocktail hour\, followed by a sit-down dinner with invited guest speakers and conclude with a panel discussion. Stay to the end for a chance to win a raffle prize! \nWe are excited to see you in-person once again. Please be sure to reserve your spot today as seating is limited.
URL:https://marketingeda.com/event/signal-power-integrity-special-interest-group/
LOCATION:Hilton Santa Clara\, 4949 Great America Parkway\, Santa Clara\, CA\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-January-31-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T090000
DTEND;TZID=America/Los_Angeles:20240125T100000
DTSTAMP:20231227T171414Z
CREATED:20231227T171414Z
LAST-MODIFIED:20231227T171414Z
UID:7455-1706173200-1706176800@marketingeda.com
SUMMARY:Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
DESCRIPTION:Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing\, powering innovations across diverse applications such as automotive and AI. Our experts will guide you through the features\, advantages\, and real-world applications of the Andes Series\, showcasing its ability to unlock the full potential of RISC-V technology. Whether you’re in the automotive industry or the AI sector\, this webinar is your gateway to understanding how Andes Series Total Solutions can elevate your projects to new heights. Don’t miss this opportunity to stay at the forefront of RISC-V advancements and explore the unlimited possibilities that lie ahead!
URL:https://marketingeda.com/event/releasing-all-potential-of-risc-v-total-solutions-of-andes-core-processors-series/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-January-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240124T080000
DTEND;TZID=Asia/Tokyo:20240126T170000
DTSTAMP:20231227T195553Z
CREATED:20231227T195553Z
LAST-MODIFIED:20231227T195553Z
UID:7462-1706083200-1706288400@marketingeda.com
SUMMARY:Automotive World 2024
DESCRIPTION:Combination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics\, connected car\, autonomous driving\, EV/HV/FCV\, lightweight\, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. \n\n1\,650 Exhibitors\n85\,000 Visitors\n170 Speakers
URL:https://marketingeda.com/event/automotive-world-2024/
LOCATION:Tokyo Big Sight\, 3 Choe-11-1 Ariake\, Tokyo\, Japan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Automotive-World-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240124T080000
DTEND;TZID=America/Los_Angeles:20240124T090000
DTSTAMP:20240103T173109Z
CREATED:20240103T173109Z
LAST-MODIFIED:20240103T173109Z
UID:7496-1706083200-1706086800@marketingeda.com
SUMMARY:Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
DESCRIPTION:Applications such as Data Centers\, High-Performance computing (HPC)\, artificial intelligence/machine learning (AI/ML)\, cloud computing\, military\, and aerospace\, automotive\, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising results for compute intensive applications. Every successive generation of PCIe has doubled the bandwidth of the previous generation for e.g. PCIe 6.0\, delivers double the bandwidth (64GT/s) of its predecessor i.e.\, PCIe 5.0 (32GT/s). \nCome join us to learn: \n1. How PCIe 6.0 can deliver such high data transfer rate of up to 64 GT/s per pin \n2. Design considerations for PCIe 5.0 and 6.0 design IPs \n3. Why verifying features such as Integrity and data encryption are critical. \n4. Why industry leading PCIe design IPs companies trust us and how stay ahead of the curve \n5. Reaching coverage closure faster through Compliance  Testsuites \n6. What’s next for PCIe. \nWe will also discuss how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs. \n  \nWhat You Will Learn: \n\nOverview of PCIe Verification\nDesign and verification considerations when planning a new PCIe project specially around PCIe Gen5 or Gen6\nUnique features to Siemens Avery PCIe Verification IP and its Compliance Test Suite:\n\nTestbench Creation and easy bring-up. \nRun time Configurations. \nTraffic Generation \nError Injection \nDebug features \nVarious applications and use-cases \n\nChallenges involved in verifying advanced PCIe Generations\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign & Verification Engineers\, Architects.\nManagers\, Directors\, Key Decision Makers.\n\n  \nWhat/Which Products are Covered:  \n\nVerification IP\, SV/UVM\, PCIe\, PCIe Compliance Test Suite\, QuestaSim & Visualizer\n\n\n\nSpeakers:\n\n\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0.  At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his master’s in computer science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\n\n\nJalaj Gupta\nVerification IP Product Engineer\, Siemens EDA\n\n\n\n\nJalaj Gupta is Verification IP Product Engineer at Siemens EDA. Jalaj is responsible for providing support for PCIe and UCIe Avery Verification IPs. He has 10 years of experience working in simulation and emulation domain\, from developing Verification IPs to transactor library development for Veloce to product engineering for leading edge Avery Verification IPs. He has worked on different protocols like USB\, Ethernet\, AMBA\, I2C and PCIe. He is based in Austin\, Texas.
URL:https://marketingeda.com/event/comprehensive-pcie-verification-solution-for-bleeding-edge-and-mission-critical-soc-ip-designs/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Seoul:20240122T080000
DTEND;TZID=Asia/Seoul:20240125T170000
DTSTAMP:20231229T165332Z
CREATED:20231229T165332Z
LAST-MODIFIED:20231229T165332Z
UID:7479-1705910400-1706202000@marketingeda.com
SUMMARY:ASP-DAC 2024
DESCRIPTION:ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions\, one of the most active regions of design\, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists\, engineers\, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.
URL:https://marketingeda.com/event/asp-dac-2024/
LOCATION:Incheon Songdo Convensia\, 123 Central Street\, Yeonsu-gu\, Incheon\, Korea\, Democratic People's Republic of
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ASP-DAC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240116T090000
DTEND;TZID=Asia/Tokyo:20240116T170000
DTSTAMP:20231211T175014Z
CREATED:20231211T175014Z
LAST-MODIFIED:20231211T175014Z
UID:7149-1705395600-1705424400@marketingeda.com
SUMMARY:RISC-V Day\, Tokyo 2024 Winter
DESCRIPTION:The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday\, January 16\, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center\, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products\, as well as key people and engineers\, and provide business opportunities such as increasing product awareness\, realizing collaboration between companies\, technology exchange\, and information gathering. We look forward to your participation on this occasion! A video of the presentation and information on materials will be posted on the website at a later date.
URL:https://marketingeda.com/event/risc-v-day-tokyo-2024-winter/
LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240109T080000
DTEND;TZID=America/Los_Angeles:20240112T170000
DTSTAMP:20231230T005013Z
CREATED:20231129T225332Z
LAST-MODIFIED:20231230T005013Z
UID:7133-1704787200-1705078800@marketingeda.com
SUMMARY:CES 2024
DESCRIPTION:Registration is now open for CES® 2024 — taking place Jan. 9-12\, in Las Vegas. \nFlip the switch on global business opportunity with CES\, where you can meet with partners\, customers\, media\, investors\, and policymakers from across the industry and the world all in one place. \nDon’t miss your chance to be a part of the most powerful tech event in the world.
URL:https://marketingeda.com/event/ces-2024/
LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240106T080000
DTEND;TZID=Asia/Kolkata:20240110T170000
DTSTAMP:20231228T190611Z
CREATED:20231227T173925Z
LAST-MODIFIED:20231228T190611Z
UID:7458-1704528000-1704906000@marketingeda.com
SUMMARY:VLSID 2024
DESCRIPTION:The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata\, India\, during January 6-10\, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders\, Indian and international industry bodies\, and academic researchers in a common platform. \nIn the present era of automation and connected things\, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift\, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”. \nBrilliant minds across the VLSI domain will brainstorm during the conference to redefine the future course of VLSI Design and Embedded research and application in India. Kolkata (Known as Calcutta during the British Imperial rule) is surrounded by several premier technical and scientific institutes like IIEST Shibpur (B. E. College\, Shibpur)\, IIT Kharagpur\, ISI Calcutta\, Calcutta University\, Jadavpur University etc. \nEast and north-eastern region of our country is a hub of innovation with a focus on emerging technologies. Over the years the region has generated huge number of ESDM professionals and academicians who are right now fueling the growth of ESDM industry. It is high time to operationalize state level high technology clusters in the field of VLSI design\, embedded systems\, cognitive system design and silicon/display/compound fab. VLSID 2024 provides the unique stage where MNCs\, start-ups\, industry bodies and academicians come together and get synergized with what the states of this region have to offer. \nOver a span of five-days of VLSID2024\, the summit will feed brains and nurture minds with state-of-the-art exhibitors\, presentations\, panel discussions\, innovation forums\, and tutorials by established technologists.
URL:https://marketingeda.com/event/vlsid-2024/
LOCATION:ITC Royal Bengal\, Kolkata\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231214T100000
DTEND;TZID=America/Los_Angeles:20231214T110000
DTSTAMP:20231120T175241Z
CREATED:20231120T175241Z
LAST-MODIFIED:20231120T175241Z
UID:7114-1702548000-1702551600@marketingeda.com
SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs
DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO
URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T100000
DTEND;TZID=America/Los_Angeles:20231213T110000
DTSTAMP:20231211T211948Z
CREATED:20231211T211948Z
LAST-MODIFIED:20231211T211948Z
UID:7152-1702461600-1702465200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III
DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T090000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231204T224640Z
CREATED:20231204T224336Z
LAST-MODIFIED:20231204T224640Z
UID:7139-1702458000-1702461600@marketingeda.com
SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics
DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA.
URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20231208T080000
DTEND;TZID=Asia/Shanghai:20231208T170000
DTSTAMP:20230925T223711Z
CREATED:20230925T223711Z
LAST-MODIFIED:20230925T223711Z
UID:6883-1702022400-1702054800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – China
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-china/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T080000
DTEND;TZID=America/Los_Angeles:20231207T090000
DTSTAMP:20231117T204354Z
CREATED:20231117T204354Z
LAST-MODIFIED:20231117T204354Z
UID:7107-1701936000-1701939600@marketingeda.com
SUMMARY:Multi-Die System Verification with Siemens Avery UCIe VIP
DESCRIPTION:Conventional monolithic SoCs are becoming a bottleneck for power\, performance\, and area (PPA)\, creating limitations for Data-intensive applications like high-performance computing (HPC)\, machine learning (ML) and artificial intelligence (AI)\, and for hyperscale data centers. These bottlenecks are challenging Moore’s law\, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law\, but the semiconductor industry needs standardized interconnects to allow scaling up these systems\, with 2D\, 2.5D and even 3D packaging technologies. \nUniversal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption\, improved performance with the same latency of the system. \nIn this online seminar\, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP\, discussing its key features such as dynamic block-level and SoC level testbench creation\, traffic generation\, error injection\, debug features\, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market\, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP. \n  \nWhat You Will Learn: \n\nWhat is the Universal Chiplet Interconnect Express (UCIe)\nWhy do we need UCIe in chiplet designs: its evolution and application.\nDesign and Verification considerations when planning a UCIe based design.\nSiemens Avery UCIe Verification IP’s unique features.\n\nTechnical Demonstration. \nEnvironment / Testbench Creation \nDynamic Configuration \nTraffic Generation \nError Injection \nDebug features \n\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign\, Verification Engineers\, Managers and Architects working on or planning UCIe design projects\n\n  \nWhat/Which Products are Covered:  \n\nUCIe\nPCIe\nCXL\nChiplets\n\n\n\n\nSpeakers\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\nJustin Bunnell\nTechnical Product Manager\nSiemens EDA\n\n\nJustin Bunnell is a Technical Product Manager at Siemens EDA\, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.
URL:https://marketingeda.com/event/multi-die-system-verification-with-siemens-avery-ucie-vip/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20231204T090000
DTEND;TZID=Europe/Paris:20231205T170000
DTSTAMP:20231128T173642Z
CREATED:20231128T172805Z
LAST-MODIFIED:20231128T173642Z
UID:7122-1701680400-1701795600@marketingeda.com
SUMMARY:IP-SoC Conference 23 - Grenoble
DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, Green Electronics\, … \nAnd over all you cannot miss The wine Tasting Party !! \nExhibition tables and “discussion panels” will favor vendor and customer meetings. \nAny question? Please contact us \nRegistration and Exhibition installation opens at 7 am. \n\n\n\n\n\n\nDay 1 – December 4th\, 2023\n\n\n\n\n\n\n\n9.00 am\nIntroduction Session\n\n\n\nWelcome : Innovation in semi conductor industry \nGabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\nEmpowering Innovation in the Age of Custom Silicon \nEric Lalardie\nDirector\nArm Ltd. \nAbout me\n\n\n\n\n9.40 am\nBreak\n\n\n\n10.00 am\nNew technology the lead of innovation\n \nChairperson: Yves Quere – CEA\n\n\n\n\nGreening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology \nPhilippe Flatresse\nProduct Marketing\nSOITEC \nAbout me\n\n\n\n\nTechnologies enabling future mobile connectivity & sensing \nFrancois Brunier\nPartnership Program Manager\nSOITEC \nAbout me\n\n\n\n\nDigital Beamforming design in mmW: A 22nm FDSOI transceiver practical case \nJérôme Prouvée\nLayout Engineer & Project Manager\nCEA \nAbout me\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.20 am\nArtificial Intelligence IP and SoC\n \nChairperson: Costas Conistis – Alphawave Semi\n\n\n\n\nMeeting the Needs of AI Training with HBM3 \nPhilip Van Den Heuvel\nRegional Sales Manager\nRambus\, Inc. \nAbout me\n\n\n\n\nInnovative Integrated IP SoC Design for Edge AI \nTim Menasveta\nDirector of IoT Product Management\nArm Ltd. \nAbout me\n\n\n\n\nTransforming Far-Edge Computer Vision with Energy-Efficient A \nVincent Huard\nChief Technology Officer\nDolphin Design \nAbout me\n\n\n\n\n12.30 pm\nLunch\n\n\n\n1.30 pm\nNew Challenges\n \nChairperson: Eric Lalardie – Arm\n\n\n\n\nThe Lossless Compression Challenge: from Networking to Data centers \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\nAddressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects \nMichael Klempa\nProduct Marking Specialist\nAlphawave Semi \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nSafety Critical Applications\n \nChairperson: Dr. Calliope-Louisa Sotiropoulou – CAST\n\n\n\n\nIP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications \nPhilipp Jacobsohn\nSenior Staff Applications Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nGRLIB: VHDL IP library for fault-tolerant SoC \nFabio Malatesta\nProduct Marketing Engineer\nFrontgrade Gaisler \nAbout me\n\n\n\n\n3.10 pm\nAutomotive Applications\n\n\n\nCAN XL – can safety go in hand with performance? \nJacek Hanke\nCEO\nDigital Core Design \nAbout me\n\n\n\n\nSolve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM \nRuud Derwig\nSenior Staff Engineer for Security IP\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nSecurity Solutions\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nWhich IP for Which Security Certification Standard\, \nLudovic Merrien\nSecurity Certification Leader\nTiempo Secure \nAbout me\n\n\n\n\nLDPC Encoder/Decoder \nManish Mahajan\nFounder\nSecantec\, Inc. \nAbout me\n\n\n\n\nSecurity from chip to cloud with PQC (Post-Quantum Cryptography) \nBrice Gaignoux\nEMEA Pre-Sales Engineer\nSecure-IC \nAbout me\n\n\n\n\n5.20 pm\nBreak\n\n\n\n5.40 pm\nSecurity Solutions – 2\n \nChairperson: Ruud Derwig – Synopsys\, Inc.\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nHow will platform and communication security evolve in the quantum computing era? \nGraeme Hickey\nVP Engineering\nPQShield \nAbout me\n\n\n\n\nThe Power of Physical Unclonable Functions (PUFs) \nChris Jones\nDirector\, Field Application\nCrypto Quantique \nAbout me\n\n\n\n\n7.00 pm\nYou should not miss ! \nWine tasting party sponsored by Soitec\n\n\n\n\n8.00 pm\nBanquet sponsored by D&R\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2 – December 5th\, 2023\n\n\n\n\n\n\n\n9.00 am\nProcessor IP\n \nChairperson: Philippe Quinio – STMicroelectronics\n\n\n\n\nBeyond one-size-fits-all: The power of tailored CPUs \nMike Eftimakis\nVP Strategy & Ecosystem\nCodasip GmbH \nAbout me\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSurvey of market available processor IP \n\n\n\nDagmara Zielinska\nPartnership Program Manager\nD&Rwith Gabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\n\n\n\n\n9.40 – 11.00 am\nFrom Processor IP to Processor or supercomputer chip:  \n\nWhat is needed and what is the next success track ? \nThis panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.\n\nWith the participation of: \n\nFabio Malatesta – Product Marketing Engineer – Frontgrade Gaisler\nMike Eftimakis – VP Strategy and Ecosystem – Codasip GmbH\nLoic Lietar – Co-Founder & CEO – GreenWaves Technologies\nThierry Lelégard – Head of Platform Security – SiPearl\n\n\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.30 am\nAnalog IP\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\nAdaptive Voltage Scaling (AVS): Enhancing Chip Efficiency \nVincent Telandro\nProduct Marketing manager (Power Management IP)\nDolphin Design \nAbout me\n\n\n\n\nTechnology Analysis: what you need to know before embarking on analog design migration \nJean-François Lambert\nDirector of Business Development\nThalia \nAbout me\n\n\n\n\n12.15 pm\nLunch\n\n\n\n1.20 pm\nDesign Platform\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHybrid Cloud Management for IP Development \n\n\n\nSundar M\nDirector\nTessolve Semiconductor Private Limitedwith Pitchumani Guruswamy\nTessolve Semiconductor Private Limited \nAbout me\n\n\n\n\nOnline Only\n\n\n\n\nA novel approach for SoC design resource management and prediction \nChouki Aktouf\nCo-Founder\nInnova Advanced Technologies \nAbout me\n\n\n\n\nMulti-IO co-processor with TSN \nVincent Laporte\nCTO – V.P. BU\nCetraC \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nVerification Platform\n \nChairperson: Patrick Blouet\n\n\n\n\nIP QA Best Practices \nLionel Couder\nSr. Applications Engineer\nSiemens Digital Industries Software \nAbout me\n\n\n\n\nImportant Considerations for Verification of CXL Devices \nNicolas Dai\nApplication Engineer Architect\nCadence Design Systems\, Inc. \nAbout me\n\n\n\n\n3.10 pm\nMonitoring Platform\n\n\n\nChip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology. \nVsevolod Sergeenko\nRFID Team Leader\nNTLab \nAbout me\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nDan Alexandrescu\nR&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nGive Away – Event Closure
URL:https://marketingeda.com/event/ip-soc-conference-23-grenoble/
LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-23-Grenoble.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T090000
DTEND;TZID=America/Los_Angeles:20231130T100000
DTSTAMP:20231115T181114Z
CREATED:20231115T181059Z
LAST-MODIFIED:20231115T181114Z
UID:7097-1701334800-1701338400@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs with Efabless
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n\nOpenFrame – a new version of Caravel that gives 50% more area\nGPIO configuration questions\nThe new cocotb testing framework\nIPM – The new IP manager tool\nOpenLane design integration options\nGFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics-with-efabless/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231129T100000
DTEND;TZID=America/Los_Angeles:20231129T110000
DTSTAMP:20231120T172317Z
CREATED:20231113T181552Z
LAST-MODIFIED:20231120T172317Z
UID:7076-1701252000-1701255600@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part II
DESCRIPTION:Synopsys Webinar – Part II \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-ii/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-29-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20231128T080000
DTEND;TZID=Asia/Tokyo:20231128T170000
DTSTAMP:20230925T223508Z
CREATED:20230925T223508Z
LAST-MODIFIED:20230925T223508Z
UID:6881-1701158400-1701190800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Japan
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-japan/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231127T100000
DTEND;TZID=Europe/London:20231127T143000
DTSTAMP:20231108T173556Z
CREATED:20231108T173556Z
LAST-MODIFIED:20231108T173556Z
UID:7054-1701079200-1701095400@marketingeda.com
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:The FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda: \n\n\n\n10:00\nArrival and Registration\n\n\n10.30\nPeter Davies\, Thales – Security in FPGA-based Systems\n\n\n11:15\nMark Frost\, Intel – Security in FPGA\n\n\n11:35\nIan Pearson\, Microchip – System and Device Level Security Considerations\n\n\n11:55\nMaximilian Werner\, Efinix Inc – Efinix FPGA Encryption solution\n\n\n12:15\nAnkith Srinivasan & Guests – How and why we use FPGAs in our systems\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed
URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet-2/
LOCATION:Thales\, 350 Longwater Avenue\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-FPGA-November-23-1200x600-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20231123T080000
DTEND;TZID=Asia/Taipei:20231123T170000
DTSTAMP:20230925T223336Z
CREATED:20230925T223336Z
LAST-MODIFIED:20230925T223336Z
UID:6879-1700726400-1700758800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-taiwan-singapore/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231121T080000
DTEND;TZID=America/Los_Angeles:20231121T170000
DTSTAMP:20230925T223154Z
CREATED:20230925T223154Z
LAST-MODIFIED:20230925T223154Z
UID:6877-1700553600-1700586000@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – EMEA
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-emea/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T170000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231108T222010Z
CREATED:20231108T222010Z
LAST-MODIFIED:20231108T222010Z
UID:7064-1700154000-1700154000@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n– OpenFrame – a new version of Caravel that gives 50% more area \n– GPIO configuration questions \n– The new cocotb testing framework \n– IPM – The new IP manager tool \n– OpenLane design integration options \n– GFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T110000
DTEND;TZID=America/Los_Angeles:20231116T120000
DTSTAMP:20231009T172654Z
CREATED:20231009T172654Z
LAST-MODIFIED:20231009T172654Z
UID:6930-1700132400-1700136000@marketingeda.com
SUMMARY:System Simulation of Versal ACAP Designs
DESCRIPTION:AVersal ACAP\, developed by Xilinx/AMD\, is a groundbreaking adaptable platform composed of AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads\, including machine learning\, embedded computing\, and high-performance computing. \nIn this webinar\, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. We will also show how to run a system simulation of a Versal example design. \nRiviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL\, PS and AIE. The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application\, Riviera-PRO’s simulator for the PL kernels\, and  QEMU for the PS host application. SystemC models are also available for the AIE and NoC\, which can also be simulated in Riviera-PRO. \n  \nAgenda:\n\nVersal ACAP Overview\nVersal Simulation Flows and Simulation Models\nIntroduction to QEMU\nHardware Emulation (System Simulation)\nDemo\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/system-simulation-of-versal-acap-designs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231113T182451Z
CREATED:20231113T182330Z
LAST-MODIFIED:20231113T182451Z
UID:7079-1700128800-1700132400@marketingeda.com
SUMMARY:Webinar Series | RISC-V Ready for Prime Time?
DESCRIPTION:Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. \nWhether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation\, this webinar will provide invaluable insights\, practical strategies\, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration. \nSign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2 \n  \nAGENDA\n\nIntroduction to RISC-V: Understanding the modularity and appeal of RISC-V.\nCore Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs\, ASICs\, and FPGAs.\nVerification Strategies: Unveiling the tools and methodologies to address power\, performance\, concurrency\, inter-core communication\, synchronization\, security\, and safety concerns.\nReal-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.\nQ&A Session: An opportunity to get your questions answered by our experts.
URL:https://marketingeda.com/event/webinar-series-risc-v-ready-for-prime-time/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Impare-November-16-2023.jpg
END:VEVENT
END:VCALENDAR