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BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240116T090000
DTEND;TZID=Asia/Tokyo:20240116T170000
DTSTAMP:20231211T175014Z
CREATED:20231211T175014Z
LAST-MODIFIED:20231211T175014Z
UID:7149-1705395600-1705424400@marketingeda.com
SUMMARY:RISC-V Day\, Tokyo 2024 Winter
DESCRIPTION:The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday\, January 16\, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center\, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products\, as well as key people and engineers\, and provide business opportunities such as increasing product awareness\, realizing collaboration between companies\, technology exchange\, and information gathering. We look forward to your participation on this occasion! A video of the presentation and information on materials will be posted on the website at a later date.
URL:https://marketingeda.com/event/risc-v-day-tokyo-2024-winter/
LOCATION:Ito International Research Center\, The University of Tokyo\, Tokyo\, Japan
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Tokyo-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240109T080000
DTEND;TZID=America/Los_Angeles:20240112T170000
DTSTAMP:20231230T005013Z
CREATED:20231129T225332Z
LAST-MODIFIED:20231230T005013Z
UID:7133-1704787200-1705078800@marketingeda.com
SUMMARY:CES 2024
DESCRIPTION:Registration is now open for CES® 2024 — taking place Jan. 9-12\, in Las Vegas. \nFlip the switch on global business opportunity with CES\, where you can meet with partners\, customers\, media\, investors\, and policymakers from across the industry and the world all in one place. \nDon’t miss your chance to be a part of the most powerful tech event in the world.
URL:https://marketingeda.com/event/ces-2024/
LOCATION:Las Vegas Covention and World Trade Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CES-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240106T080000
DTEND;TZID=Asia/Kolkata:20240110T170000
DTSTAMP:20231228T190611Z
CREATED:20231227T173925Z
LAST-MODIFIED:20231228T190611Z
UID:7458-1704528000-1704906000@marketingeda.com
SUMMARY:VLSID 2024
DESCRIPTION:The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata\, India\, during January 6-10\, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders\, Indian and international industry bodies\, and academic researchers in a common platform. \nIn the present era of automation and connected things\, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift\, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”. \nBrilliant minds across the VLSI domain will brainstorm during the conference to redefine the future course of VLSI Design and Embedded research and application in India. Kolkata (Known as Calcutta during the British Imperial rule) is surrounded by several premier technical and scientific institutes like IIEST Shibpur (B. E. College\, Shibpur)\, IIT Kharagpur\, ISI Calcutta\, Calcutta University\, Jadavpur University etc. \nEast and north-eastern region of our country is a hub of innovation with a focus on emerging technologies. Over the years the region has generated huge number of ESDM professionals and academicians who are right now fueling the growth of ESDM industry. It is high time to operationalize state level high technology clusters in the field of VLSI design\, embedded systems\, cognitive system design and silicon/display/compound fab. VLSID 2024 provides the unique stage where MNCs\, start-ups\, industry bodies and academicians come together and get synergized with what the states of this region have to offer. \nOver a span of five-days of VLSID2024\, the summit will feed brains and nurture minds with state-of-the-art exhibitors\, presentations\, panel discussions\, innovation forums\, and tutorials by established technologists.
URL:https://marketingeda.com/event/vlsid-2024/
LOCATION:ITC Royal Bengal\, Kolkata\, India
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSID-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231214T100000
DTEND;TZID=America/Los_Angeles:20231214T110000
DTSTAMP:20231120T175241Z
CREATED:20231120T175241Z
LAST-MODIFIED:20231120T175241Z
UID:7114-1702548000-1702551600@marketingeda.com
SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs
DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO
URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T100000
DTEND;TZID=America/Los_Angeles:20231213T110000
DTSTAMP:20231211T211948Z
CREATED:20231211T211948Z
LAST-MODIFIED:20231211T211948Z
UID:7152-1702461600-1702465200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III
DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T090000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231204T224640Z
CREATED:20231204T224336Z
LAST-MODIFIED:20231204T224640Z
UID:7139-1702458000-1702461600@marketingeda.com
SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics
DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA.
URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20231208T080000
DTEND;TZID=Asia/Shanghai:20231208T170000
DTSTAMP:20230925T223711Z
CREATED:20230925T223711Z
LAST-MODIFIED:20230925T223711Z
UID:6883-1702022400-1702054800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – China
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-china/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T080000
DTEND;TZID=America/Los_Angeles:20231207T090000
DTSTAMP:20231117T204354Z
CREATED:20231117T204354Z
LAST-MODIFIED:20231117T204354Z
UID:7107-1701936000-1701939600@marketingeda.com
SUMMARY:Multi-Die System Verification with Siemens Avery UCIe VIP
DESCRIPTION:Conventional monolithic SoCs are becoming a bottleneck for power\, performance\, and area (PPA)\, creating limitations for Data-intensive applications like high-performance computing (HPC)\, machine learning (ML) and artificial intelligence (AI)\, and for hyperscale data centers. These bottlenecks are challenging Moore’s law\, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law\, but the semiconductor industry needs standardized interconnects to allow scaling up these systems\, with 2D\, 2.5D and even 3D packaging technologies. \nUniversal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption\, improved performance with the same latency of the system. \nIn this online seminar\, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP\, discussing its key features such as dynamic block-level and SoC level testbench creation\, traffic generation\, error injection\, debug features\, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market\, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP. \n  \nWhat You Will Learn: \n\nWhat is the Universal Chiplet Interconnect Express (UCIe)\nWhy do we need UCIe in chiplet designs: its evolution and application.\nDesign and Verification considerations when planning a UCIe based design.\nSiemens Avery UCIe Verification IP’s unique features.\n\nTechnical Demonstration. \nEnvironment / Testbench Creation \nDynamic Configuration \nTraffic Generation \nError Injection \nDebug features \n\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign\, Verification Engineers\, Managers and Architects working on or planning UCIe design projects\n\n  \nWhat/Which Products are Covered:  \n\nUCIe\nPCIe\nCXL\nChiplets\n\n\n\n\nSpeakers\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\nJustin Bunnell\nTechnical Product Manager\nSiemens EDA\n\n\nJustin Bunnell is a Technical Product Manager at Siemens EDA\, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.
URL:https://marketingeda.com/event/multi-die-system-verification-with-siemens-avery-ucie-vip/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20231204T090000
DTEND;TZID=Europe/Paris:20231205T170000
DTSTAMP:20231128T173642Z
CREATED:20231128T172805Z
LAST-MODIFIED:20231128T173642Z
UID:7122-1701680400-1701795600@marketingeda.com
SUMMARY:IP-SoC Conference 23 - Grenoble
DESCRIPTION:A worldwide connected Event !! \nIP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. \nThe event is the annual opportunity for IP providers and IP consumers to share information about technology trends\, innovative IP SoC products\, Breaking IP/SoC News\, Market evolution and more. \nThe Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives\, market analyzer and technical experts from Foundry/technology\, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business. \nAs far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging\, Security\, Artificial Intelligence\, Green Electronics\, … \nAnd over all you cannot miss The wine Tasting Party !! \nExhibition tables and “discussion panels” will favor vendor and customer meetings. \nAny question? Please contact us \nRegistration and Exhibition installation opens at 7 am. \n\n\n\n\n\n\nDay 1 – December 4th\, 2023\n\n\n\n\n\n\n\n9.00 am\nIntroduction Session\n\n\n\nWelcome : Innovation in semi conductor industry \nGabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\nEmpowering Innovation in the Age of Custom Silicon \nEric Lalardie\nDirector\nArm Ltd. \nAbout me\n\n\n\n\n9.40 am\nBreak\n\n\n\n10.00 am\nNew technology the lead of innovation\n \nChairperson: Yves Quere – CEA\n\n\n\n\nGreening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology \nPhilippe Flatresse\nProduct Marketing\nSOITEC \nAbout me\n\n\n\n\nTechnologies enabling future mobile connectivity & sensing \nFrancois Brunier\nPartnership Program Manager\nSOITEC \nAbout me\n\n\n\n\nDigital Beamforming design in mmW: A 22nm FDSOI transceiver practical case \nJérôme Prouvée\nLayout Engineer & Project Manager\nCEA \nAbout me\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.20 am\nArtificial Intelligence IP and SoC\n \nChairperson: Costas Conistis – Alphawave Semi\n\n\n\n\nMeeting the Needs of AI Training with HBM3 \nPhilip Van Den Heuvel\nRegional Sales Manager\nRambus\, Inc. \nAbout me\n\n\n\n\nInnovative Integrated IP SoC Design for Edge AI \nTim Menasveta\nDirector of IoT Product Management\nArm Ltd. \nAbout me\n\n\n\n\nTransforming Far-Edge Computer Vision with Energy-Efficient A \nVincent Huard\nChief Technology Officer\nDolphin Design \nAbout me\n\n\n\n\n12.30 pm\nLunch\n\n\n\n1.30 pm\nNew Challenges\n \nChairperson: Eric Lalardie – Arm\n\n\n\n\nThe Lossless Compression Challenge: from Networking to Data centers \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\nAddressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects \nMichael Klempa\nProduct Marking Specialist\nAlphawave Semi \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nSafety Critical Applications\n \nChairperson: Dr. Calliope-Louisa Sotiropoulou – CAST\n\n\n\n\nIP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications \nPhilipp Jacobsohn\nSenior Staff Applications Engineer\nSmartDV Technologies \nAbout me\n\n\n\n\nGRLIB: VHDL IP library for fault-tolerant SoC \nFabio Malatesta\nProduct Marketing Engineer\nFrontgrade Gaisler \nAbout me\n\n\n\n\n3.10 pm\nAutomotive Applications\n\n\n\nCAN XL – can safety go in hand with performance? \nJacek Hanke\nCEO\nDigital Core Design \nAbout me\n\n\n\n\nSolve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM \nRuud Derwig\nSenior Staff Engineer for Security IP\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nBreak\n\n\n\n4.20 pm\nSecurity Solutions\n \nChairperson: Bart Stevens – Rambus\, Inc.\n\n\n\n\nWhich IP for Which Security Certification Standard\, \nLudovic Merrien\nSecurity Certification Leader\nTiempo Secure \nAbout me\n\n\n\n\nLDPC Encoder/Decoder \nManish Mahajan\nFounder\nSecantec\, Inc. \nAbout me\n\n\n\n\nSecurity from chip to cloud with PQC (Post-Quantum Cryptography) \nBrice Gaignoux\nEMEA Pre-Sales Engineer\nSecure-IC \nAbout me\n\n\n\n\n5.20 pm\nBreak\n\n\n\n5.40 pm\nSecurity Solutions – 2\n \nChairperson: Ruud Derwig – Synopsys\, Inc.\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nBart Stevens\nSenior Director of Product Marketing\nRambus\, Inc. \nAbout me\n\n\n\n\nHow will platform and communication security evolve in the quantum computing era? \nGraeme Hickey\nVP Engineering\nPQShield \nAbout me\n\n\n\n\nThe Power of Physical Unclonable Functions (PUFs) \nChris Jones\nDirector\, Field Application\nCrypto Quantique \nAbout me\n\n\n\n\n7.00 pm\nYou should not miss ! \nWine tasting party sponsored by Soitec\n\n\n\n\n8.00 pm\nBanquet sponsored by D&R\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDay 2 – December 5th\, 2023\n\n\n\n\n\n\n\n9.00 am\nProcessor IP\n \nChairperson: Philippe Quinio – STMicroelectronics\n\n\n\n\nBeyond one-size-fits-all: The power of tailored CPUs \nMike Eftimakis\nVP Strategy & Ecosystem\nCodasip GmbH \nAbout me\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSurvey of market available processor IP \n\n\n\nDagmara Zielinska\nPartnership Program Manager\nD&Rwith Gabrièle Saucier\nCEO\nD&R \nAbout me\n\n\n\n\n\n\n\n\n9.40 – 11.00 am\nFrom Processor IP to Processor or supercomputer chip:  \n\nWhat is needed and what is the next success track ? \nThis panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.\n\nWith the participation of: \n\nFabio Malatesta – Product Marketing Engineer – Frontgrade Gaisler\nMike Eftimakis – VP Strategy and Ecosystem – Codasip GmbH\nLoic Lietar – Co-Founder & CEO – GreenWaves Technologies\nThierry Lelégard – Head of Platform Security – SiPearl\n\n\n\n\n\n\n11.00 am\nBreak\n\n\n\n11.30 am\nAnalog IP\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\nAdaptive Voltage Scaling (AVS): Enhancing Chip Efficiency \nVincent Telandro\nProduct Marketing manager (Power Management IP)\nDolphin Design \nAbout me\n\n\n\n\nTechnology Analysis: what you need to know before embarking on analog design migration \nJean-François Lambert\nDirector of Business Development\nThalia \nAbout me\n\n\n\n\n12.15 pm\nLunch\n\n\n\n1.20 pm\nDesign Platform\n \nChairperson: Philippe Flatresse – SOITEC\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHybrid Cloud Management for IP Development \n\n\n\nSundar M\nDirector\nTessolve Semiconductor Private Limitedwith Pitchumani Guruswamy\nTessolve Semiconductor Private Limited \nAbout me\n\n\n\n\nOnline Only\n\n\n\n\nA novel approach for SoC design resource management and prediction \nChouki Aktouf\nCo-Founder\nInnova Advanced Technologies \nAbout me\n\n\n\n\nMulti-IO co-processor with TSN \nVincent Laporte\nCTO – V.P. BU\nCetraC \nAbout me\n\n\n\n\n2.10 pm\nBreak\n\n\n\n2.30 pm\nVerification Platform\n \nChairperson: Patrick Blouet\n\n\n\n\nIP QA Best Practices \nLionel Couder\nSr. Applications Engineer\nSiemens Digital Industries Software \nAbout me\n\n\n\n\nImportant Considerations for Verification of CXL Devices \nNicolas Dai\nApplication Engineer Architect\nCadence Design Systems\, Inc. \nAbout me\n\n\n\n\n3.10 pm\nMonitoring Platform\n\n\n\nChip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology. \nVsevolod Sergeenko\nRFID Team Leader\nNTLab \nAbout me\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nDan Alexandrescu\nR&D Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\n4.00 pm\nGive Away – Event Closure
URL:https://marketingeda.com/event/ip-soc-conference-23-grenoble/
LOCATION:Hotel Europole\, 29 rue Pierre-Sémard\, Grenoble\, France
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-23-Grenoble.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T090000
DTEND;TZID=America/Los_Angeles:20231130T100000
DTSTAMP:20231115T181114Z
CREATED:20231115T181059Z
LAST-MODIFIED:20231115T181114Z
UID:7097-1701334800-1701338400@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs with Efabless
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n\nOpenFrame – a new version of Caravel that gives 50% more area\nGPIO configuration questions\nThe new cocotb testing framework\nIPM – The new IP manager tool\nOpenLane design integration options\nGFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics-with-efabless/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231129T100000
DTEND;TZID=America/Los_Angeles:20231129T110000
DTSTAMP:20231120T172317Z
CREATED:20231113T181552Z
LAST-MODIFIED:20231120T172317Z
UID:7076-1701252000-1701255600@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part II
DESCRIPTION:Synopsys Webinar – Part II \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-ii/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-29-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20231128T080000
DTEND;TZID=Asia/Tokyo:20231128T170000
DTSTAMP:20230925T223508Z
CREATED:20230925T223508Z
LAST-MODIFIED:20230925T223508Z
UID:6881-1701158400-1701190800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Japan
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-japan/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231127T100000
DTEND;TZID=Europe/London:20231127T143000
DTSTAMP:20231108T173556Z
CREATED:20231108T173556Z
LAST-MODIFIED:20231108T173556Z
UID:7054-1701079200-1701095400@marketingeda.com
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:The FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda: \n\n\n\n10:00\nArrival and Registration\n\n\n10.30\nPeter Davies\, Thales – Security in FPGA-based Systems\n\n\n11:15\nMark Frost\, Intel – Security in FPGA\n\n\n11:35\nIan Pearson\, Microchip – System and Device Level Security Considerations\n\n\n11:55\nMaximilian Werner\, Efinix Inc – Efinix FPGA Encryption solution\n\n\n12:15\nAnkith Srinivasan & Guests – How and why we use FPGAs in our systems\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed
URL:https://marketingeda.com/event/fpga-frontrunner-meet-greet-2/
LOCATION:Thales\, 350 Longwater Avenue\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-FPGA-November-23-1200x600-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20231123T080000
DTEND;TZID=Asia/Taipei:20231123T170000
DTSTAMP:20230925T223336Z
CREATED:20230925T223336Z
LAST-MODIFIED:20230925T223336Z
UID:6879-1700726400-1700758800@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-taiwan-singapore/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231121T080000
DTEND;TZID=America/Los_Angeles:20231121T170000
DTSTAMP:20230925T223154Z
CREATED:20230925T223154Z
LAST-MODIFIED:20230925T223154Z
UID:6877-1700553600-1700586000@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – EMEA
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-emea/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T170000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231108T222010Z
CREATED:20231108T222010Z
LAST-MODIFIED:20231108T222010Z
UID:7064-1700154000-1700154000@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n– OpenFrame – a new version of Caravel that gives 50% more area \n– GPIO configuration questions \n– The new cocotb testing framework \n– IPM – The new IP manager tool \n– OpenLane design integration options \n– GFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T110000
DTEND;TZID=America/Los_Angeles:20231116T120000
DTSTAMP:20231009T172654Z
CREATED:20231009T172654Z
LAST-MODIFIED:20231009T172654Z
UID:6930-1700132400-1700136000@marketingeda.com
SUMMARY:System Simulation of Versal ACAP Designs
DESCRIPTION:AVersal ACAP\, developed by Xilinx/AMD\, is a groundbreaking adaptable platform composed of AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads\, including machine learning\, embedded computing\, and high-performance computing. \nIn this webinar\, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. We will also show how to run a system simulation of a Versal example design. \nRiviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL\, PS and AIE. The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application\, Riviera-PRO’s simulator for the PL kernels\, and  QEMU for the PS host application. SystemC models are also available for the AIE and NoC\, which can also be simulated in Riviera-PRO. \n  \nAgenda:\n\nVersal ACAP Overview\nVersal Simulation Flows and Simulation Models\nIntroduction to QEMU\nHardware Emulation (System Simulation)\nDemo\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/system-simulation-of-versal-acap-designs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231113T182451Z
CREATED:20231113T182330Z
LAST-MODIFIED:20231113T182451Z
UID:7079-1700128800-1700132400@marketingeda.com
SUMMARY:Webinar Series | RISC-V Ready for Prime Time?
DESCRIPTION:Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. \nWhether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation\, this webinar will provide invaluable insights\, practical strategies\, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration. \nSign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2 \n  \nAGENDA\n\nIntroduction to RISC-V: Understanding the modularity and appeal of RISC-V.\nCore Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs\, ASICs\, and FPGAs.\nVerification Strategies: Unveiling the tools and methodologies to address power\, performance\, concurrency\, inter-core communication\, synchronization\, security\, and safety concerns.\nReal-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.\nQ&A Session: An opportunity to get your questions answered by our experts.
URL:https://marketingeda.com/event/webinar-series-risc-v-ready-for-prime-time/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Impare-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T090000
DTEND;TZID=America/Los_Angeles:20231116T100000
DTSTAMP:20231115T180404Z
CREATED:20231115T180404Z
LAST-MODIFIED:20231115T180404Z
UID:7094-1700125200-1700128800@marketingeda.com
SUMMARY:Boost SoC debug and analytics with embedded software and smart monitors
DESCRIPTION:On-chip monitors and debug structures can dramatically simplify debug\, validation\, analytics\, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this webinar\, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative to extract even more insights out of your on-chip monitors and debug structures for analytics and optimization\, and to create a self-contained on-chip monitoring system. \nWe will explore how the Tessent Embedded SDK can be used to build embedded software applications to orchestrate Tessent Embedded Analytics on-chip smart monitors. With the combination of embedded software and a complete on-chip monitoring solution\, you can perform non-intrusive real-time logging\, cache more data for later analysis\, enable real-time performance analysis and anomaly detection. \n  \nWhat you will learn: \n\nDiscover the Tessent Embedded Software Development Kit (Embedded SDK)\, a suite of software utilities that allows SoCs to be equipped with self-contained monitoring and analytics capabilities\nExplore which debug\, optimization and monitoring tasks can be simplified using embedded software.\nLearn how to develop embedded applications using the Tessent Embedded SDK\n\n  \nWho Should Attend: \n\nEmbedded SW Engineers\nSilicon bring-up engineers\nSoC architects\n\n  \nSpeaker\n \nNaga Nagarajan \nSoftware Engineer \nSiemens EDA \n  \nNaga Nagarajan is a software engineer at Siemens EDA. Naga began his career with UltraSoC (acquired by Mentor Graphics which is now Siemens EDA) where he focused on improving the host-based analytics software product known as SystemInsight. Naga now focuses on the development of the Tessent Embedded SDK products\, including the entire implementation of critical features such as in-life\, real-time performance monitoring and analytics. Naga holds an MEng in Electrical and Electronic Engineering.
URL:https://marketingeda.com/event/boost-soc-debug-and-analytics-with-embedded-software-and-smart-monitors/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Seoul:20231116T080000
DTEND;TZID=Asia/Seoul:20231116T170000
DTSTAMP:20230925T223032Z
CREATED:20230925T223032Z
LAST-MODIFIED:20230925T223032Z
UID:6875-1700121600-1700154000@marketingeda.com
SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Korea
DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today.
URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-korea/
LOCATION:CA
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231115T090000
DTEND;TZID=America/New_York:20231115T170000
DTSTAMP:20231018T180605Z
CREATED:20231018T180605Z
LAST-MODIFIED:20231018T180605Z
UID:6969-1700038800-1700067600@marketingeda.com
SUMMARY:ASIP University Day 2023
DESCRIPTION:ASIP University Day: Domain-Specific Processor Design using ASIP Designer\n\n\nApplication-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough.  Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as artificial intelligence\, image and video processing or automated driving assistance have fueled the development of such ASIPs\, and triggered many university projects.  Processor design projects such as the RISC-V initiative also initiated a lot of interest.  With all the commercial activity around RISC-V these days\, it has outgrown UC Berkeley. \nSynopsys ASIP Designer is the market leading tool for ASIP design\, verification\, and programming. It is used by leading companies around the globe with hundreds of successful projects to date. \nAt this informal event\, leading university teams will present results from their ongoing ASIP projects in a variety of application domains. Synopsys will share insight on market trends\, and provide a technical update on ASIP Designer along with reference examples.
URL:https://marketingeda.com/event/asip-university-day-2023/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-15-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T110000
DTEND;TZID=America/Los_Angeles:20231114T120000
DTSTAMP:20231103T204425Z
CREATED:20231103T204425Z
LAST-MODIFIED:20231103T204425Z
UID:7040-1699959600-1699963200@marketingeda.com
SUMMARY:Why Chiplets with UCIe are the Next Big Thing
DESCRIPTION:Artificial intelligence (AI) and virtual reality (VR) require fast\, efficient\, low-power technologies. Transistors are becoming harder and harder to shrink\, so chiplets are a promising alternative. Chiplets are small\, modular dies that use UCIe\, an open industry standard\, to communicate with each other. Combined in a Systems-on-Package (SoP)\, they provide superior performance\, reduced power consumption\, and increased design flexibility for customized applications such as cell phones\, autonomous vehicles\, etc. In this panel session\, signal and power integrity experts will discuss: \n  \n\nIndustry trends and why chiplets with UCIe are the next big thing.\nSignal and power integrity considerations when integrating chiplets and UCIe interfaces.\nEDA tools evolved\, and how to streamline chiplets integration into the design workflow.\n\nSpeakers:\n\n\n\nHeeSoo Lee\nSerDes/DDR Product Owner\, Keysight Technologies\n\n\nHeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division\, located in Santa Rosa\, Calif. He has held several positions in Keysight Technologies\, Agilent Technologies and Hewlett-Packard\, including consulting business manager\, technical marketing lead and field applications engineer since 1989. Prior to these positions\, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF\, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University\, South Korea. \n\nHeidi Barnes\nSenior Application Engineer and Power Integrity Product Owner\, Keysight Technologies\n\n\nHeidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight\, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation\, her recent activities include the application of electromagnetic\, transient\, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017. \n\nRandy White\nMemory Solutions Program Manager\, Keysight Technologies\n\n\nRandy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server\, mobile\, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques\, including de-embedding algorithms\, measurement/model correlation\, high-speed measurements for real-time & sampling oscilloscopes\, and BERTs & AWGs. He has participated on many standards committees\, including PCI-SIG\, USB-IF\, SATA-IO\, and JEDEC\, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
URL:https://marketingeda.com/event/why-chiplets-with-ucie-are-the-next-big-thing/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231110T193817Z
CREATED:20231110T193817Z
LAST-MODIFIED:20231110T193817Z
UID:7070-1699956000-1699959600@marketingeda.com
SUMMARY:Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
DESCRIPTION:As semiconductor industry leaders\, Bosch\, Infineon\, Nordic Semiconductor\, NXP\, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors\, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software\, this webinar will offer key insights into developing your own ISO 26262-grade\, Certified ASIL RISC-V automotive chip solution. Don’t miss this opportunity to stay ahead in the evolving semiconductor landscape. \nSpeakers: \nMarvin Chao\, Andes Technology Director of Solution Architecture\, will provide insights into the functionality and capabilities of the ISO 26262-certified AndesCore N25F-SE CPU IP. Learn how this new open-source CPU ISA is addressing the unique demands of automotive applications\, ensuring safety\, reliability\, and performance. \nChuck Brokish\, Green Hills Software Director of Automotive Business Development\, will demonstrate how Green Hills’ MULTI and TimeMachine Software Development Tools\, µ-velOSity Real-Time Operating System\, and Hardware Debugging and Trace Probes can be effectively used to write and debug ISO 26262-certified software that runs efficiently on the N25F-SE CPU IP. \n*This webinar is in partnership with SemiWiki\, Andes\, and Green Hills Software*
URL:https://marketingeda.com/event/leverage-certified-risc-v-ip-to-craft-asil-iso-26262-grade-automotive-chips/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-November-14-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T130000
DTEND;TZID=America/New_York:20231109T140000
DTSTAMP:20231030T181412Z
CREATED:20231030T181412Z
LAST-MODIFIED:20231030T181412Z
UID:7012-1699534800-1699538400@marketingeda.com
SUMMARY:Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace\, Government\, and Defense Systems
DESCRIPTION:Join industry experts from aerospace\, government\, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI)\, highlighting some of the technological\, manufacturing\, and economic complexities as well as security\, reliability\, and safety challenges.  The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research program plans to grow the 3DHI R&D ecosystem. Whether you are an engineer or a policymaker looking to deepen your 3DHI knowledge\, this panel offers insightful discussions to help anticipate and address future microelectronics design challenges for aerospace\, government\, and defense systems. \nSpeakers\nIan Land\nSynopsys\nSenior Director\, Security\, Government and Aerospace Solutions\nModerator \nDr. Carl McCants\nSpecial Assistant to the DARPA Director \nDr. Josh Fryman\nIntel Corporation\nFellow \nRob Aitken\nSynopsys\nDistinguished Architect
URL:https://marketingeda.com/event/tackling-challenges-in-3d-heterogenous-integrated-3dhi-microelectronics-for-aerospace-government-and-defense-systems/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231109T090000
DTEND;TZID=America/Los_Angeles:20231109T133000
DTSTAMP:20231027T171914Z
CREATED:20231027T171914Z
LAST-MODIFIED:20231027T171914Z
UID:7001-1699520400-1699536600@marketingeda.com
SUMMARY:CHIPS Alliance - FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
DESCRIPTION:IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side\, the concept of package managers is widely used to build a product from many different sources\, but chip designers often rely on ad-hoc solutions which tends to build up a maintenance cost and burden. Fortunately FuseSoC and Edalize exists to help. Being the most popular package manager for IP cores\, there are already hundreds of FuseSoC-compatible IP cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so\, and it is being increasingly used inside small and large companies for development of proprietary systems as well. With support for almost 40 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification. Sounds great\, doesn’t it? It sure does\, and this presentation will take you through the basics of FuseSoC to help you get started\, using VeeRwolf\, the CHIPS Alliance-governed reference platform for the VeeR family of CPU cores as an example\, and looks beyond this to how FuseSoC can help you focus on your core business instead of your cores.
URL:https://marketingeda.com/event/chips-alliance-fusesoc-package-manager-and-build-abstraction-tool-for-fpga-asic-development/
LOCATION:Google\, 237 Moffett Park Drive\, Sunnyvale\, CA\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Chips-Alliance-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231030T180110Z
CREATED:20231030T175759Z
LAST-MODIFIED:20231030T180110Z
UID:7009-1699437600-1699441200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part I
DESCRIPTION:Synopsys Webinar – Part I  \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-i/
LOCATION:CA
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20231107T090000
DTEND;TZID=Asia/Kolkata:20231108T180000
DTSTAMP:20231103T191339Z
CREATED:20231103T191339Z
LAST-MODIFIED:20231103T191339Z
UID:7036-1699347600-1699466400@marketingeda.com
SUMMARY:IESA AI Summit
DESCRIPTION:Experience the unprecedented growth opportunities in the semiconductor and electronics industry\, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions\, captivating emerging markets in the realm of AI.\nWitness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI\, igniting a renaissance in the electronics landscape. \nIn the dynamic realm of the Intelligent Electronics & Semiconductor ecosystem\, the India Electronics and Semiconductor Association (IESA) eagerly explores the immense potential of AI in the hardware sector. Unlock the limitless possibilities of AI and shape the future of the semiconductor industry. \nEmbrace cutting-edge technologies\, network with industry experts\, and drive innovation at the forefront of AI’s revolution in hardware.
URL:https://marketingeda.com/event/iesa-ai-summit/
LOCATION:Trident Hotel Hyderabad\, Hyderabad\, India
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IESA-AI-Summit-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231106T090000
DTEND;TZID=America/Los_Angeles:20231106T120000
DTSTAMP:20230926T165725Z
CREATED:20230926T165725Z
LAST-MODIFIED:20230926T165725Z
UID:6885-1699261200-1699272000@marketingeda.com
SUMMARY:RISC-V 101
DESCRIPTION:The RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard\, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. \nYou’ve seen the headlines and stories. Now\, here’s your chance to learn all about RISC-V and why it is being rapidly adopted by organizations of all size around the world. RISC-V 101 is your introduction to RISC-V and a primer on the ISA and ecosystem. \nThis free\, special event will cover the history of RISC-V and why organizations around the world are choosing it as the architecture for their computing needs. \nLearn more about RISC-V’s ecosystem\, including contributions from commercial companies\, research institutes\, consortia and government organizations. Discover how they are using RISC-V in their own applications and developing technologies that are powering solutions in a wide range of markets including data center\, automotive\, mobile\, embedded and more. \nRISC-V 101 will also feature breakout sessions to explore specific topics\, such as commercial solutions\, software development\, careers and getting started in technical committees. \nIf you have wanted to better understand what the hype is about\, here’s your chance to hear directly from and meet our community. On the eve of RISC-V Summit North America\, come to RISC-V 101 to learn how RISC-V could impact your future trajectory. \nThere is no cost to attend\, but you must register to guarantee your seat. Register now to unlock your understanding of RISC-V!
URL:https://marketingeda.com/event/risc-v-101/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-November-6-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231106T080000
DTEND;TZID=America/Los_Angeles:20231108T170000
DTSTAMP:20230905T182638Z
CREATED:20230905T182638Z
LAST-MODIFIED:20230905T182638Z
UID:6779-1699257600-1699462800@marketingeda.com
SUMMARY:RISC-V Summit US
DESCRIPTION:Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V\, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy unprecedented design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis November\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies to network and build relationships and to experience much more. \n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo full of community members showcasing their the latest community innovations and offerings.\n\nIt’s community-curated content and innovation at the heart of the next wave of growth for RISC-V. \nFind out what’s happening in Automotive\, Data Centers\, Embedded\, Mobile\, AI/ML\, Security\, Software Stacks\, Development Tools\, Systems on a Chip\, Chiplets and more! It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. Meet your heroes. It’s all during RISC-V Week North America\, this November. Come join us! \nJoin us in Santa Clara\, CA for RISC-V Summit 2023! \nFor more information\, visit https://events.linuxfoundation.org/riscv-summit/.
URL:https://marketingeda.com/event/risc-v-summit-us/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-SUMMIT-US-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Denver:20231102T093000
DTEND;TZID=America/Denver:20231102T170000
DTSTAMP:20231019T045430Z
CREATED:20231019T045430Z
LAST-MODIFIED:20231019T045430Z
UID:6972-1698917400-1698944400@marketingeda.com
SUMMARY:RISC-V in Space
DESCRIPTION:Join us for “RISC-V in… Space” on November 2\, 2023\, as we explore the exciting intersection of RISC-V\, electronics design\, and space! \n\n\n\nAgenda\n\n\n\n\n\n9:30 AM – 10:00 AM \nRegistration & Welcome \n\n\n\n\n10:00 AM – 12:00 PM \nCase Study Presentations: Tenstorrent\, Synopsys\, RISC AI\, Arteris IP \n\n\n\n\n12:00 PM – 1:00 PM \nLunch Buffet \n\n\n\n\n1:00 PM – 3:00 PM \nCase Study Presentations: Breker Systems\, Imperas\, Cycuity\, Codasip \n\n\n\n\n3:00 PM – 5:00 PM \nNetworking Reception with appetizers and refreshments \n\n\n\n\n\n\nAbout this event\n\n\n7 hours\nMobile eTicket\n\n\n\n\nTenstorrent is hosting a meet up in Denver aimed at practitioners and entrepreneurs developing electronic systems and components for space applications. Alongside partners Codasip\, Cycuity\, Breker Systems\, Imperas\, RISC AI\, Synopsys\, and Arteris IP we are excited to invite you to explore with us at the Omni Interlocken Hotel in Broomfield\, CO. \nThrough user-group discussions\, case studies\, and application notes (and steering clear of sales pitches) we’ll explore the exciting sector of space electronics with crucial emphasis on: \n\nArtificial Intelligence & Machine Learning\nEmbedded Processing\nSecurity\nDesign Verification
URL:https://marketingeda.com/event/risc-v-in-space/
LOCATION:Omni Interlocken Hotel\, 5000 Interlocken boulevard\, Broomfield\, CO\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Temstorrent-November-2-2023.jpg
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END:VCALENDAR