BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20241106T093000
DTEND;TZID=America/Chicago:20241106T170000
DTSTAMP:20241017T160903Z
CREATED:20241017T160613Z
LAST-MODIFIED:20241017T160903Z
UID:8425-1730885400-1730912400@marketingeda.com
SUMMARY:Verification Academy Live: Austin
DESCRIPTION:Overview \nThis seminar will update you on technologies and techniques you can adopt to\nincrease your verification productivity today. Specifically\, we will cover: \n\nHow the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains.\nProtocol and memory verification solutions you need for your next silicon verification project.\nData-driven verification with automated analytics\, collaboration\, and traceability capabilities.\nTechnologies and techniques you can adopt to increase your DFT productivity.\n\n‌\n‌ \nAgenda \n9:30 am – 10:00 am\nRegistration and check-in\nCoffee and networking with your peers\n‌\n10:00 am – 10:05 am\nWelcome/Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n‌\n10:05 am – 11:00 am\nKeyNote: Smart Verification – Faster is not Enough\nAbhi Kolpekwar | VP & GM\, Digital Verification Technologies Division \nThe electronics industry is on the brink of an unprecedented paradigm shift. The AI/ML-focused chips account for 20% of the semiconductor market\, a figure set to skyrocket to 73% by 2030\, fueled by the ongoing digital transformation. This seismic shift will significantly impact the architecture\, design\, and manufacturing of computing\, networking\, and communication solutions\, necessitating careful consideration of power\, performance\, security\, and safety concerns. Conventional verification flows\, reliant on disparate point tools\, will struggle to meet the demands of emerging systems. This keynote explores the prevailing macro-trends shaping today’s digital transformation before outlining a visionary approach to functional verification. By leveraging collective wisdom across tools\, technologies\, workflows\, and methodologies\, this new paradigm promises productivity gains beyond the reach of traditional methods.\n‌\n11:00 am – Noon\nQuesta Verification IQ:\nBoost verification predictability and efficiency with Big Data\nAhmed ElKady | Product Engineer \nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost.\n‌\nNoon – 12:45 pm\nLunch and networking\n‌\n12:45 pm – 1:15 pm\nQuesta Verification IQ: Sneak Peek of Debug IQ and Regression IQ\n‌\nContinuation of the Questa Verification IQ session.\n‌\n1:15 pm – 2:00 pm\nThe New Leader in Verification IP: Questa + Avery Solutions\nLuis Rodriguez | Senior Technical Product Manager & VIP Architect \nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n‌\n2:00 pm – 2:30 pm\nCapturing additional DFT coverage thru Functional Fault Grading\nByron Brinson | Product Engineer \nIdeally\, for manufacturing test coverage the goal is to achieve 100%. This becomes even more important for chips used in safety critical applications. However\, there are usually limitations regarding the amount of coverage that the DFT infrastructure can provide within a chip. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.\n‌\nb\nAccelerating Verification Closure with Siemens DFT Tailored Verification Solutions\nRick Koster | Product Engineer \nAs semiconductor designs evolve to more complex architectures\, 3DICs\, and heterogeneous integration\, verification engineers face increasing pressure to accelerate DFT verification closure. Siemens offers a comprehensive technology suite tailored to industry leading Tessent solutions\, designed to address the growing complexity and increasing challenges in Design for Test (DFT). This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows\, delivering industry leading performance and enhanced user experience\, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.\n‌\n3:00 pm- 5:00 pm\nTopGolf happy hour & networking\n‌ \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/verification-academy-live-austin/
LOCATION:Top Golf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-6-2024.jpg
END:VEVENT
END:VCALENDAR