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SUMMARY:Rambus Design Summit 2023
DESCRIPTION:Back for its fourth year\, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center\, AI/ML\, automotive and IoT applications. \n\n\nAgenda + Abstracts\n\n\n\n\n\nRambus Design Summit will take place over two days\, with day one focusing on memory & interface solutions\, and day two on security solutions. Take a look at the agenda below – all times in Pacific Daylight Time (PDT). \n\n\n\n\n\n\n\nTuesday\, July 18: Memory & Interface Solutions\n\nTackling advanced data center workloads requires ever increasing levels of memory bandwidth and capacity\, as well as high-speed interconnects. Hear Rambus technology experts share their insights on future memory and interconnect requirements in the data center covering critical enabling technologies including DDR5\, HBM3\, PCIe 6.0\, GDDR6\, LPDDR5X\, CXL\, and MIPI/VESA video compression. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: CXL Technology: Revolutionizing the Data Center \nSpeaker: Mark Orthodoxou\, Vice President of Strategic Marketing\nAbstract: The need for more memory bandwidth and capacity continues to rise\, with applications like generative AI pushing current data center infrastructure to the limit. The leading companies at every level of the data center value chain are coalescing around CXL technology as a path to revolutionize the data center. Join Mark Orthodoxou to hear how CXL promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage\, as well as enabling new tiered-memory solutions and composable architectures.\n\n\n8:30am\nInnovations in CXL 3.0: Novel Device Types\, Capabilities\, and Interconnects \nSpeaker: Danny Moore\, Senior Product Marketing Manager\nAbstract: CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type\, CXL Multi-Headed Devices\, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.\n\n\n9:00am\nSystem Level Design Considerations for PCIe 6.0 \nSpeaker: Lou Ternullo\, Senior Director of Product Marketing\nAbstract: PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate\, PAM4 signaling\, forward error correction\, and a low power L0p mode. In this presentation\, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design\, including how to get the most out of each of the PCIe devices.\n\n\n9:30am\nLeveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays \nSpeakers: Simon Bussières\, Director of Systems Architecture\nJoe Rodriguez\, Product Marketing Manager\nAbstract: Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions\, faster refresh rates\, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality\, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.\n\n\n10:00am\nMeeting the Needs of Generative AI Training with HBM3 \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI training models are growing in both size and sophistication at a lightning pace\, requiring more and more bandwidth. With its unique 2.5D/3D architecture\, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.\n\n\n10:30am\nPowering AI/ML Inference with GDDR6 Memory \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: GDDR6 memory offers an impressive combination of bandwidth\, capacity\, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.\n\n\n11:00am\nLPDDR5X: Delivering High Bandwidth and Power Efficiency \nSpeaker: Vinitha Seevaratnam\, Senior Product Marketing Manager\nAbstract: The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT\, automotive\, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.\n\n\n11:30am\nWhat’s Next for DDR5 Memory? \nSpeaker: John Eble\, Vice President of Product Marketing\nAbstract: With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory\, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels\, be deployed in new applications beyond RDIMMs\, and how it is tailored for client computing systems.\n\n\n12:00pm\nHigh-Performance Memory: Ask Me Anything \nSpeakers: Tim Messegee\, Senior Director of Solutions Marketing\nSteven Woo\, Fellow and Distinguished Inventor\nJohn Eble\, Vice President of Product Marketing\nMark Orthodoxou\, Vice President of Strategic Marketing\nFrank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI is just one of the many applications driving the relentless need for better memory performance\, capacity and efficiency in the data center. Join our experts as they discuss some of the biggest memory challenges facing the industry today\, contemplate how the industry will innovate to meet future data center memory needs\, and answer all your questions!\n\n\n\n\n\n\nWednesday\, July 19: Security Solutions\n\nSecurity anchored in hardware provides the foundation for protecting data and devices at all stages of the semiconductor lifecycle. Join Rambus Security experts as they share their insights on security threats facing the industry including those that will arise in the era of quantum computers. Learn how you can protect hardware and data at rest\, in motion and in use with Root of Trust\, MACsec\, Inline Memory Encryption\, and more. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: Emerging Security Challenges in Highly Interconnected Semiconductor Systems \nSpeaker: Neeraj Paliwal\, VP General Manager\nAbstract: The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity\, reliability\, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats\, such as supply chain attacks\, intellectual property theft\, hardware Trojans\, side-channel attacks\, fault injection attacks\, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.\n\n\n8:30am\nSelecting the right Root of Trust HSM Design for Your Next Project \nSpeaker: Bart Stevens\, Senior Director of Product Marketing\nAbstract: A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation\, Bart Stevens will guide you through the labyrinth of Root of Trust designs\, including what problems they can solve and what solutions are available to implement in your next silicon design.\n\n\n9:00am\nProtecting Devices and Data in the Quantum Era \nSpeakers: Gijs Willemse\, Senior Director of Product Management\nAbstract: Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods\, that is\, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.\n\n\n9:30am\nHardware Security: Ask Me Anything \nSpeaker: Tim Messegee\, Senior Director of Solutions Marketing\nBart Stevens\, Senior Director of Product Marketing\nGijs Willemse\, Senior Director of Product Management\nScott Best\, Senior Technical Director\nAbstract: Whether it’s security technology trends\, the threat of quantum computers\, implementation issues or anything in between\, our security experts are ready to tackle your questions in this Ask Me Anything session.\n\n\n10:00am\nSecuring MCUs with SCA Protection in IoT Designs \nSpeaker: Marcel Van Loon\, Senior Principal Engineer Systems Architecture\nAbstract: A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.\n\n\n10:30am\nCybersecurity: A Top Priority for the Automotive Industry \nSpeaker: Adiel Bahrouch\, Director of Business Development\nAbstract: Automotive systems\, and the semiconductors used within them\, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation\, while meeting the safety and security requirements unique to the automotive industry.\n\n\n11:00am\nThe Convergence of MACsec and IPsec in Data Center Silicon Designs \nSpeaker: Maxim Demchenko\, Technical Director\nAbstract: Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.\n\n\n11:30am\nMemory Encryption for Data in Use Protection to Enable Confidential Computing in Data Center Designs \nSpeaker: Ajay Kapoor\, Senior Principal Engineer Systems Architecture\nAbstract: There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.\n\n\n12:00pm\nSecuring the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management \nSpeaker: Matt Orzen\, Technical Director Systems Architecture\nAbstract: The semiconductor industry is the lifeblood of the digital economy. The design\, manufacturing and consumption of chips is a global ecosystem\, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability\, functionality\, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon\, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/rambus-design-summit-2023/
LOCATION:TX
CATEGORIES:IP,Seminar
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