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BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20241106T093000
DTEND;TZID=America/Chicago:20241106T170000
DTSTAMP:20260407T085317
CREATED:20241017T160613Z
LAST-MODIFIED:20241017T160903Z
UID:8425-1730885400-1730912400@marketingeda.com
SUMMARY:Verification Academy Live: Austin
DESCRIPTION:Overview \nThis seminar will update you on technologies and techniques you can adopt to\nincrease your verification productivity today. Specifically\, we will cover: \n\nHow the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains.\nProtocol and memory verification solutions you need for your next silicon verification project.\nData-driven verification with automated analytics\, collaboration\, and traceability capabilities.\nTechnologies and techniques you can adopt to increase your DFT productivity.\n\n‌\n‌ \nAgenda \n9:30 am – 10:00 am\nRegistration and check-in\nCoffee and networking with your peers\n‌\n10:00 am – 10:05 am\nWelcome/Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n‌\n10:05 am – 11:00 am\nKeyNote: Smart Verification – Faster is not Enough\nAbhi Kolpekwar | VP & GM\, Digital Verification Technologies Division \nThe electronics industry is on the brink of an unprecedented paradigm shift. The AI/ML-focused chips account for 20% of the semiconductor market\, a figure set to skyrocket to 73% by 2030\, fueled by the ongoing digital transformation. This seismic shift will significantly impact the architecture\, design\, and manufacturing of computing\, networking\, and communication solutions\, necessitating careful consideration of power\, performance\, security\, and safety concerns. Conventional verification flows\, reliant on disparate point tools\, will struggle to meet the demands of emerging systems. This keynote explores the prevailing macro-trends shaping today’s digital transformation before outlining a visionary approach to functional verification. By leveraging collective wisdom across tools\, technologies\, workflows\, and methodologies\, this new paradigm promises productivity gains beyond the reach of traditional methods.\n‌\n11:00 am – Noon\nQuesta Verification IQ:\nBoost verification predictability and efficiency with Big Data\nAhmed ElKady | Product Engineer \nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost.\n‌\nNoon – 12:45 pm\nLunch and networking\n‌\n12:45 pm – 1:15 pm\nQuesta Verification IQ: Sneak Peek of Debug IQ and Regression IQ\n‌\nContinuation of the Questa Verification IQ session.\n‌\n1:15 pm – 2:00 pm\nThe New Leader in Verification IP: Questa + Avery Solutions\nLuis Rodriguez | Senior Technical Product Manager & VIP Architect \nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n‌\n2:00 pm – 2:30 pm\nCapturing additional DFT coverage thru Functional Fault Grading\nByron Brinson | Product Engineer \nIdeally\, for manufacturing test coverage the goal is to achieve 100%. This becomes even more important for chips used in safety critical applications. However\, there are usually limitations regarding the amount of coverage that the DFT infrastructure can provide within a chip. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.\n‌\nb\nAccelerating Verification Closure with Siemens DFT Tailored Verification Solutions\nRick Koster | Product Engineer \nAs semiconductor designs evolve to more complex architectures\, 3DICs\, and heterogeneous integration\, verification engineers face increasing pressure to accelerate DFT verification closure. Siemens offers a comprehensive technology suite tailored to industry leading Tessent solutions\, designed to address the growing complexity and increasing challenges in Design for Test (DFT). This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows\, delivering industry leading performance and enhanced user experience\, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.\n‌\n3:00 pm- 5:00 pm\nTopGolf happy hour & networking\n‌ \nWe look forward to seeing you!\n‌\nSiemens Advanced Functional Verification Team \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/verification-academy-live-austin/
LOCATION:Top Golf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241003T113000
DTEND;TZID=America/Los_Angeles:20241003T170000
DTSTAMP:20260407T085317
CREATED:20240827T163546Z
LAST-MODIFIED:20240827T163546Z
UID:8283-1727955000-1727974800@marketingeda.com
SUMMARY:Signoff Special Interest Group
DESCRIPTION:Join us at this year’s Synopsys Signoff SIG (Special Interest Group) event. \nSignoff is a critical quality control checkpoint in the chip development process\, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year’s Synopsys Signoff SIG event\, we’ll explore how signoff can help meet these scalability challenges. We’ll here from several industry-leading companies how they are using the latest technology advances in timing\, power\, extraction\, and eco to realize the full PPA potential of their designs with the fastest path to design closure. \n\n\n\n\n\n\n\n\nAgenda\n\n\nMore details coming soon. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n11:30 – 12:30 PM PDT\n\n\nRegistration Check in & Lunch\n\n\nBadge pick-up begins at 11:30. Lunch will be served\, come early for a chance to eat and network before sessions begin. \nRead Less \n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n12:30 – 01:15 PM PDT\n\n\nKeynote\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n01:15 – 04:05 PM PDT\n\n\nTechnical Sessions\n\n\n\n\n\n\n\n\n\n\n\n\n\nThu. October 03\, 2024\n04:05 – 05:00 PM PDT\n\n\nNetworking Reception\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/signoff-special-interest-group/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-3-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T093000
DTEND;TZID=America/Los_Angeles:20240516T140000
DTSTAMP:20260407T085317
CREATED:20240424T162625Z
LAST-MODIFIED:20240424T162625Z
UID:7907-1715851800-1715868000@marketingeda.com
SUMMARY:Keysight EDA Connect Tour - Burlington
DESCRIPTION:As AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nAgenda\n\n\n\n09:30 a.m.\nDoors open\n\n\n10:00 a.m.\nWelcome\n\n\n10:10 a.m.\nRapid EM-Circuit Co-Design of Microwave ICs\, Packages\, and Modules\n\n\n11:00 a.m.\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs/ Chiplets\n\n\n11:45 a.m.\nLoad Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML\n\n\n12:30 p.m.\nNew System Verification Tools in ADS for Circuit Designers\n\n\n1:00 p.m.\nLunch Session- Keysight Eggplant- Software Test Automation\n\n\n\n\n\n\n1:30 p.m.\nKeysight Design Data and IP Management\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/keysight-eda-connect-tour-burlington/
LOCATION:Eddie V’s Restaurant\, 50 South Avenue\, Burlington\, MA\, United States
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230905T091500
DTEND;TZID=Asia/Jerusalem:20230905T164500
DTSTAMP:20260407T085317
CREATED:20230901T162634Z
LAST-MODIFIED:20230901T162634Z
UID:6763-1693905300-1693932300@marketingeda.com
SUMMARY:Real Intent Static Sign-Off Seminar in Israel
DESCRIPTION:Time\nTopic\nSpeaker\n\n\n09:15 – 09:45\nCheck-in and light breakfast\n\n\n\n09:45 – 10:00\nIntroduction of Real Intent and speakers\nUri Farkash\, Real Intent – Senior Sales Director\n\n\n10:00 – 10:30\nKeynote Speaker\nDr. Prakash Narain\, Real Intent – President and CEO\n\n\n10:30 – 10:45\nAn Overview Static Sign-off\nDr. Prakash Narain\, Real Intent – President and CEO\n\n\n10:45 – 11:45\nConnectivity Case Studies & Avoiding Glitch Bugs\nOren Katzir\, Real Intent – VP\, Application Engineering\n\n\nPolina Gemelfarb \, Real Intent – Senior FAE\n\n\n11:45 – 12:15\nTutorial: Advanced RDC Verification\nPolina Gemelfarb \, Real Intent – Senior FAE\n\n\n12:15 – 12:45\nExpert Users Track: CDC Signoff – from Gamble to Certainty\nMilca Tarshish\, Intel WCS – Senior VLSI Engineer\n\n\nDoron Stein\, Intel WCS – Senior CAD Engineer\n\n\n12:45 – 14:00\nLunch & Networking\n\n\n\n14:00 – 14:30\nExpert Users Track: Best Practices for Static Sign-Off with Continuous Integration\nItai Resh\, Hailo – VLSI Project Lead\n\n\n14:30 – 15:15\nEarly DFT and Test gaps detection\nOren Katzir\, Real Intent – VP\, Application Engineering\n\n\n15:15 – 15:45\nDynamic and Formal CDC\nRoman Paleria\, Real Intent – FAE Manager\n\n\n15:45 – 16:15\nComponent Level CDC Workshop\nEvgeny Zhyvov\, Real Intent – Principal Engineer\n\n\n16:15 – 16:30\nAdvancements in LINT\nRoman Paleria \, Real Intent – FAE Manager\n\n\n16:30 – 16:45\nClosing remarks & Prize draw\nUri Farkash\, Real Intent – Senior Sales Director\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/real-intent-static-sign-off-seminar-in-israel/
LOCATION:VERT Lagoon\, Netanya\, Israel
CATEGORIES:EDA,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Real-Intent-September-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T080000
DTEND;TZID=America/Los_Angeles:20230719T170000
DTSTAMP:20260407T085317
CREATED:20230630T191347Z
LAST-MODIFIED:20230630T191347Z
UID:6568-1689667200-1689786000@marketingeda.com
SUMMARY:Rambus Design Summit 2023
DESCRIPTION:Back for its fourth year\, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center\, AI/ML\, automotive and IoT applications. \n\n\nAgenda + Abstracts\n\n\n\n\n\nRambus Design Summit will take place over two days\, with day one focusing on memory & interface solutions\, and day two on security solutions. Take a look at the agenda below – all times in Pacific Daylight Time (PDT). \n\n\n\n\n\n\n\nTuesday\, July 18: Memory & Interface Solutions\n\nTackling advanced data center workloads requires ever increasing levels of memory bandwidth and capacity\, as well as high-speed interconnects. Hear Rambus technology experts share their insights on future memory and interconnect requirements in the data center covering critical enabling technologies including DDR5\, HBM3\, PCIe 6.0\, GDDR6\, LPDDR5X\, CXL\, and MIPI/VESA video compression. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: CXL Technology: Revolutionizing the Data Center \nSpeaker: Mark Orthodoxou\, Vice President of Strategic Marketing\nAbstract: The need for more memory bandwidth and capacity continues to rise\, with applications like generative AI pushing current data center infrastructure to the limit. The leading companies at every level of the data center value chain are coalescing around CXL technology as a path to revolutionize the data center. Join Mark Orthodoxou to hear how CXL promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage\, as well as enabling new tiered-memory solutions and composable architectures.\n\n\n8:30am\nInnovations in CXL 3.0: Novel Device Types\, Capabilities\, and Interconnects \nSpeaker: Danny Moore\, Senior Product Marketing Manager\nAbstract: CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type\, CXL Multi-Headed Devices\, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.\n\n\n9:00am\nSystem Level Design Considerations for PCIe 6.0 \nSpeaker: Lou Ternullo\, Senior Director of Product Marketing\nAbstract: PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate\, PAM4 signaling\, forward error correction\, and a low power L0p mode. In this presentation\, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design\, including how to get the most out of each of the PCIe devices.\n\n\n9:30am\nLeveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays \nSpeakers: Simon Bussières\, Director of Systems Architecture\nJoe Rodriguez\, Product Marketing Manager\nAbstract: Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions\, faster refresh rates\, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality\, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.\n\n\n10:00am\nMeeting the Needs of Generative AI Training with HBM3 \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI training models are growing in both size and sophistication at a lightning pace\, requiring more and more bandwidth. With its unique 2.5D/3D architecture\, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.\n\n\n10:30am\nPowering AI/ML Inference with GDDR6 Memory \nSpeaker: Frank Ferro\, Senior Director of Product Marketing\nAbstract: GDDR6 memory offers an impressive combination of bandwidth\, capacity\, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.\n\n\n11:00am\nLPDDR5X: Delivering High Bandwidth and Power Efficiency \nSpeaker: Vinitha Seevaratnam\, Senior Product Marketing Manager\nAbstract: The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT\, automotive\, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.\n\n\n11:30am\nWhat’s Next for DDR5 Memory? \nSpeaker: John Eble\, Vice President of Product Marketing\nAbstract: With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory\, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels\, be deployed in new applications beyond RDIMMs\, and how it is tailored for client computing systems.\n\n\n12:00pm\nHigh-Performance Memory: Ask Me Anything \nSpeakers: Tim Messegee\, Senior Director of Solutions Marketing\nSteven Woo\, Fellow and Distinguished Inventor\nJohn Eble\, Vice President of Product Marketing\nMark Orthodoxou\, Vice President of Strategic Marketing\nFrank Ferro\, Senior Director of Product Marketing\nAbstract: Generative AI is just one of the many applications driving the relentless need for better memory performance\, capacity and efficiency in the data center. Join our experts as they discuss some of the biggest memory challenges facing the industry today\, contemplate how the industry will innovate to meet future data center memory needs\, and answer all your questions!\n\n\n\n\n\n\nWednesday\, July 19: Security Solutions\n\nSecurity anchored in hardware provides the foundation for protecting data and devices at all stages of the semiconductor lifecycle. Join Rambus Security experts as they share their insights on security threats facing the industry including those that will arise in the era of quantum computers. Learn how you can protect hardware and data at rest\, in motion and in use with Root of Trust\, MACsec\, Inline Memory Encryption\, and more. \n\n\n\nTime\nSession\n\n\n\n\n8:00am\nKeynote: Emerging Security Challenges in Highly Interconnected Semiconductor Systems \nSpeaker: Neeraj Paliwal\, VP General Manager\nAbstract: The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity\, reliability\, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats\, such as supply chain attacks\, intellectual property theft\, hardware Trojans\, side-channel attacks\, fault injection attacks\, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.\n\n\n8:30am\nSelecting the right Root of Trust HSM Design for Your Next Project \nSpeaker: Bart Stevens\, Senior Director of Product Marketing\nAbstract: A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation\, Bart Stevens will guide you through the labyrinth of Root of Trust designs\, including what problems they can solve and what solutions are available to implement in your next silicon design.\n\n\n9:00am\nProtecting Devices and Data in the Quantum Era \nSpeakers: Gijs Willemse\, Senior Director of Product Management\nAbstract: Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods\, that is\, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.\n\n\n9:30am\nHardware Security: Ask Me Anything \nSpeaker: Tim Messegee\, Senior Director of Solutions Marketing\nBart Stevens\, Senior Director of Product Marketing\nGijs Willemse\, Senior Director of Product Management\nScott Best\, Senior Technical Director\nAbstract: Whether it’s security technology trends\, the threat of quantum computers\, implementation issues or anything in between\, our security experts are ready to tackle your questions in this Ask Me Anything session.\n\n\n10:00am\nSecuring MCUs with SCA Protection in IoT Designs \nSpeaker: Marcel Van Loon\, Senior Principal Engineer Systems Architecture\nAbstract: A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.\n\n\n10:30am\nCybersecurity: A Top Priority for the Automotive Industry \nSpeaker: Adiel Bahrouch\, Director of Business Development\nAbstract: Automotive systems\, and the semiconductors used within them\, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation\, while meeting the safety and security requirements unique to the automotive industry.\n\n\n11:00am\nThe Convergence of MACsec and IPsec in Data Center Silicon Designs \nSpeaker: Maxim Demchenko\, Technical Director\nAbstract: Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.\n\n\n11:30am\nMemory Encryption for Data in Use Protection to Enable Confidential Computing in Data Center Designs \nSpeaker: Ajay Kapoor\, Senior Principal Engineer Systems Architecture\nAbstract: There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.\n\n\n12:00pm\nSecuring the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management \nSpeaker: Matt Orzen\, Technical Director Systems Architecture\nAbstract: The semiconductor industry is the lifeblood of the digital economy. The design\, manufacturing and consumption of chips is a global ecosystem\, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability\, functionality\, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon\, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/rambus-design-summit-2023/
LOCATION:TX
CATEGORIES:IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rambus-July-18-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230328T083000
DTEND;TZID=America/Los_Angeles:20230328T113000
DTSTAMP:20260407T085317
CREATED:20230309T220840Z
LAST-MODIFIED:20230309T220902Z
UID:6090-1679992200-1680003000@marketingeda.com
SUMMARY:ESD Alliance Export Seminar
DESCRIPTION:The ESD Alliance Export Committee will hold a seminar called “The Impact of New Regulations on the Semiconductor Design Ecosystem.” This seminar is presented by the ESD Alliance\, a SEMI Technology Community\, and will be hosted by Cadence Design Systems at their San Jose Headquarters. The Cadence Government and Trade Team will cover general trade compliance concepts\, how export control and sanctions regulations affect the industry\, as well as current trends and emerging issues. \nBreakfast Hosted by Cadence \n\nTime\n8:30 am – 11:30 am \n\n\nADD TO CALENDAR\n\n\nLocation\nCadence Design Systems\n2655 Seely Avenue\nSan Jose\, CA 95134\nUnited States \nThe discussion will help attendees understand why and how governments implement trade controls\, what “exports” are and how they take place in different business contexts\, and common due diligence methods – such as customer screening – that United States companies use to incorporate regulatory compliance into their business processes. Finally\, the discussion will address recent regulatory updates which address current issues such as US-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem. \n\nMeet the Speakers\n \nAda Loo\nGroup Director and Associate General Counsel\,\nCadence Design Systems \nBiography\n \nWilliam Duffy\nCorporate Counsel (Government and Trade\, Cadence Legal) \nBiography\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/esd-alliance-export-seminar/
LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States
CATEGORIES:EDA,IP,Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESDA-March-28-2023.jpg
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DTSTART;TZID=America/Chicago:20220825T093000
DTEND;TZID=America/Chicago:20220825T143000
DTSTAMP:20260407T085317
CREATED:20220805T191404Z
LAST-MODIFIED:20220805T191404Z
UID:5021-1661419800-1661437800@marketingeda.com
SUMMARY:Austin Verification Seminar
DESCRIPTION:Join Siemens EDA for an in-person seminar focused on hot issues in design verification\, and solutions you can implement today. \n\n\nAbout this event\n\n\n\nOverview\nDelivering high product quality without sacrificing today’s demanding product schedules means boosting verification productivity and cutting bug escapes. Product development teams must speed time to coverage closure\, requiring new and improved technologies that make a meaningful difference in a verification cycle. \n\n\n\n\nAgenda\n9:00 – 9:30 \nArrival and check-in \nIntroductions and networking with your peers. \n\n\n\n\n9:30 – 10:15 \nKeynote: The state of functional verification: crisis or opportunity? \nPresenter: Harry Foster | Chief Scientist Verification \nHas the industry finally reached a breaking point in terms of a verification crisis? This talk quantitatively answers this question by presenting the latest industry trends in functional verification based on the 2022 Wilson Research Group Functional Verification Study. Although some of this year’s findings are disturbing\, a key point of this talk is to prescribe a holistic and philosophical change in the way we approach design with a foundation based on bug prevention to avert an impending crisis. \n\n\n\n\n10:15 – 10:45 \nTechnology update: Static and formal and the next normal. \nPresenter: Chris Giles | Head of Product Management – Static & Formal Technologies \nNew normals come and go\, but the past three years have been a period of monumental and unexpected change. Succeeding in the market today requires more than working harder but doing the same thing. This session will describe how Siemens EDA’s investments in Static and Formal technologies will help you reduce risk exposure now and for the next new normal. \n\n\n\n\n10:45 – 11:30 \nProductive development via static and formal linting. \nPresenter: Walter Gude | Application Engineering Consultant \nStatic and Formal technologies are each capable of linting RTL to find coding errors and non-compliance before a testbench is ever written. However\, each of these solutions has a sweet spot in the development flow. Learn in this session what each contributes to the overall linting solution\, and when to use what for maximum efficiency\, even in design creation. \n\n\n\n\n11:30 – 12:15 \nMaster-level CDC: Why your CDC methodology is probably working against you. \nPresenter: Vinayak Desai | Principal Product Engineer \nWhile some teams still haven’t adopted CDC verification to ensure success\, those who have consider the problem solved. This perspective leads to complacency and ignores an entire series of issues that condemn projects into rework that no project can afford today in the era of the next normal. This session will identify the issues that often get overlooked in domain crossing analyses and will provide you with strategies to avoid future failures. \n\n\n\n\n12:15 – 1:00 \nLunch will be provided. \n\n\n\n\n1:00 – 1:45 \nUsing Formal technology to secure complex ICs in a connected world. \nPresenter: John Hallman| Product Owner – Trust & Security \nAircraft\, automobiles\, and many other products rely on complex microelectronic components now more than ever to monitor\, control and process critical information. This connected world\, enabled by these devices\, poses increasing challenges to personal safety\, financial loss\, exposure of personal information\, and operation failure. Functional verification of microelectronic devices requires thorough methods and securing the IC in the system requires even more. Siemens’ OneSpin tools and apps have technologies built upon world class formal engines and provide results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment platform\, perform processor verification\, and offer completeness checking to perform security verification in your IC. \n\n\n\n\n1:45 – 2:30 \nQuantify mutation coverage. \nPresenter: David Landoll | Solution Architect \nFor engineers new to property-based verification\, their critical questions are typically “How good are the properties I’ve already added?” and “What properties should I add next?” For engineers now proficient at adding properties to their design\, their critical questions that remain are “Do my properties cover the entire design?”\, “What properties am I missing?”\, and “Did I do anything wrong setting up the formal testbench?”. Learn in this session how mutation coverage can answer all these questions and more. Mutation coverage can measure the quality of a formal testbench\, provide precise\, actionable information on what parts of the design are verified\, and highlights RTL code that could still be hiding bugs. Additionally\, this technology reveals potential issues in the testbench that might corrupt metrics and give a false sense of confidence. \n\n\n\n\n========================================= \nSeating for this seminar will be limited\, please register to save your seat. \nBy supplying my contact information and registering for this event\, I authorize Siemens Digital Industries Software and its affiliates to contact me via email\, or phone (if provided) about its products as described in detail here. Please visit our privacy statement. \n========================================== \n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/austin-verification-seminar/
LOCATION:Hotel Granduca Austin\, 320 South Capital of Texas Highway\, West Lake Hills\, TX\, 78746\, United States
CATEGORIES:Seminar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-EDA-August-25-2022.jpg
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