BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.2//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20210314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20211107T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Denver
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:20230312T090000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:20231105T080000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:20240310T090000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:20241103T080000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:20250309T090000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:20251102T080000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Jerusalem
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20220325T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20221029T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20230324T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20231028T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20240329T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20241026T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20250328T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20251025T230000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20220313T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20221106T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Taipei
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241217T080000
DTEND;TZID=Asia/Kolkata:20241220T170000
DTSTAMP:20241122T213230Z
CREATED:20241122T213230Z
LAST-MODIFIED:20241122T213230Z
UID:8530-1734422400-1734714000@marketingeda.com
SUMMARY:IEEE Asian Test Symposium 2024
DESCRIPTION:The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the world\, not just from Asia\, to present and discuss various aspects of system\, board and device testing with design\, manufacturing and field considerations in mind. \nThe 33th IEEE Asian Test Symposium (ATS 2024)\nDecember 17-20\, 2024\, Ahmedabad\, Gujarat\, India \n  \n\nThe Asian Test Symposium started 1992 in Hiroshima\, Japan\, as an annual symposium in the Asia Pacific region. Since then\, the symposium has continued its growth and development\, visiting various historic cities in Asia. This year it is marking its 33rd anniversary to Ahmedabad\, India. We welcome all the contributors to the heritage city of India.\n\n\nThe walled city of Ahmadabad was founded by Sultan Ahmad Shah in 1411 AD on the eastern bank of the Sabarmati River. On July 8th\, 2017\, a remarkable moment unfolded as Ahmedabad earned the title of India’s first-ever UNESCO World Heritage City.\n\n\nScope\n\n\n\nThe Asian Test Symposium (ATS) provides an international forum for engineers and researchers from all countries of the world\, especially from Asia\, to present and discuss various aspects of device\, board and system testing with design\, manufacturing and field considerations in mind. \n\n\n\n\nMajor topics including\, but not limited to: \n\n\n\n\n\n\n\n\n\nAutomatic Test Pattern Generation (ATPG)\nAnalog Test / Mixed-Signal Test\nBoundary Scan Test\nBoard and System Test\nBuilt-In Self-Test\nDesign for Testability (DFT)\nDesign Verification and Validation\nDefect-Based Testing\nDelay and Performance Test\nDiagnosis and Debug\nDependable System\nEconomics of Test\n\n\n\n\n\n\n\n\n\n\nFault Modeling and Simulation\nFault Tolerance\nHigh-Speed I/O Test / RF Testing\nMemory Test / FPGA Test\nOn-Line Test\nSystem-on-a-Chip Test\nSystem-in-package (SiP) / 3D Test\nSoftware Testing / Software Design for Testing\nTest Compression\nTemperature / Power-aware Test\nTest Quality\nYield Analysis and Enhancement
URL:https://marketingeda.com/event/ieee-asian-test-symposium-2024/
LOCATION:Courtyard by Marriott\, Ahmedabad\, Sindhu Bhawan Roa\, Ahmedabad\, India
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ATS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241217T080000
DTEND;TZID=Asia/Kolkata:20241219T170000
DTSTAMP:20241207T004316Z
CREATED:20241207T004316Z
LAST-MODIFIED:20241207T004316Z
UID:8560-1734422400-1734627600@marketingeda.com
SUMMARY:EDAPS 2024
DESCRIPTION:The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) symposium\, a flagship event in the Asia-Pacific region\, has consistently served as a platform for dissemmination of latest research in the areas of electrical design of chip\, package and system. Designers and researchers across the world come forth to share and discuss their work on all aspects of electrical packaging including modeling\, design and simulation\, fabrication and characterization. This symposium consists of technical paper presentation\, poster sessions\, industry exhibits\, workshops and tutorials. \n  \nEDAPS is sponsored by the IEEE Electronic Packaging Society. \nEDAPS will be an excellent forum to highlight the latest advances in the high-speed and high-performance semiconductor industry. Engineers and researchers will engage in the 3 full day conference and workshop\, to be held during December 17-19 at the Taj Yeshwantpur\, in Bangalore\, India. The forum offers a great opportunity for sponsorships and for the related companies to build their brands in this leading international platform.
URL:https://marketingeda.com/event/edaps-2024/
LOCATION:Taj Yeshawantpur\, 2275 Tumkur Road\, Yeshwantpur\, Bangalore\, India
CATEGORIES:EDA,Semiconductor,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20241126T120000
DTEND;TZID=Europe/London:20241126T130000
DTSTAMP:20241107T165901Z
CREATED:20241022T165229Z
LAST-MODIFIED:20241107T165901Z
UID:8444-1732622400-1732626000@marketingeda.com
SUMMARY:DVClub Europe - AI/ML in Verification
DESCRIPTION:This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. \n\n\nAgenda (GMT):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction – Mike Bartley\, Tessolve \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nHardik Raina\, Agnisys\, Inc – Genetic Algorithms for Automated Verification from VCD Data.\n\n\n\n\n12.20 GMT\nPaula Mathias\, Cadence Design System – AI-based SVA Generation\n\n\n\n\n12.40 GMT\nDavid Kelf\, Breker Verification Systems – VerifyGPT! Is it possible and what do we need in place?\n\n\n\n\n13.00 GMT\n  \nClose
URL:https://marketingeda.com/event/dvclub-europe-ai-ml-in-verification-2/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-26-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241120T090000
DTEND;TZID=America/Los_Angeles:20241120T180000
DTSTAMP:20241113T213239Z
CREATED:20241113T213125Z
LAST-MODIFIED:20241113T213239Z
UID:8510-1732093200-1732125600@marketingeda.com
SUMMARY:Tower Semiconductor - Technical Global Symposium 2024
DESCRIPTION:TGS offers a wonderful opportunity for networking\, learning\, and sharing\nthe latest technology developments with our community\, as well as\nmeeting with Tower’s executives and team of experts.\nWe invite you to join us! \n\n\nTime\n\n\n\n\nSession\n\n\n\n\nSpeaker\n\n\n\n\n9:00 – 10:00\n\n\n\n\nRegistration\n\n\n\n\n10:00 – 10:05\n\n\n\n\nOpening\n\n\n\n\nMr. Lei Qin\, SVP of Worldwide Sales\n\n\n\n\n10:05 – 10:40\n\n\n\n\nCEO Keynote\n\n\n\n\nMr. Russell Ellwanger\, CEO\n\n\n\n\n10:40 – 11:00\n\n\n\n\nWhy an Analog Foundry is Critical for AI\n\n\n\n\nDr. Avi Strum\, CTO\n\n\n\n\n11:00 – 11:30\n\n\n\n\nInvited Talk by Nvidia:\nIntegrated Optics Ecosystem for Future Gen AI Systems\n\n\n\n\nDr. Ashkan Seyedi\, Director\, LinkX Products\, Nvidia\n\n\n\n\n11:30 – 12:00\n\n\n\n\nMarket Megatrends and Tower’s Technology Solutions in RF Mobile\, Infrastructure\, Power\, and Sensors\n\n\n\n\nDr. Marco Racanelli\, President\n\n\n\n\n12:00 – 13:30\n\n\n\n\nLunch\n\n\n\n\n13:30 – 14:15\n\n\n\n\nTower’s RF and Silicon Photonics Technology Platforms – Advanced Solutions for High-speed Connectivity\n\n\n\n\nDr. Ed Preisler\, VP & Co-General Manager of RF Business Unit\n\n\n\n\n14:15 – 15:00\n\n\n\n\nTower’s Power 65nm BCD and 0.18um BCD Offering for Power Applications\n\n\n\n\nDr. David Mistele\, Director of Power Management R&D\n\n\n\n\n15:00 – 15:15\n\n\n\n\nCoffee Break\n\n\n\n\n15:15 – 15:45\n\n\n\n\nTechnologies for the Future of Digital Imaging\, from Sensors to Displays\n\n\n\n\nDr. Benoit Dupont\, Marketing Director of Sensors and Display Business\n\n\n\n\n15:45 -16:15\n\n\n\n\nTower’s Design Enablement – Transforming Ideas into Products\, Rapidly and Accurately\n\n\n\n\nDr. Samir Chaudhry\, VP of Design Enablement\n\n\n\n\n16:15 – 16:45\n\n\n\n\nAerospace and Defense – Partner for R&D and Manufacturing Solutions\n\n\n\n\nDr. David Howard\, Executive Director & Fellow\n\n\n\n\n16:45 – 17:00\n\n\n\n\nClosing Remarks\n\n\n\n\n\n\n\n\n\n17:00 – 18:00\n\n\n\n\nCocktail
URL:https://marketingeda.com/event/tower-semiconductor-technical-global-symposium-2024/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,Semiconductor,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tower-November-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241003T080000
DTEND;TZID=America/Los_Angeles:20241004T170000
DTSTAMP:20241004T174051Z
CREATED:20241002T224220Z
LAST-MODIFIED:20241004T174051Z
UID:8372-1727942400-1728061200@marketingeda.com
SUMMARY:Electronic Design Process Symposium (EDPS) - 2024
DESCRIPTION:EDPS 2024 is now taking shape. The place to be is once again SEMI\, in Milpitas\, and the dates are Thursday and Friday\, Oct 3rd and 4th\, 2024. \nRegistration is now open: https://2024-ieee-edps.eventbrite.com. Who needs to register? Please see the Registration page. \nTalks from EDPS 2023 and the last 24 years of EDPS\, are are available and searchable\, on the Prior Years page. \nDay 1\, Thursday 9:00am; Session 1\n9:05am\n\nEnergy and Thermal Management of Chips\, Systems and Datacenters Necessitates a Return to Fundamentals\nChandrakant Patel\nHP\n\n  \nThe latter part of 20th century witnessed the rise of the compute utility made up of large-scale data centers housing densely packed compute\, storage and networking equipment. The cyber age data centers became modern day factories requiring megawatts of power for the information technology (IT) equipment much like the process equipment in a factory of the machine age. Electrical energy supplied to the chips and systems in the data centers turned into multi-megawatts of heat energy which in turn required heat removal means. The active heat removal means also required power. While many innovative measures have been used for heat removal and energy management in data centers\, there is a substantial gap in application of fundamentals of engineering when compared to the approaches taken by the contributors of the 19th and early 20th century machine age. As an example\, machine age contributors performed exergy (2nd law of thermodynamics) analysis and deemed it necessary to build a hydro-electric plant as part of the design of an Aluminum factory. Indeed\, majority of data centers today rely on the power infrastructure built by our predecessors. Given the inexorable trajectory of data centers strongly driven by AI\, and associated demands on available energy\, it is time we returned to such fundamentals particularly given the environmental challenges. \nIn my talk\, I will present a holistic approach that traces the energy flow from a power plant to a chip\, and from the chip core to the cooling tower. \n10:00am\n\nEnabling Effortless Machine Learning for Embedded Edge Applications\nGopal Hegde\nSiMa.ai\n\n  \nMachine Learning is a game changing technology of our generation and similar Internet in the 1990s\, will impact every aspect of our life. While Machine Learning use cases and applications are well established in the cloud & IoT devices\, in the embedded edge market\, its usage is in its infancy. We at SiMa.ai are focused on disrupting this market by turbo charging embedded compute with the addition of machine learning. Embedded edge has space and power constraints and has a huge expertise gap relative to cloud computing when it comes to machine learning. The presentation covers market requirements\, key challenges and our unique software first approach to machine learning at embedded edge. We will discuss key market segments\, their unique requirements and how our silicon and software solutions provide a way for our customers to easily develop and deploy machine learning solutions that address their use cases and applications. \n10:35am\n\nAI: Trailblazing the Next Generation of Semiconductor Innovation\nVishal Khandewal\nSynopsys\n\n  \nWith AI-based applications coming pervasively mainstream through ChatGPT\, digital healthcare\, and almost everything else we do with our devices daily\, digital chip design is seeing an exponential push towards complexity\, performance\, power\, and time-to market. EDA tool flows are becoming mission critical to meet the demands of a hardware-led 4th industrial revolution that is driving everything towards being intelligent\, connected\, monitored and data-driven. In this talk we go into the details of how hardware design and EDA tools are evolving to deliver the next generation of performance\, power\, and productivity (PP&P) boost. Even with exponential growth in design productivity in the past decade\, overall design cycle is not meeting its intended targets. The technical complexity of advanced node design with new dominant effects like thermal and IR\, are leading to highly complex tool/methodology flows. This is where at Synopsys\, we have taken a full tool-stack approach to build pervasive AI into our tools to deliver unprecedented PP&P boost. We will share examples of applications ranging from design implementation\, verification\, test\, and analog/manufacturing to showcase the potential of this technology and how it is reshaping chip design workflows. Many of these technologies are taking us closer to the no-human-in-the-loop goal for chip design. With serious talent shortage and increase in solution complexity beyond human expertise\, AI-augmented solutions for chip design are the way forward. \n11:10am\n\nHarnessing LLMs for Advanced EDA Platforms: Code Generation and Beyond\nAkhilesh Kumar\nAnsys\n\n  \nLarge Language Models (LLMs) such as GPT-4\, Gemini\, Llama etc.\, have demonstrated astounding capabilities in a range of tasks such as knowledge extraction\, Q&A\, summarization\, code generation\, contextual problem solving etc. The LLMs can also be adapted to specific applications through a variety of methods such as fine tuning\, in-context learning\, RAG\, agent-based systems etc.\, making them quite versatile. \nModern EDA platforms\, such as Ansys SeaScape\, have sophisticated workflows\, hundreds of user APIs\, complex input data requirements\, and require deep domain knowledge and expertise for efficiently using the platform. This talk will discuss how LLMs can greatly improve the productivity and user experiences for such EDA platforms. The talk presents an overview of code generation techniques using LLMs and will discuss our experience in developing an LLM-based code generation solution for the Ansys SeaScape platform. Going beyond the code generation\, this presentation will discuss creating an LLM agent-based copilot for providing intuitive assistance to the users of the Ansys SeaScape platform for a variety of operational modalities. \n12:45pm\n\nThe Application of AI to Chip Design\nMark Ren\nNVidia\n\n  \nThe applications of AI in chip design undergo an evolutionary path. \nInspired by the success of AlphaGO\, Reinforcement Learning techniques were deployed to a number of design problems\, achieving results showing the potential of AI. \nThe advancement of Large Language Models further enabled the application of AI in a much broader set of design activities. \nLLM-based copilots can improve design productivity by providing knowledge and coding assistance; agents can provide further assistance in key design tasks such as analysis\, debugging\, and optimization. \nThe evolution of AI will continue\, and we will discuss critical challenges to realizing its revolutionary potential in the chip design process \n1:35pm\n\nHow AI is changing every aspect of EDA\, starting from transistor-level simulation\nSathishkumar Balasubramanian\nSiemens\n\n  \nThere is a lot of hype in the industry around AI\, but behind the hype there is the reality. That reality is that AI really is impacting virtually every aspect of semiconductor design. However\, its not as simple as taking general purpose AI solutions and hoping they work for EDA\, the risks are too high and when dealing with parts per billion (or trillion) in acceptable errors\, hallucinations are not acceptable. What is needed are Verifiable AI solutions that deliver results that users can trust and that reduce the overall resources needed to complete a task. At Siemens EDA we have been able to leverage Verifiable AI to accelerate virtually every aspect of the design and verification process. \nIn this presentation we will explore the requirements for\, and state of the art of\, AI in EDA application. We will explore AI’s impact on every aspect of design starting from transistor-level simulation. \n2:10pm\n\nTest\, Repair and Reliability Challenges of Chip-let Interconnects\nSreejit Chakravarty\nAmpere Computing\n\n  \nChip-let based design\, fueled by various advanced packaging technologies\, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement\, during high volume manufacturing\, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. RAS solutions required to address such reliability issues are highlighted. \n2:45pm\n\nArtificial Intelligence and Machine Learning for RF and Microwave Design\nJianjun Xu\nKeysight\n\n  \nThis talk reviews some powerful and practical Artificial Intelligence and Machine Learning (AI/ML) technologies for applications in traditional RF and Microwave design and beyond. After a very brief overview of the AI/ML landscape\, we focus on Artificial Neural Networks (ANNs) and provide several key examples of modern ANN applications to electronic\, electro-thermal\, and electro-chemical device modeling\, and behavioral modeling to illustrate the substantial benefits and generality of present techniques. \nThe talk concludes with a discussion of the potential of AI/ML technologies to address and solve future challenging and important RF and Microwave design problems\, e.g.\, for 6G. \n3:30pm\n\nPromises and Challenges of Digital Twin for Semiconductor Manufacturing\nAla Moradian\nApplied Materials\n\n  \nThe advancement of cutting-edge technologies like Artificial Intelligence (AI)\, Large Language Models (LLM)\, and Electric Vehicles (EV) demands sophisticated semiconductor devices with precise specifications. \nConcurrently\, the emergence of digital twins and AI stands as pivotal in facilitating the development and enablement of such technologies. \nThis talk delves into the vision and significance of AppliedTwin(tm)\, a proposed digital twin framework tailored for semiconductor manufacturing. \nAppliedTwin delineates various levels of abstractions ranging from digital fabrication facility down to digital twin of individual devices\, each characterized by distinct attributes governing their interaction with physical assets\, fidelity\, etc. \nApplied Materials has spearheaded the application of digital twins in semiconductor manufacturing with the introduction of EcoTwin(tm)\, a platform designed to promote sustainability. \nIn this talk the critical role of digital twins in propelling innovation and efficiency in semiconductor equipment manufacturing. \n4:05pm\n\nMaking Data Center Digital Twins a Reality\nPaul Harrison\nCadence\n\n  \nThis talk will discuss the application of Digital Twins to Data Centers. \nHistorically decisions for data center operations were made based on rules of thumb or the person who would most confidently put across their point of view. \nCabinet power densities continue to rise\, accelerated by AI\, increasing the need complex technologies like liquid cooling to be more widely implemented. This means data center operations have become more difficult to manage\, while the impact of their downtime can be catastrophic for companies. Fortunately\, data center operators are starting to adopt CFD-based Digital Twins to help inform their operational decisions\, improve their understanding\, and reduce the risks. This talk will explain how to create a Data Center Digital Twin\, some of the challenges with creating them\, how they integrate with data sources and existing processes\, and the benefits to operators this technology brings. \n4:40pm\n\nInnovating Semiconductor Manufacturing with ML-augmented Digital Twins\nNorman Chang\nElectronics\, Semiconductor\, and Optics BU\, Ansys\n\n  \nDeveloping each processing step in semiconductor manufacturing has heavily relied on in-situ sensors in the equipment and numerous try-outs in recipe generation. However\, with advancements in multiphysics simulation technologies\, an innovative ML-augmented hybrid simulation methodology has been developed. This methodology combines the strengths of multiphysics simulation and in-situ measurement in building semiconductor processing digital twins. In this talk\, we will review the current state-of-the-art digital twin technologies and identify the gaps that need to be addressed to fully utilize digital twins in developing new process recipes in semiconductor manufacturing. \n6:45pm\n\nSemiconductors and Artificial Intelligence:The Virtuous Cycle\nPushkar Apte\nSEMI\n\n  \nArtificial Intelligence (AI) has taken the world by storm\, and has become a strategic imperative for most industries. While the concept of AI is over half a century old\, it has accelerated rapidly just over the past decade\, in large part due to amazing advances in semiconductor chips. In turn\, AI is driving growth in semiconductor revenues and improvements in operational efficiency\, creating a virtuous cycle. \nHowever\, there are formidable roadblocks ahead. AI models and datasets are growing at an exponential rate\, far outpacing hardware advances – creating both performance and sustainability challenges. System-level innovation is required for continued progress in AI\, which requires meaningful collaboration and data-sharing – often difficult in an industry where IP is critical. \nThis presentation will focus on this virtuous cycle between semiconductors and AI\, highlighting the benefits\, challenges and solution paths for continued progress. \nDay 2\, Friday 9:00am; Session 1\n9:05am\n\nIs AI intelligent?\nRonjon Nag\nStanford Medicine\n\n  \nArtificial intelligence is in the news daily\, and people ask whether they are truly intelligent. \nMaybe it still lacks the depth of human intelligence today\, but where is already cleverer\, and what stops it from reaching the ultimate pinnacle of ”general intelligence” – could that ever be possible? We will consider the implications of creating truly intelligent machines and the potential consequences for human society. \n10:00am\n\nTrust Based Modeling for Improved Security\nNaresh Sehgal\nDeeply Human AI\n\n  \nThe present state of Edge Computing is an environment of different computing capabilities connected via various communication paths. Actors on the Edge may interact with each other and a central datacenter. An important part of information security is the evaluation of trust between actors\, whether those actors are people or machines. Although many distributed trust models exist\, our proposed model introduces three key concepts. The first concept is that trust is not bidirectional between two parties. The second concept is that trust is different between different actors\, based upon the nature of their relationships. The third concept is that trust depends on the content of a transaction. We will present some real-life examples to illustrate these concepts. \n10:35am\n\nAdvancing Hardware Security in the Post-Quantum Cryptography Landscape: Challenges and Solutions\nQian Wang\nU. Cal. Merced\n\n  \nHardware security in the era of post-quantum cryptography has become increasingly crucial due to the potential threat quantum computers pose to traditional cryptographic algorithms. Post-quantum cryptography aims to develop cryptographic algorithms that are resistant to attacks from quantum computers. However\, ensuring the security of these algorithms requires not only advancements in software but also robust hardware security measures. In this talk\, we will first discuss the implementation of quantum-resistant cryptographic modules on hardware platforms\, necessitating upgrades in both hardware and firmware to accommodate new algorithms efficiently. Moreover\, hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks\, where an attacker exploits information leaked through physical characteristics such as power consumption or electromagnetic radiation. Post-quantum cryptographic hardware must incorporate countermeasures to mitigate these risks. \n11:20am\n\nScaling to Meet the Needs of AI\nPradeep Dubey\nIntel\n\n  \nArtificial intelligence (AI) is impacting not just what computing can do for us\, rather how computing gets done. Fast-evolving AI algorithms are driving demand for growing performance at an unprecedented rate and scale. This talk is about some of our research aimed at exploring technological and system-level opportunities for cost-effective scaling of emerging AI datacenters. \n1:00pm\n\nThe Future of Generative AI: Key Technology Trends and Innovations\nShiva Kintali\nR3AI\n\n  \nLLMs have emerged as powerful tools\, revolutionizing various domains from natural language processing to content generation\, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention. \nWhile they offer convenience and productivity\, we dissect how they can also be manipulated and weaponized by malicious actors\, raising concerns about inherent biases\, jailbreaking potential\, security concerns\, privacy issues\, misinformation\, deepfakes\, cyber threats and their unsettling societal consequences. We explore how biases present in training data\, historical injustices\, and societal prejudices can be perpetuated and even amplified by these models\, posing a significant threat to fairness\, equity\, and inclusivity. \nThis talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges\, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences. \n1:35pm\n\nEmerging Technologies for Computing Paradigm Shift\nBrandon Wang\nSynopsys\n\n  \nThe explosive growth of AI has triggered a rapid increase in semiconductor demand\, leading to soaring power consumption and unsustainable water usage. This presentation will explore emerging technologies essential for driving a paradigm shift towards energy-efficient computing. Topics will include the “Shift Left” design methodology\, the impact of SLMs (Small Language Models) on computational efficiency in AI\, and the potential of neuromorphic and quantum computing as next-generation architectures. These advancements are poised to enable significant digital transformation and drive pervasive intelligence across various industries. The speaker will also provide insights into how organizations can stay at the cutting edge of these innovations\, offering a forward-looking perspective on the future of computational systems and the strategic steps needed to lead in this rapidly evolving landscape. \n2:10pm\n\nTBD\nChris Cheng\nHewlett-Packard Enterprise\n 
URL:https://marketingeda.com/event/electronic-design-process-symposium-edps-2024/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/edps-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240914T080000
DTEND;TZID=America/Los_Angeles:20240919T170000
DTSTAMP:20240909T164418Z
CREATED:20240909T164418Z
LAST-MODIFIED:20240909T164418Z
UID:8313-1726300800-1726765200@marketingeda.com
SUMMARY:46th Annual EOS/ESD Symposium & Exhibits
DESCRIPTION:The EOS/ESD Symposium is dedicated to the understanding of issues related to electrostatic discharge and electrical transients/overstress\, and the application of this knowledge to the solution of problems in consumer\, industrial\, and automotive applications\, including electronic components\, as well as in systems\, subsystems\, and equipment.
URL:https://marketingeda.com/event/46th-annual-eos-esd-symposium-exhibits/
LOCATION:Peppermill Resort and Casino\, 2707 South Virginia Street\, Reno\, NV\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EOSESD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Denver:20240909T080000
DTEND;TZID=America/Denver:20240911T170000
DTSTAMP:20240524T202400Z
CREATED:20240524T202400Z
LAST-MODIFIED:20240524T202400Z
UID:8043-1725868800-1726074000@marketingeda.com
SUMMARY:MLCAD Symposium 2024
DESCRIPTION:The symposium focuses on Machine Learning (ML) for all aspects of CAD and electronic system design. The symposium is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The symposium program will have keynote and invited speakers in addition to technical presentations.\nMLCAD 2024 will be held physically in Snowbird\, Utah. \nFocus\nAdvances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However\, design processes present challenges that require synergetic advances in ML and CAD as compared to traditional ML applications. As such\, the purpose of the symposium is to discuss\, define and provide a roadmap for the special needs for ML for CAD where CAD is broadly defined to include both design-time techniques as well as run-time techniques.\nTopics of interest to this symposium include but are not limited to:\n• LLM-CAD: Large Language Model for CAD\n• ML approaches to logic design.\n• ML for physical design.\n• ML for analog design.\n• ML for FPGA designs.\n• ML methods to predict and optimize circuit aging and reliability.\n• Labeled and unlabeled data in ML for CAD.\n• ML for power and thermal management.\n• ML techniques for resource management in many-cores.\n• ML for Design Technology Co-Optimization (DTCO).\n• ML for design verification.\n• ML for manufacturing test.
URL:https://marketingeda.com/event/mlcad-symposium-2024/
LOCATION:Snowbird\, 9385 Snowbird Center Trail\, Sandy\, UT\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MLCAD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240709T120000
DTEND;TZID=Asia/Kolkata:20240709T160000
DTSTAMP:20240621T162414Z
CREATED:20240621T162353Z
LAST-MODIFIED:20240621T162414Z
UID:8103-1720526400-1720540800@marketingeda.com
SUMMARY:Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve
URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Symposium,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240624T080000
DTEND;TZID=Europe/Berlin:20240628T170000
DTSTAMP:20240304T193822Z
CREATED:20240304T193822Z
LAST-MODIFIED:20240304T193822Z
UID:7702-1719216000-1719594000@marketingeda.com
SUMMARY:RISC-V Summit Europe 2024
DESCRIPTION:The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry\, government\, research\, academia and ecosystem support – that are building the future of innovation on RISC-V. \nRISC-V\, the open standard instruction set architecture (ISA)\, is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success\, with one-third of RISC-V’s global community based in Europe. \nRISC-V Summit Europe takes place from Monday 24th to Friday 28th June\, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe\, and for this reason the conference is designed to help attendees to explore both commercial and research applications. \nRISC-V Summit Europe is an opportunity not to be missed. Come to Munich to be part of the new wave of European computing innovation!
URL:https://marketingeda.com/event/risc-v-summit-europe-2024/
LOCATION:MOC Conference\, Lilienthalallee 40\, Munich\, Germany
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20240528T093000
DTEND;TZID=Asia/Jerusalem:20240528T173000
DTSTAMP:20240522T193335Z
CREATED:20240522T193335Z
LAST-MODIFIED:20240522T193335Z
UID:8027-1716888600-1716917400@marketingeda.com
SUMMARY:FV-Israel\, Summit 2024
DESCRIPTION:Connect with industry experts\, academics\, and enthusiasts for discussions on FV in Israel. \nExplore new developments from top semiconductor firms\, advanced EDA tools\, and academic research. \nEngage with leaders\, exchange insights\, and help shape the future of FV in Israel and globally. \nDistinguished Speaker \nDadi Perlmutter\nTechnology and social entrepreneur and former VP at Intel
URL:https://marketingeda.com/event/fv-israel-summit-2024/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FV-Israel-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240528T090000
DTEND;TZID=Asia/Shanghai:20240528T160000
DTSTAMP:20240522T200534Z
CREATED:20240522T194800Z
LAST-MODIFIED:20240522T200534Z
UID:8030-1716886800-1716912000@marketingeda.com
SUMMARY:TSMC 2024 China Technology Symposium
DESCRIPTION:Get the latest on:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC Technology Symposium! \n\n\n\n09:00 – 10:00\nRegistration & Ecosystem Pavilion\n\n\n10:00 – 10:10\nWelcome & Opening Remarks\n\n\n10:10 – 10:30\nMarket Update and Outlook\n\n\n10:30 – 11:00\nTechnology Leadership\n\n\n11:00 – 11:25\nCoffee Break & Ecosystem Pavilion\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 12:15\nAdvanced Technology Design Solutions\n\n\n12:15 – 13:25\nLunch & Ecosystem Pavilion\n\n\n13:25 – 13:45\nAdvanced Technology\n\n\n13:45 – 14:05\n3DFabric Technology\n\n\n14:05 – 14:40\nCoffee Break & Ecosystem Pavilion\n\n\n14:40 – 15:00\nAutomotive & eNVM Technology\n\n\n15:00 – 15:20\nIoT Technology\n\n\n15:20 – 15:40\nAdvanced RF and Analog Technology\n\n\n15:40 – 16:00\nLucky Draw
URL:https://marketingeda.com/event/tsmc-2024-china-technology-symposium/
LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240514T080000
DTEND;TZID=Europe/London:20240514T170000
DTSTAMP:20240503T191344Z
CREATED:20240430T203151Z
LAST-MODIFIED:20240503T191344Z
UID:7935-1715673600-1715706000@marketingeda.com
SUMMARY:TSMC 2024 Technology Symposium - Europe
DESCRIPTION:Agenda\n\n\nEurope Technology Symposium\n*The agenda is subject to change\n\n\n\n08:30 – 09:30\n\nRegistration & Ecosystem Pavilion\n\n\n\n09:30 – 09:40\n\nWelcome & Opening Remarks\n\n\n\n09:40 – 10:20\n\nCEO Perspectives\n\n\n\n10:20 – 10:40\n\nMarket Update and Outlook\n\n\n\n10:40 – 11:10\n\nTechnology Leadership\n\n\n\n11:10 – 11:30\n\nCoffee Break & Ecosystem Pavilion\n\n\n\n11:30 – 11:55\n\nManufacturing Excellence\n\n\n\n11:55 – 12:20\n\nAdvanced Technology Design Solutions\n\n\n\n12:20 – 13:40\n\nLunch & Ecosystem Pavilion\n\n\n\n13:40 – 14:05\n\nHPC Platform – Advanced Technology and 3DFabric\n\n\n\n14:05 – 14:25\n\neNVM Technology Platform\n\n\n\n14:25 – 14:45\n\nAutomotive Platform\n\n\n\n14:45 – 15:15\n\nCoffee Break & Ecosystem Pavilion\n\n\n\n15:15 – 15:30\n\nAdvanced RF and Analog Technology Platform\n\n\n\n15:30 – 15:45\n\nIoT Technology Platform\n\n\n\n15:45 – 16:00\n\nHigh Voltage BCD/Power GaN Technology\n\n\n\n16:10 – 17:00\n\nSocial Hour
URL:https://marketingeda.com/event/tsmc-2024-technology-symposium-europe/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:Foundry,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T170000
DTSTAMP:20240325T163321Z
CREATED:20240325T163321Z
LAST-MODIFIED:20240325T163321Z
UID:7759-1713945600-1713978000@marketingeda.com
SUMMARY:TSMC 2024 Technology Symposium - North America
DESCRIPTION:Learn about:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-2024-technology-symposium-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T153000
DTSTAMP:20240222T182630Z
CREATED:20240222T182630Z
LAST-MODIFIED:20240222T182630Z
UID:7686-1711015200-1711035000@marketingeda.com
SUMMARY:AI-Powered Electromagnetics Symposium
DESCRIPTION:Accelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization \nHow are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such as electromagnetic interference (EMI)\, electromagnetic compatibility (EMC)\, power integrity\, and signal integrity play? \nDiscover how Cadence is transforming electromagnetic (EM) simulation for optimal design performance with innovative\, AI-driven multiphysics optimization software and breakthrough 3D EM analysis. \nJoin our CadenceCONNECT: AI-Powered EM Symposium\, where industry experts\, including Cadence\, Meta\, Microsoft\, and more\, will share insights highlighting how the Cadence Clarity 3D Solver and Optimality Intelligent Explorer workflow streamlines design results in optimized electronic product designs. \n\n\n\n\n\n\n\n\n\n\n\n\nAgenda \n10:00am – 10:30am               Registration | Light Breakfast \n10:30am – 12:00pm               Morning Sessions \n12:00pm – 1:00pm                 Lunch | Live Demonstrations \n1:00pm – 2:30pm                   Afternoon Sessions \n2:30pm – 3:30pm                   Networking Event | Live Demonstrations
URL:https://marketingeda.com/event/ai-powered-electromagnetics-symposium/
LOCATION:Cadence Design Systems\, Building 5\, 2655 Seely Avenue\, San Jose\, CA\, 95131\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240215T123000
DTEND;TZID=Asia/Kolkata:20240215T170000
DTSTAMP:20240207T181103Z
CREATED:20240207T181103Z
LAST-MODIFIED:20240207T181103Z
UID:7591-1708000200-1708016400@marketingeda.com
SUMMARY:SiFive RISC-V Day
DESCRIPTION:Leadership in the RISC-V Era: India’s Exciting New Opportunity\nJoin SiFive for an informative afternoon session\, featuring key thought leaders in the fast -growing global RISC-V ecosystem. Krste Asanovic\, inventor of RISC-V and SiFive founder will be joined by academic and business leaders to provide an overview of RISC-V and the latest advances as well as talk about how RISC-V is a great opportunity for India to leap ahead in semiconductor technology leadership. \nIndia’s strengths in software and hardware design are helping it jump ahead as RISC-V takes hold around the world\, but the open standard brings a lot of competition from other regions. Our guests will discuss India’s strengths and talk about advances to date and how the country\, and the companies doing business here should think about the opportunities ahead. \nJoin us for SiFive RISC-V Day India on February 15\, 2024. Attend this free event to meet the pioneers driving RISC-V. A networking lunch will be held before the event. Don’t miss out!
URL:https://marketingeda.com/event/sifive-risc-v-day/
LOCATION:Hilton Bangalore Embassy GolfLinks\, Embassy Golf Links Business Park\, Bangalore\, 560071\, India
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SiFive-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231112T080000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231031T163704Z
CREATED:20231031T163344Z
LAST-MODIFIED:20231031T163704Z
UID:7015-1699776000-1700154000@marketingeda.com
SUMMARY:ISTFA 2023
DESCRIPTION:Saving global resources by increasing energy efficiency is among the most significant problems that global society must address today. To achieve this\, a major target is developing efficient and reliable power electronics devices for providing the required high-performing hardware components. Power semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) technologies are becoming increasingly important since they allow smaller sizes\, lighter weight\, lower costs\, and higher efficiency of power electronics systems. For these innovative components\, there are still many issues to be resolved regarding the lack of robustness and reliability. This arises from significant failure risks during manufacturing and consequently may form roadblocking obstacles on the way to the mass market. The complexity of highly integrated SiC and GaN devices requires an in-depth understanding of defect formation and degradation mechanisms as well as adapted failure analysis methodologies. \nShare your experiences and advance the industry and your career at the 49th International Symposium for Testing and Failure Analysis\, the premier event for the microelectronics failure analysis community. We invite you to submit your work for publication and to present to the industry in Phoenix\, Arizona\, for the 49th year of ISTFA. \nKey Topics: \n\nAI Applications for Failure Analysis\nBoards and Systems\nCase Studies: Device Analysis\nCase Studies: FA Process and workflows\nDetecting and Preventing Counterfeit Microelectronics\nDie Level Fault Isolation\nEmerging FA Techniques and Concepts\nFIB Circuit Edit\nFIB Sample Preparation\nHardware Security & Counterfeiting\nMicroscopy Analysis and Material Characterization\nNanoprobing and Electrical Characterization\nPackage Level Fault Isolation\nPackaging and Assembly\nESD/EOS Failure Analysis\nPower Devices (Si\, SiC\, GaN)\nProduct Yield\, Test and Diagnostics\nSample Preparation and Device De-processing\nScanning Probe Analysis\nSystem in Package and 3D Devices\n\nKeynote Session\n \nDr. Peter Friedrichs\, Vice President SiC Infineon\nTuesday\, November 14 at 8:30 a.m.\nExhibit Halls – West Hall 1-2 – Industry Forum \nWide band gap power devices and related robustness and reliability aspects\nSilicon carbide (SiC) devices offer many advantages\, especially in power-conversion circuits for applications where efficiency is at a premium. These include solar inverters and electric vehicles\, which may also be expected to remain in service for decades. For these applications\, a combination of very high efficiency and long-term reliability is essential. The challenge in deploying SiC in such applications is that the technology is at an earlier stage of development than silicon. This means that the best ways of deploying SiC are still being explored\, and that some failure modes unique to SiC devices still need to be better understood and more effectively mitigated. Infineon has been working on these issues for years and so has the insights and experience necessary to both help customers deploy SiC devices to their advantage\, and to understand and mitigate their failure mechanisms to ensure the necessary reliability. The contribution will give insides into specific aspects regarding long term reliability and failure modes of sic power devices\, taking into account application relevant mission profiles.
URL:https://marketingeda.com/event/istfa-2023/
LOCATION:Phoenix Convention Center\, 100 North Third Street\, Phoenix\, AZ\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISTFA-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20231010T083000
DTEND;TZID=Asia/Jerusalem:20231010T164500
DTSTAMP:20230918T202326Z
CREATED:20230918T202326Z
LAST-MODIFIED:20230918T202326Z
UID:6814-1696926600-1696956300@marketingeda.com
SUMMARY:Synopsys Verification Technical Symposium 2023 - Israel
DESCRIPTION:Join us for a day filled with insights\, innovation\, and networking in the semiconductor industry. \nThe verification landscape is evolving\, and we’re here to help you navigate it. At this symposium\, we’ll be going through some of the most challenging use cases in chip design today\, while exploring best practices and the latest innovations for each use case. \nHere’s what’s on the agenda:\n– General sessions\, including an Executive Keynote.\n– Topics covering Power Efficiency\, Protocols\, and Cloud Solutions.\n– Choose between two tracks: Software (simulation\, static\, formal) and Hardware (emulation and prototyping). \nIf you have any immediate questions\, please feel free to reach out to us at verificationts@synopsys.com.
URL:https://marketingeda.com/event/synopsys-verification-technical-symposium-2023-israel/
LOCATION:Daniel Herzliya Hotel\, Ramat Yam St 60\, Herzliya\, Israel
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-10-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230630T080000
DTEND;TZID=Asia/Tokyo:20230630T170000
DTSTAMP:20230621T194040Z
CREATED:20230621T193324Z
LAST-MODIFIED:20230621T194040Z
UID:6557-1688112000-1688144400@marketingeda.com
SUMMARY:TSMC 2023 Technology Symposium - Japan
DESCRIPTION:Japan Technology Symposium\n\nDate\nFriday\, June 30\nTime\n9:30 a.m. – 5:20 p.m.\nVenue\nThe Yokohama Bay Hotel Tokyu\n2-3-7\, Minatomirai\, Nishi-ku\, Yokohama 220-8543\nRegistration will be closed on 6/21. Seats are limited.\n\nVoD (Video on Demand) will be available starting from 7/21.\nRegistration will close on 7/12. \nGet the latest on:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-2023-technology-symposium-japan/
LOCATION:The Yokohama Bay Hotel Tokyu\, 2-3-7\, Minatomirai\, Nishi-ku\, Yokohama\, Japan
CATEGORIES:Foundry,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-Japan.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20230611T080000
DTEND;TZID=Asia/Tokyo:20230616T170000
DTSTAMP:20230228T182652Z
CREATED:20230228T182652Z
LAST-MODIFIED:20230228T182652Z
UID:6035-1686470400-1686934800@marketingeda.com
SUMMARY:2023 Symposium on VLSI Technology and Circuits
DESCRIPTION:VLSI Symposium is an international conference on semiconductor technology and circuits that offers an opportunity to interact and synergize on topics spanning the range from process technology to system-on-chip. \nWe appreciate you to visit the VLSI symposium website. We also would like to invite you to join “2023 Symposium on VLSI technology and Circuits\,” which will be held from Sunday\, June 11 to Friday\, June 16 at Rihga Royal Hotel Kyoto in Japan. 2023 Symposium is planned as a fully in-person event in Kyoto for the first time in four years. On-demand access to technical papers will be available for people who cannot travel to Kyoto. We keep monitoring the COVID-19 pandemic and will inform you any changes in the symposium program. \nAbout the Symposium\nProfessors Shoji Tanaka and Walter Kosonocky\, founders of the Symposium\, first organized the VLSI Technology Symposium in 1981 with the hope of offering an opportunity for world’s top technologists to engage in an open exchange of ideas on what was quickly becoming a revolution in the world’s industrial capability. Since then\, the Symposium has been held annually and has grown to be an important and valuable event for people working in the VLSI business. The presentation of high-quality papers has made it possible for attendees to learn about new directions in the development of VLSI technology. The friendly atmosphere has made this an enjoyable learning experience. \nThe Symposium on VLSI Technology has alternated each year between sites in US and Japan. In 1987\, the first Symposium on VLSI Circuits was held in conjunction with the Technology Symposium in recognition of the growing interest to provide the same small but intense and open forum for discussing circuit and system implementations. Since then\, this annual meeting has increased its value over the past 30 years. We are confident that so many new technologies and circuits were introduced in the past Symposia and thus have contributed to the prosperity of the world. Its sponsors continue to be the IEEE Electron Devices Society and Solid-State Circuits Society\, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics\, Information and Communication Engineers. \nFor many reasons\, these meetings have remained linked for the past years to provide opportunities for technology people and circuit and system designers to interact with each other. These interactions are augmented with short courses\, invited speakers and several evening panel discussions\, Forums\, Workshops. In recognition of the efforts of organizers\, authors and participants to make the Symposia successful\, there is ample banquet and entertainment prearranged. \nIn its 42nd year of delivering a unique convergence of technology and circuits for the microelectronics industry\, the 2022 Symposium on VLSI Technology & Circuits had been merged into one Symposium to maximize the synergy across both domains. \nAfter the 2020 meeting had been held in a fully virtual format due to COVID-19\, the 2022 meeting was held in Honolulu\, Hawaii. This year it will be returning to the RIHGA Royal Hotel in Kyoto\, Japan in June of 2023. \nDATE AND LOCATION\nThe 2023 Symposium on VLSI Technology and Circuits will be held on June 11-16\, 2023\, JST respectively.\nAll the meetings will be held at RIHGA Royal Hotel Kyoto\, Horikawa Shiokoji\, Shimogyo ku \, Kyoto 600 8237\, Japan. \nHeld as a six-day at the Rihga Royal Hotel\, as well as selected presentations and panel sessions\, the Symposium will feature advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles. \nThe weeklong Symposium will continue its reputation as the microelectronics industry’s premiere international conference integrating technology\, circuits\, and systems with a range and scope unlike any other conferences. In addition to the technical presentations\, the Symposium program will feature a demonstration session\, evening panel discussions\, joint focus sessions\, short courses\, workshops\, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposium theme.
URL:https://marketingeda.com/event/2023-symposium-on-vlsi-technology-and-circuits/
LOCATION:Rihga Royal Hotel\, Kyoto\, Japan
CATEGORIES:IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2023-Symposium.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230508T080000
DTEND;TZID=America/New_York:20230510T170000
DTSTAMP:20230508T022819Z
CREATED:20230508T022819Z
LAST-MODIFIED:20230508T022819Z
UID:6363-1683532800-1683738000@marketingeda.com
SUMMARY:The 32nd Microelectronics Design and Test Symposium (MDTS 2023)
DESCRIPTION:Theme\n\nArtificial Intelligence\, Machine Learning\, and Deep Learning: Tactical and Strategic Impacts to Microelectronics Design and Test \nAbout MDTS 2023\nThe IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics\, share their visions in modern microelectronic technologies\, and foster academic-industry collaboration.  The 32nd MDTS features artificial intelligence (AI)\, machine learning (ML)\, and deep learning (DL).  AI/ML/DL algorithms can be used to improve design and test by evaluating the accuracy and effectiveness of models\, design rules\, and test coverage.  In addition\, new circuits and chip architectures for AI/ML/DL applications are emerging\, presenting new challenges to design and test in the form of reticle-size die\, chiplets\, and hardware/software co-design.
URL:https://marketingeda.com/event/the-32nd-microelectronics-design-and-test-symposium-mdts-2023/
LOCATION:Crowne Plaza – Desmond Hotel\, 660 Albany Shaker Rd\, Albany\, NY\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MDTS-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T080000
DTEND;TZID=America/Los_Angeles:20230426T170000
DTSTAMP:20230404T195733Z
CREATED:20230404T195733Z
LAST-MODIFIED:20230404T195733Z
UID:6230-1682496000-1682528400@marketingeda.com
SUMMARY:TSMC - North America Technology Symposium
DESCRIPTION:Join us and learn about:\n\nTSMC’s smartphone\, HPC\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and SoIC\nTSMC’s manufacturing excellence\, capacity expansion plan\, and green manufacturing achievement\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-north-america-technology-symposium/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Semiconductor,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2023-Technology-Symposium.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230418T100000
DTEND;TZID=America/Los_Angeles:20230418T170000
DTSTAMP:20230314T174241Z
CREATED:20230314T174241Z
LAST-MODIFIED:20230314T174241Z
UID:6148-1681812000-1681837200@marketingeda.com
SUMMARY:Static Sign-Off Symposium 2023
DESCRIPTION:Advanced Static Sign-Off Methodologies\n\n\nLeading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals\, along with results achieved in accelerating early functional verification and sign-off of digital designs. \nTopics will include: AI/ML\, targeted sign-off\, incremental sign-off\, multimode\, hierarchical\, dynamic CDC\, and more. \nAdvanced Static Sign-Off Methodology Presenters: \n\nRaj Khanna – Esperanto\nIgor Arsovski – Groq\nLouis Cardillo – NVIDIA\nPrakash Narain – Real Intent\nYC Lee – Samsung Electronics\nZeev Brunin – Speedata\n\nStatic sign-off domains covered: \n\nRTL linting\nClock domain crossing (CDC)\nReset domain crossing (RDC)\nDesign for Test (DFT)\nConnectivity & glitch\n\nFollowing the methodology discussions\, there will be a panel covering: \nMaximizing Design Efficiency with Static Sign-Off Methods
URL:https://marketingeda.com/event/static-sign-off-symposium-2023/
LOCATION:DoubleTree Hotel\, 2050 Gateway Place\, San Jose\, CA\, 95110\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Real-Intent-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230326T080000
DTEND;TZID=America/Los_Angeles:20230329T170000
DTSTAMP:20230310T181227Z
CREATED:20230310T181227Z
LAST-MODIFIED:20230310T181227Z
UID:6101-1679817600-1680109200@marketingeda.com
SUMMARY:International Symposium on Physical Design (ISPD) 2023
DESCRIPTION:General Information\nThe International Symposium on Physical Design (ISPD) provides a premier forum to exchange ideas and promote innovative research in all aspects of physical design ranging from traditional topics for ASIC and FPGA designs to emerging technologies that impact physical design of integrated circuits (ICs). In 2023\, ISPD will be online with virtual participation\, with both live video and recorded sessions. The 32nd symposium will highlight key new directions and leading-edge theoretical and experimental contributions to the field. \nWe will also pay tribute to Professor Malgorzata Marek-Sadowska (University of California at Santa Barbara) for her contributions to the physical design community. \n  \nRegistration is now open. Please register here.\n  \nLocation\nISPD 2023 will be held online\, with virtual participation across the world. There is a strong technical program including peer-reviewed papers\, invited papers\, and keynotes. Continuing the tradition of ISPD\, we have a contest and a great social program. \nImportant Dates\n\n\n\nContest registration deadline\nJanuary 15\, 2023\n\n\nCamera-ready paper or abstract + bio for invited speakers\nJanuary 29\, 2023\n\n\nSpeaker presentation videos due\nFebruary 26\, 2023\n\n\nSymposium\nMarch 26-29\, 2023\n\n\n\nSponsors\n\n\n\n\nSponsor\n\n\n\n\n\nTechnical Sponsors\n\n\n\n\n\n\nSupporters\n\n\n\n\nGold\n\n\n\n\n\n\n\nSilver
URL:https://marketingeda.com/event/international-symposium-on-physical-design-ispd-2023/
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/ISPD-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230313T080000
DTEND;TZID=America/Los_Angeles:20230317T170000
DTSTAMP:20230302T002531Z
CREATED:20230302T002531Z
LAST-MODIFIED:20230302T002531Z
UID:6053-1678694400-1679072400@marketingeda.com
SUMMARY:SEMI-THERM
DESCRIPTION:SEMI-THERM is an international symposium dedicated to the thermal management and characterization of electronic components and systems. SEMI-THERM provides knowledge covering all thermal scales from integrated circuits to facilities\, fosters discussions between thermal engineers\, professionals\, and industry experts\, and encourages the exchange of information on academic and industrial advances in electronics cooling. \n\n\nSymposium Highlights\n\n\n\nTechnical Sessions\nTechnical Short Courses\nTutorials\nVendor Exhibits\nVendor Workshops\nProduct Tear Downs\nPanel Discussions\nPoster / Dialog Session\n\n\n\nClick the Detailed Agenda button below to see the current details of the technical sessions and short courses. Additions to the schedule\, including the Keynote Presentation\, How-to Courses\, Panel Discussions\, and Industry Awards will be updated as available.
URL:https://marketingeda.com/event/semi-therm/
LOCATION:DoubleTree Hotel\, 2050 Gateway Place\, San Jose\, CA\, 95110\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-THERM-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221129T080000
DTEND;TZID=America/Los_Angeles:20221129T120000
DTSTAMP:20221011T180112Z
CREATED:20221011T180041Z
LAST-MODIFIED:20221011T180112Z
UID:5291-1669708800-1669723200@marketingeda.com
SUMMARY:Memory Technology Symposium
DESCRIPTION:Advancements in memory technology are fueling rapid growth in big data applications across AI\, 5G\, Automotive\, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated\, while the latest technology nodes have introduced some new ones. At Synopsys\, there is a corporate-wide commitment to developing broad-based solutions that address these challenges. \nWhy attend?\nThe Synopsys Memory Technology Symposium\, a first-of-its-kind virtual event dedicated to memory design and development\, aims to provide a forum for leading Memory\, IP\, SoC Companies and Synopsys experts to share their perspectives on the industry’s most compelling and topical challenges across four themes: Design Technology Co-optimization (DTCO)\, Design Shift Left\, IP\, and Silicon Reliability. Register to learn more!​
URL:https://marketingeda.com/event/memory-technology-symposium/
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Screen-Shot-2022-10-11-at-10.57.56-AM.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20221121T080000
DTEND;TZID=Asia/Taipei:20221123T170000
DTSTAMP:20221115T191652Z
CREATED:20221115T191639Z
LAST-MODIFIED:20221115T191652Z
UID:5403-1669017600-1669222800@marketingeda.com
SUMMARY:Asian Test Symposium 2022
DESCRIPTION:The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system\, board\, and device testing with design\, manufacturing\, and field consideration in mind.
URL:https://marketingeda.com/event/asian-test-symposium-2022/
LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ATS-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20221027T083000
DTEND;TZID=Europe/London:20221027T173000
DTSTAMP:20221007T183857Z
CREATED:20221007T183857Z
LAST-MODIFIED:20221007T183857Z
UID:5272-1666859400-1666891800@marketingeda.com
SUMMARY:Synopsys Technology Symposium 2022 - UK
DESCRIPTION:Synopsys Northern Europe is hosting a Technical Symposium providing updates on all aspects of doing state of the art designs at emerging and established nodes. \nThis event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that our experts will share. \nSynopsys technical experts will provide an “under the hood” look at proven and new technologies that designers can use to accelerate their aggressive time schedules and to achieve challenging Performance\, Power and Area goals. \nMultiple tracks will be offered where experts will update you on exciting new technologies and features that are now available. \nWe will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere. \n  \nYou will also have the opportunity to win one of our prizes in our Prize draw at the end of the day.
URL:https://marketingeda.com/event/synopsys-technology-symposium-2022-uk/
LOCATION:Hilton Reading\, Drake Way\, Reading\, RG2 0GQ\, United Kingdom
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-27-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221019T080000
DTEND;TZID=America/Los_Angeles:20221019T113000
DTSTAMP:20221005T171014Z
CREATED:20221005T171014Z
LAST-MODIFIED:20221005T171014Z
UID:5262-1666166400-1666179000@marketingeda.com
SUMMARY:Synopsys Photonic Symposium
DESCRIPTION:Photonics and photonic IC technologies are crucial to support rapidly evolving internet\, healthcare\, mobility\, and security needs. Driven by data communications\, photonic ICs are moving rapidly from the laboratory to mainstream and fueling a wave of innovations and product introductions. \nJoin our virtual Photonic Symposium to hear about the latest developments\, application requirements\, best practices\, and future outlook. \nOur lineup of speakers includes industry leaders from: \n\nGlobalFoundries\nIntel\nOptica\nPOET Technologies\nSouthern Methodist University\, Department of Electrical and Computer Engineering\nSynopsys\nYole Group\n\nWho Should Attend?\nAttendees will learn about photonic IC technology advances and market trends\, as well as photonic applications in LiDAR\, quantum computing\, and co-packaged optics.
URL:https://marketingeda.com/event/synopsys-photonic-symposium-2/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-October-19-2022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221006T080000
DTEND;TZID=America/Los_Angeles:20221007T170000
DTSTAMP:20220920T032644Z
CREATED:20220920T032644Z
LAST-MODIFIED:20220920T032644Z
UID:5217-1665043200-1665162000@marketingeda.com
SUMMARY:2022 IEEE Electronic Design Process Symposium (EDPS)
DESCRIPTION:We are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. \n\n\nAbout this event\n\n\n\n2022 IEEE EDPS will be held on Oct 6 and Oct 7 2022 in Milpitas\, CA. \nWe have invited industry practitioners and leaders from academia to present their work in following areas: \n\nInnovative Designs and Design Techniques including Design Co-optimization\nDesign for Trust/Design for Security\nAdvanced Packaging\, 3DIC\nDesign Technology Co-optimization/Systems Technology Co-optimization\nMachine Learning/Artificial Intelligence in System Design and EDA\nSystem Reliability\n5G Infrastructure\nSilicon Photonics\nSmart Manufacturing\n\nCheck out 2022 IEEE EDPS website for additional program details. \nPlease join us at SEMI facility in Milpitas\, CA this fall! The registration includes refreshments\, breakfast\, and lunch on both days\, as well as dinner on Thursday!
URL:https://marketingeda.com/event/2022-ieee-electronic-design-process-symposium-edps/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EDPS-2022.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220929T083000
DTEND;TZID=America/Los_Angeles:20220929T170000
DTSTAMP:20220810T163128Z
CREATED:20220810T163042Z
LAST-MODIFIED:20220810T163128Z
UID:5043-1664440200-1664470800@marketingeda.com
SUMMARY:Silicon Realization TechSummit
DESCRIPTION:This year’s event brings together Synopsys’ Digital Design Technical Symposium and Verification Day into a single event – Synopsys Silicon Realization TechSummit. This one-day\, in-person event is designed to inform executives\, managers\, and design and verification engineers about how the EDA industry is evolving.\n\nWhat Attendees Can Expect​\n\nA keynote and presentations from leaders in the EDA community.\nEngaging sessions focused on key technologies that make it possible for SoC designers to accelerate coverage closure and deliver energy-efficient chips with optimal power-performance-area faster than ever before.\nPanel discussions and a networking event where you can mingle with technologists and ask them you’re own challenging questions about the future of EDA.\n\nWe hope you’ll join us to learn about the challenges facing chip designers and the innovative digital design and verification solutions helping to solve them. Be sure to save the date!
URL:https://marketingeda.com/event/silicon-realization-techsummit/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-29-2022.jpg
END:VEVENT
END:VCALENDAR